74HC/HCT283 4-bit binary full adder with fast carry Product speci

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74HC/HCT283 4-bit binary full adder with fast carry Product speci

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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT283 4-bit binary full adder with fast carry
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
FEATURES High-speed 4-bit binary addition Cascadable 4-bit increments Fast internal look-ahead carry Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT283 high-speed Si-gate CMOS devices compatible with power Schottky (LSTTL). They specified compliance with JEDEC standard 74HC/HCT283 4-bit binary words plus plus incoming carry. binary appears outputs out-going carry (COUT) according equation:
74HC/HCT283
2(A2 +4(A3 8(A4 16COUT Where plus. symmetry binary function, "283" used with either active HIGH operands (positive logic) active operands (negative logic); function table. case active operands results COUT should interpreted also active LOW. With active HIGH inputs, must held when "carry intended. Interchanging inputs equal weight does affect operation, thus CIN, assigned arbitrarily pins etc. "583" version.
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay COUT COUT Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition December 1990 input capacitance power dissipation capacitance package notes CONDITIONS UNIT
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". DESCRIPTION SYMBOL COUT NAME FUNCTION outputs operand inputs operand inputs carry input ground carry output positive supply voltage
74HC/HCT283
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
Fig.4 Functional diagram.
FUNCTION TABLE PINS logic levels active HIGH active Note HIGH voltage level voltage level example 1001 1010 -10011 active HIGH, example active LOW, example (carry COUT
EXAMPLE(2)
December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
Fig.5 Logic diagram.
December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay propagation delay propagation delay propagation delay propagation delay COUT propagation delay COUT output transition time typ. max. min. max. +125 min. max. UNIT
74HC/HCT283
TEST CONDITIONS WAVEFORMS Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tTHL/ tTLH
Fig.6
December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT283
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below.
INPUT
UNIT LOAD COEFFICIENT 1.50 1.00 0.40 0.50
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay propagation delay propagation delay propagation delay propagation delay propagation delay COUT propagation delay COUT output transition time typ. max. min. max. +125 min. max. Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 UNIT WAVEFORMS TEST CONDITIONS
December 1990
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
WAVEFORMS APPLICATION INFORMATION
74HC/HCT283
Fig.7 3-bit adder.
50%; VCC. HCT:
Fig.6
Waveforms showing inputs (CIN, outputs COUT) propagation delays output transition times.
Fig.8 2-bit 1-bit adder.
Fig.9 5-input encoder.
Notes Figs Figure shows 3-bit adder using "283". Tying operand inputs fourth adder (A3, makes dependent equal carry from third adder. Based same principle, Figure shows method dividing "283" into 2-bit 1-bit adder. third stage adder (A2, used simply means transferring carry into fourth stage (via transferring carry from second stage Note that long long same, HIGH LOW, they influence Similarly, when same, carry into third stage does influence carry third stage. Figure shows method implementing 5-input encoder, where December 1990 Fig.10 5-input majority gate.
inputs equally weighted. outputs produce binary number equal number inputs that HIGH. Figure shows method implementing 5-input majority gate. When three more inputs HIGH, output HIGH. PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".

74HC/HCT283 4-bit binary full adder with fast carry Product speci

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