Publication Revision GeodeSC1200/SC1201 Processor Data Book
|
|
|
Top Searches for this datasheet
GeodeSC1200/SC1201 Processor Data Book
Publication Revision
GeodeSC1200/SC1201 Processor Data Book
2004 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Contacts www.amd.com pcs.support@amd.com Trademarks AMD, Arrow logo, combinations thereof, Geode, Virtual System Architecture trademarks Advanced Micro Devices, Inc. Microsoft Windows registered trademarks Microsoft Corporation United States other jurisdictions. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
GeodeSC1200/SC1201 Processor Data Book
Contents
Revision
Contents
List Figures List Tables GeodeSC1200/SC1201 Processor
General Description Features
Architecture Overview
Module Video Processor Module Core Logic Module SuperI/O Module Clock, Timers, Reset Logic
Signal Definitions
Ball Assignments Strap Options Multiplexing Configuration Signal Descriptions
General Configuration Block
Configuration Block Addresses Multiplexing, Interrupt Selection, Base Address Registers WATCHDOG High-Resolution Timer Clock Generators PLLs
SuperI/O Module
Features Module Architecture Configuration Structure Access Standard Configuration Registers Real-Time Clock (RTC) System Wakeup Control (SWC) ACCESS.bus Interface Legacy Functional Blocks
GeodeSC1200/SC1201 Processor Data Book
Revision
Contents
Core Logic Module
Feature List Module Architecture Register Descriptions Chipset Register Space
Video Processor Module
Module Architecture Functional Description Register Descriptions
Debugging Monitoring
Testability (JTAG)
Electrical Specifications
General Specifications Characteristics Characteristics
10.0 Package Specifications
10.1 Thermal Characteristics 10.2 Physical Dimensions
Appendix
Support Documentation
Order Information Macrovision Product Notice Data Book Revision History
GeodeSC1200/SC1201 Processor Data Book
List Figures
Revision
List Figures
Figure 1-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 4-1. Figure 4-2. Figure 4-3. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Figure 5-11. Figure 5-12. Figure 5-13. Figure 5-14. Figure 5-15. Figure 5-16. Figure 5-17. Figure 5-18. Figure 5-19. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Figure 6-14. Figure 6-15. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Block Diagram Signal Groups 432-EBGA Ball Assignment Diagram 481-TEPBGA Ball Assignment Diagram WATCHDOG Block Diagram Clock Generation Block Diagram Recommended Oscillator External Circuitry Block Diagram Detailed Block Diagram Standard Configuration Register File Structure Standard Configuration Registers Recommended Oscillator External Circuitry External Oscillator Connections Divider Chain Control Power Supply Connections Typical Battery Configuration Typical Battery Current: Battery Backed Power Mode 25°C Typical Battery Current: Normal Operation Mode Interrupt/Status Timing Transfer Start Stop Conditions ACCESS.bus Data Transaction ACCESS.bus Acknowledge Cycle Complete ACCESS.bus Data Transaction UART Mode Register Bank Architecture IRCP/SP3 Register Bank Architecture Core Logic Module Block Diagram Non-Posted Fast-PCI Access Cycles with Delayed Transaction Enabled Read from Memory Write Memory Change Sub-ISA Back Timer Interrupt Controllers Interrupt Mapping Generation General Purpose Timer UDEF Trap Tree Example Table Example AC97 V2.0 Codec Signal Connections Audio Tree Example Typical Setup Video Processor Block Diagram NTSC Lines, Field NTSC Lines, Even Field Block Diagram
GeodeSC1200/SC1201 Processor Data Book
Revision
List Figures
Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 7-9. Figure 7-10. Figure 7-11. Figure 7-12. Figure 7-13. Figure 7-14. Figure 7-15. Figure 7-16. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 9-8. Figure 9-9. Figure 9-10. Figure 9-11. Figure 9-12. Figure 9-13. Figure 9-14. Figure 9-15. Figure 9-16. Figure 9-17. Figure 9-18. Figure 9-19. Figure 9-20. Figure 9-21. Figure 9-22. Figure 9-23. Figure 9-24. Figure 9-25. Figure 9-26. Figure 9-27. Figure 9-28. Figure 9-29. Figure 9-30. Figure 9-31. Figure 9-32. Figure 9-33. Figure 9-34. Figure 9-35. Figure 9-36. Figure 9-37. Figure 9-38. Figure 9-39. Figure 9-40. Figure 9-41. Figure 9-42. Figure 9-43.
Capture Video Mode Example Using Video Frame Buffer Capture Video Mode Weave Example Using Video Frame Buffers Video Block Diagram Horizontal Downscaler Block Diagram Linear Interpolation Calculation Mixer/Blender Block Diagram Graphics/Video Frame with Alpha Windows Color Alpha Blending Logic TVOUT Block Diagram Voltage Levels Power Sequence Block Diagram Differential Input Sensitivity Common Mode Range General Drive level Measurement Points Memory Controller Drive Level Measurement Points Memory Controller Output Valid Timing Diagram Read Data Setup Hold Timing Diagram Video Input Port Timing Diagram Video Output Port Timing Diagram Timing Diagram Signals: Rising Falling Timing Diagram Start Stop Condition Timing Diagram Start Condition TIming Diagram Data Timing Diagram Testing Setup Slew Rate Minimum Timing Curves Output Signals PCICLK Timing Measurement Points Load Circuits Maximum Time Measurements Output Timing Measurement Conditions Input Timing Measurement Conditions Reset Timing Sub-ISA Read Operation Timing Diagram Sub-ISA Write Operation Timing Diagram Output Timing Diagram Input Timing Diagram Reset Timing Diagram Register Transfer to/from Device Timing Diagram Data Transfer to/from Device Timing Diagram Multiword Data Transfer Timing Diagram Initiating UltraDMA Data Burst Timing Diagram Sustained UltraDMA Data Burst Timing Diagram Host Pausing UltraDMA Data Burst Timing Diagram Device Terminating UltraDMA Data Burst Timing Diagram Host Terminating UltraDMA Data Burst Timing Diagram Initiating UltraDMA Data Burst Timing Diagram Sustained UltraDMA Data Burst Timing Diagram Device Pausing UltraDMA Data Burst Timing Diagram Host Terminating UltraDMA Data Burst Timing Diagram Device Terminating UltraDMA Data Burst Timing Diagram Data Signal Rise Fall Timing Diagram Source Differential Data Jitter Timing Diagram Width Timing Diagram Receiver Jitter Tolerance Timing Diagram UART, Sharp-IR, SIR, Consumer Remote Control Timing Diagram Fast Timing (MIR FIR) Diagram
GeodeSC1200/SC1201 Processor Data Book
List Figures
Revision
Figure 9-44. Figure 9-45. Figure 9-46. Figure 9-47. Figure 9-48. Figure 9-49. Figure 9-50. Figure 9-51. Figure 9-52. Figure 9-53. Figure 9-54. Figure 9-55. Figure 9-56. Figure 9-57. Figure 9-58. Figure 9-59. Figure 10-1. Figure 10-2. Figure 10-3.
Standard Parallel Port Typical Data Exchange Timing Diagram Enhanced Parallel Port Timing Diagram Forward Mode Timing Diagram Reverse Mode Timing Diagram AC97 Reset Timing Diagram AC97 Sync Timing Diagram AC97 Clocks Diagram AC97 Data TIming Diagram AC97 Rise Fall Timing Diagram AC97 Power Mode Timing Diagram PWRBTN# Trigger ONCTL# Timing Diagram GPWIO ONCTL# Timing Diagram Power-Up Sequencing With PWRBTN# Timing Diagram Power-Up Sequencing Without PWRBTN# Timing Diagram Measurement Points Timing Diagram JTAG Test Timing Diagram Heatsink Example 432-Terminal EBGA Package (Body Size: 40x40x1.72 Pitch: 1.27 481-Terminal TEPBGA Package (Body Size: 40x40x2.38 Pitch: 1.27
GeodeSC1200/SC1201 Processor Data Book
Revision
List Figures
GeodeSC1200/SC1201 Processor Data Book
List Tables
Revision
List Tables
Table 2-1. Table 2-2. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-15. Table 5-16. Table 5-17. Table 5-18. Table 5-19. Table 5-20. Table 5-21. Table 5-22. Table 5-23. Table 5-24. Table 5-25. Table 5-26. SC1200/SC1201 Processor Memory Controller Register Summary SC1200/SC1201 Processor Memory Controller Registers Signal Definitions Legend 432-EBGA Ball Assignment Sorted Ball Number 432-EBGA Ball Assignment Sorted Alphabetically Signal Name 481-TEPBGA Ball Assignment Sorted Ball Number 481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name Strap Options Two-Signal/Group Multiplexing Three-Signal/Group Multiplexing Four-Signal/Group Multiplexing General Configuration Block Register Summary Multiplexing, Interrupt Selection, Base Address Registers WATCHDOG Registers High-Resolution Timer Registers Crystal Oscillator Circuit Components Core Clock Frequency Strapped Core Clock Frequency Clock Generator Configuration Configuration Options Assignments Standard Configuration Registers Control Configuration Register Control Configuration Registers Relevant Configuration Registers Configuration Registers Relevant Registers Relevant IRCP/SP3 Registers IRCP/SP3 Configuration Register Relevant Serial Ports Registers Serial Ports Configuration Register Relevant ACB1 ACB2 Registers ACB1 ACB2 Configuration Register Relevant Parallel Port Registers Parallel Port Configuration Register Crystal Oscillator Circuit Components System Power States Register Registers Divider Chain Control Test Selection Periodic Interrupt Rate Encoding Binary Formats Standard Extended Time Range Limits CEIR Protocols
GeodeSC1200/SC1201 Processor Data Book
Revision
List Tables
Table 5-27. Table 5-28. Table 5-29. Table 5-30. Table 5-31. Table 5-32. Table 5-33. Table 5-34. Table 5-35. Table 5-36. Table 5-37. Table 5-38. Table 5-39. Table 5-40. Table 5-41. Table 5-42. Table 5-43. Table 5-44. Table 5-45. Table 5-46. Table 5-47. Table 5-48. Table 5-49. Table 5-50. Table 5-51. Table 5-52. Table 5-53. Table 5-54. Table 5-55. Table 5-56. Table 5-57. Table 5-58. Table 5-59. Table 5-60. Table 5-61. Table 5-62. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 6-10. Table 6-11. Table 6-12. Table 6-13. Table 6-14. Table 6-15. Table 6-16. Table 6-17. Table 6-18. Table 6-19.
Banks Common Control Status Register Bank CEIR Wakeup Configuration Control Register Banks Common Control Status Registers Bank CEIR Wakeup Configuration Control Registers Register Registers Parallel Port Register First Level Offset Parallel Port Register Second Level Offset Parallel Port First Level Offset Parallel Port Second Level Offset Bank Register Bank Selection Encoding Bank Register Bank Register Bank Register Bank Bank Bank Bank Bank Register Bank Selection Encoding Bank Register Bank Register Bank Register Bank Register Bank Register Bank Register Bank Register Bank Bank Bank Bank Bank Bank Bank Bank Physical Region Descriptor Format UltraDMA/33 Signal Definitions Cycle Multiplexed Sub-ISA Balls Interrupt Mapping Wakeup Events Capability Power Planes Control Signals Sleep States Power Planes Sleep/Global States Power Management Events Device Power Management Programming Summary Masters That Drive Specific Slots AC97 Interface Physical Region Descriptor Format Cycle Types Configuration Address Register (0CF8h) Header/Bridge Configuration Registers GPIO Support Summary F0BAR0: GPIO Support Registers Summary F0BAR1: Support Registers Summary Header Registers Status ACPI Support Summary F1BAR0: Status Registers Summary F1BAR1: ACPI Support Registers Summary
GeodeSC1200/SC1201 Processor Data Book
List Tables
Revision
Table 6-20. Table 6-21. Table 6-22. Table 6-23. Table 6-24. Table 6-25. Table 6-26. Table 6-27. Table 6-28. Table 6-29. Table 6-30. Table 6-31. Table 6-32. Table 6-33. Table 6-34. Table 6-35. Table 6-36. Table 6-37. Table 6-38. Table 6-39. Table 6-40. Table 6-41. Table 6-42. Table 6-43. Table 6-44. Table 6-45. Table 6-46. Table 6-47. Table 6-48. Table 6-49. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 7-9. Table 7-10. Table 8-1. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12. Table 9-13. Table 9-14.
Header Registers Controller Support Summary F2BAR4: Controller Support Registers Summary Header Registers Audio Support Summary F3BAR0: Audio Support Registers Summary Header Registers X-Bus Expansion Support Summary F5BAR0: Control Support Registers Summary PCIUSB: Configuration Register Summary USB_BAR: Controller Registers Summary Legacy Register Summary Header/Bridge Configuration Registers GPIO Support F0BAR0+I/O Offset: GPIO Configuration Registers F0BAR1+I/O Offset: Interface Configuration Registers Header Registers Status ACPI Support F1BAR0+I/O Offset: Status Registers F1BAR1+I/O Offset: ACPI Support Registers Header/Channels Registers Controller Configuration F2BAR4+I/O Offset: Controller Configuration Registers Header Registers Audio Configuration F3BAR0+Memory Offset: Audio Configuration Registers Header Registers X-Bus Expansion F5BAR0+I/O Offset: X-Bus Expansion Registers PCIUSB: Configuration Registers USB_BAR+Memory Offset: Controller Registers Channel Control Registers Page Registers Programmable Interval Timer Registers Programmable Interrupt Controller Registers Keyboard Controller Registers Real-Time Clock Registers Miscellaneous Registers Direct Mode Capture Mode Configurations Valid Mixing/Blending Configurations Truth Table Alpha Blending Flicker Filter Operation Header Registers Video Processor Support Summary F4BAR0: Video Processor Configuration Registers Summary F4BAR2: Support Registers Summary Header Registers Video Processor Support Registers F4BAR0+Memory Offset: Video Processor Configuration Registers F4BAR2+Memory Offset: Configuration Registers JTAG Mode Instruction Support Electro Static Discharge (ESD) Absolute Maximum Ratings Operating Conditions Power Planes External Interface Signals System Conditions Used Measure SC1200/SC1201 Current During State Characteristics State Characteristics Active Idle, Sleep, States Ball Capacitance Inductance Balls with PU/PD Resistors Buffer Types Default Levels Measurement Switching Parameters Memory Controller Timing Parameters Video Input Port Timing Parameters Video Output Port Timing Parameters
GeodeSC1200/SC1201 Processor Data Book
Revision
List Tables
Table 9-15. Table 9-16. Table 9-17. Table 9-18. Table 9-19. Table 9-20. Table 9-21. Table 9-22. Table 9-23. Table 9-24. Table 9-25. Table 9-26. Table 9-27. Table 9-28. Table 9-29. Table 9-30. Table 9-31. Table 9-32. Table 9-33. Table 9-34. Table 9-36. Table 9-37. Table 9-38. Table 9-39. Table 9-40. Table 9-41. Table 9-42. Table 9-43. Table 9-44. Table 9-45. Table 9-46. Table 9-47. Table 9-48. Table 10-1. Table 10-2. Table A-1. Table A-2.
Timing Parameters VESA Compatible (RED, GREEN, BLUE Outputs) Outputs: CVBS, SVY/TVR, SVC/TVB, CVBS/TVG) ACCESS.bus Input Timing Parameters ACCESS.bus Output Timing Parameters Specifications Clock Parameters Timing Parameters Measurement Condition Parameters Sub-ISA Timing Parameters SERIRQ General Timing Parameters Register Transfer to/from Device Timing Parameters Data Transfer to/from Device Timing Parameters Multiword Data Transfer Timing Parameters UltraDMA Data Burst Timing Parameters Timing Parameters UART, Sharp-IR, SIR, Consumer Remote Control Timing Parameters Fast Port Timing Parameters Standard Parallel Port Timing Parameters Forward Mode Timing Parameters Reverse Mode Timing Parameters Reset Timing Parameters AC97 Sync Timing Parameters AC97 Clocks Parameters AC97 Timing Parameters AC97 Signal Rise Fall Timing Parameters AC97 Power Mode Timing Parameters PWRBTN# Timing Parameters Power Management Event (GPWIO) ONCTL# Timing Parameters Power-Up Sequence Using Power Button Timing Parameters Power-Up Sequence Using Power Button Timing Parameters JTAG Timing Parameters Case-to-Ambient Thermal Resistance Example Revision History Edits Current Revision
GeodeSC1200/SC1201 Processor Data Book
GeodeSC1200/SC1201 Processor
Revision
1.0AMD GeodeSC1200/SC1201 Processor
General Description
Core Logic module includes: PC/AT functionality, interface, interface, interface, interface, Advanced Configuration Power Interface (ACPI) version compliant power management, audio codec interface. SuperI/O module has: three serial ports (UART1, UART2, UART3 with fast infrared), parallel port, ACCESS.bus (ACB) interfaces, real-time clock (RTC). These features, combined with device's power consumption, enable small form factor design making ideal core set-top advanced multimediatype device. Figure shows relationships between modules. GeodeSC1200 SC1201 processors members Geode processor family fully integrated system chips. SC1200/SC1201 processor includes: Geode processor module combines advanced performance with MMXsupport, fully accelerated graphics, 64-bit synchronous DRAM (SDRAM) interface, controller, display controller. low-power Video Processor module with hardware video accelerator scaling, filtering, color space conversion, Video Input Port (VIP), NTSC/PAL encoder. SC1201 (only) processor Macrovision copy protection support (see "Macrovision Product Notice" page 461).
Memory Controller Graphics Accelerator Controller Display Controller
Video Processor
Video Scaling Config. Block Video Input Port (VIP) Host Interface Fast-PCI Clock Reset Logic Fast X-Bus Video Mixer
Core
Bridge PCI/Sub-ISA GPIO Audio Codec X-Bus
Core Logic
DMAC Mgmnt Configuration
Parallel Port ACB1
SuperI/O
ACB2 UART1 UART2
UART3
Figure 1-1. Block Diagram
GeodeSC1200/SC1201 Processor Data Book
Revision
GeodeSC1200/SC1201 Processor
Features
Video Processor Module
Video Accelerator:
General Features
32-Bit processor, MHz, with instruc-
tion support
Memory controller with 64-bit SDRAM interface graphics accelerator controller with hardware video accelerator CCIR-656 video input port with direct video full
Flexible video scaling support (horizontally vertically) Bilinear interpolation filters (with taps, eight phases) smooth output video
Video/Graphics Mixer:
screen display
PC/AT functionality controller interface, channels USB, three ports, OHCI (OpenHost Controller Interface)
8-Bit value alpha blending Three blending windows with constant alpha value Color
Video Input Port (VIP):
version compliant
Audio, AC97/AMC97 version compliant Virtual System Architecturetechnology (VSA) support Power management, ACPI (Advanced Configuration
Video capture display CCIR-656 VESA Video Interface Port v1.1 compliant Lock display timing video input timing (GenLock) Able transfer video data into main memory Direct video transfer full screen display Separate memory location
Video Output Port (VOP):
VESA Video Interface Port Rev. Task format
Interface:
Power Interface) version compliant
Package:
432-Terminal EBGA (Enhanced Ball Grid Array) 481-Terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) Processor Module
Core:
Uses three 8-bit DACs Support 1280x1024 non-interlaced bpp, 1024x768 non-interlaced bpp,
Interface:
32-Bit x86, MHz, with compatible instruction support unified cache Integrated (Floating Point Unit) Re-entrant (System Management Mode) enhanced
Graphics Accelerator:
Direct connection panels 800x600 non-interlaced graphics, 1024x768 non-interlaced graphics, IDE: FPCLK Parallel Port: FPCLK
Interface:
Accelerates BitBLTs, line draw text Supports raster operations Supports transparent BLTs Runs core clock frequency
Memory Controller:
64-Bit SDRAM interface frequency range Direct interface with CPU/cache, display controller graphic accelerator Supports clock suspend power-down/ self-refresh banks SDRAM devices total) SODIMM
Display Controller:
Uses four 10-bit DACs 720x480 NTSC 720x576 NTSC-M, PAL-M/B/D/G/H/I Luminance filtering with oversampling sinx/x correction Chrominance filtering with oversampling Flicker filter with three-line buffer graphics display Composite, S-Video YCrCb component video outputs Analog video output interface supports SCART standard (both RGBCvbs YCCvbs) Support (Vertical Blanking Interval) transfer from Video Port input Encoder
Hardware graphics frame buffer compress/ decompress Hardware cursor, 32x32 pixels
GeodeSC1200/SC1201 Processor Data Book
GeodeSC1200/SC1201 Processor
Revision Interface:
Generation Support: Wide Screen Signaling (WSS) Closed caption Extended Data Services (EDS) Copy Generation Management System (CGMS) Four-field NTSC eight-field generation Macrovision copy protection version 7.1.L1 (SC1201 only, "Macrovision Product Notice" page 461) Core Logic Module
Audio Codec Interface:
channels four external devices Supports ATA-33 synchronous mode transfers, MB/s
Universal Serial (USB):
OpenHCI compliant Three ports SuperI/O Module
Real-Time Clock (RTC):
AC97/AMC97 (Rev. 2.0) codec interface channels
PC/AT Functionality:
DS1287, MC146818 PC87911 compatible Multi-century calendar
ACCESS.bus (ACB) Interface:
Programmable Interrupt Controller (PIC), 8259Aequivalent Programmable Interval Timer (PIT), 8254-equivalent Controller (DMAC), 8237-equivalent
Power Management:
interface ports
Parallel Port:
compliant IEEE 1284 compliant, including level
Serial Port (UART):
ACPI v1.0 compliant state control three power planes Cx/Sx state control clocks PLLs Thermal event input Wakeup event support: Three general-purpose events AC97 codec event UART2 signal Infrared (IR) event
UART1, 16550A compatible (SIN, SOUT, BOUT pins), used SmartCard interface UART2, 16550A compatible Enhanced UART with fast Infrared (IR) Other Features
High-Resolution Timer:
32-Bit counter with count interval
WATCHDOG Timer:
General Purpose I/Os (GPIOs):
multiplexed GPIO signals
Count (LPC) Interface:
Interfaces INTR, SMI, Reset
Clocks:
Specification v1.0 compatible
Interface:
v2.1 compliant with wakeup capability 32-Bit data path, Glueless interface external device Fixed priority 3.3V signal support only
Input (external crystals): 32.768 (internal clock oscillator) (internal clock oscillator) Output: AC97 clock (24.576 MHz) Memory controller clock MHz) clock MHz)
JTAG Testability:
Sub-ISA Interface:
Bypass, Extest, Sample/Preload, IDcode, Clamp,
Voltages:
addressing Supports chip select Flash EPROM boot device Supports either: M-Systems DiskOnChip DOC2000 Flash file system NAND EEPROM Supports chip selects external devices 8-Bit (optional 16-bit) data width Shares balls with signals subtractive agent
Internal logic: 1.8V Standby logic: 1.8V I/O: 3.3V Standby I/O: 3.3V Battery used): 3.0V
GeodeSC1200/SC1201 Processor Data Book
Revision
GeodeSC1200/SC1201 Processor
GeodeSC1200/SC1201 Processor Data Book
Architecture Overview
Revision
2.0Architecture Overview
illustrated Figure page SC1200/ SC1201 processor contains following modules integrated device: Module: Combines advanced performance with support, fully accelerated graphics, 64-bit synchronous DRAM (SDRAM) interface controller. Integrates silicon revision 8.1.1. Video Processor Module: low-power support module with hardware video accelerator scaling, filtering color space conversion, video input port (VIP). Includes NTSC/PAL encoder. Core Logic Module: Includes PC/AT functionality, interface, Universal Serial (USB) interface, ACPI compliant power management, audio codec interface. SuperI/O Module: Includes Serial Ports, Infrared (IR) Port, Parallel Port, ACCESS.bus interfaces, Real-Time Clock (RTC).
SC1200/SC1201 processor's device contained module. Software detect revision reading DIR0 DIR1 Configuration registers (see Configuration registers GeodeGX1 Processor Data Book). GeodeSC1200/SC1201 Processor Specification Update document contains specific values.
2.1.1
Memory Controller
module connected external SDRAM devices. more information Section 3.4.2 "Memory Interface Signals" page "Memory Controller" chapter GeodeGX1 Processor Data Book. There some differences SC1200/SC1201 processor's memory controller stand-alone processor's memory controller: There drive strength/slew control SC1200/ SC1201 that GX1. bits that control this function MC_MEM_CNTRL1 MC_MEM_CNTRL2 registers. processor, these bits marked reserved. SC1200/SC1201 supports banks memory. supports four banks memory. addition, SC1200/SC1201 supports maximum eight devices supports devices. With this difference, MC_BANK_CFG register different.
Module
processor (silicon revision 8.1.1) central module SC1200/SC1201 processor. detailed information regarding module, refer GeodeGX1 Processor Data Book GeodeGX1 Processor Silicon Revision 8.1.1 Specification Update documents.
Table page summarizes 32-bit registers contained SC1200/SC1201 processor's memory controller. Table page gives detailed register/bit formats.
GeodeSC1200/SC1201 Processor Data Book
Revision
Architecture Overview
Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary
GX_BASE+ Memory Offset 8400h-8403h 8404h-8407h 8408h-840Bh 840Ch-840Fh 8414h-8417h 8418h-841Bh 841Ch-841Fh Width (Bits) Type Name/Function MC_MEM_CNTRL1. Memory Controller Control Register MC_MEM_CNTRL2. Memory Controller Control Register MC_BANK_CFG. Memory Controller Bank Configuration MC_SYNC_TIM1. Memory Controller Synchronous Timing Register MC_GBASE_ADD. Memory Controller Graphics Base Address Register MC_DR_ADD. Memory Controller Dirty Address Register MC_DR_ACC. Memory Controller Dirty Access Register Reset Value 248C0040h 00000801h 41104110h 2A733225h 00000000h 00000000h 0000000xh
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers
Description MC_MEM_CNTRL1 (R/W) Reset Value: 248C0040h
GX_BASE+ 8400h-8403h 31:30 28:27 25:24 23:22 20:18
MDCTL (MD[63:0] Drive Strength). strongest, weakest. RSVD (Reserved). Write MABACTL (MA[12:0] BA[1:0] Drive Strength). strongest, weakest. RSVD (Reserved). Write MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). strongest, weakest. RSVD (Reserved). Write RSVD (Reserved). Must written Wait state X-Bus x_data during read cycles debug only. SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio. 000: Reserved 001: 010: 011: (Default) 100: 101: 110: 111:
Ratio does take effect until SDCLKSTRT (bit this register) transitions from SDCLKSTRT (Start SDCLK). Start operating SDCLK using ratio shift value (selected bits [20:18] this register). Clear. Enable. This must transition from zero (written zero) (written one) order start SDCLK change shift value. 16:8 RFSHRATE (Refresh Interval). This field determines number processor core clocks multiplied between refresh cycles DRAM. default, refresh interval 00h. Refresh turned default. RFSHSTAG (Refresh Staggering). This field determines number clocks between RFSH commands each four banks during refresh cycles: SDRAM clocks SDRAM clocks (Default) SDRAM clocks SDRAM clocks Staggering used help reduce power spikes during refresh refreshing bank time. only bank installed, this field must written 2CLKADDR (Two Clock Address Setup). Assert memory address extra clock before asserted. Disable. Enable. This used compensate address setup high frequencies and/or high loads. GeodeSC1200/SC1201 Processor Data Book
Architecture Overview
Revision
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued)
Description RFSHTST (Test Refresh). This bit, when high, generates refresh request. This only used testing purposes. XBUSARB (X-Bus Round Robin). When round robin enabled, processor, graphics pipeline, priority display controller requests arbitrated same priority level. When disabled, processor requests arbitrated higher priority level. High priority display controller requests always have highest arbitration priority. Disable. Enable round robin. SMM_MAP (SMM Region Mapping). Maps memory region GX_BASE+400000 physical address A0000 BFFFF SDRAM. Disable. Enable. RSVD (Reserved). Write SDRAMPRG (Program SDRAM). When this set, memory controller will program SDRAM register using LTMODE MC_SYNC_TIM1. This must transition from zero (written zero) (written one) order program SDRAM devices. GX_BASE+8404h-8407h 31:14 13:12 RSVD (Reserved). Write SDCLKCTL (SDCLK High Drive/Slew Control). Controls high drive slew rate SDCLK[3:0] SDCLK_OUT. strongest, weakest. RSVD (Reserved). Write SDCLKOMSK# (Enable SDCLK_OUT). Turns output. Enable. Disable. SDCLK3MSK# (Enable SDCLK3). Turns output. Enable. Disable. SDCLK2MSK# (Enable SDCLK2). Turns output. Enable. Disable. SDCLK1MSK# (Enable SDCLK1). Turns output. Enable. Disable. SDCLK0MSK# (Enable SDCLK0). Turns output. Enable. Disable. SHFTSDCLK (Shift SDCLK). This function allows shifting SDCLK meet SDRAM setup hold time requirements. shift function will take effect until SDCLKSTRT (bit MC_MEM_CNTRL1) transitions from 000: shift 001: Shift core clock 010: Shift core clock 011: Shift core clock RSVD (Reserved). Write (Read Data Phase). Selects read data latched core clock after rising edge SDCLK. Core clock. Core clocks. FSTRDMSK (Fast Read Mask). allow core reads bypass request FIFO. Disable. Enable. 100: Shift core clocks 101: Shift core clocks 110: Shift core clocks 111: Reserved MC_MEM_CNTRL2 (R/W) Reset Value: 00000801h
GeodeSC1200/SC1201 Processor Data Book
Revision
Architecture Overview
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued)
Description MC_BANK_CFG (R/W) Reset Value: 41104110h
GX_BASE+8408h-840Bh 31:16 RSVD (Reserved). Write 0070h RSVD (Reserved). Write
SODIMM_MOD_BNK (SODIMM Module Banks Banks Selects number module banks installed SODIMM SODIMM: Module bank (Bank only) Module banks (Bank
RSVD (Reserved). Write SODIMM_COMP_BNK (SODIMM Component Banks Banks Selects number component banks module bank SODIMM: Component banks Component banks Banks must have same number component banks.
10:8
RSVD (Reserved). Write SODIMM_SZ (SODIMM Size Banks Selects size SODIMM: 000: 001: 010: 011: 100: 101: 110: 111:
This size total both banks Also, banks must same size. RSVD (Reserved). Write SODIMM_PG_SZ (SODIMM Page Size Banks Selects page size SODIMM: 000: 001: 010: 011: 1xx: 111: SODIMM installed
Both banks must have same page size. RSVD (Reserved). Write MC_SYNC_TIM1 (R/W) Reset Value: 2A733225h
GX_BASE+840Ch-840Fh 30:28 RSVD (Reserved). Write
LTMODE (CAS Latency). latency delay, SDRAM clock cycles, between registration read command availability first piece output data. This parameter significantly affects system performance. Optimal setting should used. SODIMM used, BIOS interrogate EEPROM across ACCESS.bus interface determine this value: 000: Reserved 001: Reserved 010: 011: 100: 101: 110: 111:
This field will take effect until SDRAMPRG (bit MC_MEM_CNTRL1) transitions from 27:24 (RFSH RFSH/ACT Command Period, tRC). Minimum number SDRAM clock between RFSH RFSH/ACT commands: 0000: Reserved 0001: 0010: 0011: 23:20 0000: Reserved 0001: 0010: 0011: 18:16 0100: 0101: 0110: 0111: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1100: 1101: 1110: 1111:
(ACT Command Period, tRAS). Minimum number SDRAM clocks between commands:
RSVD (Reserved). Write (PRE Command Period, tRP). Minimum number SDRAM clocks between commands: 000: Reserved 001: 010: 011: 100: 101: 110: 111:
14:12
RSVD (Reserved). Write (Delay Time READ/WRT Command, tRCD). Minimum number SDRAM clock between READ/ commands. This parameter significantly affects system performance. Optimal setting should used: 000: Reserved 001: 010: 011: 100: 101: 110: 111: GeodeSC1200/SC1201 Processor Data Book
Architecture Overview
Revision
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued)
10:8 Description RSVD (Reserved). Write (ACT(0) ACT(1) Command Period, tRRD). Minimum number SDRAM clocks between command different component banks within same module bank. memory controller does perform back-to-back Activate commands different component banks without READ WRITE command between them. Hence, this field should written 001. RSVD (Reserved). Write (Data-in Command Period, tDPL). Minimum number SDRAM clocks from time last write datum sampled till bank precharged: 000: Reserved 001: Note: 010: 011: 100: 101: 110: 111:
RSVD (Reserved). Leave unchanged. Always returns 101h. Refer SDRAM manufacturer's specification more information component banks. MC_GBASE_ADD (R/W) Reset Value: 00000000h
GX_BASE+8414h-8417h 31:18 RSVD (Reserved). Write (Test Enable TEST[3:0]).
TEST[3:0] driven (normal operation). TEST[3:0] pins used output test information TECTL (Test Enable Shared Control Pins). RASB#, CASB#, CKEB, WEB# (normal operation). RASB#, CASB#, CKEB, WEB# used output test information 15:12 10:0 (Select). This field used debug purposes only should left zero normal operation. RSVD (Reserved). Write GBADD (Graphics Base Address). This field indicates graphics memory base address, which programmable boundaries. This field corresponds address bits [29:19]. Note that BC_DRAM_TOP must value lower than Graphics Base Address. GX_BASE+8418h-841Bh 31:10 RSVD (Reserved). Write DRADD (Dirty Address). This field address index that used access Dirty with MC_DR_ACC register. This field does auto increment. MC_DR_ACC (R/W) Reset Value: 0000000xh MC_DR_ADD (R/W) Reset Value: 00000000h
GX_BASE+841Ch-841Fh 31:2 RSVD (Reserved). Write
(Dirty Bit). This read/write accessible. (Valid Bit). This read/write accessible.
GeodeSC1200/SC1201 Processor Data Book
Revision
Architecture Overview
2.1.2
Fast-PCI
2.2.1
Module Interface
module communicates with Core Logic module Fast-PCI that work MHz. Fast-PCI internal SC1200/SC1201 processor connected General Configuration Block (see Section page details General Configuration Block). This supports seven masters. requests (REQs) fixed priority. seven masters order priority are: Channel Channel Audio External REQ0# External REQ1#
Video Processor connected module following way: Video Processor's DOTCLK output signal used module's DCLK input signal. module's PCLK output signal used GFXCLK input signal Video Processor.
2.2.2
Video Input Port
Video Input Port (VIP) within Video Processor contains standard interface that typically connected media processor encoder. clock supplied externally connected device; typically MHz. Video input sent module's video frame buffer (Capture Video mode) used directly (Direct Video mode).
2.2.3
Core Logic Module Interface
Video Processor interfaces Core Logic module accessing function configuration registers.
2.1.3
Display 2.2.4
Video Processor drives three DACs with 135M pixels second. interface these DACs monitored external balls SC1200/SC1201 processor. more information, Section 3.4.4 "CRT/TFT Interface Signals" page
module generates display timing, controls internal signals CRT_VSYNC CRT_HSYNC Video Processor module. module interfaces with Video Processor video data graphics data bus. Video data. module uses core clock, divided (typically MHz). drives video data using this clock. Internal signals VID_VAL VID_RDY used data-flow handshake signals between module Video Processor. Graphics data. module uses internal DCLK signal, supplied Video Processor, drive 18-bit graphics-data Video Processor. Each bits this define different color. Each these 6-bit color definitions expanded adding zero lines) form 8-bit bus, Video Processor. more information about module's interface Video Processor, "Display Controller" chapter GeodeGX1 Processor Data Book.
Core Logic Module
Core Logic module described detail Section page 161. Core Logic module connected Fast-PCI bus. uses signal AD28 IDSEL configuration functions except which uses AD29.
2.3.1
Other Core Logic Module Interfaces
following interfaces Core Logic module implemented external signals SC1200/SC1201 processor. Each interface listed below with reference descriptions relevant signals. IDE: Section 3.4.10 "IDE Interface Signals" page AC97: Section 3.4.15 "AC97 Audio Interface Signals" page PCI: Section 3.4.7 "PCI Interface Signals" page
Video Processor Module
Video Processor provides high resolution graphics CRT, TFT/DSTN interface. following subsections provide summary Video Processor interfaces with other modules SC1200/SC1201 processor. detailed information about Video Processor, Section page 331.
GeodeSC1200/SC1201 Processor Data Book
Architecture Overview
Revision
USB: Section 6.2.4 "Universal Serial Bus" page 167. function uses signal AD29 IDSEL configuration. LPC: Section 3.4.9 "Low Count (LPC) Interface Signals" page Sub-ISA: Section 3.4.8 "Sub-ISA Interface Signals" page Section 6.2.5 "Sub-ISA Interface" page 167, Section "Pin Multiplexing, Interrupt Selection, Base Address Registers" page GPIO: Section 3.4.17 "GPIO Interface Signals" page More detailed information about each these interfaces provided Section "Module Architecture" page 162. Super/IO Block Interfaces: Section "Pin Multiplexing, Interrupt Selection, Base Address Registers" page Section 3.4.6 "ACCESS.bus Interface Signals" page Section 3.4.14 "Fast Infrared (IR) Port Interface Signals" page Section 3.4.13 "Parallel Port Interface Signals" page Core Logic module interface module consists seven miscellaneous connections, interface signals, plus display controller connections. Note that PC/AT legacy signals NMI, WM_RST, A20M virtual functions executed (System Management Mode) BIOS. PSERIAL one-way serial from Core Logic module used communicate powermanagement states VSYNC information emulation. IRQ13 input from processor indicating that floating point error detected that INTR should asserted. INTR level output from integrated 8259A PICs asserted unmasked interrupt request (IRQn) sampled active. SMI# level-sensitive interrupt that configured assert number different system events. After SMI# assertion, entered program execution begins base address space. Once asserted, SMI# remains active until source cleared. SUSP# SUSPA# handshake signals implementing Clock Stop clock throttling. CPU_RST resets asserted approximately after negation POR#. interface signals.
SuperI/O Module
SuperI/O (SIO) module PC98 ACPI compliant that offers single-cell solution most commonly used peripherals. module incorporates: Serial Ports, Infrared Communication Port that supports FIR, MIR, HP-SIR, Sharp-IR, Consumer Electronics-IR, full IEEE 1284 Parallel Port, ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), Real-Time Clock (RTC) that provides timekeeping.
Clock, Timers, Reset Logic
addition four main modules (i.e., GX1, Core Logic, Video Processor SIO) that make SC1200/ SC1201 processor, following blocks logic have also been integrated: Clock Generators described Section "Clock Generators PLLs" page 103. Configuration Registers described Section "Pin Multiplexing, Interrupt Selection, Base Address Registers" page WATCHDOG timer described Section "WATCHDOG" page High-Resolution timer described Section "High-Resolution Timer" page 101.
2.5.1
Reset Logic
This section provides description reset flow SC1200/SC1201 processor. 2.5.1.1 Power-On Reset Power-on reset (POR) triggered assertion POR# signal. Upon power-on reset, following things happen: Strap balls sampled. PLL4, PLL5, PLL6 reset, disabling their output. When POR# signal negated, clocks lock then each outputs clock. PLL6 last clock generator output clock. Section "Clock Generators PLLs" page 103. Certain WATCHDOG High-Resolution Timer register bits cleared. 2.5.1.2 System Reset System reset causes signal PCIRST# issued, thus triggering reset agents. system reset triggered following events: Power-on, indicated POR# signal assertion. WATCHDOG reset event (see Section 4.3.2 "WATCHDOG Registers" page 100). Software initiated system reset.
GeodeSC1200/SC1201 Processor Data Book
Revision
Architecture Overview
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
3.0Signal Definitions
This section defines signals describes external interface SC1200/SC1201 processor. Figure shows signals organized their functional groups. Where signals multiplexed, default signal name listed first separated plus sign (+). slash signal name means that function always enabled available (i.e., cycle multiplexed).
System Interface
POR# X32I X32O X27I X27O PCIRST# BOOT16+ROMCS# LPC_ROM+PCICLK1 TFT_PRSNT+SDATA_OUT FPCI_MON+PCICLK0 DID0+GNT0#, DID1+GNT1# MD[63:0] MA[12:0] BA[1:0] CS[1:0]# RASA# CASA# WEA# DQM[7:0] CKEA SDCLK[3:0] SDCLK_IN SDCLK_OUT
CVBS+Cr+TVB SVY+Cb+TVR+CVBS SVC+Cr+Cb+TVB+TVR CVBS+Y+TVG TVCOMP TVRSET TVREF TVIOM
Interface
Straps
HSYNC VSYNC VREF SETRES RED, GREEN, BLUE IDE_ADDR2+TFTD4 IDE_ADDR1+TFTD2 IDE_ADDR0+TFTD3 IDE_DATA15+TFTD7 IDE_DATA14+TFTD17 IDE_DATA13+TFTD15 IDE_DATA12+TFTD13 IDE_DATA11+GPIO41 IDE_DATA10+DDC_SCL IDE_DATA9+DDC_SDA IDE_DATA8+GPIO40 IDE_DATA7+INTD# IDE_DATA6+IRQ9 IDE_DATA5+CLK27M IDE_DATA4+FP_VDD_ON IDE_DATA3+TFTD12 IDE_DATA2+TFTD14 IDE_DATA1+TFTD16 IDE_DATA0+TFTD6 IDE_IOR0#+TFTD10 IDE_IOW0#+TFTD9 IDE_CS0#+TFTD5 IDE_CS1#+TFTDE IDE_IORDY0+TFTD11 IDE_DREQ0+TFTD8 IDE_DACK0#+TFTD0 IDE_RST#+TFTDCK IRQ14+TFTD1
Interface
Memory Interface
GeodeSC1200/SC1201 Processor
ACCESS.bus Interface
AB1C+GPIO20+DOCCS# AB1D+GPIO1+IOCS1# GPIO12+AB2C GPIO13+AB2D ACK#+TFTDE+VOPCK AFD#/DSTRB#+TFTD2+VOPD1 BUSY/WAIT#+TFTD3+VOPD2 ERR#+TFTD4+VOPD3 INIT#+TFTD5+VOPD4 PD7+TFTD13 PD6+TFTD1+VOPD0 PD[5:0]+TFTD[11:6]+VOPD[7:5] PE+TFTD14 SLCT+TFTD15 SLIN#/ASTRB#+TFTD16 STB#/WRITE#+TFTD17 VPD[7:0] VPCKIN
IDE/TFT Interface
Parallel Port/ TFT/VOP Interface
Video Port Interface
Note:
Straps default signal, shown with system signals reader convenience. However, also listed figure with appropriate functional group.
Figure 3-1. Signal Groups
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Interface
POWER_EN OVER_CUR# DPOS_PORT1 DNEG_PORT1 DPOS_PORT2 DNEG_PORT2 DPOS_PORT3 DNEG_PORT3
Serial Ports (UARTs)/IDE Interface
Port Interface
AC97 Audio Interface
Power Management Interface
JTAG Interface
PCICLK0+FPCI_MON PCICLK1+LPC_ROM PCICLK INTA#, INTB# FRAME# GeodeLOCK# SC1200/SC1201 PERR# SERR# Processor REQ[1:0]# GNT0#+DID0 SIN1 GNT1#+DID1 SIN2+SDTEST3 A[23:0]/AD[23:0] SOUT1+CLKSEL1 D[7:0]/AD[31:24] SOUT2+CLKSEL2 D[11:8]/C/BE[3:0]# GPIO7+RTS2#+IDE_DACK1#+SDTEST0 D12/PAR GPIO8+CTS2#+IDE_DREQ1+SDTEST4 D13/TRDY# GPIO18+DTR1#/BOUT1 D14/IRDY# D15/STOP# GPIO11+RI2#+IRQ15 BHE#/DEVSEL# GPIO9+DCD2#+IDE_IOW1#+SDTEST2 GPIO17+TFTDCK+IOCS0# GPIO10+DSR2#+IDE_IORDY1+SDTEST1 GPIO1+IOCS1+TFTD12 ROMCS#/BOOT16 GPIO20+DOCCS#+TFTD0 IRRX1+SIN3 RD#+CLKSEL0 IRTX+SOUT3 GPIO14+DOCR#+IOR# BIT_CLK GPIO15+DOCW#+IOW# SDATA_OUT+TFT_PRSNT GPIO0+TRDE# SDATA_IN GPIO19+INTC#+IOCHRDY SDATA_IN2 SYNC+CLKSEL3 AC97_CLK GPIO32+LAD0 AC97_RST# GPIO33+LAD1 GPIO16+PC_BEEP GPIO34+LAD2 GPIO35+LAD3 GPIO36+LDRQ# CLK32 GPIO37+LFRAME# GPWIO[2:0] GPIO38+IRRX2+LPCPD LED# GPIO39+SERIRQ ONCTL# PWRBTN# PWRCNT[1:2] TEST1+PLL6B TEST0+PLL2B THRM# TEST3+GXCLK+FP_VDD_ON TEST2+PLL5B GTEST TDP, TRST#
Sub-ISA/PCI Interface
GPIO/LPC Interface
Test Measurement Interface
Figure 3-1.
remaining subsections this chapter describe:
Signal Groups (Continued)
Section "Multiplexing Configuration": Lists multiplexing options their configurations. Section "Signal Descriptions": Detailed descriptions each signal according functional group.
Section "Ball Assignments": Provides ball assignment diagram tables listing signals sorted according ball number alphabetically signal name. Section "Strap Options": Several balls read power-up that state SC1200/SC1201 processor. This section provides details regarding those balls.
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Ball Assignments
Table 3-1. Signal Definitions Legend
Mnemonic AVSS AVCC Definition Analog Ground ball: Analog Power ball: Analog General Configuration Block registers. Refer Section "General Configuration Block" page Location General Configuration Block cannot determined software. GeodeSC1200/SC1201 Processor Specification Update document. MCR[x] Input ball Bidirectional ball Miscellaneous Configuration Register register, located GCB. Refer Section "Configuration Block Addresses" page further details. Output ball Open-drain Pull-down Multiplexing Register register, located GCB, used configure balls with multiple functions. Refer Section "Configuration Block Addresses" page further details. Pull-up TRI-STATE Power ball: 1.2V Power ball: 3.3V Ground ball symbol signal name indicates that active asserted state occurs when signal voltage level. Otherwise, signal asserted when high voltage level. signal name indicates both functions always enabled (i.e., cycle multiplexed). signal name indicates function available ball, that either strapping options register programming required select desired function.
SC1200/SC1201 processor highly configurable illustrated Figure page Strap options register programming used various modes operation specific signals specific balls. This section describes which signals available which balls provides configuration information: Figure page Figure page Illustrations EBGA TEPBGA ball assignments. Table page Table page Lists signals according ball number. Power Rail, Signal Type, Buffer Type and, where relevant, Pull-Up PullDown resistors indicated each ball this table. multiplexed balls, necessary configuration each signal listed well. Table page Table page Quick reference signal list sorted alphabetically listing signal names ball numbers. tables this chapter several common abbreviations. Table lists mnemonics their meanings Notes: each GPIO signal, there optional pull-up resistor relevant ball. After system reset, pull-up present. This pull-up resistor disabled registers Core Logic module. configuration without regard selected ball function (except GPIO12, GPIO13, GPIO16). Alternate functions GPIO12, GPIO13, GPIO16 control pull-up resistors. more information, Section 6.4.1 "Bridge, GPIO, Registers Function page 210. Configuration settings listed this table with regard Multiplexing Register (PMR). Section "Pin Multiplexing, Interrupt Selection, Base Address Registers" page detailed description this register.
PMR[x]
VCORE
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
IDAT13 IDAT10 IDAT8 IRST# IDAT5 IDAT1 IORDY0 IAD0 ICS0# GP18
AD29 AD26 AD22 AD19 AD16 CBE3# SERR# CBE1# AD14 AD12 CBE0# AD31 AD27 DVSL#
X27I
VPLL3 LED#
TRDY# PERR# AD15
IDAT15 IDAT12
IDAT7 IDAT4 IDAT0
SOUT1 PWRE TEST2 X32I
RQ0# AD30
AD28 AD24 AD21 AD17 IRDY# LOCK#
AD13 AD11 AD10
ICS1# IAD2 IDAT14 IDAT11 IDAT9 IIOR0# IDAT6 IDAT3 IDRQ0 IDCK0# IAD1 OVCR# TEST1 VCORE VCORE
PRST# GNT1# PCK0 GNT0# AD25 AD20 AD18 CBE2# STP#
VCORE VCORE VCORE VCORE
IDAT2 IIOW0# IRQ14 SIN1 X27O TEST0 X32O VBAT
FRM# PCLK REQ1# PCK1
AVSSP3 PBTN# OCTL# GPW0 THRM# GPW1 GPW2 PCNT1 PCNT2
IOR#
AD23
IOW# RMCS# GP20 GP19
TRDE#
VSBL CK32 GP11 SDIN2 IRRX1 POR# DQM0
HSYN VSYN IRTX GP17 VSSCRT VCCCRT AVSSCRT AVCCCRT VCORE VCCCRT GREEN AVCCCRT BLUE AVSSCRT VCORE VREF STRS AVSSCRT VPLL2 AVSSP2 VCORE SLCT
VCORE
VCORE WEA# CASA# RASA#
ACK# VCORE
SLIN#
VCORE INIT#
GeodeSC1200/SC1201 Processor
CS0#
VCORE MA10
DQM4 VCORE VCORE MD33 MD32
MD36 MD35 MD34
VCORE MD39 MD38 MD37 MD46 MD47 MD45
ERR# VCORE
VCORE MD44
STB# AFD# CVBS
MD41 MD42 MD43
TVIOM AVCCTV AVSSTV TVREF CVBS TVCOMP TVRST INTB# INTA# D+P3 D-P3 AVCCUSB SIN2 VPCKI VPD4 VPD0 VCORE VCORE VCORE SDCK1 VCORE VCORE VCORE
CKEA SDCK0 DQM5 MD40 DQM1
(Top View)
MD14 MD15 MA11
AVSSUSB D-P2 D-P1 D+P2 D+P1 GP10
MD13
MD28 MD55 MD51 MD48 MD23 SDCKO MA12 MD11 MD10 SDCKI MD12
VPD7 VPD6 VPD2 GP38 GP35 GP32 GP12 AB1C ACCK ACRT# SDCK3 MD56 MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6 MD22 MD19
SOUT2 TRST#
VPD1 GP37 GP34
SDATO SDATI
MD59 MD62
MD26 MD30 MD53
MD21 MD18 CS1#
GTST VPD5 VPD3 GP39 GP36 GP33 GP13 AB1D SYNC BITCK GP16 GXCK MD57 MD60 MD63 SDCK2 MD24 MD27 MD31 MD52 MD49 DQM2 MD20 MD17 MD16
Note:
Signal names have been abbreviated this figure space constraints. Ball Ball Strap Option Ball Multiplexed Ball
Figure 3-2. 432-EBGA Ball Assignment Diagram
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2. 432-EBGA Ball Assignment Sorted Ball Number
Ball Signal Name AD29 AD26 AD22 AD19 AD16 C/BE3# SERR# C/BE1# AD14 AD12 C/BE0# Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI -A26 Cycle Multiplexed Cycle Multiplexed TFTD16 IDE_IORDY0 TFTD11 IDE_ADDR0 TFTD3 IDE_CS0# TFTD5 Cycle Multiplexed DTR1#/BOUT1 Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed AD27 Cycle Multiplexed DEVSEL# BHE# Cycle Multiplexed (PU22.5) X27I AD31 GPIO18 (PU22.5) (PU22.5) Cycle Multiplexed CLK27M IDE_DATA1 Cycle Multiplexed IDE_RST# TFTDCK IDE_DATA5 Cycle Multiplexed GPIO40 Cycle Multiplexed
Ball
Signal Name
Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI OPCI INTS1, TS1/4 O1/4 INTS1, TS1/4 INTS1, TS1/4 INTS1, O1/4 O1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1 O1/4 O1/4 O1/4 O1/4 O1/4 INTS, O8/8 O8/8 WIRE -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -VIO Cycle Multiplexed Cycle Multiplexed -VIO PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[16] PMR[16] -Cycle Multiplexed Cycle Multiplexed
-VIO
-Cycle Multiplexed
IDE_DATA13 TFTD15 IDE_DATA10 DDC_SCL
IDE_DATA8
INPCI, (PU22.5) ODPCI (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI
Cycle Multiplexed
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-2.
Ball Signal Name TRDY# PERR# AD15 IDE_DATA15 TFTD7 IDE_DATA12 TFTD13 IDE_DATA7 INTD# IDE_DATA4 FP_VDD_ON IDE_DATA0 TFTD6 SOUT1 CLKSEL1 POWER_EN TEST2 PLL5B REQ0#
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name AD30 -Cycle Multiplexed -VIO -Cycle Multiplexed Cycle Multiplexed -VIO -PMR[24] PMR[24] PMR[24] PMR[24] -VIO -C11 AD13 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -VIO -Strap (SeeTable page 60.) -PMR[29] PMR[29] -VIO -C18 IDE_CS1# TFTDE IDE_ADDR2 TFTD4 IDE_DATA14 TFTD17 AD10 AD11 PMR[24] LOCK# AD21 AD17 IRDY# (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) AD24 AD28 Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI INPCI, OPCI -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI O1/4 O1/4 O1/4 O1/4 INTS1, TS1/4 O1/4 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed -VIO -Cycle Multiplexed Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -INPCI, OPCI OPCI INPCI, OPCI OPCI -INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -INTS1, TS1/4 INTS INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -O8/8 Cycle Multiplexed
INSTRP (PD100) O1/4 O2/5 INT, TS2/5
INPCI (PU22.5)
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2.
Ball Signal Name IDE_DATA11 GPIO41 C202 IDE_DATA9 DDC_SDA IDE_IOR0# TFTD10 IDE_DATA6 IRQ9 IDE_DATA3 TFTD12 IDE_DREQ0 TFTD8 IDE_DACK0# TFTD0 IDE_ADDR1 TFTD2 OVER_CUR# TEST1 PLL6B X32I VPLL3 PCIRST# GNT1# DID1 PCICLK0 FPCI_MON GNT0# DID0 AD25 AD20 AD18
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name C/BE2# STOP# PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[29] PMR[29] TFTD14 -VBAT -VIO -Strap (See Table page 60.) -Strap (See Table page 60.) -Strap (See Table page 60.) Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed E304, AVSSPLL3 PWRBTN# ONCTL# PCICLK1 LPC_ROM IDE_IOW0# TFTD9 IRQ14 TFTD1 SIN1 X27O TEST0 PLL2B X32O VBAT LED# FRAME# PCICLK REQ1# (PU22.5) (PU22.5) VCORE VCORE VCORE VCORE VCORE VCORE IDE_DATA2 Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -INPCI, OPCI OPCI -INTS1, TS1/4 O1/4 O1/4 O1/4 INTS1 O1/4 INTS WIRE O2/5 INT, TS2/5 WIRE -OD14 INPCI, OPCI INPCI OPCI VBAT -VSB -VIO -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[29] PMR[29] -Strap (See Table page 60.) -VSB -VIO -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type INTS1, TS1/4 INTS1, O1/4 INTS1, TS1/4 INT, O1/4 O1/4 INTS1, TS1/4 INTS1 INTS1, TS1/4 O1/4 INTS1 O1/4 O1/4 O1/4 O1/4 O1/4 INTS O2/5 INTS, TS2/5 -WIRE -OPCI OPCI PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24]
INSTRP (PD100) OPCI
INSTRP (PD100) OPCI
INSTRP (PD100) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI
INSTRP (PD100) (PU100) -INBTN OD14
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-2.
Ball Signal Name GPWIO0 IOR# DOCR# GPIO14 CLKSEL0 AD23 F314, THRM# PWRCNT1 IOW# DOCW# GPIO15 ROMCS# BOOT16
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GPIO20 Buffer1 Power Rail Configuration (PU/PD) Type INT, (PU22.5) (PMR[23]3 PMR[7] (PMR[23]3 PMR[15] PMR[7] (PMR[23]3 PMR[7] (PMR[23]3 PMR[15] PMR[7] PMR[23]3 PMR[15] PMR[9] PMR[4] PMR[9] PMR[4] PMR[9] PMR[4] -VSB -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] F3BAR0+Memory Offset 08h[21] -PMR[6] PMR[6] (PMR[23]3 PMR[5] (PMR[23]3 PMR[15] PMR[5] (PMR[23]3 PMR[5] (PMR[23]3 PMR[15] PMR[5] PMR[23]3 PMR[15] AVCCCRT -PMR[6] PMR[6]
Buffer1 Power Rail Configuration (PU/PD) Type (PU100) (PU22.5) INTS, TS2/14 O3/5 O3/5 INTS, O3/5 -O3/5 -VIO -PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] -Strap (See Table page 60.) Cycle Multiplexed
DOCCS#
(PU22.5)
O3/5
TFTD0 GPIO19 INTC# IOCHRDY
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
O1/4 INTS, O3/5 INTS INTS1 -O2/5 INTS, O8/8 INTS INTS1 INTS O1/4 O1/4 O8/8 O8/8 INTS, O3/5
INSTRP (PD100) (PU22.5) INPCI, OPCI OPCI INTS -OD14 O3/5 -O3/5 O3/5 INTS, O3/5 O3/5 -VSB -VSB -VIO
-H28 VSBL CLK32 GPIO11 RI2# IRQ15 SDATA_IN2 HSYNC VSYNC IRTX SOUT3 GPIO17
-PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] -Strap (See Table page 60.) -PMR[12] PMR[12]
INSTRP (PD100) (PU100) (PU100) (PU22.5) INTs, TS2/14 INTS, TS2/14
GPWIO1 GPWIO2 PWRCNT2 TRDE# GPIO0
IOCS0#
(PU22.5)
O3/5
O3/5 INTS, O3/5
TFTDCK (PMR[23]3 PMR[13] (PMR[23] PMR[15] PMR[13]
GPIO1
INT, (PU22.5)
(PU22.5)
O1/4 INTS INTS INTS INT, TS2/5 INT, TS2/5 WIRE
IRRX1 SIN3
J304 J314
POR# VSSCRT VCCCRT
IOCS1#
(PU22.5)
O3/5
(PMR[23] PMR[13] (PMR[23]3 PMR[15] PMR[13] PMR[23]3 PMR[15]
TFTD12
(PU22.5)
O1/4
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2.
Ball K294 K304 K314 L294 L314 M294 Signal Name AVSSCRT AVCCCRT VCORE VCORE AVCCCRT GREEN DQM0 AVCCCRT BLUE AVSSCRT VCORE VCORE WEA# CASA# RASA# VREF SETRES AVSSCRT CS0# VPLL2 AVSSPLL2 VCORE VCORE MA10
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball -VIO -VIO -AVCCCRT
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 -INT, TS2/5 -WIRE -INT, TS2/5 -O2/5 -WIRE -O2/5 O2/5 O2/5 WIRE WIRE -O2/5 O2/5 O2/5 -O2/5
Signal Name BUSY/WAIT#
Buffer1 Power Rail Configuration (PU/PD) Type -O2/5 -VIO -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON (PU/PD under software control.) PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
TFTD3 -F_C/BE3# F_AD7 U14, DQM4 VCORE TFTD15 T44, SLCT F_C/BE2# TFTD14 F_C/BE1# VOPD2
O1/4
O1/4
O1/4
(PU22.5 PD22.5)
-INT
O1/4
-VIO -VIO -AVCCCRT -VIO AVCCCRT
O1/4
O1/4
O1/4
O2/5 O2/5 -O2/5 INT, O14/14 O1/4
AVCCCRT -VIO -VIO
TFTD13
O14/14
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-2.
Ball U34, Signal Name ACK#
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball W14, Signal Name SLIN#/ASTRB# Buffer1 Power Rail Configuration (PU/PD) Type O14/14 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Buffer1 Power (PU/PD) Type Rail Configuration PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -VIO
TFTDE
O1/4
TFTD16
O1/4
F_IRDY#
O14/14
VOPCK
O1/4
W24,
FPCICLK
O1/4
INT, O14/14 O1/4
TFTD9
U294 U314 V14,
VCORE VCORE MD33 MD32
-INT, TS2/5 -INT, TS2/5 INT, O14/14 O1/4
F_AD3
O14/14
W34,
INT, O14/14 O1/4
TFTD8 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON W294 W304 W314 Y14, VOPD7
TFTD10
O1/4
F_AD4
O14/14
F_AD2
O14/14
V24,
INT, O14/14 O1/4
VCORE VCORE MD39 MD38 MD37
-INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, O14/14 O1/4
TFTD11
F_AD5
O14/14
PMR[23]3 (PMR[27] FPCI_MON PMR[23] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO
INT, O14/14 O1/4
TFTD1
TFTD7
VOPD0
O1/4
VOPD6
O1/4
F_AD6
O14/14
F_AD1
O14/14
V294 V304 V314
MD36 MD35 MD34
-INT, TS2/5 INT, TS2/5 INT, TS2/5
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2.
Ball Y34, Signal Name INIT#
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name Buffer1 Power Rail Configuration (PU/PD) Type O14/14 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3= PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376. -VIO
Buffer1 Power (PU/PD) Type Rail Configuration O14/14 PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -INT, TS2/5 INT, O14/14 O1/4 -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
AB14, STB#/WRITE#
TFTD5
O1/4
TFTD17
O1/4
F_FRAME#
O14/14
VOPD4
O1/4
AB24, AFD#/DSTRB#
O14/14
SMI_O
O14/14
TFTD2
O1/4
Y294 Y314
MD46 MD47
-INT, TS2/5
VOPD1
O1/4
INTR_O
O14/14
AA14,
CVBS
WIRE
TFTD6
AB28 AB294 AB304 AB314
MD41 MD42 MD43 TVIOM
-INT, TS2/5 INT, TS2/5 INT, TS2/5 WIRE WIRE
VOPD5
O1/4
F_AD0
O14/14
-INT,
AA34, ERR#
AVCCTV -AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376.
TFTD4
O1/4
VOPD3
O1/4
AC28 AC29 AC30 AC31
AVCCTV AVSSTV CKEA SDCLK0 DQM5 MD40 CVBS
-O2/5 O2/5 O2/5 INT, TS2/5 WIRE
-VIO
F_C/BE0#
O1/4
AA28 AA29 AA30 AA314
VCORE VCORE MD44 MD45
-INT, TS2/5 -INT, TS2/5
-VIO -VIO
AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376. AVCCTV -AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376.
TVREF CVBS
WIRE WIRE
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-2.
Ball AD28 AD29 AD30 AD31 AE44 AE28 AE29 AE30 AE31 AF34 AF28
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GPIO6 DTR2#/BOUT2 IDE_IOR1# SDTEST5 GPIO7 RTS2# IDE_DACK1# -VIO -AVCCUSB -VIO -VIO -AVCCUSB AVCCUSB
Signal Name TVCOMP TVRSET INTA# DPOS_PORT3 INTB# DNEG_PORT3 AVCCUSB MD14 MD15 DQM1 AVSSUSB DNEG_PORT2 DNEG_PORT1 GPIO9 DCD2# IDE_IOW1# SDTEST2
Buffer1 Power (PU/PD) Type Rail Configuration (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) WIRE O2/5 O2/5 O2/5 O2/5 WIRE -INPCI INUSB, OUSB O2/5 O2/5 -O2/5 INPCI -INUSB, OUSB -INT, TS2/5 INT, TS2/5 -O2/5 -INUSB, OUSB INUSB, OUSB INTS, O1/4 INTS O1/4 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INUSB, OUSB INUSB, OUSB AVCCUSB
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTS, O1/4 O1/4 O1/4 O2/5 INTS, O1/4 O1/4 O1/4 O2/5 Diode OPCI -O2/5 -INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 -VIO -VIO -VIO PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8]
AVCCTV -VIO
AVCCTV -VIO AVCCUSB -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] -AH274 -AH28 -AH29 AH304 AH314 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH234 AH244 AH254 AH264
SDTEST0 VPCKIN VPD4 VPD0 VCORE VCORE VCORE SDCLK1 VCORE VCORE VCORE MD28 MD55 MD51 MD48 MD23 SDCLK_OUT MA12 MD11 MD10
AF294 AF30 AF31 AG24 AG34
AG28 AG294 AG304 AG314 AH14
MA11 MD13 DPOS_PORT2 DPOS_PORT1
AVCCUSB
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2.
Ball Signal Name GPIO10 DSR2# IDE_IORDY1 SDTEST1 GPIO8 CTS2# IDE_DREQ1 SDTEST4 SIN2 SDTEST3 VPD7 VPD6 VPD2 GPIO38/IRRX2
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball AJ13 Signal Name AB1C Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) INAB, PMR[23]3 (PMR[23] PMR[15] PMR[23]3 PMR[15] PMR[7] PMR[23]3 PMR[15] PMR[7] PMR[25] FPCI_MON FPCI_MON -VIO -VIO -Strap (SeeTable page 60.) -VIO -PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTS, O8/8 INTS INTS1 O2/5 INTS, O8/8 INTS INTS1 O2/5 -INTS O2/5 INPCI INPCI, OPCI -VIO PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] -PMR[28] PMR[28] -PMR[14]6 PMR[22]6 IRRX2 input connected input path GPIO38. There logic required enable IRRX2, just simple connection. Hence, when GPIO38 selected function, IRRX2 also selected. PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14] PMR[22]6 PMR[14] PMR[22]6 PMR[19] PMR[19]
GPIO20
INT, (PU22.5) O3/5
DOCCS#
AJ14 AJ15
AC97_CLK AC97_RST# F_STOP#
O2/5 O2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 INT, TS2/5 -INT INT, TS2/5 -O8/8
AJ16 AJ17
SDCLK3 MD56 MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6
AJ184 AJ194 AJ20 AJ21 AJ224 AJ234 AJ244 AJ254 AJ26 AJ27
MD22 MD19 SDCLK_IN MD12 SOUT2 CLKSEL2
AJ284 AJ29 AJ30 AJ314
LPCPD# AJ10 GPIO35 LAD3 AJ11 GPIO32 LAD0 AJ12 GPIO12 AB2C
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB,
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) INPCI INPCI -INT INPCI, OPCI OPCI
TRST# VPD1 GPIO37 LFRAME#
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-2.
Ball AK10 Signal Name GPIO34 LAD2 AK11 AK12 AK13 SDATA_OUT TFT_PRSNT AK14 SDATA_IN F_GNT0# AK15 AK16 AK17 AK184 AK194 AK20 AK21 AK224 AK234 AK244 AK25 AK26 AK274 AK284 AK29 AK30 AK31 MD59 MD62 MD26 MD30 MD53 MD21 MD18 CS1# GTEST VPD5 VPD3 GPIO39 SERIRQ GPIO36 LDRQ#
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball AL10 Signal Name GPIO33 LAD1 AL11 GPIO13 AB2D AL12 AB1D Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB, INAB, PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[19] PMR[19] PMR[23]3 (PMR[23] PMR[15] PMR[23]3 PMR[15] PMR[13] PMR[23]3 PMR[15] PMR[13] -Strap (See Table page 60.) FPCI_MON FPCI_MON PMR[0] FPCI_MON PMR[0] FPCI_MON FPCI_MON (PMR[29] PMR[23]3 (PMR[23]3 PMR[15] PMR[23]3 PMR[15] PMR[29] PMR[23]3
Buffer1 Power (PU/PD) Type Rail Configuration (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI -OAC97 -VIO PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 -Strap (See Table page 60.) FPCI_MON FPCI_MON -VIO -VIO -VIO -VIO
INSTRP (PD100) (PU22.5) (PD22.5) (PU22.5) (PU22.5) O2/5 -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 -WIRE INPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI
GPIO1
INT, (PU22.5) O3/5
IOCS1#
AL13 -PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 AL244 AL254 AL26 AL27
SYNC CLKSEL3
OAC97
INSTRP (PD100) O1/4
AL14
BIT_CLK F_TRDY#
AL15
GPIO16 PC_BEEP F_DEVSEL#
INT, (PU22.5) O2/5 O2/5 O2/5
AL16
GXCLK
FP_VDD_ON TEST3 AL174 AL184 AL194 AL20 AL21
O1/4 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5
MD57 MD60 MD63 SDCLK2 MD24 MD27 MD31 MD52 MD49 DQM2 MD20
AL224 AL234
PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-2.
Ball AL28
432-EBGA Ball Assignment Sorted Ball Number (Continued)
TFT_PRSNT strap determines power-on reset (POR) state PMR[23]. back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). LPC_ROM strap determines power-on reset (POR) state PMR[14] PMR[22].
Signal Name MD17 MD16
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 INT, TS2/5 -VIO
AL294 AL30 AL31
Buffer Type definitions, refer Table 9-10 page 391. need tolerant protection system level (DDC_SCL, DDC_SDA).
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-3. 432-EBGA Ball Assignment Sorted Alphabetically Signal Name
Signal Name AB1C AB1D AB2C AB2D AC97_CLK AC97_RST# ACK# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Ball AJ13 AL12 AJ12 AL11 AJ14 AJ15 Signal Name AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AFD#/DSTRB# AVCCCRT AVCCTV AVCCUSB AVSSCRT AVSSPLL2 AVSSPLL3 AVSSTV AVSSUSB BHE# BIT_CLK BLUE BOOT16 BUSY/WAIT# C/BE0# C/BE1# C/BE2# C/BE3# CASA# CKEA CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 CS0# CS1# CTS2# CVBS Ball AL14 AC2, AC28 AL13 AC2, AK29 AB3, AD1, Signal Name DCD2# DDC_SCL DDC_SDA DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# DOCR# DOCW# DPOS_PORT1 DPOS_PORT2 DPOS_PORT3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DSR2# DTR1#/BOUT1 DTR2#/BOUT2 ERR# F_AD0 F_AD1 F_AD2 F_AD3 F_AD4 F_AD5 Ball AJ13 AF31 AL26 AJ21 AC30 AJ26 AJ20
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-3.
Signal Name F_AD6 F_AD7 F_C/BE0# F_C/BE1# F_C/BE2# F_C/BE3# F_DEVSEL# F_FRAME# F_GNT0# F_IRDY# F_STOP# F_TRDY# FP_VDD_ON FPCI_MON FPCICLK FRAME# GNT0# GNT1# GPIO0 GPIO1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO20 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AL15 AK14 AJ15 AL14 B23, AL16 AL12 AJ12 AL11 AL15 AJ13 AJ11 AL10 AK10 AJ10 Signal Name GREEN GTEST GXCLK HSYNC IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0 IDE_DREQ1 IDE_IOR0# IDE_IOR1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_RST# INIT# INTA# INTB# INTC# INTD# INTR_O IOCHRDY IOCS0# IOCS1# IOR# IOW# IRDY# IRQ9 Ball AL16 AL12 Signal Name IRQ14 IRQ15 IRRX1 IRTX LAD0 LAD1 LAD2 LAD3 LDRQ# LED# LFRAME# LOCK# LPC_ROM LPCPD# MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 Ball AJ11 AL10 AK10 AJ10 AE28 AE29 AE31 AD28 AD29 AD30 AD31 AG28 AH29 AG30 AG29 AH31 AH30 AJ31 AG31 AF28 AF29 AL29 AL28 AK28 AJ28 AL27 AK27
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-3.
Signal Name MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 ONCTL# OVER_CUR# PC_BEEP PCICLK PCICLK0 PCICLK1
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AJ27 AH27 AL21 AJ22 AK22 AL22 AH23 AJ23 AK23 AL23 AC31 AB29 AB30 AB31 AA29 AA31 AH26 AL25 AJ25 AH25 AL24 AK24 AJ24 AH24 AJ17 AL17 AJ18 AK18 AL18 AJ19 AK19 AL19 AL15 Signal Name PCIRST# PERR# PLL2B PLL5B PLL6B POR# POWER_EN PWRBTN# PWRCNT1 PWRCNT2 RASA# REQ0# REQ1# RI2# ROMCS# RTS2# SDATA_IN SDATA_IN2 SDATA_OUT SDCLK_IN SDCLK_OUT SDCLK0 SDCLK1 SDCLK2 SDCLK3 SDTEST0 SDTEST1 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SETRES SIN1 SIN2 SIN3 SLCT Ball AK14 AK13 AJ30 AH28 AC29 AH16 AL20 AJ16 Signal Name SLIN#/ASTRB# SMI_O SOUT1 SOUT2 SOUT3 STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT TFTD0 TFTD1 TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD9 TFTD10 TFTD11 TFTD12 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 TFTDCK TFTDE THRM# TRDE# TRDY# TRST# TVCOMP TVIOM Ball AL13 AL16 AK13 C25, D25, C26, A26, C17, A27, B24, B18, C24, D24, C21, A25, C23, B19, D23, A19, A24, C18, A22, C16, AC2,
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-3.
Signal Name TVREF TVRSET VBAT VCCCRT VCORE (Total
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AC2, D11, D13, D15, D17, D19, D21, L28, N28, R28, T30, U28, W28, AA4, AA28, AH11, AH13, AH15, AH17, AH19, AH21 A30, B11, B16, B20, B25, B31, C29, G30, M30, Y30, AE2, AE30, AJ3, AJ29, AK1, AK6, AK11, AK16, AK20, AK25, AK31, AL2, AL30 Signal Name VOPD2 VOPD3 VOPD4 VOPD5 VOPD6 VOPD7 VPCKIN VPD0 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VPLL2 VPLL3 VREF VSBL Ball VSSCRT VSYNC WEA# X27I X27O X32I X32O Signal Name (Total Ball A31, B12, B15, B17, B21, B26, B30, D10, D12, D14, D18, D20, D22, F30, K28, L30, M28, P28, R30, U30, V28, Y28, AA2, AA30, AB4, AB28, AF2, AF30, AH10, AH12, AH14, AH18, AH20, AH22, AK2, AK7, AK12, AK15, AK17, AK21, AK26, AK30, AL1, AL31
(Total
VOPCK VOPD0 VOPD1
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
VPLL2 STB# CVBS TVRST D+P3 D-P3 D+P1 D-P1 TVIOM AVSSTV TVCMP D+P2 D-P2 GP10 TVREF INTB# AVSSUSB
AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC AVCCCT GREEN BLUE
AD29 AD28 REQ0# AD23
VSNC
AVSSCT STRES
BUSY ACK#
SLIN# INIT#
AD26 AD24
AD25 GNT0# GNT1# RMCS# GP19 FRM# IOR#
IRTX VSSCT AVCCCT AVSSCTAVSSCT AVSSP2 SLCT AVCCCT VREF
AD21 AD22 AD20 AD27 AD31 PCK1 AD16 AD19 AD18 DVSL# TRDY# IRDY# CBE2# AD17 STOP#
TRDE# VCCCT
ERR# AFD# AVCCTV CVBS
INTA# AVCCUSB SOUT SIN2 TRST#
GTST VPCKI VPD7
SRR# PRR# LOCK# CBE3# AD13 CBE1# AD15 AD11 AD14
VPD6 VPD5 VPD4 VPD3
GeodeVCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE
VPD2 VPD1 VPD0 GP39 GP38 GP37
CBE0#
AD10 AD12
GP36 GP35 GP34 GP33 GP32 GP13
GP12 AB1D AB1C
ICS1#
VCORE
VCORE SYNC ACCK
VCORE VCORE VCORE VCORE IAD2 VCORE
VCORE VCORE VCORE VCORE VCORE ACRST# BITCK SDCK3 GXCK GP16 MD57 SDCK1
IDAT15 IDAT14 IDAT13 IDAT12 IDAT11
VCORE VCORE VCORE VCORE
VCORE VCORE VCORE VCORE
IDAT10 IDAT9 IDAT8 IIOR0# IRST# IDAT7 IDAT6 IDAT5 IDAT4 IDAT3
IDAT1 IDAT2 IDAT0 IDRQ0 IIORY0 IIOW0# IAD0 IDACK0# IAD1
SC1200/SC1201 Processor
(Top View)
CK32 POR# GP11 WEA# MD34 MD37 MD41 DQM1 MD13 CASA# RASA# MA10 MD32 MD33 MD36 MD47 MD45 MD42 SDCK0 MD35 MD46 MD38 MD39 MD43 DQM5
MD58 MD59 MD60 MD56 SDCK2 MD61 MD62 MD63 MD24 DQM7
MD25 MD26 MD27 DQM3 MD52 MD29 MD30 MD31 MD28
IRQ14 ICS0# SOUT1 OVRCUR# GP18 SIN1 X27I TEST1 PBTN# GPW0
MD50 MD49 MD54 MD53 MD21 DQM6 DQM2 MD55 MA11 CS1# MD18 MD48 MD20 MD51 MD11 SDCKI MD19 MD22 MD17
PWRE X27O TEST0 TEST2 X32I
X32O VPLL3 ONCT# GPW2
AVSSP3 THRM#GPW1 PCNT1 IRRX1 VBAT LED# VSBL PCNT2 SDATI2
MD15
MD14 MD12 SDCKO MD16
DQM0 CS0#
DQM4
MD44 MD40 CKEA
MD10 MA12 MD23
Note:
Signal names have been abbreviated this figure space constraints. Ball Ball Strap Option Ball Multiplexed Ball
Figure 3-3. 481-TEPBGA Ball Assignment Diagram
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4. 481-TEPBGA Ball Assignment Sorted Ball Number
Ball Signal Name AD30 PCICLK0 FPCI_MON REQ1# PCIRST# PCICLK IOW# DOCW# GPIO15 GPIO20 Buffer1 Power Rail Configuration (PU/PD) Type -INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 60.) -PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] (PMR[23] PMR[7] (PMR[23]3 PMR[15] PMR[7] (PMR[23]3 PMR[7] (PMR[23]3 PMR[15] PMR[7] PMR[23]3 PMR[15] (PMR[23]3 PMR[5] (PMR[23]3 PMR[15] PMR[5] (PMR[23]3 PMR[5] (PMR[23]3 PMR[15] PMR[5] PMR[23]3 PMR[15] -AVCCCRT
Ball
Signal Name
Buffer1 Power Rail Configuration (PU/PD) Type INT, O14/14 O1/4 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376. AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376. AVCCTV -AVCCUSB AVCCUSB
-VIO
-Cycle Multiplexed
A186,
TFTD13
F_AD7
O14/14
INSTRP (PD100) (PU22.5) (PU22.5) INPCI OPCI O3/5 O3/5 INTS, O3/5
-INT, O14/14 O1/4
TFTD1
VOPD0
O1/4
F_AD6
O14/14
INT, (PU22.5)
A216,
INT, O14/14 O1/4
DOCCS#
(PU22.5)
O3/5
TFTD7
VOPD6
O1/4
TFTD0 GPIO17
(PU22.5) (PU22.5)
O1/4 INTS, O3/5
F_AD1
O14/14
A226,
STB#/WRITE#
O14/14
IOCS0#
(PU22.5)
O3/5
TFTD17
O1/4
TFTDCK HSYNC AVCCCRT GREEN BLUE VPLL2
(PU22.5)
O1/4 O1/4 -WIRE WIRE
F_FRAME#
O14/14
-A25
CVBS
WIRE
AVCCCRT
CVBS TVRSET DPOS_PORT3 DNEG_PORT3
WIRE
WIRE INUSB, OUSB INUSB, OUSB
A276
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-4.
Ball A286 A296 Signal Name DPOS_PORT1 DNEG_PORT1 AD29 AD28 REQ0# AD23 CLKSEL0 B176, VSYNC AVSSCRT SETRES BUSY/WAIT#
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball B186, Signal Name ACK# Buffer1 Power Rail Configuration (PU/PD) Type PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Buffer1 Power Rail Configuration (PU/PD) Type INUSB, OUSB INUSB, OUSB -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -Cycle Multiplexed Cycle Multiplexed AVCCUSB AVCCUSB -VIO
TFTDE -Cycle Multiplexed FPCICLK VOPCK
O1/4
O1/4
O1/4
SLIN#/ASTRB#
-O14/14
TFTD16
O1/4
INPCI (PU22.5) INPCI, OPCI OPCI -O3/5
F_IRDY#
O14/14
-VIO
-Strap (See Table page 60.)
B216,2
INIT#
O14/14
INSTRP (PD100) O3/5 -O1/4 WIRE -WIRE -INT -VIO AVCCCRT
TFTD5
O1/4
VOPD4
O1/4
SMI_O -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON B276 B286 TVIOM AVSSTV TVCOMP DPOS_PORT2 DNEG_PORT2 GPIO10 DSR2# IDE_IORDY1 SDTEST1
O14/14
-AVCCCRT
(PU22.5) (PU22.5) (PU22.5) (PU22.5)
-WIRE -WIRE INUSB, OUSB INUSB, OUSB INTS, O8/8 INTS INTS1 O2/5
AVCCTV
-VIO
AVCCTV -AVCCUSB AVCCUSB -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
TFTD3
O1/4
VOPD2
O1/4
F_C/BE1#
O1/4
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4.
Ball Signal Name AD26 AD24 AD25 GNT0# DID0 GNT1# DID1 ROMCS# BOOT16 GPIO19 INTC# IOCHRDY IRTX SOUT3 C176,2 VSSCRT AVCCCRT AVSSCRT AVSSCRT AVSSPLL2 SLCT
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball C196,2 Signal Name Buffer1 Power (PU/PD) Type Rail Configuration INT, O14/14 O1/4 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 60.) -Strap (See Table page 60.) -VIO -Strap (See Table page 60.) PMR[9] PMR[4] PMR[9] PMR[4] PMR[9] PMR[4] -VIO -PMR[6] PMR[6] -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Cycle Multiplexed
TFTD11 Cycle Multiplexed F_AD5
O14/14
-VIO
-Cycle Multiplexed
C206,2
INT, O14/14 O1/4
TFTD9
F_AD3
O14/14
INSTRP (PD100) OPCI
C216,2
INT, O14/14 O1/4
INSTRP (PD100) -O3/5
TFTD6
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) INTS, O3/5 INTS INTS1 -O8/8 O8/8 -INT
VOPD5
O1/4
F_AD0
O14/14
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
-WIRE
AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376.
TVREF INTB# AVSSUSB GPIO9 DCD2# IDE_IOW1# SDTEST2
WIRE -INPCI -INTS, O1/4 INTS O1/4 O2/5
AVCCTV -VIO -VIO -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
TFTD15
O1/4
F_C/BE3#
O1/4
INT, O14/14 O1/4
TFTD10
F_AD4
O14/14
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-4.
Ball Signal Name GPIO7 RTS2# IDE_DACK1# SDTEST0 GPIO8 CTS2# IDE_DREQ1 SDTEST4 AD21 AD22 AD20 AD27 AD31 PCICLK1 LPC_ROM FRAME# IOR# DOCR# GPIO14 GPIO1
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name TRDE# GPIO0 VCCCRT AVCCCRT VREF Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5 PD22.5) O3/5 INTS, O3/5 -WIRE -AVCCCRT PMR[12] PMR[12] -PMR[23]3 (PMR[27] FPCI_MON (PU/PD under software control.) PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3 PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTS, O1/4 O1/4 O1/4 O2/5 INTS, O8/8 INTS INTS1 O2/5 INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 60.) -VIO -PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] (PMR[23]3 PMR[13] (PMR[23]3 PMR[15] PMR[13] (PMR[23]3 PMR[13] (PMR[23]3 PMR[15] PMR[13] PMR[23]3 PMR[15] Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] Cycle Multiplexed
D176,
TFTD14
O1/4
F_C/BE2#
O1/4
-INT, O14/14 O1/4
D206,
TFTD8
VOPD7
O1/4
F_AD2
O14/14
INSTRP (PD100) (PU22.5) (PU22.5) -INPCI, OPCI O3/5 O3/5 INTS, O3/5
D216, ERR#
INT,
TFTD4
O1/4
VOPD3
O1/4
F_C/BE0#
O1/4
INT, (PU22.5)
IOCS1#
(PU22.5)
O3/5
TFTD12
(PU22.5)
O1/4
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4.
Ball Signal Name
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name TRDY# IRDY# C/BE2# AD17 -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] -Strap (See Table page 60.) -VIO -Cycle Multiplexed Cycle Multiplexed LOCK# C/BE3# Cycle Multiplexed PMR[28] PMR[28] -H30 VPD6 VPD5 VPD4 VPD3 AD13 VPCKIN STOP# VPD7 SERR# PERR# GTEST Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PD22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI INPCI INPCI, OPCI INPCI, OPCI -INT -VIO -Cycle Multiplexed -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type O14/14 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 PMR[15] (PMR[27] FPCI_MON (PMR[23]3= PMR[15] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
D226, AFD#/DSTRB#
TFTD2
O1/4
VOPD1
O1/4
INTR_O
O14/14
AVCCTV CVBS
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
-WIRE
AVCCTV F4BAR0+ Memory Offset C08h[4:3] description page 376. -VIO -VIO
INTA# AVCCUSB GPIO6 DTR2#/BOUT2 IDE_IOR1# SDTEST5
-INPCI -INTS, O1/4 O1/4 O1/4 O2/5 O8/8
SOUT2 CLKSEL2
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) Diode WIRE INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INTS O2/5 INPCI OPCI INPCI
AD16
INPCI, (PU22.5) ODPCI (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI
AD19
AD18
Cycle Multiplexed
DEVSEL# BHE#
-Cycle Multiplexed
SIN2 SDTEST3
TRST#
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-4.
Ball Signal Name C/BE1# AD15 VPD2 VPD1 VPD0 GPIO39 SERIRQ AD11 AD14 GPIO38/IRRX2
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name AD10 Cycle Multiplexed Cycle Multiplexed LDRQ# -PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 Cycle Multiplexed GPIO34 LAD2 GPIO33 LAD1 -VIO -Cycle Multiplexed PMR[14] PMR[22]4 IRRX2 input connected input path GPIO38. There logic required enable IRRX2, just simple connection. Hence, when GPIO38 selected function, IRRX2 also selected. PMR[14]4 PMR[22]4 -VIO -PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 Cycle Multiplexed Cycle Multiplexed VCORE VCORE
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -INPCI, OPCI OPCI INPCI, OPCI Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -INPCI, OPCI OPCI -INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB, -INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI -VIO Cycle Multiplexed Cycle Multiplexed -VIO PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[19] PMR[19] -Cycle Multiplexed -VIO -Cycle Multiplexed -VIO PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed
AD12
GPIO36
GPIO35 LAD3
GPIO32 LAD0
GPIO13 AB2D
LPCPD# GPIO37 LFRAME# C/BE0#
(PU22.5) (PU22.5) (PU22.5)
OPCI -INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4.
Ball Signal Name VCORE VCORE GPIO12 AB2C AB1D
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball PMR[19] PMR[23]3 (PMR[23] PMR[15] PMR[23]3 PMR[15] PMR[13] PMR[23]3 PMR[15] PMR[13] PMR[23]3 (PMR[23] PMR[15] PMR[23]3 PMR[15] PMR[7] PMR[23]3 PMR[15] PMR[7] Cycle Multiplexed PMR[24] PMR[24] Cycle Multiplexed Signal Name VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE -VIO -Strap (See Table page 60.) -U19 Strap (See Table page 60.) -PMR[25] -U28 VCORE VCORE AC97_RST# F_STOP# IDE_ADDR2 TFTD4 Buffer1 Power Rail Configuration (PU/PD) Type -INPCI, OPCI OPCI O1/4 O1/4 INPCI, OPCI OPCI -O2/5 O2/5 -VIO -FPCI_MON FPCI_MON PMR[24] PMR[24] Cycle Multiplexed -VIO -Cycle Multiplexed
Buffer1 Power (PU/PD) Type Rail Configuration (PU22.5) (PU22.5) (PU22.5) -INAB, O8/8 INAB, INAB, -VIO -PMR[19]
GPIO1
INT, (PU22.5) O3/5
IOCS1#
AB1C
(PU22.5)
INAB,
GPIO20
INT, (PU22.5) O3/5
DOCCS#
INPCI, OPCI OPCI O1/4 O1/4 INPCI, OPCI OPCI -OAC97
IDE_CS1# TFTDE
VCORE VCORE VCORE VCORE VCORE VCORE SDATA_OUT TFT_PRSNT
INSTRP (PD100) OAC97
SYNC CLKSEL3
INSTRP (PD100) O2/5
AC97_CLK
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-4.
Ball Signal Name BIT_CLK F_TRDY# SDATA_IN F_GNT0# IDE_DATA15 TFTD7 IDE_DATA14 TFTD17 IDE_DATA13 TFTD15 VCORE VCORE VCORE VCORE SDCLK3 GXCLK
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball W286 PMR[24] PMR[24] DDC_SCL PMR[24] PMR[24] DDC_SDA PMR[24] -VIO -(PMR[29] PMR[23]3 (PMR[23]3 PMR[15] PMR[23]3 PMR[15] PMR[29] PMR[23]3 PMR[0] FPCI_MON PMR[0] FPCI_MON FPCI_MON -VIO -PMR[24] PMR[24] PMR[24] PMR[24] -AB2 AA306 AA316 MD62 MD63 IDE_DATA4 FP_VDD_ON AA28 AA296 CLK27M SDCLK2 MD61 Y306 Y316 MD60 MD56 IDE_RST# TFTDCK IDE_DATA7 INTD# IDE_DATA6 IRQ9 IDE_DATA5 Y296 MD59 Y286 IDE_IOR0# TFTD10 MD58 IDE_DATA8 GPIO40
Buffer1 Power Rail Configuration (PU/PD) Type O1/4 O2/5 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -O2/5 O2/5 FPCI_MON FPCI_MON FPCI_MON FPCI_MON PMR[24]
Signal Name VCORE MD57 SDCLK1 IDE_DATA10
Buffer1 Power Rail Configuration (PU/PD) Type -INT, TS2/5 O2/5 -INTS1, TS1/4 INTS1, TS1/4 INT, INTS1, TS1/4 INTS1, O1/4 O1/4 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O1/4 O1/4 INTS1, TS1/4 INTS INTS1, TS1/4 INTS1 INTS1, TS1/4 O1/4 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INTS1, TS1/4 O1/4 -VIO -VIO -VIO -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24]
IDE_DATA9
FP_VDD_ON TEST3 GPIO16 PC_BEEP F_DEVSEL# IDE_DATA12 TFTD13 IDE_DATA11 GPIO41 VCORE VCORE VCORE
O1/4 O2/5
INT, (PU22.5) O2/5 O2/5 -INTS1, TS1/4 O1/4 INTS1, TS1/4 INTS1, O1/4
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4.
Ball Signal Name IDE_DATA3 TFTD12 AB286 AB29 AB30 AB31 MD24 DQM7 IDE_DATA1 TFTD16 IDE_DATA2 TFTD14 IDE_DATA0 TFTD6 IDE_DREQ0 TFTD8 AC286 AC296 AC306 AC31 MD25 MD26 MD27 DQM3 IDE_IORDY0 TFTD11 IDE_IOW0# TFTD9 IDE_ADDR0 TFTD3 IDE_DACK0# TFTD0 AD28 AD29
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball AE316 Signal Name MD28 IRQ14 TFTD1 -VIO -PMR[24] PMR[24] PMR[24] AF296 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -AG4 -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -AH4 -PMR[24] PMR[24] -AH12 WEA# -AH13 AH116 AH10
Buffer1 Power Rail Configuration (PU/PD) Type INTS1, TS1/4 O1/4 INT, TS2/5 -O2/5 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INTS1 O1/4 O1/4 O1/4 O1/4 O1/4 O1/4 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O1/4 O1/4 -VIO PMR[24] PMR[24]
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 INTS1 O1/4 O1/4 O1/4 O8/8 -PMR[24] PMR[24] PMR[24] PMR[24] -Strap (See Table page 60.) -PMR[16] PMR[16] -PMR[29] PMR[29] -PMR[29] PMR[29] -VSB -VSB
IDE_CS0# TFTD5
SOUT1 CLKSEL1 OVER_CUR#
INSTRP (PD100) (PU22.5) (PU22.5) (PU100) (PU100) INTS INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INTS, O8/8 O8/8 INTS WIRE O2/5 INTS, TS2/5 INT, TS2/5 O2/5 O2/5 INT, TS2/5 O1/4 WIRE O2/5 INT, TS2/5 -INBTN INTS, TS2/14 -O2/5 INTS INT, TS2/5 INT, TS2/5 O2/5
AF28
MD50 MD49 MD54 MD53 GPIO18 DTR1#/BOUT1
AF306 AF316
SIN1 X27I TEST1 PLL6B
AG286 AG29 AG30 AG316
MD21 DQM6 DQM2 MD55 POWER_EN X27O TEST0 PLL2B PWRBTN# GPWIO0 CLK32 POR#
MD52 MD29 MD30 MD31 IDE_ADDR1 TFTD2
AD306 AD316
AE28 AE29 AE30
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-4.
Ball AH14 AH15 AH166 AH176 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH286 AH296 AH30
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball AJ166 AJ176 AJ186 AJ196 AJ206 AJ21 -VIO -AJ30 -PMR[29] PMR[29] VBAT VBAT -VSB -VIO -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] -VIO -AK14 -AK19 -VIO AK186 MD46 AK15 AK16 AK176 AK66, PWRCNT1 IRRX1 SIN3 AK96 AK10 AK116 AK12 AK13 INT, TS2/5 -INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 RASA# MD35 AJ28 AJ29
Signal Name MD34 MD37 MD41 DQM1 MD13 MA11 CS1# MD18 MD48 MD20 MD51 TEST2 PLL5B
Buffer1 Power (PU/PD) Type Rail Configuration (PU100) (PU22.5) (PU22.5) (PU22.5) -O2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 -O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 WIRE WIRE -OD14 INTS, TS2/14 -INTS, O8/8 INTS INTS1 -VIO -VIO
Signal Name MD33 MD36 MD47 MD45 MD42 SDCLK0 MD11 SDCLK_IN
Buffer1 Power Rail Configuration (PU/PD) Type (PU100) INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 -O2/5 O2/5 -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 -INTS INTs, TS2/14 OD14 -INTS INTS INT, TS2/5 -INT, TS2/5 O2/5 -O2/5 O2/5 -VIO -VIO -VIO -VSB -VSB -VIO -VIO -VIO -PMR[6] PMR[6]
AJ22 AJ23 AJ24 AJ25 AJ266 AJ27
MD19 MD22 MD17 AVSSPLL3 THRM# GPWIO1
AJ316
AH316
AJ56,
X32I X32O VPLL3 ONCTL# GPWIO2 GPIO11 RI2# IRQ15
AJ96 AJ10 AJ116 AJ12 AJ13 AJ14 AJ15
CASA# MA10 MD32
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-4.
Ball AK206 AK21 AK22 AK23 AK246 AK25 AK266 AK276 AK28 AK296 AK30 AK31 AL76, AL96 AL106 AL11 AL12 AL13 AL14 AL15 AL16 AL176 AL186 AL19 AL206 AL216 AL22 AL23 AL24 AL25
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball AL266 AL276 AL28 AL29 AL30 AL31 -VSB -VSB -VIO -VIO -VIO -F3BAR0+Memory Offset 08h[21]
Signal Name MD43 DQM5 MD15 MD14 MD12 SDCLK_OUT MD16 VBAT LED# VSBL PWRCNT2 SDATA_IN2 DQM0 CS0# DQM4 MD38 MD39 MD44 MD40 CKEA
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 O2/5 -O2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 -OD14 -OD14 INTS INT, TS2/5 INT, TS2/5 O2/5 O2/5 -O2/5 O2/5 -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 -VIO -VIO
Signal Name MD10 MA12 MD23
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 -VIO
Buffer Type definitions, refer Table 9-10 "Buffer Types" page 391. tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). TFT_PRSNT strap determines power-on reset (POR) state PMR[23]. LPC_ROM strap determines power-on reset (POR) state PMR[14] PMR[22]. need tolerant protection system level (DDC_SCL, DDC_SDA). back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-5. 481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name
Signal Name AB1C AB1D AB2C AB2D AC97_CLK AC97_RST# ACK# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Ball Signal Name AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AFD#/DSTRB# AVCCCRT AVCCTV AVCCUSB AVSSCRT AVSSPLL2 AVSSPLL3 AVSSTV AVSSUSB BHE# BIT_CLK BLUE BOOT16 BUSY/WAIT# C/BE0# C/BE1# C/BE2# C/BE3# CASA# CKEA CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 CS0# CS1# CTS2# CVBS Ball A12, C13, B14, C14, AJ13 AK14 AJ12 A24, AL22 C23, AL12 AH27 A23, A24, Signal Name DCD2# DDC_SCL DDC_SDA DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# DOCR# DOCW# DPOS_PORT1 DPOS_PORT2 DPOS_PORT3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DSR2# DTR1#/BOUT1 DTR2#/BOUT2 ERR# F_AD0 F_AD1 F_AD2 F_AD3 F_AD4 F_AD5 Ball AL11 AH23 AG30 AC31 AL15 AK21 AG29 AB31
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-5.
Signal Name F_AD6 F_AD7 F_C/BE0# F_C/BE1# F_C/BE2# F_C/BE3# F_DEVSEL# F_FRAME# F_GNT0# F_IRDY# F_STOP# F_TRDY# FP_VDD_ON FPCI_MON FPCICLK FRAME# GNT0# GNT1# GPIO0 GPIO1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2 GREEN
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball V30, D10, Signal Name GTEST GXCLK HSYNC IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0 IDE_DREQ1 IDE_IOR0# IDE_IOR1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_RST# INIT# INTA# INTB# INTC# INTD# INTR_O IOCHRDY IOCS0# IOCS1# IOR# IOW# IRDY# IRQ9 IRQ14 Ball D10, Signal Name IRQ15 IRRX1 IRTX LAD0 LAD1 LAD2 LAD3 LDRQ# LED# LFRAME# LOCK# LPC_ROM LPCPD# MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 Ball AL14 AH15 AK15 AJ24 AL24 AK23 AJ23 AL23 AH22 AH21 AJ14 AH26 AL28 AH10 AL10 AH11 AJ11 AK11 AL25 AL27 AL26 AJ26 AK27 AH24 AK26 AK24 AK29 AJ31 AH28 AJ28 AH30 AG28 AJ30
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-5.
Signal Name MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 ONCTL# OVER_CUR# PC_BEEP PCICLK PCICLK0 PCICLK1 PCIRST#
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AL29 AB28 AC28 AC29 AC30 AE31 AD29 AD30 AD31 AJ15 AJ16 AH16 AK17 AJ17 AH17 AL17 AL18 AL21 AH20 AJ20 AK20 AL20 AJ19 AK18 AJ18 AH29 AF29 AF28 AH31 AD28 AF31 AF30 AG31 AA29 AA30 AA31 Signal Name PERR# PLL2B PLL5B PLL6B POR# POWER_EN PWRBTN# PWRCNT1 PWRCNT2 RASA# REQ0# REQ1# RI2# ROMCS# RTS2# SDATA_IN SDATA_IN2 SDATA_OUT SDCLK_IN SDCLK_OUT SDCLK0 SDCLK1 SDCLK2 SDCLK3 SDTEST0 SDTEST1 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SETRES SIN1 SIN2 SIN3 SLCT SLIN#/ASTRB# Ball AK12 AJ27 AK28 AJ21 AA28 Signal Name SMI_O SOUT1 SOUT2 SOUT3 STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT TFTD0 TFTD1 TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD9 TFTD10 TFTD11 TFTD12 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 TFTDCK TFTDE THRM# TRDE# TRDY# TRST# TVCOMP TVIOM Ball A20, D22, B17, D21, B21, C21, A21, D20, C20, C18, C19, D10, A18, D17, C17, B20, A22, A10, B18,
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-5.
Signal Name TVREF TVRSET VBAT VCCCRT VCORE (Total
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball A24, N13, N14, N18, N19, P13, P14, P18, P19, P28, T28, T29, T30, T31, U28, V13, V14, V18, V19, W13, W14, W18, A30, B13, B16, B19, B31, C10, C22, C25, C29, D14, D18, G29, K29, M30, W31, AB3, AB29, AE3, AE29, AH4, AH14, AH18, AJ7, AJ10, AJ22, AJ25, AJ29, AK1, AK13, AK16, AK19, AK31, AL2, AL30, VSSCRT Signal Name VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VPLL2 VPLL3 VREF VSBL (Total Ball A13, A16, A19, A31, B10, B22, B25, B30, D13, D19, D25, G28, G30, K30, M31, N15, N16, N17, N28, P15, P16, P17, R13, R14, R15, R16, R17, R18, R19, R28, R29, R30, R31, T13, T14, T15, T16, T17, T18, T19, U13, U14, U15, U16, U17, U18, U19, V15, V16, V17, V28, W15, W16, W17, W30, AB2, AB30, AE2, AE4, AE28, AE30, AH7, AH13, AH19, AH25, AK2, AK7, AK10, AK22, AK25, AK30, AL1, AL13, AL16, AL19, AL31 Signal Name VSYNC WEA# X27I X27O X32I X32O Ball AH12
(Total
VOPCK VOPD0 VOPD1 VOPD2 VOPD3 VOPD4 VOPD5 VOPD6 VOPD7 VPCKIN VPD0 VPD1
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Strap Options
resistor with value placed balls listed Table 3-6. value resistor important ensure that proper state read during power-up sequence. ball read correctly power-up, SC1200/SC1201 processor default state that causes function improperly, possibly resulting application failure.
Several balls read power-up that state SC1200/SC1201 processor. These balls typically multiplexed with other functions that outputs after power-up sequence complete. SC1200/SC1201 processor must read state balls power-up internal resistors guarantee correct state will read. Therefore, required that external
Table 3-6. Strap Options
Ball Strap Option CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 Muxed With SOUT1 SOUT2 SYNC EBGA AL13 TEPBGA Nominal Internal PD100 PD100 PD100 PD100 External PU/PD Strap Settings Strap (PD) Strap (PU) Register References GCB+I/O Offset 1Eh[9:8] (aka CCFC register bits [9:8]) (RO): Value programmed reset CLKSEL[1:0]. GCB+I/O Offset 10h[3:0] (aka MCCM register bits [3:0]) (RO): Value programmed reset CLKSEL[3:0]. GCB+I/O Offset 1Eh[3:0] (aka CCFC register bits [3:0]) (R/W, write recommended): Value programmed reset CLKSEL[3:0]. Note: Values GCB+I/O Offset 10h[3:0] 1Eh[3:0] same. BOOT16 ROMCS# PD100 Enable boot from 8-bit Enable boot from 16-bit GCB+I/O Offset 34h[3] (aka register (RO): Reads back strap setting. GCB+I/O Offset 34h[14] (R/W): Used allow ROMCS# width changed under program control. TFT_PRSNT SDATA_OUT AK13 PD100 muxed onto Parallel Port Disable boot from Disable FastPCI, INTR_O, SMI_O monitoring signals. muxed onto Parallel Port Enable boot from Enable FastPCI, INTR_O, SMI_O monitoring signals. (Useful during debug.) GCB+I/O Offset 30h[23] (aka register (R/W): Reads back strap setting. F0BAR1+I/O Offset 10h[15] Reads back strap setting allows changed under program control. GCB+I/O Offset 34h[30] (aka register (RO): Reads back strap setting. Note: normal operation, strap this signal using resistor.
Table page CLKSEL strap options.
LPC_ROM
PCICLK1
PD100
FPCI_MON
PCICLK0
PD100
DID0 DID1
GNT0# GNT1#
PD100 PD100
Defines system-level chip
GCB+I/O Offset 34h[31,29] (aka register bits (RO): Reads back strap setting. Note: These signals should connected resistor ensure level power-up.
Note:
Accuracy internal PU/PD resistors: 250K. Location (General Configuration Block) cannot determined software. GeodeSC1200/ SC1201 Processor Specification Update document.
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Multiplexing Configuration
system reset, pull-up present. This pull-up resistor disabled writing Core Logic registers. configuration without regard selected ball function. above applies pins multiplexed with GPIO, except GPIO12, GPIO13, GPIO16.
tables that follow list multiplexing options their configurations. Certain multiplexing options chosen signal; others available only group signals. Where ever GPIO multiplexed with another function, there optional pull-up resistor this pin; after
Table 3-7. Two-Signal/Group Multiplexing
Default EBGA TEPBGA Signal IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_IOR0# IDE_IORDY0 IDE_DREQ0 IDE_IOW0# IDE_CS0# IDE_CS1# IDE_DACK0# IDE_RST# IRQ14 Sub-ISA TRDE# PMR[12] GPIO0 PMR[24] TFTD3 TFTD2 TFTD4 TFTD6 TFTD16 TFTD14 TFTD12 FP_VDD_ON CLK27M IRQ9 INTD# GPIO40 DDC_SDA DDC_SCL GPIO41 TFTD13 TFTD15 TFTD17 TFTD7 TFTD10 TFTD11 TFTD8 TFTD9 TFTD5 TFTDE TFTD0 TFTDCK TFTD1 GPIO PMR[12] Configuration Signal Alternate Configuration
Ball
TFT, CRT, PCI, GPIO, System PMR[24]
Ball
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-7. Two-Signal/Group Multiplexing (Continued)
Default EBGA TEPBGA Signal GPIO GPIO12 GPIO13 GPIO GPIO18 PMR[16] Infrared IRTX IRRX1 GPIO GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 UART SIN2 PMR[28] AC97 AC97_RST# SDATA_IN BIT_CLK Internal Test PLL6B PLL5B PLL2B PMR[29] TEST1 TEST2 TEST0 FPCI_MON F_STOP# F_GNT0# F_TRDY# Internal Test PMR[29] SDTEST3 PMR[14] PMR[22] LAD0 LAD1 LAD2 LAD3 LDRQ# LFRAME# LPCPD# SERIRQ Internal Test PMR[28] FPCI Monitoring FPCI_MON PMR[6] SOUT3 SIN3 PMR[14] PMR[22] DTR1#/BOUT1 PMR[19] AB2C AB2D UART PMR[16] UART PMR[6] Configuration Signal Alternate Configuration ACCESS.bus PMR[19]
Ball AJ12 AL11
Ball
Ball Ball AJ11 AL10 AK10 AJ10
Ball
Ball AJ15 AK14 AL14
Ball
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Table 3-8. Three-Signal/Group Multiplexing
Default EBGA TEPBGA Signal Configuration Sub-ISA IOR# IOW# PMR[21] PMR[2] GPIO GPIO16 PMR[0] FPCI_MON GPIO GPIO19 PMR[9] PMR[4] GPIO GPIO17 (PMR[23] PMR[5] (PMR[23] PMR[15] PMR[5] (PMR[23] PMR[7] (PMR[23] PMR[15] PMR[7] (PMR[23] PMR[13] (PMR[23] PMR[15] PMR[13] AB1C PMR[23] (PMR[23] PMR[15] PMR[23] (PMR[23] PMR[15] GPIO GPIO11 PMR[18] PMR[8] Internal Test GXCLK (PMR[29] PMR[23] (PMR[23] PMR[15] FP_VDD_ON RI2# GPIO20 IOCS0# INTC# PC_BEEP DOCR# DOCW# Signal Alternate1 Configuration Sub-ISA1 PMR[21] PMR[2] AC97 PMR[0] FPCI_MON PCI2 PMR[9] PMR[4] Sub-ISA (PMR[23] PMR[5] (PMR[23] PMR[15] PMR[5] (PMR[23] PMR[7] (PMR[23] PMR[15] PMR[7] (PMR[23] PMR[13] (PMR[23] PMR[15] PMR[13] GPIO PMR[23] PMR[15] PMR[7] PMR[23] PMR[15] PMR[13] UART2 PMR[18] PMR[8] PMR[23] PMR[15] TEST3 IRQ15 DOCCS# TFTDCK IOCHRDY GPIO14 GPIO15 Signal Alternate2 Configuration GPIO PMR[21] PMR[2] FPCI Monitoring F_DEVSEL FPCI_MON Sub-ISA PMR[9] PMR[4] TFT3 PMR[23] PMR[15]
Ball
Ball AL15
Ball
Ball
GPIO20
DOCCS#
TFTD0
PMR[23] PMR[15]
GPIO1
IOCS1#
TFTD12
PMR[23] PMR[15]
Ball AJ13
Sub-ISA PMR[23] PMR[15] PMR[7] PMR[23] PMR[15] PMR[13] IDE2 PMR[18] PMR[8] Internal Test PMR[29] PMR[23]
AL12
AB1D
GPIO1
IOCS1#
Ball
Ball AL16
combination PMR[21] PMR[2] undefined should used. combination PMR[9] PMR[4] undefined should used. These outputs reset POR# TFT_PRSNT strap pulled high PMR[10] This relates signals TFTD[17:0], TFTDE, TFTDCK.
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
Table 3-9. Four-Signal/Group Multiplexing
TEPBGA EBGA Default Signal Configuration GPIO GPIO7 GPIO8 GPIO6 GPIO9 GPIO10 Parallel Port ACK# AFD#/ DSTRB# BUSY/ WAIT# ERR# INIT# PMR[23] (PMR[27] FPCI_MON TFTDE TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD1 PMR[17] RTS2# PMR[8] CTS2# PMR[18] DTR2#/BOUT2 PMR[8] DCD2# DSR2# (PMR[23] PMR[15] (PMR[27] FPCI_MON VOPCK VOPD1 VOPD2 VOPD3 VOPD4 VOPD5 VOPD6 VOPD7 VOPD0 Signal Alternate1 Configuration UART2 PMR[17] IDE_DACK1# PMR[8] IDE_DREQ1 PMR[18] IDE_IOR1# PMR[8] IDE_IOW1# IDE_IORDY1 (PMR[23] PMR[15] (PMR[27] FPCI_MON Signal Alternate2 Configuration IDE2 Signal Alternate3 Configuration
Ball
Internal Test PMR[17] PMR[8] PMR[18] PMR[8]
PMR[17] SDTEST0 PMR[8] SDTEST4 PMR[18] SDTEST5 PMR[8] SDTEST2 SDTEST1
Ball
FPCI Monitoring FPCI_CLK INTR_O F_C/BE1# F_C/BE0# SMI_O F_AD0 F_AD1 F_AD2 F_AD6 PMR[23] (PMR[27] FPCI_MON
Three-Signal/Group Multiplexing (shown here interface clarification) SLCT SLIN# /ASTRB# STB#/ WRITE# PMR[23] (PMR[27] FPCI_MON TFTD9 TFTD10 TFTD11 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 PMR[23] (PMR[27] FPCI_MON -F_AD3 F_AD4 F_AD5 F_AD7 F_C/BE2# F_C/BE3# F_IRDY F_FRAME# PMR[23] (PMR[27] FPCI_MON
GeodeSC1200/SC1201 Processor Data Book
Signal Definitions
Revision
Signal Descriptions
Information tables that follow have duplicate information multiple tables. Multiple references contain identical information.
3.4.1
System Interface
Ball
Signal Name CLKSEL1 CLKSEL0
EBGA
TEPBGA
Type
Description Fast-PCI Clock Selects. These strap signals used internal Fast-PCI clock. 33.3 66.7 33.3 During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used.
SOUT1
CLKSEL3 CLKSEL2
AL13
Maximum Core Clock Multiplier. These strap signals used maximum allowed multiplier value core clock. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used.
SYNC SOUT2
BOOT16
Boot Bits Wide. This strap signal enables optional 16-bit wide Sub-ISA bus. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used.
ROMCS#
LPC_ROM
ROM. This strap signal forces selecting sets F0BAR1+I/O Offset 10h[15], Addressing Enable. enables SC1200/SC1201 processor boot from connected bus. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used.
PCICLK1
TFT_PRSNT
AK13
Present. strap used select multiplexing signals power-up. Enables using instead Parallel Port, ACB1, GPIO17. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used.
SDATA_OUT
FPCI_MON
Fast-PCI Monitoring. strap this ball forces selection Fast-PCI monitoring signals. normal operation, strap this signal using resistor. value this strap read MCR[30].
PCICLK0
GeodeSC1200/SC1201 Processor Data Book
Revision
Signal Definitions
3.4.1
System Interface (Continued)
Ball
Signal Name DID1 DID0
EBGA
TEPBGA
Type
Description Device Together, straps these signals define system-level chip value DID1 read MCR[29]. value DID0 read MCR[31]. DID1 DID0 should connected pull-down resistor ensure level power-up.
Other recent searches
SM5009 - SM5009 SM5009 Datasheet
OC-3 - OC-3 OC-3 Datasheet
OC-192 - OC-192 OC-192 Datasheet
MM1096 - MM1096 MM1096 Datasheet
LTC1669 - LTC1669 LTC1669 Datasheet
FH105 - FH105 FH105 Datasheet
EP3C16 - EP3C16 EP3C16 Datasheet
DQ2L - DQ2L DQ2L Datasheet
DQ1L - DQ1L DQ1L Datasheet
APTM20DHM10 - APTM20DHM10 APTM20DHM10 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
