CMOS SRAM 512K Super Power Voltage Full CMOS Static Revision
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K6F8016U3A Family
CMOS SRAM
512K Super Power Voltage Full CMOS Static
Revision History
Revision History
Initial draft
Draft Date
December 2000
Remark
Preliminary
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer yourquestions about device. have questions, please contact SAMSUNG branch offices.
Revision December 2000
K6F8016U3A Family
FEATURES
Process Technology: Full CMOS Organization: 512K Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three state output Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
K6F8016U3A families fabricated SAMSUNGs advanced full CMOS process technology. families support various operating temperature ranges have small package user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
512K Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family K6F8016U3A-B K6F8016U3A-F Operating Temperature Commercial(0~70°C) Industrial(-40~85°C) Range Speed Standby (ISB1, Typ.) 0.5µA Operating (ICC1, Max) Type
2.7~3.3V
551)/70ns
44-TSOP2-400F/R
parameter measured with 30pF test load.
DESCRIPTION
I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
Addresses
44-TSOP2 Forward
44-TSOP2 Reverse
select
Memory array 1024 rows columns
I/O1~I/O8
Data cont Data cont Data cont
Circuit Column select
I/O9~I/O16
Name A0~A18 I/O1~I/O16
Function Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs
Name
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8)
Column Addresses
Control Logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision December 2000
K6F8016U3A Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6F8016U3A-TB55 K6F8016U3A-TB70 K6F8016U3A-RB55 K6F8016U3A-RB70 Function 44-TSOP2-F, 55ns, 3.0V 44-TSOP2-F, 70ns, 3.0V 44-TSOP2-R, 55ns, 3.0V 44-TSOP2-R, 70ns, 3.0V
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6F8016U3A-TF55 K6F8016U3A-TF70 K6F8016U3A-RF55 K6F8016U3A-RF70 Function 44-TSOP2-F, 55ns, 3.0V 44-TSOP2-F, 70ns, 3.0V 44-TSOP2-R, 55ns, 3.0V 44-TSOP2-R, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout High-Z I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Active Active Active Active Active Active Active Active
Note means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.5V -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision December 2000
K6F8016U3A Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.23)
CMOS SRAM
Vcc+0.22) Unit
Note: Commercial products:TA=0 70°C, otherwise specified. Industrial products: TA=-40 85°C, otherwise specified. Overshoot: VCC+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2 Output voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) ISB1 VIN=Vss CS=VIH, OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS=VIL, WE=VIH, VIN=VIH Cycle time=1µs, 100%duty, IIO=0mA, CS0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL 2.1mA -1.0mA CS=VIH, Other inputs=VIH CSVcc-0.2V, Other inputs=0~Vcc Test Conditions 251) Unit
Super power product=10µA with special handling.
Revision December 2000
K6F8016U3A Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, R2=3150 V=2.8V
CHARACTERISTICS (Vcc=2.7~3.3V, Commercial Products: TA=0 70°C, Industrial products: TA=-40 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Access Time Read Chip Select Low-Z Output Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z tBLZ tOLZ tBHZ tOHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V
Unit
data retention waveform
CS1Vcc-0.2V,CS2Vcc-0.2V(CS1 controlled) CS2Vcc-0.2V(CS2 controlled). Super power product=4µA with special handling.
Revision December 2000
K6F8016U3A Family
TIMMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data Valid tOHZ
Data
High-Z
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision December 2000
K6F8016U3A Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
High-Z
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision December 2000
K6F8016U3A Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V
Revision December 2000
K6F8016U3A Family
PACKAGE DIMENSION
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Unit: millimeters
0~8° 0.25 0.010
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.004 .006
18.81 MAX. 0.741 18.41±0.10 0.725±0.004
0.805 0.032
0.35± 0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
THIN SMALL OUTLINE PACKAGE TYPE (400R)
0.25 0.010
0~8°
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.004 .002 0.00
18.81 MAX. 0.741 18.41± 0.10 0.725±0.004
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
Revision December 2000
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