Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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K6F8008U2M Family
Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Finalize Adopt code. Improve VIN, VOUT max. ABSOLUTE MAXIMUM RATINGS'from 3.6V VCC+0.5V. Improve OPERATING CHARACTERISTICS'from 2.4V. Revise Errata correction Improve max. RECOMMENDED OPERATING CONDI TIONS'from 0.4V 0.6V. Change from 20ns 25ns 55ns product. from 25ns 30ns 70ns product. Change tWHZ from 25ns 20ns 70ns product.
Draft Date
August 1999 February 2000
Remark
Preliminary Finalize
April 2000
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer yourquestions about device. have questions, please contact SAMSUNG branch offices.
Revision April 2000
K6F8008U2M Family
FEATURES
Process Technology: Full CMOS Organization: Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three state output Compatible Package Type: 44-TSOP2-400F/R, 48-FBGA-8.00x12.00
CMOS SRAM
GENERAL DESCRIPTION
K6F8008U2M families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial operating temperature ranges have chip scale package user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
Super Power Voltage Full CMOS Static
DUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 0.5µA Operating (ICC1, Max) Type 44-TSOP2-400F/R 48-FBGA-8.00x12.00
K6F8008U2M-F
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
parameter measured with 30pF test load.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
Addresses select Memory array 2048 rows columns
I/O1
I/O5
I/O2
I/O6
I/O3
I/O7
1~I/O8
Data cont
Circuit Column select
I/O4
I/O8 Data cont
Column Addresses
48-FBGA: View (Ball Down)
I/O1 I/O2 I/O3 I/O4 I/O8 I/O7 I/O6 I/O5 I/O8 I/O7 I/O6 I/O5 I/O1 I/O2 I/O3 I/O4
Control Logic
44-TSOP2 Forward
44-TSOP2 Reverse
Name
Function
Name A0~A19
Function Address Inputs Power Ground
CS1, Chip Select Inputs I/O1~I/ Output Enable Input Write Enable Input Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision April 2000
K6F8008U2M Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F8008U2M-TF55 K6F8008U2M-TF70 K6F8008U2M-RF55 K6F8008U2M-RF70 K6F8008U2M-FF55 K6F8008U2M-FF70 Function
CMOS SRAM
44-TSOP2-F, 55ns, 3.0V 44-TSOP2-F, 70ns, 3.0V 44-TSOP2-R, 55ns, 3.0V 44-TSOP2-R, 70ns, 3.0V 48-FBGA, 55ns, 3.0V 48-FBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT TSTG Ratings -0.2 VCC+0.5V -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision April 2000
K6F8008U2M Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.23)
CMOS SRAM
Vcc+0.2
Unit
Note: A=-40 85°C, otherwise specified. Overshoot: VCC+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CAPACITANCE (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2 Output voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) ISB1 VIN=Vss CS1=VIH, CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, 2=VIH, WE=VIH, VIN=VIH Cycle time=1µs, 100%duty, IIO=0mA, 10.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL 2.1mA -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled), Other inputs=0~Vcc Test Conditions Unit
Super power product=10µA with special handling.
Revision April 2000
K6F8008U2M Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance =3070, =3150 V=2.8V
CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product: TA=-40 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Read Chip Select Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z tOLZ tOHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V Vcc=1.5V, CS1Vcc-0.2V
Unit
data retention waveform
Vcc-0.2V,CS2 Vcc-0.2V(CS1 controlled) Vcc-0.2V(CS2 controlled). Super power product=4µA with special handling.
Revision April 2000
K6F8008U2M Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision April 2000
K6F8008U2M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision April 2000
K6F8008U2M Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change. applied case write ends going high tWR2 applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision April 2000
K6F8008U2M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Unit: millimeters(inches)
0~8° 0.25 0.010
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.002
18.81 MAX. 0.741 18.41±0.10 0.725±0.004
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
THIN SMALL OUTLINE PACKAGE TYPE (400R)
0.25 0.010
0~8°
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.006
18.81 MAX. 0.741 18.41±0.10 0.725±0.004
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
Revision April 2000
K6F8008U2M Family
PACKAGE DIMENSION
BALL FINE PITCH BGA(0.75mm ball pitch)
View Bottom View
CMOS SRAM
Unit: millimeters
INDEX MARK 0.50 0.50
C1/2 Detail 0.25/Typ. 0.85/Typ. Notes. Bump counts: 48(8row 6column) Bump pitch (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typical coplanarity: 0.08(Max)
Side View
7.90 11.90 0.30 0.20
0.75 8.00 3.75 12.00 5.25 0.35 1.10 0.85 0.25
8.10 12.10 0.40 1.20 0.30 0.08
Revision April 2000
0.30

Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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