CMOS SRAM 256K Super Power Voltage Full CMOS Static Revision

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CMOS SRAM 256K Super Power Voltage Full CMOS Static Revision

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K6F4016U4E Family
CMOS SRAM
256K Super Power Voltage Full CMOS Static
Revision History
Revision History
Initial draft Finalize
Draft Date
October 2000 March 2001
Remark
Preliminary Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision March 2001
K6F4016U4E Family
FEATURES
CMOS SRAM
GENERAL DESCRIPTION
K6F4016U4E families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial temperature range ball Chip Scale Package user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
256K Super Power Voltage Full CMOS Static
Process Technology: Full CMOS Organization: 256K Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 1.0µA2) Operating (ICC1, Max) Type
K6F4016U4E-F
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
48-TBGA-6.00x7.00
parameter measured with 30pF test load. Typical value measured VCC=3.0V, TA=25°C 100% tested.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
I/O9
I/O1
Addresses
I/O10
I/O11
I/O2
I/O3
select
Memory Cell Array
I/O12
I/O4
I/O13
I/O5
I/O1~I/O8
Data cont Data cont Data cont
Circuit Column select
I/O15
I/O14
I/O6
I/O7
I/O9~I/O16
I/O16
I/O8 Column Addresses
48-TBGA: View (Ball Down) Name A0~A17 Function Chip Select Input Output Enable Input Write Enable Input Address Inputs Name Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8)
Control Logic
1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
-2Revision March 2001
K6F4016U4E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F4016U4E-EF55 K6F4016U4E-EF70 Function
CMOS SRAM
48-TBGA, 55ns, 3.0V 48-TBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.5 VCC+0.3V(Max. 3.6V) -0.3 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision March 2001
K6F4016U4E Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage
Note: TA=-40 85°C, otherwise specified. Overshoot: Vcc+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CMOS SRAM
Symbol
-0.3
Vcc+0.3
Unit
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss CS=VIH OE=VIH WE=VIL LB=UB=VIH, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, CS0.2V, LB0.2V or/and UB0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS=VIL LB=VIL or/and UB=VIL VIN=VIL 2.1mA -1.0mA Other input =0~Vcc CSVcc-0.2V(CS controlled) LB=UBVcc-0.2V, CS0.2V(LB/UB controlled) 70ns 55ns
Unit
ICC1
Average operating current ICC2 Output voltage Output high voltage Standby Current (CMOS) ISB1
Typical value measured CC=3.0V, TA=25°C 100% tested.
Revision March 2001
K6F4016U4E Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference) Input pulse level: 2.2V Input rising falling time: Input output reference voltage: 1.5V Output load (See right): 100pF+1TTL 30pF+1TTL
VTM3)
CMOS SRAM
R12)
CL1)
R22)
Including scope capacitance =3070, =3150 V=2.8V
CHARACTERISTICS (TA=-40 85°C, Vcc=2.7~3.3V)
Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output Access Time Read Chip select low-Z output enable low-Z output Output enable low-Z output Chip disable high-Z output disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Valid Write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tBLZ tOLZ tBHZ tOHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CSVcc-0.2V VIN0V
Unit
Vcc=1.5V, CSVcc-0.2V1), VIN0V data retention waveform
CSVcc-0.2V(CS controlled) LB=UBVcc-0.2V, CS0.2V(LB/UB controlled) Typical value measured TA=25°C 100% tested.
Revision March 2001
K6F4016U4E Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2)
(WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision March 2001
K6F4016U4E Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
High-Z
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision March 2001
K6F4016U4E Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
LB/UB controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CSVCC-0.2V LB=UBVCC-0.2V LB/UB
Revision March 2001
K6F4016U4E Family
PACKAGE DIMENSION
TAPE BALL GRID ARRAY(0.75mm ball pitch)
View Bottom View
CMOS SRAM
Unit: millimeters
INDEX MARK 0.65 0.65
C1/2 Detail 0.35/Typ. 0.55/Typ. Notes. Bump counts: 48(8 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typ: Typical coplanarity: 0.08(Max)
Side View
5.90 6.90 0.40 0.80 0.30
0.75 6.00 3.75 7.00 5.25 0.45 0.90 0.55 0.35
6.10 7.10 0.50 1.00 0.40 0.08
Revision March 2001

CMOS SRAM 256K Super Power Voltage Full CMOS Static Revision

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