CMOS DRAM 4bit CMOS Dynamic with Extended Data This family 1
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KM44C16004C, KM44C16104C
CMOS DRAM
4bit CMOS Dynamic with Extended Data
This family 16,777,216 Extended Data Mode CMOS DRAMs. Extended Data Mode offers high speed random access memory cells within same row. Refresh cycle(4K Ref. Ref.), access time -6), package type (SOJ TSOP-II) optional features this family. this family have CAS-before-RAS refresh, RAS-only refresh Hidden refresh capabilities. This 16Mx4 Mode DRAM family fabricated using Samsungs advanced CMOS process realize high band-width, power consumption high reliability.
FEATURES
Part Identification KM44C16004C(5.0V, Ref.) KM44C16104C(5.0V, Ref.)
Extended Data Mode operation CAS-before-RAS refresh capability RAS-only Hidden refresh capability Fast parallel test mode capability TTL(5.0V) compatible inputs outputs Early Write output enable controlled write JEDEC Standard pinout Unit Available Plastic TSOP(II) packages +5.0V±10% power supply
Active Power Dissipation Speed
Refresh Cycles Part KM44C16004C* KM44C16104C Refresh cycle Refresh time Normal 64ms
FUNCTIONAL BLOCK DIAGRAM
Control Clocks
Generator
Refresh Control
Performance Range Speed
Refresh Counter
Memory Array 16,777,216 Cells
Sense Amps
Access mode only refresh mode cycle/64ms CAS-before-RAS Hidden refresh mode cycle/64ms
Refresh Timer
Decoder Data Buffer Data Buffer
tRAC
50ns 60ns
tCAC
13ns 15ns
84ns 104ns
20ns 25ns
A0~A12 (A0~A11)*1 A0~A10 (A0~A11)*1
Address Buffer Col. Address Buffer Column Decoder
Note) Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
KM44C16004C, KM44C16104C
CMOS DRAM
CONFIGURATION (Top Views)
KM44C160(1)04CK A12(N.C)*
KM44C160(1)04CS
A12(N.C)*
400mil SOJ)
400mil TSOP(II))
(N.C) Refresh product
Name
Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) Connection
KM44C16004C, KM44C16104C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT Tstg Address Rating -1.0 +7.0 -1.0 +7.0 +150
CMOS DRAM
Units
Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced Vss, 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -1.0*2 VCC+1.0
Units
VCC+2.0V pulse width20ns which measured -2.0 pulse width20ns which measured
OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.5V, other pins under test=0 Volt) Output Leakage Current (Data disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) Units
KM44C16004C, KM44C16104C
OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM44C16004C ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Dont care Normal Dont care Dont care Normal Dont care Dont care Dont care KM44C16104C
CMOS DRAM
Units
ICC1* Operating Current (RAS CAS, Address cycling @tRC=min.) ICC2 Standby Current (RAS=CAS=W=VIH) ICC3* RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4* Extended Data Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.) ICC5 Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* CAS-Before-RAS Refresh Current (RAS cycling @tRC=min)
*Note ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open.
specified average current. ICC1, ICC3 ICC6, address changed maximum once while RAS=VIL. ICC4, address changed maximum once within mode cycle time, tHPC.
KM44C16004C, KM44C16104C
CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)
Parameter Input capacitance A12] Input capacitance [RAS, CAS, Output capacitance [DQ0 DQ3] Symbol CIN1 CIN2
CMOS DRAM
Units
CHARACTERISTICS (0°CTA70°C, note 1,2)
Test condition VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address output Low-Z Output buffer turn-off delay from output Low-Z Transition time (rise fall) precharge time pulse width hold time hold time pulse width delay time column address delay time precharge time address set-up time address hold time Column address set-up time Column address hold time Column address lead time Read command set-up time Read command hold time referenced Read command hold time referenced Write command hold time Write command pulse width Write command lead time Write command lead time Data set-up time Symbol 3,4,10 3,4,5 3,10 6,14 Units Note
tRWC tRAC tCAC tCLZ tCEZ tOLZ tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL
KM44C16004C, KM44C16104C
CHARACTERISTICS (Continued)
Parameter Data hold time Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time delay time delay time Column address delay time set-up time (CAS -before-RAS refresh) hold time (CAS -before-RAS refresh) precharge time Access time from precharge Hyper Page cycle time Hyper Page read-modify-write cycle time precharge time (Hyper page cycle) pulse width (Hyper page cycle) hold time from precharge access time data delay precharge delay time Output buffer turn delay time from command hold time Write command set-up time (Test mode Write command hold time (Test mode precharge time (C-B-R refresh) hold time (C-B-R refresh) Output data hold time Output buffer turn delay from Output buffer turn delay from data delay hold time hold time precharge time pulse width (Hyper page Cycle) pulse width (C-B-R self refresh) precharge time (C-B-R self refresh) hold time (C-B-R self refresh) Symbol 200K 200K
CMOS DRAM
Units
Note
tREF tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPA tHPC tHPRWC tRASP tRHCP tOEA tOED tCPWD tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
6,14
15,16,17 15,16,17 15,16,17
KM44C16004C, KM44C16104C
TEST MODE CYCLE
Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address pulse width pulse width hold time hold time Column Address lead time delay time delay time Column Address delay time Hyper Page cycle time Hyper Page read-modify-write cycle time pulse width (Hyper page cycle) Access time from precharge access time data delay command hold time Symbol 200K 200K
CMOS DRAM
Note
Units 3,4,10,12 3,4,5,12 3,10,12 Note
tRWC tRAC tCAC tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
KM44C16004C, KM44C16104C
NOTES
CMOS DRAM
initial pause 200us required after power-up followed RAS-only refresh CAS-before-RAS refresh cycles before proper device operation achieved. VIH(min) VIL(max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. Measured with load equivalent load 100pF. Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Assumes that tRCDtRCD(max). This parameter defines time which output achieves open circuit condition referenced Vol. tWCS, tRWD, tCWD tAWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCStWCS(min), cycle early write cycle data output will remain high impedance duration cycle. tCWDtCWD(min), tRWDtRWD(min) tAWDtAWD(min), then cycle read-modify-write cycle data output will contain data read from selected address. neither above conditions satisfied, condition data indeterminate. Either tRCH tRRH must satisfied read cycle. These parameters referenced falling edge early write cycles falling edge controlled write cycle read-modify-write cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit, then access time controlled tAA. These specifications applied test mode. test mode read cycle, value tRAC, tAA, tCAC delayed specified values. These parameters should specified test mode cycles adding above value specified value this data sheet. tASC6ns, Assume 2.0ns goes high before high going, open circuit condition output achieved high going. goes high before high going, open circuit condition output achieved high going. tRASS100us, then precharge time must tRPS instead tRP. RAS-only refresh burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles burst refresh must executed within 64ms before after self refresh, order meet refresh specification. distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should executed with 15.6us immediately before after self refresh order meet refresh specification.
KM44C16004C, KM44C16104C
READ CYCLE
CMOS DRAM
tRAS
tCRP
tCSH tRCD tRSH tCAS tRAD
tCRP
tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tRCS
tRCH tRRH
tWEZ
tCEZ tOEZ tOEA
tOLZ tCAC
DQ3(7)
tRAC OPEN
tCLZ
tREZ
DATA-OUT
Dont care Undefined
KM44C16004C, KM44C16104C
WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCSH tCRP
tRCD tRAD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tASR
tRAH
tASC
ADDRESS
tCWL tRWL tWCS
tWCH
DQ3(7)
DATA-IN
Dont care Undefined
KM44C16004C, KM44C16104C
WRITE CYCLE CONTROLLED WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
tCSH tRCD tRSH tCAS tCRP
tRAD tRAL tASR
tRAH
tASC
tCAH
COLUMN ADDRESS
ADDRESS
tCWL tRWL
tOED
tOEH
DATA-IN
DQ3(7)
Dont care Undefined
KM44C16004C, KM44C16104C
READ MODIFY WRITE CYCLE
CMOS DRAM
tRAS
tRWC
tCRP
tRCD tRAD
tRSH tCAS
tASR
tRAH
tASC
tCAH tCSH
ADDR
COLUMN ADDRESS
tAWD tCWD
tRWL tCWL
tRWD
tOEA tOLZ tCLZ tCAC tRAC
VALID DATA-OUT
tOED tOEZ
VALID DATA-IN
DQ3(7) VI/OH VI/OL
Dont care Undefined
KM44C16004C, KM44C16104C
HYPER PAGE READ CYCLE
CMOS DRAM
tRASP
tCSH tCRP
tRHCP tHPC tHPC tCAS tHPC tCAS tCAS
tRCD tCAS tRAD
tASR
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
tREZ
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
tRRH tRCH
tCAC tCPA tOCH tOEA tCAC tOEA tOEP
tCAC tCPA
tCPA tCAC tCHO tOEP
tOEA tOEZ
VALID DATA-OUT VALID DATA-OUT
DQ3(7)
tRAC
tDOH
VALID DATA-OUT
tOEZ
tOEZ
tOLZ tCLZ
VALID DATA-OUT
Dont care Undefined
KM44C16004C, KM44C16104C
HYPER PAGE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRASP
tRHCP
tCRP
tHPC tRCD tCAS tRAD tCSH tCAS
tHPC
tRSH tCAS
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tWCS
tWCH
tWCS
tWCH tCWL
tWCS
tWCH tCWL tRWL
tCWL
DQ3(7)
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
Dont care Undefined
KM44C16004C, KM44C16104C
HYPER PAGE READ-MODIFY-WRITE CYCLE
CMOS DRAM
tRASP
tRSH tHPRWC
tCSH tCRP
tRCD tCAS tRAD tRAH
tCAS tRAL tASC
COL. ADDR COL. ADDR
tCRP
tASR
ADDR
tASC
tCAH
tCAH
tRCS
tCWL tCWD tCWD tAWD tCPWD tOEA tOED
tRWL tCWL
tAWD tRWD
tOEA tCAC tOEZ tCAC
tOED tOEZ
DQ3(7) VI/OH VI/OL
tRAC tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
KM44C16004C, KM44C16104C
HYPER PAGE READ WRITE MIXED CYCLE
CMOS DRAM
tRASP
READ(tCAC) READ(tCPA) WRITE READ(tAA)
tHPC
tHPC tCAS tASC
COL. ADDR
tRHCP tHPC tCAS tASC tCAH
tRAD tASR tRAH tASC
tCAS tCAH
tCAS tCAH
tCAH
tASC
COLUMN ADDRESS
ADDR
COLUMN ADDRESS
COL. ADDR
tRAL tRCS
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
tWED
DQ3(7) VI/OH VI/OL
tOEA tCAC tRAC
tWEZ
tWEZ
VALID
DATA-OUT
tCLZ
VALID DATA-IN
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
KM44C16004C, KM44C16104C
ONLY REFRESH CYCLE*
NOTE Dont care DOUT OPEN
CMOS DRAM
tRAS tCRP tRPC tCRP
tASR
tRAH
ADDR
BEFORE REFRESH CYCLE
NOTE Dont care
tRAS
tRPC tCSR tCHR
tRPC
tWRP
tWRH
DQ3(7)
tCEZ OPEN
Dont care Undefined
KM44C16004C, KM44C16104C
HIDDEN REFRESH CYCLE READ
CMOS DRAM
tRAS
tRAS
tCRP
tRCD
tRSH
tCHR
tRAD tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tRCS
tWRH
tOEA tOLZ tCAC tCEZ tREZ tWEZ tOEZ
DATA-OUT
DQ3(7)
tCLZ tRAC OPEN
Dont care Undefined
Hidden refresh cycle 64Mb A-dile B-die, when signal transits from High, valid data off.
KM44C16004C, KM44C16104C
HIDDEN REFRESH CYCLE WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tRAS tCRP
tRCD
tRSH
tCHR
tRAD tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tWCS
tWRP tWCH
tWRH
DQ3(7)
DATA-IN
Dont care Undefined
KM44C16004C, KM44C16104C
BEFORE SELF REFRESH CYCLE
NOTE Dont care
CMOS DRAM
tRASS
tRPS
tRPC tCSR tCHS
tRPC
DQ3(7)
tCEZ OPEN
tWRP
tWRH
TEST MODE CYCLE
NOTE Dont care tRAS tRPC
tRPC tCSR tCHR
tWTS
tWTH
DQ3(7)
tOFF OPEN
Dont care Undefined
KM44C16004C, KM44C16104C
PACKAGE DIMENSION
400mil
CMOS DRAM
Units Inches (millimeters)
0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) 0.018 (0.45) 0.030 (0.75)
0.006 (0.15) 0.012 (0.30)
0.027 (0.69) 0.841 (21.36) 0.820 (20.84) 0.830 (21.08) 0.148 (3.76) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
TSOP(II) 400mil
Units Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25) 0.841 (21.35) 0.821 (20.85) 0.829 (21.05) 0.047 (1.20)
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) 0.012 (0.30) 0.020 (0.50)
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