CMOS DRAM 16bit CMOS Dynamic with Extended Data This family

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CMOS DRAM 16bit CMOS Dynamic with Extended Data This family

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KM416C4004B, KM416C4104B
CMOS DRAM
16bit CMOS Dynamic with Extended Data
This family 4,194,304 Extended Data Mode CMOS DRAMs. Extended Data Mode offers high speed random access memory cells within same row. Refresh cycle(4K Ref. Ref.), access time (-45, optional features this family. this family have CAS-before-RAS refresh, RAS-only refresh Hidden refresh capabilities. This 4Mx16 Mode DRAM family fabricated using Samsungs advanced CMOS process realize high band-width, power consumption high reliability.
FEATURES
Part Identification KM416C4004B(5.0V, Ref.) KM416C4104B(5.0V, Ref.) Active Power Dissipation Unit Speed
Extended Data Mode operation Byte/Word Read/Write operation CAS-before-RAS refresh capability RAS-only Hidden refresh capability Fast parallel test mode capability TTL(5.0V) compatible inputs outputs Early Write output enable controlled write JEDEC Standard pinout Available Plastic TSOP(II) package +5.0V±10% power supply
Refresh Cycles Part KM416C4004B* KM416C4104B Refresh cycle Refresh time Normal 64ms
UCAS LCAS Control Clocks Lower Data Buffer Sense Amps Lower Data Buffer Upper Data Buffer Upper Data Buffer
FUNCTIONAL BLOCK DIAGRAM
Generator
Access mode only refresh mode cycle/64ms CAS-before-RAS Hidden refresh mode cycle/64ms Performance Range Speed
Refresh Timer Refresh Control Refresh Counter
Decoder
Memory Array 4,194,304 Cells
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
74ns 84ns 104ns
tHPC
17ns 20ns 25ns
A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1
Address Buffer Col. Address Buffer Column Decoder
DQ15
Note) Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
KM416C4004B, KM416C4104B
CMOS DRAM
CONFIGURATION (Top Views)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 LCAS UCAS A12(N.C)*
(400mil TSOP(II)) *(N.C) Refresh Product
Name UCAS LCAS
function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) Connection
KM416C4004B, KM416C4104B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT Tstg Rating -1.0 +7.0 -1.0 +7.0 +150
CMOS DRAM
Units
Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced Vss, 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -1.0*2 VCC+1.0*1 Units
VCC+2.0V pulse width20ns which measured -2.0 pulse width20ns which measured
OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.5V, other pins under test=0 Volt) Output Leakage Current (Data disabled, 0VVOUT VCC) Output High Voltage Level(IOH=-5mA) Output Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) Units
KM416C4004B, KM416C4104B
OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM416C4004B ICC1 ICC2 ICC3 Dont care Normal Dont care Dont care Dont care
CMOS DRAM
Units KM416C4104B
ICC4 ICC5 ICC6
Dont care Normal Dont care
ICC1 Operating Current (RAS UCAS, LCAS, Address cycling @tRC=min.) ICC2 Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3 RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4 Extended Data Mode Current (RAS=VIL, UCAS LCAS, Address cycling @tHPC =min.) ICC5 Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6 CAS-Before-RAS Refresh Current (RAS UCAS LCAS cycling @tRC=min)
*Note ICC1 ICC3 ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open.
specified average current. ICC1 ICC3 ICC6, address changed maximum once while RAS=VIL. ICC4 address changed maximum once within mode cycle time tHPC
KM416C4004B, KM416C4104B
CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)
Parameter Input capacitance A12] Input capacitance [RAS, UCAS, LCAS, Output capacitance [DQ0 DQ15] Symbol CIN1 CIN2
CMOS DRAM
Units
CHARACTERISTICS (0°CTA70°C, note 1,2)
Test condition VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address output Low-Z Output buffer turn-off delay from output Low-Z Transition time (rise fall) precharge time pulse width hold time hold time pulse width delay time column address delay time precharge time address set-up time address hold time Column address set-up time Column address hold time Column address lead time Read command set-up time Read command hold time referenced Read command hold time referenced Write command hold time Write command pulse width Write command lead time Write command lead time Data set-up time Symbol 9,19 3,4,10 3,4,5 3,10 6,21 Units Note
tRWC tRAC tCAC tCLZ tCEZ tOLZ tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL
KM416C4004B, KM416C4104B
CHARACTERISTICS (Continued)
Parameter Data hold time Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time delay time delay time Column address delay time set-up time (CAS -before-RAS refresh) hold time (CAS -before-RAS refresh) precharge time Access time from precharge Hyper Page cycle time Hyper Page read-modify-write cycle time precharge time (Hyper page cycle) pulse width (Hyper page cycle) hold time from precharge access time data delay precharge delay time Output buffer turn delay time from command hold time Write command set-up time (Test mode Write command hold time (Test mode precharge time (C-B-R refresh) hold time (C-B-R refresh) Output data hold time Output buffer turn delay from Output buffer turn delay from data delay hold time hold time precharge time pulse width (Hyper page cycle) pulse width (C-B-R self refresh) precharge time (C-B-R self refresh) hold time (C-B-R self refresh) Symbol 200K 200K
CMOS DRAM
Units 200K
Note 9,19
tREF tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPA tHPC tHPRWC tRASP tRHCP tOEA tOED tCPWD tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
7,15
6,21
22,23,24 22,23,24 22,23,24
KM416C4004B, KM416C4104B
TEST MODE CYCLE
Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address pulse width pulse width hold time hold time Column Address lead time delay time delay time Column Address delay time Hyper Page cycle time Hyper Page read-modify-write cycle time pulse width (Hyper page cycle) Access time from precharge access time data delay command hold time Symbol 200K
CMOS DRAM
Note
Units 3,4,10,12 3,4,5,12 3,10,12 Note
tRWC tRAC tCAC tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
KM416C4004B, KM416C4104B
NOTES
CMOS DRAM
initial pause 200us required after power-up followed RAS-only refresh CAS-before-RAS refresh cycles before proper device operation achieved. VIH(min) VIL(max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. Measured with load equivalent load 100pF. Operation within tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only. tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC Assumes that tRCD tRCD (max). These parameter defines time which output achieves open circuit condition referenced Vol. tWCS tRWD tCWD tAWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min), cycle early write cycle data output will remain high impedance duration cycle. tCWD tCWD (min), tRWD tRWD (min) tAWD tAWD (min), then cycle read-modify-write cycle data output will contain data read from selected address. neither above conditions satisfied, condition data indeterminate. Either tRCH tRRH must satisfied read cycle. These parameters referenced falling edge early write cycles falling edge controlled write cycle read-modify-write cycles. Operation within tRAD (max) limit insures that tRAC (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled tAA. These specifications applied test mode. test mode read cycle, value tRAC tAA, tCAC delayed specified values. These parameters should specified test mode cycles adding above value specified value this data sheet. tASC tCAH referenced earlier falling edge. specified from later rising edge previous cycle earlier falling edge next cycle. tCWD referenced later falling edge word read-modify-write cycle.
KM416C40(1)04B Truth Table
LCAS UCAS Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write
KM416C4004B, KM416C4104B
tCWL specified from falling edge earlier rising edge. tCSR referenced earlier falling edge before transition low. tCHR referenced later rising edge after transition low.
CMOS DRAM
LCAS
UCAS
tCSR
tCHR
specified earlier falling edge specified later falling edge early write cycle. LCAS UCAS
DQ15
tASC 6ns, Assume 2.0ns goes high before high going, open circuit condition output achieved high going. goes high before high going, open circuit condition output achieved high going. tRASS 100us, then precharge time must tRPS instead tRP. RAS-only refresh burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles burst refresh must executed within 64ms before after self refresh, order meet refresh specification. distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should executed with 15.6us immediately before after self refresh order meet refresh specification.
KM416C4004B, KM416C4104B
WORD READ CYCLE
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS tCRP
tCRP
LCAS
tCSH tRCD tRSH tCAS tCRP
tRAD tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tRCS
tRCH tRRH
tOLZ
tOEA tCAC tCLZ tCEZ tOEZ
DATA-OUT
DQ15
tRAC OPEN
tCAC tRAC OPEN tCLZ tOEZ
DATA-OUT
tCEZ
Dont care Undefined
KM416C4004B, KM416C4104B
LOWER BYTE READ CYCLE
NOTE OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tRPC
tCRP
LCAS
tCSH tRCD tRAD tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tASR
tRAH
tASC
ADDRESS
tRCS
tRCH tRRH tCEZ tOEZ tOEA tCAC tCLZ
DATA-OUT
DQ15
tRAC OPEN
tOLZ OPEN
Dont care Undefined
KM416C4004B, KM416C4104B
UPPER BYTE READ CYCLE
NOTE OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS tCRP
tCRP
LCAS
tRPC tRAD tRAL
tASR
tRAH
tASC
tCAH
COLUMN ADDRESS
ADDRESS
tRCS
tRCH tRRH tCEZ tOEZ tOEA tOLZ
DQ15
OPEN tCAC tRAC OPEN tCLZ
DATA-OUT
Dont care Undefined
KM416C4004B, KM416C4104B
WORD WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS
tCSH tRCD tRSH tCAS tRAD
tCRP
tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tWCS
tWCH
DATA-IN
DQ15
DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
LOWER BYTE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCRP
LCAS
tCSH tRCD tRSH tCAS tRAD tCRP
tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tWCS
tWCH
DATA-IN
DQ15
Dont care Undefined
KM416C4004B, KM416C4104B
UPPER BYTE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS tCRP
tCRP
LCAS
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
ADDRESS
tWCS
tWCH
DQ15
DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
WORD WRITE CYCLE CONTROLLED WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS
tCSH tRCD tRSH tCAS tRAD
tCRP
tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tCWL tRWL
tOED
tOEH
DATA-IN
DQ15
DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
LOWER BYTE WRITE CYCLE CONTROLLED WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tRPC
tCRP
LCAS
tCSH tRCD tRSH tCAS tRAD tCRP
tASR
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ADDRESS
tCWL tRWL
tOED
tOEH
DATA-IN
DQ15
Dont care Undefined
KM416C4004B, KM416C4104B
UPPER BYTE WRITE CYCLE CONTROLLED WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCRP
UCAS
tCSH tRCD tRSH tCAS tCRP
tCRP
tCRP
LCAS
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
ADDRESS
tCWL tRWL
tOED
tOEH
DQ15
DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
WORD READ MODIFY WRITE CYCLE
CMOS DRAM
tRWC tRAS
tCRP
UCAS
tRCD
tRSH tCAS
tCRP
LCAS
tRCD tRAD
tRSH tCAS tCSH
tASR
tRAH
tASC
tCAH
ADDR.
COLUMN ADDRESS
tAWD tCWD
tRWL tCWL
tRWD tOEA tOLZ tCLZ tCAC tOED tOEZ
VALID DATA-OUT
VI/OH VI/OL
tRAC
VALID DATA-IN
tOLZ tCLZ tCAC
DQ15 VI/OH VI/OL
tRAC
tOED tOEZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
LOWER-BYTE READ MODIFY WRITE CYCLE
CMOS DRAM
tRWC tRAS
tCRP
UCAS
tRPC
tCRP
LCAS
tRCD
tRSH tCAS
tRAD tCSH tASR tRAH tASC tCAH
ADDR.
COLUMN ADDRESS
tAWD tCWD
tRWL tCWL
tRWD tOEA
tOLZ tCLZ tCAC
VI/OH VI/OL DQ15
tOED tOEZ
VALID DATA-OUT
tRAC
VALID DATA-IN
OPEN
Dont care Undefined
KM416C4004B, KM416C4104B
UPPER-BYTE READ MODIFY WRITE CYCLE
CMOS DRAM
tRWC tRAS
tCRP
UCAS
tRCD
tRSH tCAS
tCRP
LCAS
tRPC
tRAD tCSH tASR tRAH tASC tCAH
ADDR
COLUMN ADDRESS
tAWD tCWD
tRWL tCWL
tRWD tOEA
OPEN tOLZ tCLZ tCAC tOED tOEZ
VALID DATA-OUT
DQ15 VI/OH VI/OL
tRAC
VALID DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE WORD READ CYCLE
CMOS DRAM
tRASP
tCSH tCRP
UCAS
tRHCP tHPC tHPC tCAS tHPC tCAS tCAS
tRCD
tCAS
tCRP
LCAS
tRCD tRAD tRAH tASC
tCAS tCAS
tCAS
tCAS
tREZ
tASR
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
tRRH tRCH
tCPA tCAC tOCH
tCAC tCPA
tCPA tCAC tCHO tOEP
tOEA tOEA tCAC tOEP tDOH
VALID DATA-OUT
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ tCAC
DQ15
tOEP tDOH
VALID DATA-OUT
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOLZ tCLZ
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE LOWER BYTE READ CYCLE
CMOS DRAM
tRASP
tCRP
UCAS
tRPC tCSH tHPC tRCD tCAS tCAS tCAS tHPC tCAS tRHCP tHPC tREZ
LCAS
tASR
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH tASC
COLUMN ADDR
tCAH
COLUMN ADDRESS
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
tRRH tRCH
tCPA tCAC tOCH tOEA tCAC tOEP tDOH
VALID DATA-OUT
tCAC tCPA tCHO tOEP
tCPA tCAC
tOEA
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
DQ15
tOLZ tCLZ OPEN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE UPPER BYTE READ CYCLE
CMOS DRAM
tRASP
tCSH tCRP
UCAS
tRHCP tHPC tHPC tCAS tHPC tCAS tCAS tRPC
tRCD tCAS
tCRP
LCAS
tRPC
tASR
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR.
tASC
tCAH
tREZ
ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
tRRH tRCH
tCPA tCAC tOCH
tCAC tCPA tCHO tOEP
tCPA tCAC
tOEA tOEA
OPEN tCAC tOEP tDOH
VALID DATA-OUT
DQ15
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE WORD WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRASP
tRHCP
tCRP
UCAS
tHPC tRCD tCAS tHPC tRCD tCAS tRAD tCSH tCAS
tHPC tCAS
tRSH tCAS tCRP
tCRP
LCAS
tHPC
tRSH tCAS tRAL
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
DQ15
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE LOWER BYTE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRASP
tRHCP
tRPC tCRP
UCAS
tCRP
LCAS
tHPC tRCD tCAS tRAD tCSH tCAS
tHPC
tRSH tCAS tRAL
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
DQ15
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE UPPER BYTE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRASP
tRHCP
tCRP
UCAS
tHPC tRCD tCAS tCAS
tHPC
tRSH tCAS tRPC
tCRP
LCAS
tRAD tCSH tASR
tRAL tCAH tASC tCAH
tRAH
tASC
tASC
tCAH
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
DQ15
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE WORD READ MODIFY WRITE CYCLE
CMOS DRAM
tRASP
tHPRWC tRSH
tCSH tCRP
tRCD tCAS
tCAS tCAS tCAS
tCRP
UCAS
tCRP
LCAS
tRCD
tCRP
tRAD tRAH tASR
ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tRAL tCAH
tRCS
tCWL tCWD tAWD tRWD
tRCS tCWD tAWD tCPWD tOEA
tRWL tCWL
tOEA tOED tCAC tOEZ tCAC
tOED tOEZ
VI/OH VI/OL
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOED tCAC
DQ15 VI/OH VI/OL
tOEZ
tCAC tOEZ
tOED
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE LOWER BYTE READ MODIFY WRITE CYCLE
CMOS DRAM
tRASP
tHPRWC tRPC
tCSH tCRP
UCAS
tCRP
LCAS
tRCD tCAS tRAD tRAH
tRSH tCAS
tCRP
tASR
ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tCAH
tRAL
tRCS
tCWL tCWD
tRCS
tRWL tCWL tCWD
tAWD tRWD
tAWD tCPWD tOEA tOED tCAC tOEZ tOED
tOEA tCAC tOEZ
VI/OH VI/OL
tRAC
tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
DQ15 VI/OH VI/OL
OPEN
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE MODE UPPER BYTE READ MODIFY WRITE CYCLE
CMOS DRAM
tRASP
tHPRWC tRSH tCAS tRPC
tCSH tCRP
tRCD tCAS
tCRP
UCAS
tCRP
LCAS
tRAD tRAH tASR
ADDR
tASC
COL. ADDR
tCAH
tASC
COL. ADDR
tCAH
tRAL
tRCS
tCWL tCWD
tRCS
tRWL tCWL tCPWD tCWD tAWD
tAWD tRWD
tOEA
tOEA
VI/OH VI/OL
OPEN tOLZ tOED tCAC tOEZ tCAC tOEZ tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOLZ tOED
DQ15 VI/OH VI/OL
tRAC tCLZ
Dont care Undefined
KM416C4004B, KM416C4104B
HYPER PAGE READ WRITE MIXED CYCLE
CMOS DRAM
tRASP
READ(tCAC READ(tCPA WRITE READ(tAA
tHPC
UCAS
tHPC tCAS tHPC tCAS tCAH
tRHCP tHPC tCAS tHPC tCAS
tRCD
tCAS
tCAS tHPC
LCAS
tRAD tASR tRAH tASC
tCAS
tCAS
tCAH
tASC
COLUMN ADDRESS
tCAH
tASC
tASC
tCAH
COL. ADDR
ADDR
COLUMN ADDRESS
COL. ADDR
tRAL tRCS
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
tWED
VI/OH VI/OL
tOEA tCAC tRAC
tWEZ
tWEZ
VALID
DATA-OUT
VALID DATA-IN
VALID DATA-OUT
tREZ
VALID DATA-OUT
DQ15 VI/OH VI/OL
tOEA tCAC tRAC
tWEZ
tWEZ
VALID
DATA-OUT
VALID DATA-IN
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
KM416C4004B, KM416C4104B
ONLY REFRESH CYCLE
NOTE Dont care DOUT OPEN
CMOS DRAM
tRAS tCRP tRPC
UCAS
tCRP
LCAS
tASR
tRAH
ADDR
BEFORE REFRESH CYCLE
NOTE Dont care
tRAS tRPC tCSR tCHR
tRPC
UCAS
LCAS
tCSR
tCHR
DQ15
tCEZ OPEN
OPEN tWRP tWRH
Dont care Undefined
KM416C4004B, KM416C4104B
HIDDEN REFRESH CYCLE READ
CMOS DRAM
tRAS
tRAS
tCRP
UCAS
tRCD
tRSH
tCHR
tCRP
LCAS
tRCD tRAD
tRSH
tCHR
tASR
tRAH
tASC
tCAH
COLUMN ADDRESS
ADDRESS
tRCS
tWRH
tRAL
tOEA tCEZ tREZ tWEZ tOLZ tOEZ
DATA-OUT
tCAC tCLZ
tRAC OPEN
DQ15
OPEN
DATA-IN DATA-OUT
Dont care Undefined
Hidden refresh cycle 64Mb A-die B-die, when signal transits from High, valid data off.
KM416C4004B, KM416C4104B
HIDDEN REFRESH CYCLE WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tRAS
tCRP
UCAS
tRCD
tRSH
tCHR
tCRP
LCAS
tRCD
tRSH
tCHR
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
ADDRESS
tWRH tWCS
tWRP tWCH
DATA-IN
DQ15
DATA-IN
Dont care Undefined
KM416C4004B, KM416C4104B
BEFORE SELF REFRESH CYCLE
NOTE Dont care
CMOS DRAM
tRASS
tRPS
tRPC
UCAS
tRPC tCSR tCHS
LCAS
tCSR
tCHS
DQ15
tCEZ OPEN
OPEN tWRP tWRH
TEST MODE CYCLE
NOTE Dont care
tRAS
tRPC tCSR tCHR
tRPC
UCAS
LCAS
tCSR
tCHR
tWTS tCEZ
tWTH
DQ15
OPEN
Dont care Undefined
KM416C4004B, KM416C4104B
PACKAGE DIMENSION
TSOP(II) 400mil
CMOS DRAM
Units Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25)
0.841 (21.35) 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) 0.010 (0.25) 0.018 (0.45) 0.030 (0.75)
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05) 0.010 (0.25) 0.018 (0.45)

CMOS DRAM 16bit CMOS Dynamic with Extended Data This family

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