CMOS DRAM 4bit CMOS Dynamic with Fast Page Mode This family
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KM44C16000C, KM44C16100C
CMOS DRAM
4bit CMOS Dynamic with Fast Page Mode
This family 16,777,216 Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access memory cells within same row. Refresh cycle(4K Ref. Ref.), access time(-5 -6), package type(SOJ TSOP-II) optional features this family. this family have CAS-before-RAS refresh, RAS-only refresh Hidden refresh capabilities. This 16Mx4 Fast Page Mode DRAM family fabricated using Samsungs advanced CMOS process realize high band-width, power consumption high reliability.
FEATURES
Part Identification KM44C16000C(5.0V, Ref.) KM44C16100C(5.0V, Ref.)
Fast Page Mode operation CAS-before-RAS refresh capability RAS-only Hidden refresh capability Fast parallel test mode capability TTL(5.0V) compatible inputs outputs Early Write output enable controlled write JEDEC Standard pinout Available Plastic TSOP(II) packages +5.0V±10% power supply
Active Power Dissipation Unit Speed
Refresh Cycles Part KM44C16000C* KM44C16100C Refresh cycle Refresh time Normal 64ms
Control Clocks
FUNCTIONAL BLOCK DIAGRAM
Generator
Refresh Control Refresh Counter Memory Array 16,777,216 Cells
Sense Amps
Access mode only refresh mode cycle/64ms CAS-before-RAS Hidden refresh mode cycle/64ms Performance Range Speed
Refresh Timer
Decoder Data Buffer Data Buffer
tRAC
50ns 60ns
tCAC
13ns 15ns
90ns 110ns
35ns 40ns
A0~A12 (A0~A11)*1 A0~A10 (A0~A11)*1
Address Buffer Col. Address Buffer Column Decoder
Note) Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
KM44C16000C, KM44C16100C
CMOS DRAM
CONFIGURATION (Top Views)
KM44C160(1)00CK
KM44C160(1)00CS
A12(N.C)*
A12(N.C)*
400mil SOJ)
400mil TSOP(II))
(N.C) Refresh product
Name
Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) Connection
KM44C16000C, KM44C16100C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT Tstg Address Rating -1.0 +7.0 -1.0 +7.0 +150
CMOS DRAM
Units
Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced Vss, 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -1.0*2 VCC+1.0
Units
VCC+2.0V pulse width20ns which measured -2.0 pulse width20ns which measured
OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.5V, other pins under test=0 Volt) Output Leakage Current (Data disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) Units
KM44C16000C, KM44C16100C
OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM44C16000C ICC1 ICC2 Dont care Normal Dont Care Dont Care KM44C16100C
CMOS DRAM
Units
ICC3
Dont care
ICC4 ICC5 ICC6
Dont care Normal Dont care
ICC1* Operating Current (RAS CAS, Address cycling @tRC=min.) ICC2 Standby Current (RAS=CAS=W=VIH) ICC3* RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4* Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* CAS-Before-RAS Refresh Current (RAS cycling @tRC=min)
*Note ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open.
specified average current. ICC1, ICC3 ICC6, address changed maximum once while RAS=VIL. ICC4, address changed maximum once within fast page mode cycle time, tPC.
KM44C16000C, KM44C16100C
CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)
Parameter Input capacitance A12] Input capacitance [RAS, CAS, Output capacitance [DQ0 DQ3] Symbol CIN1 CIN2
CMOS DRAM
Units
CHARACTERISTICS (0°CTA70°C, note 1,2)
Test condition VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.4V Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address output Low-Z Output buffer turn-off delay Transition time (rise fall) precharge time pulse width hold time hold time pulse width delay time column address delay time precharge time address set-up time address hold time Column address set-up time Column address hold time Column address lead time Read command set-up time Read command hold time referenced Read command hold time referenced Write command hold time Write command pulse width Write command lead time Write command lead time Data set-up time Data hold time Symbol 3,4,10 3,4,5 3,10 Units Note
tRWC tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL
KM44C16000C, KM44C16100C
CHARACTERISTICS (Continued)
Parameter Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time delay time delay time Column address delay time precharge delay time set-up time (CAS -before-RAS refresh) hold time (CAS -before-RAS refresh) precharge time Access time from precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time precharge time (Fast Page cycle) pulse width (Fast Page cycle) hold time from precharge access time data delay Output buffer turn delay time from command hold time Write command set-up time (Test mode Write command hold time (Test mode precharge time (C-B-R refresh) hold time (C-B-R refresh) pulse width (C-B-R self refresh) precharge time (C-B-R self refresh) hold time (C-B-R self refresh) Symbol 200K
CMOS DRAM
Units 200K
Note
tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPRWC tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS
13,14,15 13,14,15 13,14,15
KM44C16000C, KM44C16100C
TEST MODE CYCLE
Parameter Random read write cycle time Read-modify-write cycle time Access time from Access time from Access time from column address pulse width pulse width hold time hold time Column Address lead time delay time delay time Column Address delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time pulse width (Fast Page cycle) Access time from precharge access time data delay command hold time Symbol 200K 200K
CMOS DRAM
Note
Units 3,4,10,12 3,4,5,12 3,10,12 Note
tRWC tRAC tCAC tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPRWC tRASP tCPA tOEA tOED tOEH
KM44C16000C, KM44C16100C
NOTES
CMOS DRAM
initial pause 200us required after power-up followed RAS-only refresh CAS-before-RAS refresh cycles before proper device operation achieved. VIH(min) VIL(max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. Measured with load equivalent load 100pF. Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Assumes that tRCDtRCD(max). tOFF(min)and tOEZ(max) define time which output achieves open circuit condition referenced Vol. tWCS, tRWD, tCWD tAWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCStWCS(min), cycle early write cycle data output will remain high impedance duration cycle. tCWDtCWD(min), tRWDtRWD(min) tAWDtAWD(min), then cycle read-modify-write cycle data output will contain data read from selected address. neither above conditions satisfied, condition data indeterminate. Either tRCH tRRH must satisfied read cycle. These parameters referenced falling edge early write cycles falling edge read-modify-write cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit, then access time controlled tAA. These specifications applied test mode. test mode read cycle, value tRAC, tAA, tCAC delayed specified values. These parameters should specified test mode cycles adding above value specified value this data sheet. tRASS100us, then precharge time must tRPS instead tRP. RAS-only refresh burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles burst refresh must executed within 64ms before after self refresh, order meet refresh specification. distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should executed with 15.6us immediately before after self refresh order meet refresh specification.
KM44C16000C, KM44C16100C
READ CYCLE
CMOS DRAM
tRAS
tCSH tCRP
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
tRAH
tASC
ADDRESS
tRCS
tRCH tRRH tOFF tOEZ tOEA tCAC
DQ3(7)
tRAC OPEN
tCLZ
DATA-OUT
Dont care Undefined
KM44C16000C, KM44C16100C
WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCSH tCRP
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
tRAH
tASC
ADDRESS
tCWL tRWL tWCS
tWCH
DQ3(7)
DATA-IN
Dont care Undefined
KM44C16000C, KM44C16100C
WRITE CYCLE CONTROLLED WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tCSH tCRP
tRCD tRAD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tASR
tRAH
tASC
ADDRESS
tCWL tRWL
tOED
tOEH
DATA-IN
DQ3(7)
Dont care Undefined
KM44C16000C, KM44C16100C
READ MODIFY WRTIE CYCLE
CMOS DRAM
tRWC tRAS
tCRP
tRCD tRAD tRAH
tRSH tCAS tCAH tCSH
tASR
tASC
COLUMN ADDRESS
ADDR
tAWD tCWD
tRWL tCWL
tRWD tOEA tCLZ tCAC
DQ3(7) VI/OH VI/OL
tRAC
tOED tOEZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
KM44C16000C, KM44C16100C
FAST PAGE READ CYCLE
CMOS DRAM
tRASP
tRHCP
tCRP
tRCD tCAS tRAD tASC tCSH tCAH
COLUMN ADDRESS
tCAS
tRSH tCAS
tASR
ADDR
tRAH
tASC
tCAH
tASC
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
tRCH
tRCS
tRAL tRCS
tRRH tRCH
tCAC tOEA
tCAC tOEA
tCAC tOEA
DQ3(7)
tRAC tCLZ
tOEZ
VALID DATA-OUT
tOFF tCLZ
tOEZ
VALID DATA-OUT
tOFF tCLZ
VALID DATA-OUT
tOFF tOEZ
Dont care Undefined
KM44C16000C, KM44C16100C
FAST PAGE WRITE CYCLE EARLY WRITE
NOTE DOUT OPEN
CMOS DRAM
tRASP
tRHCP
tCRP
tRCD tCAS tRAD tASC
tCAS
tRSH tCAS tRAL
tASR
tRAH
tCSH tCAH
COLUMN ADDRESS
tASC
tCAH
tASC
tCAH
ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
tWCH tCWL
tWCS
tWCH
tWCS
tWCH tCWL tRWL
tCWL
DQ3(7)
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
Dont care Undefined
KM44C16000C, KM44C16100C
FAST PAGE READ MODIFY WRITE CYCLE
CMOS DRAM
tRASP
tCSH tRCD tRSH tCAS tRAD tRAH tASR tASC
COL. ADDR
tCRP tCAS tPRWC
tCAH
tRAL tASC
COL. ADDR
tCAH
ADDR
tRCS
tRWL tCWL tCWD tAWD tRWD tOEA tOED tCAC tOEZ tCWD tAWD tCPWD tOEA tCAC tOEZ tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tCWL
tOED
DQ3(7) VI/OH VI/OL
tRAC tCLZ
Dont care Undefined
KM44C16000C, KM44C16100C
ONLY REFRESH CYCLE
NOTE Dont care DOUT OPEN
CMOS DRAM
tRAS
tCRP
tRPC
tCRP
tASR
ADDR
tRAH
BEFORE REFRESH CYCLE
NOTE Dont care
tRAS
tRPC tRPC tCSR tWRP tWRH tCHR
DQ3(7)
tOFF OPEN
Dont care Undefined
KM44C16000C, KM44C16100C
HIDDEN REFRESH CYCLE READ
CMOS DRAM
tRAS
tRAS
tCRP
tRCD
tRSH
tCHR
tRAD tASR
tRAH
tASC
tCAH
COLUMN ADDRESS
ADDRESS
tRAL tRCS
tWRH
tOEA tCAC tOFF tOEZ
DATA-OUT
DQ3(7)
tRAC OPEN
tCLZ
Dont care Undefined
KM44C16000C, KM44C16100C
HIDDEN REFRESH CYCLE WRITE
NOTE DOUT OPEN
CMOS DRAM
tRAS
tRAS
tCRP
tRCD tRAD
tRSH
tCHR
tASR
tRAH
tASC
tCAH
COLUMN ADDRESS
ADDRESS
tRAL
tWRH tWRP
tWCS
tWCH
DQ3(7)
DATA-IN
Dont care Undefined
KM44C16000C, KM44C16100C
BEFORE SELF REFRESH CYCLE
NOTE Dont care
CMOS DRAM
tRASS
tRPS tRPC tCHS
tRPC
tCSR
DQ3(7)
tOFF OPEN tWRP tWRH
TEST MODE CYCLE
NOTE Dont care
tRAS
tRPC tRPC tCSR tWTS tWTH tCHR
DQ3(7)
tOFF OPEN
Dont care Undefined
KM44C16000C, KM44C16100C
PACKAGE DIMENSION
400mil
CMOS DRAM
Units Inches (millimeters)
0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) 0.018 (0.45) 0.030 (0.75)
0.006 (0.15) 0.012 (0.30)
0.027 (0.69) 0.841 (21.36) 0.820 (20.84) 0.830 (21.08) 0.148 (3.76) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
TSOP(II) 400mil
Units Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25) 0.841 (21.35) 0.821 (20.85) 0.829 (21.05) 0.047 (1.20)
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) 0.012 (0.30) 0.020 (0.50)
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