Matthew Short Security Applications matt.short@motorola.com

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MPC185HWRM Rev. 2.3, 8/2003 MPC185 Hardware Reference Manual
Matthew Short Security Applications
matt.short@motorola.com
This document describes design system with MPC185 MPC8260 MPC107. describes pertinent electrical physical characteristics MPC185; functional characteristics processor, refer MPC185 Security Co-Processor User's Manual. This document contains following topics: Topic Section "Overview" Section "System Architecture" Section "Pin Assignments" Section "Signal Descriptions" Section "Pin Connections" Section "Electrical Thermal Characteristics" Section "Package Description" Section "Document Revision History" Page
locate published errata updates this document, refer site
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Overview
Overview
MPC185 flexible powerful addition networking computing system using Motorola PowerQUICC IIline integrated communications processors, system supporting protocol. MPC185 designed offload computational intensive security functions, such generation exchange, authentication, bulk encryption from host PowerPCprocessor. MPC185 optimized process algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS. addition, Motorola family security co-processors only devices market capable executing elliptic curve cryptography, which especially important secure wireless communications. MPC185 features include following: public-key execution units (PKEUs) that support following: Diffie-Hellman Programmable field size 2048 bits Elliptic curve cryptography F(p) modes Programmable field size bits Data Encryption Standard execution units (DEUs) DES, 3DES Two-key (K1, three-key (K1, modes both 3DES Advanced Encryption Standard units (AESUs) Implements Rijndael symmetric-key cipher Implements ECB, CBC, counter modes four execution unit (AFEU) Implements stream cipher compatible with algorithm 128-bit programmable message digest execution units (MDEUs) SHA-1 with 160- 256-bit message digest with 128-bit message digest HMAC with either algorithm Kasumi execution unit 3GPP systems (KEU) Implements algorithm encryption algorithm authentication random number generator (RNG) compliant external interface, with master/slave logic 32-bit address/64-bit data operation Four crypto-channels, each supporting multi-command descriptor chains Static and/or dynamic assignment crypto-execution units integrated controller Buffer size Kbytes each execution unit, with flow control large data sizes Kbytes internal scratchpad memory key, context storage 1.5-V core power supply, 3.3-V 2.5-V BGA, package body size
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System Architecture
System Architecture
MPC185 designed integrate easily into system using protocol. MPC185 ideal system using Motorola PowerQUICC communications processor shown Figure PowerPC processor memory controller. ability MPC185 master bus, allows co-processor offload data movement bottleneck normally associated with slave devices. external processor accesses MPC185 through device drivers using system memory data storage. MPC185 resides memory processor; therefore, when application requires cryptographic functions, simply creates descriptors MPC185 which define cryptographic function performed location data. MPC185 60x-mastering capability permits host processor crypto-channel with short register writes, leaving MPC185 perform reads writes system memory complete required task.
EEPROM
MPC185
MPC8265
Local
Main Memory
SRAM Network Interface
Figure 2-1. MPC185 Connected PowerQUICC
Figure shows configuration with MPC185 communicating with host processor using bridge, such MPC107.
MPC7xx, MPC74xx
MPC185
MPC107 Bridge Local
Main Memory
Network Interface Card
Application
Network Interface Card
Figure 2-2. MPC185 Connected Host using Bridge
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Assignments
Assignments
MPC185 assignments shown Table
Table MPC185 Diagram
TSIZ0 TSIZ1
TBST AACK
CLAIM Bypass
BASE3
RESET TRST
TSIZ3
TSIZ2
BASE4 BASE2 BASE1 BASE0 XLBCL KMODE MODE Range
ARTRY
AVSS
AVDD
S_DBG M_DBG
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Signal Descriptions
Signal Descriptions
Table provides pinout listing package. over signal name indicates that signal active low-for example, AACK ABB. Active-low signals referred asserted (active) when they negated when they high.
Table Descriptions
Signal Name Locations Signal Type Signals A[0:31] address bus-When MPC185 master, these signals function address system memory controller. When MPC185 slave, these address signals decoded internally address individual modules. Description
AACK
address acknowledge-A slave asserts this signal indicate that identified address tenure. Assertion this signal terminates address tenure. address busy-The MPC185 asserts this signal duration address tenure. Following AACK, which terminates address tenure, MPC185 negates fraction cycle then stops driving this signal. Address parity-The master that drives address also drives address parity signals. value driven address parity signal should give parity (odd number ones) group signals that represents. address retry-Assertion this signal indicates that transaction should retried master. Base address select-These bits initial base address MPC185 address upper bits 32-bit address range. After reset base address reprogrammed anywhere address space software. example, BASE[0:4] 00001, initial base address Talos 0x0800_0000. grant-The external arbiter asserts this signal grant ownership MPC185. request-The MPC185 asserts this signal request ownership bus. Cache inhibit-Programmable signal which indicates whether transaction should cached not. Assertion indicates that transaction should cached.
AP[0:3]
ARTRY BASE[0:4]
C15, C14, C13, A14,
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Signal Descriptions Table Descriptions (continued)
Signal Name D[0:63] Locations H16, H15, J16, J15, J14, K16, K15, K14, L16, L15, M16, M15, M14, N16, N15, N14, P16, P15, R16, R15, R14, T16, T15, T14, P13, P12, R13, R12, R11, T13, T12, T11, Signal Type Description data bus-In write transactions master drives valid data this bus. read transactions slave drives valid data this bus.
data busy-The MPC185 asserts this signal duration data tenure. Following which terminates data tenure, MPC185 negates fraction cycle then stops driving this signal. data parity-The agent that drives data also drives data parity signals. value driven data parity signal should give parity (odd number ones) group signals that represents. Global-Assertion this signal master indicates that transfer global should snooped caches system. Interrupt request-Interrupt signal that indicates that modules asserted hardware interrupt indicate that service needed system. Local claim-Indicates that slave claims transaction responsible driving during data tenure. data grant-The system arbiter asserts this signal grant data ownership MPC185. Asynchronous reset-All registers reset immediately. Upon release RESET, MPC185 will automatically clear locations internal general purpose RAM. Slave data grant-Indicates that MPC107 granted slave data that slave data transfer data processor. Transfer acknowledge-Indicates that data beat valid data bus. single-beat transfers, assertion this signal indicates termination transfer. burst transfers, asserted four times indicate transfer four data beats, with last assertion indicating termination burst transfer.
DP[0:7]
H14, L14, P14, P11,
LBCLAIM MDBG RESET
SDBG
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Signal Descriptions Table Descriptions (continued)
Signal Name TBST Locations Signal Type Description transfer burst-The master asserts this signal indicate that current transaction burst transaction (transfers four double words). Transfer error acknowledge-Assertion this signal indicates error. transfer start-Assertion this signal indicates beginning address tenure. arbiter asserts this signal slave begin address tenure. When arbiter senses this being asserted external master, will respond address tenure required. transfer size-The master drives these pins with value indicating quantity bytes transferred current transaction. transfer type-The master drives these pins during address tenure specify type transaction. Write through-The state this indicates whether transaction should cached using write-through copy-back mode. Assertion indicates that transaction should cached using write-through mode. Miscellaneous Signals XLBCLKMODE local clock mode-This input should tied high external core clock system clock ratio higher. should tied ratio 1.5:1. local mode-This input should tied high when MPC185 connected MPC8260 Harrier when connected MPC107. Scan enable-For manufacturing test only. This input should always tied low. range (OVSS) 66-100 band (OVDD) 33-66 band operating slower than MHz, must disabled using bypass (D11). Bypass (OVSS) disabled (OVDD) enabled System clock Test analog-This must have connection Test Clock-If JTAG used, this should tied VSS. Test Reset-If JTAG used, this should tied VSS. Test Mode Select-If JTAG used, this should tied OVDD. Test Input-If JTAG used, this should tied OVDD. Test output-If JTAG used, this should
TSIZ[0:3] TT[0:4]
XLBMODE
Range
Bypass
TRST
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Signal Descriptions Table Descriptions (continued)
Signal Name Locations C11, E14, Signal Type connection Powers Grounds OVDD N10, N11, N12, N13, M13, L13, K13, J13, H13, G13, F13, E13, D13, D12, D10, M10, M11, M12, L12, K12, J12, H12, G12, F12, E12, E11, E10, F10, F11, G10, G11, H10, H11, J10, J11, K10, K11, L10, supply voltage Description
IVDD
Core voltage
Ground
AVDD AVSS
Analog supply voltage (+1.5 Analog ground
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Connections
Connections
Table shows connections MPC8260 MPC107.
Table Connections
Signal Name Locations MPC8260 Connection Signals A[0:31] A[0:31] C15, C14, C13, A14, AACK AP[0:3] ARTRY Implementation-specific EXT_BG2, EXT_BG3 EXT_BR2, EXT_BR3 A[0:31] MPC107 Connection
AACK
AACK Pull OVDD pull down ARTRY Implementation-specific BG_0, BG_1 BR_0, BR_1
AP[0:3] ARTRY BASE[0:4] D[0:63]
used, this should tied OVDD D[0:63]
H16, H15, J16, J15, J14, K16, D[0:63] K15, K14, L16, L15, M16, M15, M14, N16, N15, N14, P16, P15, R16, R15, R14, T16, T15, T14, P13, P12, R13, R12, R11, T13, T12, T11, T7,.
DP[0:7] LBCLAIM MDBG RESET SDBG TBST
DP[0:7] IRQ_x LBCLAIM DBG_0, DBG_1
H14, L14, P14, P11, DP[0:7] IRQ_x DBG, EXT_DBG2, EXT_DBG3 Implementation-specific CPU_DBG TBST
DBG_LB TBST
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Connections Table Connections
Signal Name TSIZ[0:3] TT[0:4] Locations TSIZ[0:3] TT[0:4] MPC8260 Connection VSS, TSIZ[0:2] TT[0:4] MPC107 Connection
used, this should tied OVDD Miscellaneous Signals
XLBCLKMODE
This input should tied high external core clock system clock ratio higher ratio 1.5:1 This input should tied high when MPC185 connected MPC8260 Harrier when connected MPC107 This should tied range (OVSS) 66-100 band (OVDD) 33-66 band operating slower than MHz, must disabled using bypass (D11). Bypass (OVSS) disabled (OVDD) enabled Implementation-specific This must have connection JTAG used, this should tied JTAG used, this should tied JTAG used, this should tied OVDD JTAG used, this should tied OVDD JTAG used, this should
XLBMODE Range
Bypass
TRST
C11, E14,
Powers Grounds AVDD AVSS N10, N11, N12, N13, M13, L13, K13, J13, H13, G13, F13, E13, D13, D12, D10, M10, M11, M12, L12, K12, J12, H12, G12, F12, E12, E11, E10, F10, F11, G10, G11, H10, H11, J10, J11, K10, K11, L10, (+1.5
MPC107 only TSIZ pins, TSIZ[0:2]. These pins MPC185 pins TSIZ[1:3], while TSIZ[0] MPC185 must grounded.
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Electrical Thermal Characteristics
Electrical Thermal Characteristics
electrical thermal characteristics addressed this section. Topics include absolute maximum ratings, package thermal characteristics, operating conditions electrical characteristics, timing characteristics, IEEE 1149.1 timing specifications.
Absolute Maximum Ratings
Table Absolute Maximum Ratings
Characteristic Name VDDQ Absolute -0.5 -0.5 -0.5 Absolute +2.0 +4.1 +125 +4.1 Unit
Power supply voltage-core Power supply voltage-I/O
Storage temperature Static input voltage
Note: VDDQ must exceed more than time. Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted RECOMMENDED OPERATING CONDITIONS. Exposure higher than recommended voltages extended periods time could affect device reliability. This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high-impedance circuit.
Package Thermal Characteristics
Table Package Thermal Characteristics
Rating Symbol Single-layer board Four-layer board Unit Notes
Table shows thermal resistances 256-pin MBGA package.
Junction-to-ambient ft/min) Junction-to-board (bottom) Junction-to-case (top)
°C/W °C/W °C/W
Notes: Junction temperature function on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, board population, board thermal resistance. SEMI G38-87 Indicates average thermal resistance between printed circuit board. Indicates average thermal resistance between case surface cold plate method (MIL SPEC-883 Method 1012.1).
Operating Conditions Electrical Characteristics
Table shows operating conditions electrical characteristics MPC185.
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Electrical Thermal Characteristics Table Electrical Operating Conditions
Characteristic Power supply voltage-core Power supply voltage-I/O Input voltage (VDD Min) Input high voltage (VDD Max) supply current (I/O power included) Standby supply current Input leakage current Name VDDQ Ileak 1.35 -0.3 1.65 VDDQ Unit Notes
Three-state input current
Notes: Undershoot: -1.5 tKHKH. Overshoot: (not exceed tKHKH.
Timing Characteristics
Table Electrical Characteristics PowerQUICC
Condition Name Fclock tKHKH tKHQV tKHQX tDVKH tKHDX Unit
Table shows timing specifications with PowerQUICC timings assume 40-pF load.
Clock frequency Clock cycle time Clock-to-signal valid delay Clock-to-signal hold Input setup time clock-bused signals Input hold time clock
Table shows timing specifications with MPC107 other bridge/memory controller. timings assume 15-pF load.
Table Electrical Characteristics Bridge/Memory Controller
Condition Clock frequency Clock cycle time Clock-to-signal valid delay Clock-to-signal hold Input setup time clock-bused signals Input hold time clock Name Fclock tKHKH tKHQV tKHQX tDVKH tKHDX 4.35 Unit
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Electrical Thermal Characteristics
IEEE 1149.1 (JTAG) Timing Specifications
Table IEEE 1149.1 (JTAG) Timing Specifications
Condition Name tTHTH tTLQV tTSRT tDVTH tMVTH tTHDX tTHMX Unit
Table shows IEEE 1149.1 timing specifications MPC185.
cycle time clock high time clock time access time TRST pulse width
Setup times capture
Hold times capture
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Package Description
Package Description
Case Outline Package Dimensions
following sections provide package parameters mechanical dimensions.
Figure Figure show case outline package dimensions.
Figure Case Dimensions
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Document Revision History
Figure Details Case Dimensions
Document Revision History
Table Document Revision History
Rev. Substantive Change(s) Updated Table show active signals. Nontechnical reformatting. Nontechnical reformatting.
Table provides revision history this hardware specification.
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Motorola Stylized Logo registered U.S. Patent Trademark Office. digital trademark Motorola, Inc. PowerPC name trademark Corp. used under license. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2003
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Matthew Short Security Applications matt.short@motorola.com

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