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This errata describes corrections Revision MPC855T User's Manual (Orde
Top Searches for this datasheetMPC855TUMAD Rev. 1.1, 4/2004 Errata MPC855T User's Manual, Rev. This errata describes corrections Revision MPC855T User's Manual (Order MPC855TUM, Rev. MPC855T PowerPCarchitecture-based quad integrated communications controller (PowerQUICCTM). MPC855T MPC8xx core, 32-bit microprocessor that implements PowerPC architecture, incorporating memory management units (MMUs) instruction data caches. Document Revision History Table Document Revision History Rev. Substantive Change(s) Added errata items from Section (page 12-3), Section 12.5 (page 12-28), Section 27.8 (pages 27-13, 27-14), Section 27.22 (page 27-28), Section 30.4.1.2 (pages 30-9, 30-10), Section 31.4.3 (page 31-8), Section 33.1 (page 33-2), Section 43.2.12 (page 43-10). Added errata items from Section 21.2.1 (page 21-9), Section (page 22-1), Section 22.16 (page 22-14), Section 30.4.1.2 (page 30-9), Section B.3.1 (page B-4). Table provides revision history this document. Document Errata Changes right side Figure 12-2, replace `F4-VDDH' with `F4-VDDL.' Remove `T14' from list. second Table 12-5, footnote sentence that states: power-on reset, port states defined particular state until CLKOUT present clocks. section page numbers errata items added since last errata addendum boldfaced. Section/Page 12-3 12.5, 12-28 21.2.1, 21-9 MODE field (bits 28-31) Table 21-2, V.14 microcode supported. Thereby, mode 0111 should `Reserved.' More Information This Product, www.freescale.com Section, Page 21.2.1, 21-9 22-1 22.16, 22-14 27.8, 27-13 27.8, 27-14 Changes MODE field (bits 28-31) Table 21-2, DDCMP microcode supported. Thereby, mode 1001 should `Reserved.' last sentence last paragraph should removed. field (bit Table 22-9, selection second sentence paragraph (making reference V.14 applications) should removed. superscript number after PADDR1_H, PADDR1_M, PADDR1_L. superscript number after TADDR_H, TADDR_M TADDR_L. note bottom Table 27-1 with statement: address should written little endian, Motorola's big-endian format (that physical address 112233445566 should written PADDR_L 6655, PADDR_M 4433, PADDR_H 2211. TADDR should written same PADDR). 27.22, 27-28 30.4.1.2, 30-9 Change last sentence step read, "Then write 0x000E TxBD[Data. last sentence example change order string following: first j_klmn_r_stuv last last sentence example change order string following: first r_stuv_ghij_klmn last Table 31-3, replace text description with following: Division ratio 0-7. Specifies divide ratio divider clock generator. output prescalar divided (DIV FLT)), clock duty cycle. I2MOD register. minimum value digital filter disabled (FLT digital filter enabled (FLT 30.4.1.2, 30-10 31.4.3, 31-8 33.1, 33-2 footnote reference number statement sixth bullet with following footnote: power-on reset, port states defined particular state until CLKOUT present clocks. 43.2.12, 43-10 B.3.1, Change term `60x' first fourth sentences `external.' Table B-1, making reference Profibus should removed. Errata MPC855T User's Manual, Rev. MOTOROLA More Information This Product, www.freescale.com Section, Page Changes THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA Errata MPC855T User's Manual, Rev. More Information This Product, www.freescale.com REACH USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution P.O. 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. 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