This addendum describes corrections MPC8260 PowerQUICC IIFamily Refere

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This addendum describes corrections MPC8260 PowerQUICC IIFamily Refere

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MPC8260UMAD Rev.1.2,4/2004 Erratato MPC8260 PowerQUICC IITMFamily ReferenceManual,Rev
This addendum describes corrections MPC8260 PowerQUICC IIFamily Reference Manual, Revision (Order MPC8260UM). MPC8260 PowerQUICC IIFamily Reference Manual supports devices PowerQUICC IIfamily communications processors. Note that PowerQUICC core documented only partially MPC8260 PowerQUICC IIFamily Reference Manual; errata core documentation found Errata Core Reference Manual. section number page number each errata item provided left margin. Section page numbers errata appear boldface. locate published updates this document, refer world-wide
Document Revision History
Date 4/2004 Substantive Change Added errata items following sections: 4.3.2.1; 4.3.2.2; 5.3; 9.11.2.22; 14.3.5; 15.4.5; 19.7.1; 19.7.1.1; 19.7.2; 19.8.2; 19.8.5; 20.3.6; 29.10.1.1; 30.13.4; 38.4.1.1 Added Document Revision History table this document. Added errata items following sections: 5.3, 5-6; 10.8, 10-9; 11.6.4.2, 11-81; 20.3.6, 20-22; 29.5, 29-8; 30.2.2, 30-7; 30.10.1.3, 30-43; 30.10.5.3, 30-74; 30.10.5.4, 30-76; 30.10.5.5, 30-77; 33.4.3, 33-26,-27; 33.4.1.1, 33-29; 33.4.4.1.1, 33-29; 33.4.4.1.2, 33-30; 33.4.4.2, 33-35 33.4.5.1.2, 33-40; 33.4.7.1, 33.4.10, 33-54; 33.5.4.10, 33-70; 34.2, 34-4; 40-5, 40-10; 40-5, 40-16.
Table provides revision history this errata addendum.
Revision
2/2004
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Section, Page Changes
Document Errata
Changes
Table 4-4, reserved field should bits 8-13 shown Figure 4-10) 8-14. GSIU (group SIU). Table 4-6, descriptions bits 3-31 should appear follows:
3-11 12-15 XC2P-XC4P Same XC1P, XCC2-XCC4 Reserved, should cleared.
following list includes document errata:
Section/Page
4.3.1.1, 4-19
4.3.1.3, 4-21
16-27 28-31
XC5P-XC8P Same XC1P, XCC5-XCC8 Reserved, should cleared.
4.3.1.3, 4-22
Table 4-7, descriptions bits 3-31 should appear follows:
3-11 12-15 YC2P-YC8P Same YC1P, YCC2-YCC8 Reserved, should cleared.
16-27 YC5P-YC8P Same YC1P, YCC5-YCC8 28-31 Reserved, should cleared.
4.3.2.1, 4-28
Figure 4-21, note reset ("Depends reset configuration sequence.") should only apply bits [EBM, ISPS]. other bits cleared reset. definitions should reversed BCR[DAM] Table 4-9. They should appear follows:
Delay masters. Applies masters (CPU, EXT, CPM). This similar BCR[EXDD] with opposite polarity. memory controller asserts cycle following assertion when accessing address space controlled memory controller. memory controller inserts wait state between assertion assertion when accessing address space controlled memory controller.
4.3.2.1, 4-28
4.3.2.2, 4-31
Table 4-10, description PRKM 0010 contains incorrect cross-reference. should state, "See Section 29.7.1, "FCC Function Code Registers (FCRx)."
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
MOTOROLA
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Section, Page 4.3.2.8, 4-38 Changes Table 4-14 reserved field should bits 26-28 shown Figure 4-30), 26-29. (software watchdog enable). Table 5-4, following description CSRE: Note: When core disabled, CSRE must cleared. 5.4.1, 5-10 Table 5-7, following description CS10PC: Note: During reset configuration sequence, BCTL1/CS10 toggles like GPCM, regardless configuration reset configuration word. After reset configuration sequence, BCTL1/CS10 behaves according configuration SIUMCR[CS10PC].
5.3,
7.2.8.1.1, 7-17 Timing Comments
Replace description input assertion with following: Assertion depends whether controller initiate global transactions when address retry mechanism use: controller used cannot initiate global transactions-Assertion must occur least cycle following AACK current transaction; otherwise, assertion occur time during assertion DBB. system withhold assertion indicate that PowerQUICC should insert wait states extend duration data beat. controller initiate global transactions-Assertion must occur least clock cycle following AACK current transaction least clock cycle after ARTRY asserted.
7.2.8.1.2, 7-17 Timing Comments
Replace description output assertion with following: Assertion depends whether controller initiate global transactions when address retry mechanism use: controller used cannot initiate global transactions-Assertion must occur least cycle following AACK current transaction; occurs clock which current data transfer completed. controller initiate global transactions-Assertion must occur least clock cycle following AACK current transaction least clock cycle after ARTRY asserted.
8.4.4.1. 8-24
Replace third sentence paragraph that follows Figure with following (changes appear boldface): assertion ARTRY received cycle first only) assertion data tenure, PowerQUICC ignores first data beat.
MOTOROLA Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 8.4.4.1. 8-24 Changes Replace first sentence paragraph that begins, "Note that system." with following: Note that system must ensure that ARTRY never asserted later than cycle first only assertion controller initiate global transactions, system must ensure that ARTRY never asserted same cycle later then first only assertion TA.) 9.11, 9-30 Replace second paragraph with following: Both configuration memory-mapped internal registers bridge intrinsically little endian described using classic bit-numbering; that lowest memory address contains least-significant byte register, least-significant register.
9.11.1.11, 9-42
second sentence should read follows (changes appear boldface): asserts interrupt machine check only mask error condition (refer Table 9-14) set.
9.11.1.14, 9-45
Table 9-15, descriptions Transaction size, Error source, Valid information should appear follows (changes additions appear boldface):
21-20 Transaction size This size transaction doublewords bytes) (the bridge master only) doublewords doubleword doublewords doublewords source transaction. 0000 External master 0001 master 0101 others reserved.
19-16
Error source
Valid info
When this set, error capture registers (PCI_EACR, PCI_EDCR, PCI_ECCR) contain valid information. Writing this enables capture error error capture registers (PCI_EACR, PCI_EDCR, PCI_ECCR).
9.11.2.22, 9-62
Figure 9-54, reset value misplaced bit. currently shows reset (0000_0000_0001_0000). should show 5-CFG_LOCK-as reset (0000_0000_0010_0000). Figure 10-5, access SCCR[PCI_MODE, PCI_MODCK] (bits should shown read/write (R/W). Bits 25-28 (PCIDF) only read-only bits SCCR.
10.8, 10-8
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
MOTOROLA
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Section, Page 10.8, 10-9 Changes Table 10-2, following description CLPD: Note: When core disabled, CLPD must cleared. 10.10, 10-11 Replace references. Replace second fourth sentences paragraph with following: Internal logic lower voltage source; this considerably reduces power consumption.The VCCSYN value equal internal supply. more information, refer Section 1.2, "Electrical Thermal Characteristics," hardware specifications document available 11.3.1, 11-16 Table 11-4, following description BRx[V]: Note: been selected SDRAM controller valid been (BRx[31] SDRAM controller must invalidated doing following: Disable SDRAM refresh service clearing PSDMR/LSDMR[RFEN]. Wait least 60x-bus clock cycles. Clear BRx[V]. 11.3.3, 11-23 Table 11-8, description PSDMR[RFEN] should state following (changes appear boldface): Indicates that SDRAM needs refresh services. 11.3.3, 11-24 Table 11-8, following description PSDMR[LDOROPRE]: Note: value 0b00 clock cycles) gives longest time while value 0b10 clock cycles) gives least. 11.6.4.2, 11-81 following below "Note that local bus.": Also, note that address multiplexing work, bus, PSDMR[PBI] needs zero. local bus, LSDMR[PBI] needs zero. This means that address multiplexing does work when SDRAM controller same one.
MOTOROLA Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 14.3.5, 14-7 Changes Table 14-2 incorrectly lists IDMA priority levels. IDMA option should appear immediately before emergency priority (not after shown) IDMA option should appear immediately after emergency priority (not priority shown). IDMA option shown correctly last request prioritization peripherals. table should appear follows:
Priority Unchanged IDMA[1-4] emulation (default-option Emergency (from FCCs, MCCs, SCCs) IDMA[1-4] emulation (option Same relative priority IDMA[1-4] emulation (option Request
7-33
priority each IDMA channel programmed independently. RCCR[DRxQP] description Section 14.3.7, "RISC Controller Configuration Register (RCCR)."
14.3.7, 14-10
Table 14-3's description RCCR[ERAM] pertaining HiP4 devices (ERAM 16-19), starting offset additional Kbytes dual-port should 0x4000 (not 0x0000). Also, should read "RAM microcode execution." description should appear follows (changes boldface):
.25-µm (HiP4) devices: ERAM[16-19]. Enable microcode. Configure instructed download process Motorola-supplied microcode package. 0000 Disable microcode program execution from dual-port RAM. (That microcode execution starts address 0x0000 after reset.) following configurations, microcode execution starts address 0x0000 after reset: 0010 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. 0100 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. 0110 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. 1000 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. 1010 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. 1100 Microcode uses first Kbytes dual-port Kbytes starting from 0x4000. following configurations, microcode execution starts address 0x4000 after reset: 0011 Microcode uses Kbytes starting from dual-port address 0x4000. 0101 Microcode uses Kbytes starting from dual-port address 0x4000. 0111 Microcode uses Kbytes starting from dual-port address 0x4000. 1001 Microcode uses Kbytes starting from dual-port address 0x4000. Note: other configurations listed reserved.
ERAM
14.3.10, 14-12
Replace current paragraph with following. Associated with each version microcode number (REV_NUM) that uniquely identifies that specific microcode. This number hard-coded into microcode which stored CPM's internal ROM. power-up, communication processor (CP) reads this number proceeds store into miscellaneous parameter portion CPM's internal dual-port (DPR). user then access this location determine which version
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page Changes microcode contained that device. Table 14-5 describes which microcode version numbers associated with each silicon revision. Also, replace description REV_NUM Table 14-15 with following (changes additions appear boldface):
Base 0x8AF0 REV_NUM Hword Microcode revision number. working with newer silicon than what shown below, consult product page web. .29-µm (HiP3) devices: A.1-0x0001 B.2-0x003B C.2-0x007B .25-µm (HiP4) devices: A.0-0x000D B.1-0x002D C.0-0x002D
15.4.5, 15-15
first third items under `Static routing' bullet, should state rather than TSA. Table 15-5, following definition configuration RFSDx (SIxMR[6-7]) TFSDx (SIxMR[14-15]): frame sync delay used frame sync issued early during last previous frame, data corruption occur subsequent frames. avoid this problem, program 3-bit sync delay.
15.5.2, 15-19
19.7.1, 19-15
Under `Note,' replace following" with following." Then replace bulleted items with following: First, initialize registers, parameter RAM, buffer descriptors ready (TxBD[R]=1) IDMA. Then, write IDMA START command CPCR wait CPCR[FLG] cleared. Then, wait additional clocks. this point, safe program parallel port registers IDMA.
19.7.1.1, 19-16
following: When IDMA external request mode DREQ level-sensitive mode, IDMA requests service whenever DREQ signal active. This true regardless whether IDMA progress. Therefore, whenever IDMA's DREQ active, peripherals with priority lower than IDMA receive service. IDMA priority configured RCCR[DRxQP] and, because DREQ active long periods, systems that configure DREQ level-sensitive must select priority option DRxQP avoid starving other peripherals (see Table 14-2 Table 14-3). more than IDMA given same priority, lower-numbered IDMA priority over higher numbered IDMA. example, both IDMA3 IDMA4 given priority option then IDMA3 will have priority over IDMA4. addition issue described previous paragraph, there another issue consider when IDMA external request mode DREQ level-sensitive mode. When these true external peripheral device
MOTOROLA Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page Changes controlled memory controllers PowerQUICC such GPCM controller, DREQ must negated before tmax prevent DREQ negation from triggering extra IDMA transfer cycle. Refer following figure. Note that CPM_CLK. example shown, CPM_CLK MHz, with approximate clock cycle Therefore, DREQ must negated later than after first rising edge clock after negation peripheral.
19.7.2, 19-17
following note: When DREQ level-sensitive DONE input PowerQUICC system design must ensure that DONE asserted while DREQ also asserted. other words, system must request IDMA service termination same time.
19.8.2, 19-19
Table 19-4, following parameters must initialized user. Their names should appear boldface, other user-initialized parameters elsewhere manual: IBASE, DCM, IBDPTR, DPR_BUF, SS_MAX, STS, DTS, ISTATE. Change description ISTATE Table 19-4 "Internal use. Must cleared before every START_IDMA command."
19.8.5, 19-25
following note after first paragraph: always clears valid IDMA buffer descriptor before setting bits IDSR that cause interrupt core.
20.3.6, 20-22
previous version this document incorrectly stated that, lower left corner Figure20-13, "DPLL Receiver Block Diagram," label "RENC NRZI" should replaced "RENC NRZI." This incorrect. correct change follows: should state "RENC NRZI" "RENC NRZI."
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 29.5, 29-8 Changes Note that previous version this document incorrectly stated that TxBD[R] must twice. Instead, that must twice, stated below: Replace first paragraph with following (changes additions appear boldface): frame being sent FCC, periodically polls next TxBD user requested frame/buffer sent. Polling occurs every serial transmit clocks. polling algorithm depends configuration, shown following equations:
Fast Ethernet: 10BaseT: clocks clocks
user, however, request that begin processing frame/buffer without waiting normal polling time. immediate processing, after setting TxBD[R], transmit-on-demand (TOD) transmit-on-demand register (FTODR) twice activate. only once, frame/buffer will transmitted until next periodic polling request. 29.10.1.1, 29-16 step re-initialization procedure, command issued from CPCR must RESTART_TX, INIT_TX_PARAMS. second paragraph, replace sentence that begins, "The cell includes.," with following (changes appear boldface): cell includes: bytes Acell header, byte HEC, which checked setting FPSMR[HECC] (refer Table 30-47), bytes payload. [Note that description HECC referred above also contained this document errata Section 30.13.2. description shown manual] 30.10.1.3, 30-43
30.2.2, 30-7
Figure 30-23 Table 30-14 shown following:
Field
IMA_EN
UEAD CUAB EVPT
MPC8264 MPC8266 only.
Global. Asserting enables snooping connection tables. should asserted related DMAs will access local bus.
30.10.5.3, 30-74
Table 30-34, alignment column AAL1 ALL5 receive buffers should state "Burst-aligned (recommended)."
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Section, Page 30.10.5.4, 30-76 Changes Table 30-35, description RXDBPTR offset 0x04 should state following (change appears boldface): data buffer pointer. Points first location associated buffer; reside internal external memory. recommended that pointer burst-aligned. 30.10.5.5, 30-77 Table 30-35, description RXDBPTR offset 0x04 should state following (change appears boldface): data buffer pointer. Points first location associated buffer; reside internal external memory. recommended that pointer burst-aligned.
30.10.7, 30-84
0x00 UTOPIAE
Table 30-41, change description UTOPIAE following:
Hword Counts cells dropped result UTOPIA/Aprotocol violations. Violations include following: Parity error error Invalid timing RxSOC. RxClav asserted selected PHY, RxSOC should asserted cycle immediately following assertion RXENB. violation occurs RxSOC asserted that time (that late missing).
30.12.1, 30-87
following beginning section: Cell transfer Adevice (with single multiple PHYs) uses cell-level handshaking defined UTOPIA standards. does pause cell transmission does stop receiving cells from PHY.
30.12.1, 30-87
Figure 30-57, "UTOPIA Master Mode Signals," replace "TxCLAV[3-0]" with "TxCLAV[3-0]/TxClav" "RxCLAV[3-0]" with "RxCLAV[3-0]/RxClav." Table 30-44, make following additions: "/TxClav" "TXCLAV[3-0]" "/RxClav" "RXCLAV[3-0]" cross-reference Section 30.10.7, "UNI Statistics Table," RxPRTY's description.
30.12.1, 30-87
30.12.1.1, 30-88
first bulleted item should read "Direct polling uses CLAV[3-0] with selection using ADD[1-0]." Replace first sentence second bulleted item with following: Single CLAV polling uses Clav ADD[4-0].
30.12.1.1, 30-88
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 30.12.2, 30-89 Changes cross-reference Section 30.10.7, "UNI Statistics Table," RxPRTY's description. following beginning section: UTOPIA slave mode (single multiple PHY), cells transferred using cell-level octet-level handshakes defined UTOPIA standard. allows cell transfer halted paused. master negates TXENB, cell that transmitting halted. master negates RXENB, cell that receiving paused. Note following restriction halting cell transfer: there cannot halt immediately before transfer last data word. There restriction pausing cell transfer.
30.12.2, 30-89
30.13.2, 30-91
Figure 30-59, address should appear follows:
Addr
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11344(FPSMR3)
Addr
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11346 (FPSMR3)
30.13.2, 30-92
Table 30-47, replace description TPRI, TUDC, RUDC, UPLM with following (changes appear boldface):
Transmitter priority. Used adjust default priority transmitter. strongly recommended TPRI when multi-PHY mode, single-PHY mode maximal rate (either internal external rate) higher than that other FCCs; other modes, should remain cleared. Default operation Prevents elevation emergency mode Refer Table 14-2. Transmit user-defined cells Regular 53-byte cells (Disable this mode support1) User-defined cells Receive user-defined cells Regular 53-byte cells (Disable this mode support1) User-defined cells UTOPIA polling mode. Single Clav polling. Polling done using Add[4-0] Clav. Selection done using Add[4-0]. PHYs polled. Direct polling. Polling done using Clav[3-0]. Selection done using Add[1-0]. PHYs polled. Receive check check Check HEC. errors reported UTOPIAE counter (see Section 30.10.7, "UNI Statistics Table"). This option used only UTIPIA 8-bit data size.
TPRI
TUDC
RUDC
UPLM
HECC
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Section, Page 30.13.3. 30-94
TIRU
Changes Table 30-48, replace description TIRU with following:
Transmit internal rate underrun. cumulative seven cells formed between programmable rate actual rate specific PHY. transmit internal rate counter expired cell sent, either because slow performance slow performance. TIRU only when using transmit internal rate mode; Section 30.13.4, "FCC Transmit Internal Rate Registers (FTIRRx) (FCC1 FCC2 Only)."
30.13.4, 30-94
following note beginning this section: source clock internal rate timers clock, which configured CMXUAR (refer Section 16.4.1, "CMX UTOPIA Address Register"). frequency this clock must less than half clock UTOPIA interface.
30.13.4, 30-94
Replace first paragraph with following (updated portion boldface): first four devices (address FCC1 FCC2 have their transmit internal rate registers (FTIRRx_PHY0-FTIRRx_PHY3) transmit internal rate mode. this mode, total transmission rate determined internal rate timers. master, controller only polls PHY's Clav status rate determined internal rate. slave, controller attempts insert cells into FIFO internal rate. controller handle seven cells between programmable actual rate. When cell count mismatch reaches seven, TIRU event reported, Section 30.13.3, "AEvent Register (FCCE)/Mask Register (FCCM)". Note that mismatch occurs rate performance lower then internal rate. FTIRRx, shown Figure 30-61, includes initial value internal rate timer. source clock internal rate timers supplied four baud-rate generators selected CMXUAR; Section 16.4.1, "CMX UTOPIA Address Register (CMXUAR)". Note that slave mode, FTIRRx_PHY0 used regardless slave address.
30.13.4, 30-95,
Under "Example" replace second sentence equation with following (changes appear boldface): clock MHz, should programmed divide clock generate cell transmit requests every system clocks:
66MHz 155.52Mbps
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 33.3.2.1, 33-13 Changes After last paragraph Section 33.3.2.1, following section:
33.3.2.1.1 Service Latency
NOTE functionality described this section available only with latest microcode package. This optional feature allows user change behavior upon request. When enabled request will pass programmable number cells queue links group. This used order suppress from consuming large amount bandwidth before another cell transmitted. request normally places cell queue links where group contains links; after this happens then non_TRL link free pass cell over UTOPIA interface. delay long some cases layer FIFO underrun. This feature used ensure that non-TRL requests handled same manner-one cell cell transmit queues. non-TRL requests will also trigger iterations when this feature enabled. When using this feature, depth transmit queue must equal non-TRL queues. 33.4.3, 33-26,-27
0x68 0x6C ITPGRPO
Delete last Table 33-3 following rows bottom:
Hword Reserved. Must programmed zero during initialization. Required optional Service Latency enhancement only. Temp Group Order Points base 2byte temp pointer storage group. Software initialized before enabled. Microcode managed parameter. Reserved. Must programmed zero during initialization.
0x6E-0x7F
33.4.1.1, 33-29
0x0E IASNCCTR
following rows bottom Table 33-5:
Byte Required optional Service Latency enhancement only. Scheduled Number Cells Counter Number cells passed groups links upon request. Initialize IASNC. Required optional Service Latency enhancement only. Scheduled Number Cells reset IASNCtr. Number cells passed groups links upon request. Recommended value
0x0F
IASNC
Byte
33.4.4.1.1, 33-29
ISIE Figure 33-14 Table 33-6, shown following:
Field
TXSC
ISIE
ICPC
ISIE
Required optional Service Latency enhancement only. Scheduler Split Iterations Enable split, completes round robin distribution cells. split, both non-TRL requests distribute cells transmit queues.
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Section, Page Changes
33.4.4.1.2, 33-30
TRQS Figure 33-15 Table 33-7, shown following:
Field
TSTF
TIMSTF
TRQS
ICPCA
flag requested times before round robin distribution completed link will underrun still cell from round robin distribution. Microcode managed parameter initialize Used optional Service Latency enhancement only. Request requested therefore round robin distribution cells completed. Microcode managed parameter initialize Used optional Service Latency enhancement only.
TRQS
33.4.4.2, 33-35
Table 33-10 replace descriptions offsets 0x2C 0x30 with
following:
0x2C 0x30 LINK_DCBO Word Word Reserved. Must initialized zero group startups. Link overflow interrupt indication. array identifying which links have issued link overflow (DCBO) interrupt. This parameter ensures that only DCBO interrupt generated event. Microcode managed parameter. Initialize zero group startup.
33.4.5.1.2, 33-40
Figure 33-22 Table 33-17, shown following:
Field
LSTF
LIMSTF
LSTLFIP
LGSU
TQSU
Link Cell. Link cell from round robin distribution. Microcode managed parameter initialize Used optional Service Latency enhancement only.
33.4.7.1,
Offset Figure 33-29 Table 33-23, shown following:
OFFSET
DCBO IFSD IFSW
OFFSET
synchronization lost. This interrupt issued when link group with IGRSTATE[GDSS] loses synchronization, link enters HUNT state IFSM.
Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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Section, Page 33.4.10, 33-54 following section: Changes
33.4.10 Changing Version
CPCR command been added microcode change version on-the-fly without software intervention. following procedure: Before issuing command, user should initialize COMM_INFO fields parameter described Figure 33-31. issue this command, refer Section 20.4, "Command Set." opcode 1101 (0xD).
0x86
Filler
0x88 0x8A
Figure 33-31. COMM_INFO Field
Offset 0x86
Bits
Name Reserved, should cleared.
Description
9-11 12-15 0x88 0x8A
transmit group. Program group number [0-7] multiplied bytes. example, group number program 0x30. Reserved, should cleared.
0-15 Filler Filler cell CRC. 0xC602 (for version 1.0) 0xD902 (for version 1.1) 0-13 14-15 Reserved, should cleared. version Reserved version Reserved version
Wait CPCR[FLG] cleared before issuing command. Refer Section 20.4, "Command Set." 33.5.4.5.1, 33-65 order steps incorrect. Current step ("Use group order table.") should immediately follow current step ("Software should wait."). Therefore, current step becomes step current step becomes step Replace with following:
33.5.4.10, 33-70
(Group Delay Synchronized)-Group delay synchronized achieved group delay synchronized achieved. some cases, possible complete. complete link experiences problems during process example losing SYNC state IFSM. this occurs, possible determine links true differential delay with respect other member links group. order determine process completed successfully, microcode will IGRSTATE[GDSS] either following values after interrupt been generated:
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Section, Page Changes IGRSTATE[GDSS] process failed, link lost IFSM SYNC during process IGRSTATE[GDSS] process completed Software then read IGRSTATE[GDSS] this status information before deciding whether change links active state resynchronize again group level. addition above status information, ILRSTATE[ADD_NEW_M] link that caused failure process will flipped such that logically inverted with respect ILRCNTL[ADD_NEW] bit. recommended however, that software, after failure when restarting process, changes links group group unassigned state then update link group parameters their default values before starting process again. Note that link losing SYNC during process cause DCBO interrupt other links group. this situation occurs, process should restarted described above. (DCB Synchronization Lost)-Indicates that link group with IGRSTATE[GDSS] loses synchronization enters HUNT state IFSM. When this interrupt occurs, link should removed software, will longer perform automatic LASR procedure. Note that when interrupt generated, ILRSTATE[DL] set, software should clear group link receive state information described above interrupt. 34.2, 34-4 35.19, 35-27 center Figure 34-2 "DBB bus" should replaced with "60x bus." Replace second paragraph after Table 35-10 with following: receive buffer pointer, which points first location associated data buffer, reside external memory. This value must divisible 38.4.1.1, 38-10 Example representation data transmitted when should appear follows (changes appear boldface):
with REV=0, string transmitted, byte time with first first nmlk_jihg_vuts_r last
with REV=1, string half-word reversed: nmlk_jihg_vuts_r
transmitted byte time with first: first r_stuv_ghij_klmn last
39.4.3, 39-8
Table 39-3, description should read follows (changes appear boldface):
Division ratio 0-7. Specifies divide ratio divider clock generator. output prescaler divided ([DIV0-DIV7] I2MOD[FLT])) clock duty cycle. must programmed minimum value digital filter disabled (I2MOD[FLT] enabled (I2MOD[FLT]
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Section, Page 40-5, 40-10 Changes Table 40-5, TDM_A1:L1TXD column PSORA PDIRA shown below:
Function PSORA PDIRA (Output) SMC2: SMTXD PDIRA (Input) PSORA Default PDIRA (Input, Default PDIRA (Output) Input In/out Specified) Input TDM_A1: L1TXD[0] Output, nibble TDM_A1: L1TXD Inout, serial
40-5, 40-16
Table 40-7, note attached SPI: SPISEL incorrect. should refer note ("available only when primary option this function used") note
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MOTOROLA Errata MPC8260 PowerQUICC Family Reference Manual, Rev.
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MPC8260UMAD
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This addendum describes corrections MPC8260 PowerQUICC IIFamily Refere

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