Freescale Semiconductor, Inc. Introduction Introduction Modi

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DSP56303UMAD/D Rev. 11/2002 DSP56303 User's Manual
Freescale Semiconductor, Inc.
Introduction
Introduction Modified Signal Definitions Operating Mode Register (OMR) Layout Definition.2 Control Register (BCR) Layout Definition.3 Receive Register (SRX) Description Updated Programming Sheets.3
This document provides updated information revision DSP56303 User's Manual (DSP56303UM/D). updates include following: Modified signal definitions Operating Mode Register (OMR) layout definitions Control Register (BCR) layout definitions Updated Receive Register (SRX) Description Updated Programming sheets OMR, BCR, Address Attribute Registers (AAR[3-0]), Timer Registers (TLR, TCPR, TCR)
Modified Signal Definitions
Change Description
Notes 1-4, delete last sentence each note. internal keepers disabled affect device operation. Change Ground (GND) Ground (GND)5. Change Note read follows: number Ground signals listed 144-pin TQFP package. 196-ball MAP-BGA package, there connections. figure, change Grounds: Grounds4: bottom figure, following: signals listed 144-pin TQFP package. 196-ball MAP-BGA package, grounds except GNDP GNDP1 connected together referenced GND. There connections. Change note table following: Note: subsystem signals (GNDQ, GNDA, GNDD, GNDC, GNDH, GNDS) listed 144-pin TQFP package. 196-ball MAP-BGA package, grounds except GNDP GNDP1 connected together inside package referenced GND. Change signal State During Reset, Stop, Wait Reset: Output (deasserted) State during Stop/Wait depends setting: Output, deasserted Maintains last state (that asserted, remains asserted) Change signal State During Reset, Stop, Wait Ignored input
Area Change
Table 2-1,
Figure 2-1,
Table 2-3,
Table 2-8,
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Operating Mode Register (OMR) Layout Definition
Area Change
Table 2-11, 2-11 2-14
Change Description
Change title third column State During Reset1,2. note that states: Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Change note note Change State During Reset signals Ignored input. Change signal description PB14 Port B14-When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. Delete Stop column Change title third column State During Reset Change State During Reset signals Ignored input. Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Change note note
Freescale Semiconductor, Inc.
Table 2-12, 2-15 2-16 Table 2-13, 2-17 2-18 Table 2-14, 2-19 Table 2-15, 2-20
Operating Mode Register (OMR) Layout Definition
Area Change
Figure 4-2, 4-15 Replace with following:
Change Description
Stack Control/Status (SCS)
Extended Operating Mode (EOM)
Chip Operating Mode (COM)
CDP[1-0]
Reset:
After reset, these bits reflect corresponding value mode input (that MODD, MODC, MODB, MODA, respectively). Reserved bit. Read zero; write zero future compatibility
Figure 4-2. Operating Mode Register (OMR)
Area Change
Table 4-3, 4-17
Change Description
change third line Note following: Instruction Cache always uses highest internal Program
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Control Register (BCR) Layout Definition
Control Register (BCR) Layout Definition
Area Change
Figure 4-6, 4-25 Replace with following:
Change Description
Change Figure DSP56303 User's Manual following figure:
BA2W0
BDFW4
BDFW3
BDFW2
BDFW1
BDFW0
BA3W2
BA3W1
BA3W0
BA2W2
BA2W1
BA1W4
BA1W3
BA1W2
BA1W1
BA1W0
BA0W4
BA0W3
BA0W2
BA0W1
BA0W0
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Reserved bit. Read zero; write zero future compatibility
Figure 4-6. Control Register (BCR)
Area Change
Table 4-8, 4-26
Change Description
Change contents following: Reserved. Write future compatibility.
Receive Register (SRX) Description
Area Change
Section 8.6.4.1, 8-23
Change Description
Change beginning fourth paragraph from Synchronous mode" Asynchronous mode".
Updated Programming Sheets
Table B-1, DSP56L307 User's Manual, change Timers rows following:
Timers Figure B-20, Timer Prescaler Load Register (TPLR) Figure B-21, Timer Control/Status Register (TCSR) Figure B-22, Timer Load, Compare, Count Registers (TLR, TCPR, TCR) B-31 B-32 B-33
following examples replace Figure B-13), Figure B-17), Figure B-19), Figure B-22 B-33).
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Release Timing, Fast Release mode Slow Release mode Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external Stop Delay Mode, Delay 128K clock cycles Delay clock cycles Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized
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Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Address Trace Enable, Address Trace mode disabled Address Trace mode enabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled
CPD1 CPD0
Operating Mode Register Reset $00030X; latched from levels Mode pins
Reserved, Program
Figure B-2. Operating Mode Register (OMR)
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Interface Unit
NOTE: bits read/write control bits.
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Request Hold, asserted only attempted pending access always asserted
Default Area Wait Control, Bits 20-16 Area Wait Control, Bits 15-13 Area Wait Control, Bits 12-10 Area Wait Control, Bits Area Wait Control, Bits These read/write control bits define number wait states inserted into each external SRAM access designated area. value these bits should programmed zero.
Bits Name BDFW[4-0] BA3W[2-0] BA2W[2-0] BA1W[4-0] BA0W[4-0] Wait States 0-31 0-31 0-31
State, master master
20-16 15-13 12-10
BDFW[4-0]
BA3W[2-0]
BA2W[2-0]
BA1W[4-0]
BA0W[4-0]
Control Register (BCR) Reset $1FFFFF
X:$FFFFFB Read/Write
Reserved, Program
Figure B-6. Control Register (BCR)
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Interface Unit
Packing Enable, Disable internal packing/unpacking logic Enable internal packing/unpacking logic Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses
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Address Compare, Bits 23-12 BAC[11-0] address compare external address order decide whether assert Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Program Memory Enable, Disable logic during external program space accesses Enable logic during external program space accesses Address Attribute Polarity, AA/RAS signal active AA/RAS signal active high Access Type, Bits
BAT[1-0] Encoding Reserved SRAM access DRAM access Reserved
Number Address Bits Compare, Bits 11-8 BNC[3-0] number bits (from bits) that compared external address (Combinations BNC[3-0] 1111, 1110, 1101 reserved.)
BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC
BYEN BXEN BPEN BAAP BAT1 BAT0
Address Attribute Registers (AAR3) Address Attribute Registers (AAR2) Address Attribute Registers (AAR1) Address Attribute Registers (AAR0) Reset $000000
X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write
Reserved, Program Figure B-8. Address Attribute Registers (AAR[3-0])
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Timers
Timer Reload Value
Freescale Semiconductor, Inc.
Timer Load Register (TLR[0-2]) Reset $xxxxxx, value indeterminate after reset
TLR0-X:$FFFF8E Write Only TLR1-X:$FFFF8A Write Only TLR2-X:$FFFF86 Write Only
Value Compared Counter Value
Timer Compare Register (TCPR[0-2]) Reset $xxxxxx, value indeterminate after reset
TCPR0-X:$FFFF8D Read/Write TCPR1-X:$FFFF89 Read/Write TCPR2-X:$FFFF85 Read/Write
Timer Count Value
Timer Count Register (TCR[0-2]) Reset $000000
TCR0-X:$FFFF8C Read Only TCR1-X:$FFFF88 Read Only TCR2-X:$FFFF84 Read Only
Figure B-22. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
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Freescale Semiconductor, Inc.
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DSP56303UMAD/D

Freescale Semiconductor, Inc. Introduction Introduction Modi

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