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DSP56301UMAD/D Rev. 5/2003 DSP56301 User's Manual
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Introduction
Introduction.1 Modified Signal Definitions.1 Operating Mode Register (OMR) Definition.3 Control Register (DCR[5-0]) Definition.4 Receive Register (SRX) Description Updated Programming Sheets.5
This document provides updated information revision DSP56301 User's Manual (DSP56301UM/D). updates include following: Modified signal definitions Updated Operating Mode Register (OMR) definition Updated Control Register (DCR) definition Updated Receive Register (SRX) description Updated Programming sheets OMR, Address Attribute Registers (AAR[3-0]), Control Registers (DMR[5-0]), Timer Registers (TLR, TCPR, TCR), Host Data Direction Data Registers (DIRH DATH)
Modified Signal Definitions
Change Description
Notes 1-4, delete last sentence each note. Delete Note figure, change Grounds: Grounds4: bottom figure, following: signals listed 208-pin TQFP package. 252-ball MAP-BGA package, grounds except GNDP GNDP1 connected together referenced GND. following note table: Note: subsystem signals (GND GNDA, GNDD GNDN, GNDH, GNDS) listed 208-pin TQFP package. 252-ball MAP-BGA package, grounds except GNDP GNDP1 connected together inside package referenced GND. Delete last sentence signal description D[0-23]. DSP56301 does have internal keeper circuits. Change title third column State During Reset, Stop, Wait Change signal name Change signal State During Reset, Stop, Wait Reset: Output (deasserted) State during Stop/Wait depends setting: Output, deasserted Maintains last state (that asserted, remains asserted) Change signal State During Reset, Stop, Wait Ignored input
Area Change
Table 2-1, Figure 2-1,
What's New?
page note reference Table 2-12, signal HP31 changed from
Table 2-2,
Table 2-7, Table 2-8,
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Modified Signal Definitions
Area Change
Table 2-10, 2-10 2-14
Change Description
Change title third column State During Reset1,2. following notes table: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. Change State During Reset signals Ignored input. Signal HP31, change note reference after sentence "Sustained tri-state bidirectional pin." from Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete last sentence signal description. signals, change PCR0 PCRC PRR0 PRRC. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete last sentence signal description. signals, change PCR1 PCRD PRR1 PRRD. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete last sentence signal description. signals, change PCRE PRRE. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete last sentence signal description.
Table 2-12, 2-20 Table 2-13, 2-23 2-24
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Table 2-14, 2-25 2-26
Table 2-15, 2-27
Table 2-16, 2-28
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Operating Mode Register (OMR) Definition
Operating Mode Register (OMR) Definition
Area Change
Table 4-4, 4-14
Change Description
identify correct location instruction cache memory space changing contents following:
Memory Switch Mode Allows some internal data memory both) become part chip internal Program RAM. Notes: Program data placed Program RAM/Instruction Cache area changes placement after OMR[MS] (that Instruction Cache always uses highest internal Program addresses). ensure proper operation, place instructions after instruction that changes bit. ensure proper operation, while Instruction Cache enabled (SR[CE] set).
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Control Register (DCR[5-0]) Definition
Control Register (DCR[5-0]) Definition
Area Change
Table 4-12, 4-33
Change Description
bits 15-11, identify correct request sources changing contents following:
15-11
DRS[4-0]
Request Source Encodes source requests that trigger transfers. request sources external devices requesting service through IRQA, IRQB, IRQC IRQD pins, triggering transfers done from channel, transfers from internal peripherals. request sources behave edge-triggered synchronous inputs.
DRS[4-0]
Requesting Device
External (IRQA pin) External (IRQB pin) External (IRQC pin) External (IRQD pin) Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel ESSI0 receive data (RDF0 ESSI0 transmit data (TDE0 ESSI1 receive data (RDF1 ESSI1 transmit data (TDE1 receive data (RDRF transmit data (TDRE Timer0 (TCF0 Timer1 (TCF1 Timer2 (TCF2 Reserved Host slave receive data (SRRQ Host master receive data (MRRQ Host slave transmit data (STRQ Host master transmit data (MTRQ
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00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011-11011 11100 11101 11110 11111
Peripheral requests 18-21 (DRS[4-0] 111xx) serve fast request sources. Unlike regular peripheral request which peripheral generate second request until first served, fast peripheral full duplex handshake DMA, enabling maximum throughput trigger every clock cycles. This mode functional only Word Transfer mode (that 101). Fast Request mode, sets enable line peripheral. required, peripheral send cycle triggering pulse. This pulse resets enable line. decides priority algorithm that this trigger will served next cycle, enable line again, even before corresponding register peripheral accessed.
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Receive Register (SRX) Description
Receive Register (SRX) Description
Area Change
Section 8.6.4.1, 8-22
Change Description
Change beginning fourth paragraph from Synchronous mode" Asynchronous mode".
Updated Programming Sheets
Table B-1, DSP56L307 User's Manual, change Timers rows following:
Timers Figure B-25, Timer Prescaler Load Register (TPLR) Figure B-26, Timer Control/Status Register (TCSR) Figure B-27, Timer Load, Compare, Count Registers (TLR, TCPR, TCR) B-37 B-38 B-39
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following examples replace Figure B-14), Figure B-20), Figure B-21), Figure B-27 B-39), Figure B-28 B-40) DSP56301 User's Manual.
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Address Trace Enable, Address Trace mode disabled Address Trace mode enabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled Release Timing, Fast Release mode Slow Release mode Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external Stop Delay Mode, Delay 128K clock cycles Delay clock cycles Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized
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CPD1 CPD0
Operating Mode Register Reset $00030X; latched from levels Mode pins
Reserved, Program
Figure B-2. Operating Mode Register (OMR)
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Interface Unit
Packing Enable, Disable internal packing/unpacking logic Enable internal packing/unpacking logic Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses
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Address Compare, Bits 23-12 BAC[11-0] address compare external address order decide whether assert Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Program Memory Enable, Disable logic during external program space accesses Enable logic during external program space accesses Address Attribute Polarity, AA/RAS signal active AA/RAS signal active high Access Type, Bits
BAT[1-0] Encoding Reserved SRAM access DRAM access Reserved
Number Address Bits Compare, Bits 11-8 BNC[3-0] number bits (from bits) that compared external address (Combinations BNC[3-0] 1111, 1110, 1101 reserved.)
BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC
BYEN BXEN BPEN BAAP BAT1 BAT0
Address Attribute Registers (AAR3) Address Attribute Registers (AAR2) Address Attribute Registers (AAR1) Address Attribute Registers (AAR0) Reset $000000
X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write
Reserved, Program Figure B-8. Address Attribute Registers (AAR[3-0])
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet Three-Dimensional Mode, Three-Dimensional mode disabled Three-Dimensional mode enabled
Channel Enable, Disables channel operation Enables channel operation Interrupt Enable, Disables Interrupt Enables interrupt Transfer Mode, Bits 21-19
DTM[2:0] Triggered request request request request request reserved reserved Cleared
Counter Mode Offset Register Selection DOR0 DOR1 DOR2 DOR3 None None
Address Mode, Bits Non-Three-Dimensional Addressing Modes (D3D=0) DAM[2-0] source DAM[5-3] Destination
DAM[5-3] DAM[2-0] 110-111 Addressing Mode update Postincrement-by-1 reserved
Transfer Mode block transfer word transfer line transfer block transfer block transfer word transfer
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Three-Dimensional Addressing Modes (D3D=1)
DAM[5-3] DAM2 Addressing Mode update Postincrement-by-1 Offset Selection DOR0 DOR1 DOR2 DOR3 None None DOR[0-1] DOR[2-3]
Channel Priority, Bits 18-17
DPR[1:0] Channel Priority Priority level (lowest) Priority level Priority level Priority level (highest)
Continuous Mode Enable, Disables continuous mode Enables continuous mode Request Source, Bits 15-11
DRS[4:0] 00000-00011 00100-01001 01010-01011 01100-01101 01110-01111 10000-10010 10011-11011 11100-11101 11110-11111 Requesting Device External (IRQA, IRQB, IRQC, IRQD) Transfer done from channel 0,1,2,3,4,5 ESSI0 Receive, Transmit Data ESSI1 Receive, Transmit Data Receive, Transmit Data Timer0, Timer1, Timer2 Reserved Host Slave/Master Receive Data Host Slave/Master Transmit Data
Addressing Mode Offset Selection Source: Source: DOR[0-1] Destination: Defined DAM[5-3] Source: Defined DAM[5-3] Destination: Destination: DOR[2-3] Counter Layout
[1-0]
Mode DCOH[23-12] DCOM[11-6] DCOL[5-0] Mode DCOH[23-18] DCOM[17-6] DCOL[5-0] Mode DCOH[23-18] DCOM[17-12] DCOL[11-0] Reserved
Destination Space, Bits
DSS[1:0] Destination Memory Memory Space Memory Space Memory Space Reserved
Source Space, Bits
DSS[1:0] Source Memory Memory Space Memory Space Memory Space Reserved
DTM[2-0] DPR[1-0] DCON DRS[4-0]
DAM[5-0]
DDS[1-0]
DSS[1-0]
Control Registers (DCR5-DCR0) Reset $000000
X:$FFFFD8, X:$FFFFDC, X:$FFFFE0, X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write
Figure B-9. Control Registers (DCR[5-0])
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Timers
Timer Reload Value
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Timer Load Register (TLR[0-2]) Reset $xxxxxx, value indeterminate after reset
TLR0-X:$FFFF8E Write Only TLR1-X:$FFFF8A Write Only TLR2-X:$FFFF86 Write Only
Value Compared Counter Value
Timer Compare Register Reset $xxxxxx, value indeterminate after reset
TCPR0-X:$FFFF8D Read/Write TCPR1-X:$FFFF89 Read/Write TCPR2-X:FFFF85 Read/Write
Timer Count Value
Timer Count Register Reset $000000
TCR0-X:$FFFF8C Read Only TCR1-X:$FFFF88 Read Only TCR2-X:$FFFF84 Read Only
Figure B-27. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
GPIO
DIR23
Port (HI32)
DIR21
DIR22
DIR20
DIR19
DIR18
DIR17
DIR16
DIR14
DIR13
DIR12
DIR11
DIR10
DIR9
DIR8
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DIR15
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Host Port GPIO Direction Register (DIRH) Reset: $000000
X:$FFFFCE Read/Write
DAT23
DAT22
DAT21
DAT20
DAT19
DAT18
DAT17
DAT16
DAT15
DAT14
DAT13
DAT12
DAT11
DAT10
DAT9
DAT8
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Host Port GPIO Data Register (DATH) Reset: $000000
X:$FFFFCF Read/Write
DATH DIRH Functionality DATx DIRx GPIO Pin1
Read-only bit. value read binary value pin. corresponding configured input. Read/write bit. value written same value read. corresponding configured output, driven with data written DATx.
Non-GPIO Pin1
Read-only bit. Does contain significant data. Read/write bit. value written same value read.
Note: Defined selected mode
Figure B-28. Host Data Direction Host Data Registers (DIRH, DATH)
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Updated Programming Sheets
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DSP56301UMAD/D, REV.
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