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ALTIVECPIM/D 6/1999 Rev.
AltiVec Technology Programming Interface Manual
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Overview
High-Level Language Interface
Application Binary Interface
AltiVec Operations Predicates
AltiVec Instruction Set/Operations/Predicates Cross-Reference
Glossary Terms Abbreviations
Index
Overview
High-Level Language Interface
Application Binary Interface
AltiVec Operations Predicates
AltiVec Instruction Set/Operations/Predicates Cross-Reference
Glossary Terms Abbreviations
Index
CONTENTS
Paragraph Number Title Page Number
Audience Organization. Suggested Reading. xvii PowerPC Documentation. xvii General Information. xviii Chapter
Overview
High-Level Language Interface Application Binary Interface (ABI) Chapter
High-Level Language Interface
2.2.1 2.2.2 2.3.1 2.3.2 2.3.3 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.5.1 2.5.2 2.5.3 2.5.4 Data Types Keywords. Keyword Predefine Method. Context Sensitive Keyword Method. Alignment Alignment Vector Types Alignment Non-Vector Types Alignment Aggregates Unions Containing Vector Types Extensions C/C++ Operators Types sizeof() Assignment Address Operator Pointer Arithmetic. Pointer Dereferencing Type Casting Operators Vector Literals Vector Literals Casts. Value Adjusting Pointers Operators Representing AltiVec Operations. Programming Interface Chapter
Application Binary Interface (ABI)
Data Representation Register Usage Conventions
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Contents
CONTENTS
Paragraph Number 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 3.4.3 3.8.1 3.8.2 Title Page Number
Stack Frame SVR4 EABI Stack Frame. Apple Macintosh Stack Frame Vector Register Saving Restoring Functions Function Calls SVR4 EABI Parameter Passing Varargs. Apple Macintosh Parameter Passing without Varargs. Apple Macintosh Parameter Passing with Varargs 3-10 malloc(), vec_malloc(), 3-10 setjmp() longjmp() 3-11 Debugging Information. 3-11 printf() scanf() Control Strings. 3-12 Output Conversion Specifications 3-12 Input Conversion Specifications. 3-14 Chapter
AltiVec Operations Predicates
Vector Status Control Register. Byte Ordering. Notation Conventions. Generic Specific AltiVec Operations. AltiVec Predicates 4-133 Appendix AltiVec Instruction Set/Operation/Predicate Cross-Reference
Glossary Terms Abbreviations Index
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ILLUSTRATIONS
Figure Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 Title Page Number
SVR4 EABI Stack Frame Apple Macintosh Stack Frame. Vector Status Control Register (VSCR) VSCR Moved Vector Register Big-Endian Byte Ordering Vector Register Operation Description Format Absolute Value Sixteen Integer Elements (8-bit) Absolute Value Eight Integer Elements (16-bit). Absolute Value Four Integer Elements (32-bit) Absolute Value Four Floating-Point Elements (32-bit) Saturated Absolute Value Sixteen Integer Elements (8-bit) 4-10 Saturated Absolute Value Eight Integer Elements (16-bit). 4-11 Saturated Absolute Value Four Integer Elements (32-bit). 4-11 Sixteen Integer Elements (8-bit) 4-12 Eight Integer Elements (16-bit) 4-13 Four Integer Elements (32-bit) 4-13 Four Floating-Point Elements (32-bit). 4-14 Carryout Four Unsigned Integer Adds (32-bit). 4-15 Saturating Sixteen Integer Elements (8-bit) 4-16 Saturating Eight Integer Elements (16-bit). 4-17 Saturating Four Integer Elements (32-bit) 4-17 Logical Bit-Wise 4-18 Logical Bit-Wise with Complement 4-19 Average Sixteen Integer Elements (8-bit) 4-21 Average Eight Integer Elements (16-bit). 4-22 Average Four Integer Elements (32-bit). 4-22 Round Plus Infinity Four Floating-Point Integer Elements (32-Bit) 4-23 Compare Bounds Four Floating-Point Elements (32-Bit). 4-24 Compare Equal Sixteen Integer Elements (8-bits) 4-25 Compare Equal Eight Integer Elements (16-Bit) 4-26 Compare Equal Four Integer Elements (32-Bit) 4-26 Compare Equal Four Floating-Point Elements (32-Bit) 4-26 Compare Greater-Than-or-Equal Four Floating-Point Elements (32-Bit) 4-27 Compare Greater-Than Sixteen Integer Elements (8-bits). 4-28 Compare Greater-Than Eight Integer Elements (16-Bit) 4-29 Compare Greater-Than Four Integer Elements (32-Bit) 4-29 Compare Greater-Than Four Floating-Point Elements (32-Bit) 4-29 Compare Less-Than-or-Equal Four Floating-Point Elements (32-Bit). 4-30 Compare Less-Than Sixteen Integer Elements (8-bits) 4-31 Compare Less-Than Eight Integer Elements (16-Bit). 4-32 Compare Less-Than Four Integer Elements (32-Bit). 4-32 Compare Less-Than Four Floating-Point Elements (32-Bit) 4-32 Convert Four Integer Elements Four Floating-Point Elements (32-Bit) 4-33
Illustrations
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ILLUSTRATIONS
Figure Page Title Number Number 4-42 Convert Four Floating-Point Elements Four Saturated Signed Integer Elements (32-Bit) 4-34 4-43 Convert Four Floating-Point Elements Four Saturated Unsigned Integer Elements (32-Bit) 4-35 4-44 Format Type (32-bit) 4-38 4-45 Format Type (64-bit) 4-38 4-46 Format Type (32-bit) 4-40 4-47 Format Type (64-bit) 4-40 4-48 Format Type (32-bit) 4-42 4-49 Format Type (64-bit) 4-42 4-50 Format Type (32-bit) 4-44 4-51 Format Type (64-bit) 4-44 4-52 Raised Exponent Estimate Floating-Point Four Floating-Point Elements (32-Bit) 4-46 4-53 Round Minus Infinity Four Floating-Point Integer Elements (32-Bit) 4-47 4-54 Vector Load Indexed Operation 4-48 4-55 Vector Load Element Indexed Operation 4-50 4-56 Vector Load Indexed Operation 4-51 4-57 Log2 Estimate Floating-Point Four Floating-Point Elements (32-Bit). 4-53 4-58 Multiply-Add Four Floating-Point Elements (32-Bit). 4-56 4-59 Multiply-Add Four Floating-Point Elements (32-Bit). 4-57 4-60 Maximum Sixteen Integer Elements (8-Bit) 4-58 4-61 Maximum Eight Integer Elements (16-bit) 4-59 4-62 Maximum Four Integer Elements (32-bit) 4-59 4-63 Maximum Four Floating-Point Elements (32-bit) 4-60 4-64 Merge Eight High-Order Elements (8-Bit). 4-61 4-65 Merge Four High-Order Elements (16-bit) 4-62 4-66 Merge High-Order Elements (32-bit). 4-62 4-67 Merge Eight Low-Order Elements (8-Bit) 4-63 4-68 Merge Four Low-Order Elements (16-bit) 4-64 4-69 Merge Low-Order Elements (32-bit) 4-64 4-70 Vector Move from VSCR. 4-65 4-71 Minimum Sixteen Integer Elements (8-Bit). 4-66 4-72 Minimum Eight Integer Elements (16-bit). 4-67 4-73 Minimum Four Integer Elements (32-bit) 4-67 4-74 Minimum Four Floating-Point Elements (32-bit) 4-68 4-75 Multiply-Add Eight Integer Elements (16-Bit) 4-69 4-76 Multiply-Add Eight Integer Elements (16-Bit) 4-70 4-77 Multiply Sixteen Integer Elements (8-Bit) 4-71 4-78 Multiply Eight Integer Elements (16-Bit). 4-72 4-79 Multiply-Sum Integer Elements (16-Bit 32-Bit). 4-73 4-80 Vector Move VSCR 4-74 4-81 Even Multiply Eight Integer Elements (8-Bit) 4-75
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ILLUSTRATIONS
Figure Number 4-82 4-83 4-84 4-85 4-86 4-87 4-88 4-89 4-90 4-91 4-92 4-93 4-94 4-95 4-96 4-97 4-98 4-99 4-100 4-101 4-102 4-103 4-104 4-105 4-106 4-107 4-108 4-109 4-110 4-111 4-112 4-113 4-114 4-115 4-116 4-117 4-118 4-119 4-120 Title Page Number
Even Multiply Four Integer Elements (16-Bit) 4-75 Multiply Eight Integer Elements (8-Bit) 4-76 Multiply Four Integer Elements (16-Bit) 4-76 Negative Multiply-Subtract Four Floating-Point Elements (32-Bit) 4-77 Logical Bit-Wise 4-78 Logical Bit-Wise 4-79 Pack Sixteen Unsigned Integer Elements (16-Bit) Sixteen Unsigned Integer Elements (8-Bit) 4-80 Pack Eight Unsigned Integer Elements (32-Bit) Eight Unsigned Integer Elements (16-Bit) 4-80 Pack Eight Pixel Elements (32-Bit) Eight Elements (16-Bit) 4-81 Pack Sixteen Integer Elements (16-Bit) Sixteen Integer Elements (8-Bit) 4-82 Pack Eight Integer Elements (32-Bit) Eight Integer Elements (16-Bit). 4-82 Pack Sixteen Integer Elements (16-Bit) Sixteen Unsigned Integer Elements (8-Bit) 4-83 Pack Eight Integer Elements (32-Bit) Eight Unsigned Integer Elements (16-Bit) 4-83 Permute Sixteen Integer Elements (8-Bit). 4-84 Reciprocal Estimate Four Floating-Point Elements (32-Bit) 4-85 Left Rotate Sixteen Integer Elements (8-Bit). 4-86 Left Rotate Eight Integer Elements (16-bit). 4-86 Left Rotate Four Integer Elements (32-bit). 4-87 Round Nearest Four Floating-Point Integer Elements (32-Bit) 4-88 Reciprocal Square Root Estimate Four Floating-Point Elements (32-Bit) 4-89 Bit-Wise Conditional Select Vector Contents (128-bit) 4-90 Shift Bits Left Sixteen Integer Elements (8-Bit) 4-91 Shift Bits Left Eight Integer Elements (16-bit) 4-92 Shift Bits Left Four Integer Elements (32-Bit). 4-92 Bit-Wise Conditional Select Vector Contents (128-bit) 4-93 Shift Bits Left Vector (128-Bit) 4-95 Left Byte Shift Vector (128-Bit) 4-96 Copy Contents Sixteen Integer Elements (8-Bit) 4-97 Copy Contents Eight Elements (16-bit) 4-97 Copy Contents Four Integer Elements (32-Bit). 4-98 Copy Value into Sixteen Signed Integer Elements (8-Bit). 4-99 Copy Value into Eight Signed Integer Elements (16-Bit) 4-100 Copy Value into Four Signed Integer Elements (32-Bit) 4-101 Copy Value into Sixteen Signed Integer Elements (8-Bit). 4-102 Copy Value into Eight Signed Integer Elements (16-Bit) 4-103 Copy Value into Four Signed Integer Elements (32-Bit) 4-104 Shift Bits Right Sixteen Integer Elements (8-Bit) 4-105 Shift Bits Right Eight Integer Elements (16-bit) 4-106 Shift Bits Right Four Integer Elements (32-Bit) 4-106
Illustrations
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Figure Page Title Number Number 4-121 Shift Bits Right Sixteen Integer Elements (8-Bit) 4-107 4-122 Shift Bits Right Eight Integer Elements (16-bit) 4-108 4-123 Shift Bits Right Four Integer Elements (32-Bit) 4-108 4-124 Shift Bits Right Vector (128-Bit) 4-110 4-125 Right Byte Shift Vector (128-Bit) 4-111 4-126 Vector Store Indexed 4-112 4-127 Vector Store Element. 4-115 4-128 Vector Store Indexed 4-116 4-129 Subtract Sixteen Integer Elements (8-bit) 4-118 4-130 Subtract Eight Integer Elements (16-bit). 4-119 4-131 Subtract Four Integer Elements (32-bit) 4-119 4-132 Subtract Four Floating-Point Elements (32-bit) 4-120 4-133 Carryout Four Unsigned Integer Subtracts (32-bit) 4-121 4-134 Subtract Saturating Sixteen Integer Elements (8-bit) 4-122 4-135 Subtract Saturating Eight Integer Elements (16-bit) 4-123 4-136 Subtract Saturating Four Integer Elements (32-bit) 4-123 4-137 Four Sums Integer Elements (32-Bit). 4-124 4-138 Four Sums Integer Elements (32-Bit). 4-124 4-139 Saturated Sums Four Signed Integer Elements (32-Bit) 4-125 4-140 Saturated Five Signed Integer Elements (32-Bit) 4-126 4-141 Round-to-Zero Four Floating-Point Integer Elements (32-Bit) 4-127 4-142 Unpack High-Order Elements (8-Bit) Elements (16-Bit) 4-128 4-143 Unpack High-Order Pixel Elements (16-Bit) Elements (32-Bit) 4-129 4-144 Unpack High-Order Signed Integer Elements (16-Bit) Signed Integer Elements (32-Bit) 4-129 4-145 Unpack Low-Order Elements (8-Bit) Elements (16-Bit) 4-130 4-146 Unpack Low-Order Pixel Elements (16-Bit) Elements (32-Bit) 4-130 4-147 Unpack Low-Order Signed Integer Elements (16-Bit) Signed Integer Elements (32-Bit) 4-131 4-148 Logical Bit-Wise 4-132 4-149 Equal Sixteen Integer Elements (8-bits) 4-134 4-150 Equal Eight Integer Elements (16-Bit). 4-135 4-151 Equal Four Integer Elements (32-Bit). 4-135 4-152 Equal Four Floating-Point Elements (32-Bit) 4-136 4-153 Greater Than Equal Sixteen Integer Elements (8-bits) 4-137 4-154 Greater Than Equal Eight Integer Elements (16-Bit) 4-138 4-155 Greater Than Equal Four Integer Elements (32-Bit) 4-138 4-156 Greater Than Equal Four Floating-Point Elements (32-Bit) 4-139 4-157 Greater Than Sixteen Integer Elements (8-bits). 4-140 4-158 Greater Than Eight Integer Elements (16-Bit). 4-141 4-159 Greater Than Four Integer Elements (32-Bit) 4-141 4-160 Greater Than Four Floating-Point Elements (32-Bit) 4-142 4-161 Bounds Four Floating-Point Elements (32-Bit) 4-143
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ILLUSTRATIONS
Figure Number 4-162 4-163 4-164 4-165 4-166 4-167 4-168 4-169 4-170 4-171 4-172 4-173 4-174 4-175 4-176 4-177 4-178 4-179 4-180 4-181 4-182 4-183 4-184 4-185 4-186 4-187 4-188 4-189 4-190 4-191 4-192 4-193 4-194 4-195 4-196 4-197 4-198 4-199 4-200 4-201 4-202 4-203 4-204 Title Page Number
Less Than Equal Sixteen Integer Elements (8-bits). 4-144 Less Than Equal Eight Integer Elements (16-Bit). 4-145 Less Than Equal Four Integer Elements (32-Bit) 4-145 Less Than Equal Four Floating-Point Elements (32-Bit) 4-146 Less Than Sixteen Integer Elements (8-bits) 4-147 Less Than Eight Integer Elements (16-Bit) 4-148 Less Than Four Integer Elements (32-Bit). 4-148 Less Than Four Floating-Point Elements (32-Bit). 4-149 Four Floating-Point Elements (32-Bit). 4-150 Equal Sixteen Integer Elements (8-bits) 4-151 Equal Eight Integer Elements (16-Bit). 4-152 Equal Four Integer Elements (32-Bit). 4-152 Equal Four Floating-Point Elements (32-Bit) 4-153 Greater Than Equal Four Floating-Point Elements (32-Bit) 4-154 Greater Than Four Floating-Point Elements (32-Bit) 4-155 Less Than Equal Four Floating-Point Elements (32-Bit) 4-156 Less Than Four Floating-Point Elements (32-Bit). 4-157 Numeric Four Floating-Point Elements (32-Bit) 4-158 Equal Sixteen Integer Elements (8-bits). 4-159 Equal Eight Integer Elements (16-Bit) 4-160 Equal Four Integer Elements (32-Bit) 4-160 Equal Four Floating-Point Elements (32-Bit) 4-161 Greater Than Equal Sixteen Integer Elements (8-bits) 4-162 Greater Than Equal Eight Integer Elements (16-Bit) 4-163 Greater Than Equal Four Integer Elements (32-Bit). 4-163 Greater Than Equal Four Floating-Point Elements (32-Bit). 4-164 Greater Than Sixteen Integer Elements (8-bits). 4-165 Greater Than Eight Integer Elements (16-Bit) 4-166 Greater Than Four Integer Elements (32-Bit) 4-166 Greater Than Four Floating-Point Elements (32-Bit) 4-167 Less Than Equal Sixteen Integer Elements (8-bits). 4-168 Less Than Equal Eight Integer Elements (16-Bit) 4-169 Less Than Equal Four Integer Elements (32-Bit) 4-169 Less Than Equal Four Floating-Point Elements (32-Bit) 4-170 Less Than Sixteen Integer Elements (8-bits) 4-171 Less Than Eight Integer Elements (16-Bit). 4-172 Less Than Four Integer Elements (32-Bit). 4-172 Less Than Four Floating-Point Elements (32-Bit) 4-173 Four Floating-Point Elements (32-Bit) 4-174 Equal Sixteen Integer Elements (8-bits). 4-175 Equal Eight Integer Elements (16-Bit) 4-176 Equal Four Integer Elements (32-Bit) 4-176 Equal Four Floating-Point Elements (32-Bit) 4-177
Illustrations
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ILLUSTRATIONS
Figure Page Title Number Number 4-205 Greater Than Equal Four Floating-Point Elements (32-Bit) 4-178 4-206 Greater Than Four Floating-Point Elements (32-Bit) 4-179 4-207 Less Than Equal Four Floating-Point Elements (32-Bit) 4-180 4-208 Less Than Four Floating-Point Elements (32-Bit) 4-181 4-209 Numeric Four Floating-Point Elements (32-Bit). 4-182 4-210 Bounds Four Floating-Point Elements (32-Bit) 4-183
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TABLES
Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 Title Page Number
AltiVec Data Types Vector Literal Format Description Increment Value vec_step Data Type AltiVec Registers. Vector Registers Valid Format Specifications setjmp() longjmp() 3-11 VSCR Field Descriptions. Notation Conventions Precedence Rules Data Stream Stop Argument Types. 4-36 Data Stream Touch Argument Types 4-39 Data Stream Touch Store Argument Types 4-41 Data Stream Touch Store Transient Argument Types 4-43 Data Stream Touch Transient Argument Types 4-45 Vector Indexed Argument Types. 4-49 Load Element Indexed Argument Types 4-50 Load Indexed Argument Types. 4-52 Vector Shift Left Argument Types 4-54 Load Shift Right Argument Types 4-55 Vector Move from Vector Status Control Registers Argument Type Mapping. 4-65 Move Vector Status Control Register Argument Types 4-74 Special Value Results Reciprocal Estimates 4-85 Special Value Results Reciprocal Square Root Estimates 4-89 Store Indexed Argument Types 4-113 Store Index Argument Types. 4-117 Instructions Operations/Predicates Cross-Reference. Operations Instructions Cross-Reference Predicate Instruction Cross-Reference A-14
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Tables
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TABLES
Table Number Title Page Number
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About This Book
primary objective this manual help programmers provide software that compatible across family processors using technology. locate published errata updates this document, refer website This book that discuss AltiVec architecture, books are: AltiVec: Programming Interface Manual (AltiVec PIM) used reference guide high-level programmers. AltiVec provides mechanism programmers access AltiVec functionality from programming languages such C++. AltiVec programming model with AltiVec instruction extension PowerPC architecture. AltiVec: Programming Environments Manual (AltiVec PEM) used reference guide assembler programmers. AltiVec provides description each instruction that includes instruction format, individualized legend that provides such information level(s) PowerPC architecture which instruction found, privilege level instruction, help understanding instruction works.
beyond scope this manual describe individual AltiVec technology implementations PowerPC processors. must kept mind that each PowerPC processor unique implementation AltiVec technology. information this book subject change without notice, described disclaimers title page this book. with technical documentation, responsibility sure they using most recent version documentation. more information, contact your sales representative visit website
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About This Book
Audience
This manual intended system software application programmers want develop products using AltiVec technology extension PowerPC processors general. assumed that reader understands operating systems, microprocessor system design, basic principles RISC processing, AltiVec Instruction Set.
Organization
Following summary brief description major sections this manual: Chapter useful those want general understanding what programming model AltiVec technology. Chapter Language useful software engineers need understand access AltiVec functionality from high level languages such C++. Chapter Binary Interface describes AltiVec extensions System Application Binary Interface PowerPC Processor Supplement (SVR4 ABI), PowerPC Embedded Application Binary Interface (EABI), Appendix PowerPC Compiler Guide (AIX ABI), Apple Macintosh ABI. Chapter Operations alphabetically AltiVec operations predicates. Each AltiVec operation predicate description includes pseudocode functional description illustrating that function, valid argument types that AltiVec operation predicate, result type that argument types, AltiVec instruction generated that arguments. Appendix Instruction Set/Operation/Predicate crossreferences AltiVec instruction set, operations, predicates functionality. This manual also includes glossary index.
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Suggested Reading
This section lists additional reading that provides background information this manual well general information about AltiVec technology PowerPC architecture.
PowerPC Documentation
PowerPC documentation organized following types documents: books provide details about individual PowerPC implementations intended used conjunction with PowerPC Microprocessor Family: Programming Environments Manual. PowerPC Microprocessor Family: Programming Environments, Rev. provides information about resources PowerPC architecture that common PowerPC processors. This document describes both 32-bit portions architecture. MPCFPE/AD (Motorola order Implementation Variances Relative Rev. Programming Environments Manual available world-wide Addenda/errata some processors have follow-on parts addendum provided that describes additional features changes functionality follow-on part. These addenda intended with corresponding manuals. Hardware provide data regarding timing, signal behavior, thermal characteristics, well other design considerations each PowerPC implementation. Technical PowerPC implementation technical summary that provides overview features. This document roughly equivalent overview (Chapter manual. PowerPC Microprocessor Family: Reference Guide: MPCPRG/D (Motorola order concise reference that includes register summary, memory control model, exception vectors, PowerPC instruction set. PowerPC Microprocessor Family: Pocket Reference Guide: MPCPRGREF/D (Motorola order This foldout card provides overview PowerPC registers, instructions, exceptions 32-bit implementations. Application short documents contain useful information about design issues useful programmers engineers working with PowerPC processors (available worldwide Documentation support chips
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About This Book
xvii
Additional literature AltiVec technology PowerPC implementations being released processors become available. current list AltiVec technology PowerPC documentation, refer website
General Information
following documentation provides useful information about PowerPC architecture computer architecture general: following books available from Morgan-Kaufmann Publishers, Pine Street, Sixth Floor, Francisco, 94104; Tel. (800) 745-7323 (U.S.A.), (415) 392-2665 (International); internet address: mkp@mkp.com. PowerPC Architecture: Family RISC Processors, Second Edition, International Business Machines, Inc. Updates architecture accessible world-wide PowerPC Microprocessor Common Hardware Reference Platform: System Architecture, Apple Computer, Inc., International Business Machines, Inc., Motorola, Inc. Macintosh Technology Common Hardware Reference Platform, Apple Computer, Inc. Computer Organization Design, David Patterson John Hennessy. Computer Architecture: Quantitative Approach, Second Edition, John Hennessy David Patterson. PowerPC Programming Intel Programmers, McClanahan; Books Worldwide, Inc., East Hillsdale Boulevard, Suite 400, Foster City, 94404; Tel. (800) 434-3422 (U.S.A.), (415) 655-3022 (International).
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Chapter Overview
This document programming model with AltiVec instruction extension PowerPC architecture. There three types programming interfaces described this document: high-level language interface, intended within programming languages such application binary interface (ABI) low-level coding conventions assembly language interface
Although higher-level application programming interface (API) such mediaLib intended with AltiVec, such addressed this document. further details mediaLib AltiVec website AltiVec-enabled compiler implementing model described this document value _VEC_ decimal integer 10205.
High-Level Language Interface
high-level language interface AltiVec programmer able AltiVec technology from programming languages such C++. describes fundamental data type AltiVec programming model. Details this interface described Chapter Language
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Chapter Overview
Application Binary Interface (ABI)
Application Binary Interface (ABI)
AltiVec Programming Model extends existing PowerPC ABIs extension independent endian mode. reviews what data types what register usage conventions vector register also discusses stack frame. vector register save restore functions included section advocate uniformity among compilers method used saving restoring vector registers. Programming Interface Manual provides valid argument types AltiVec operations predicates well AltiVec instruction(s) generated that arguments. AltiVec operations predicates organized alphabetically Chapter Operations
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Chapter High-Level Language Interface
AltiVec high-level language interface: Provides expressive mechanism programmers access AltiVec functionality from programming languages such C++. Note: Access AltiVec functionality from Java applications currently addressed this will likely addressed through higher level such mediaLib. minimal language extensions that clearly describes intent programmer while minimizing impact existing PowerPC compilers development tools. minimal library extensions needed support AltiVec functionality.
Data Types
AltiVec programming model introduces fundamental data types, described Table 2-1.
Table 2-1. AltiVec Data Types
C/C++ Type vector unsigned char vector signed char vector bool char vector unsigned short unsigned short vector unsigned short vector signed short signed short vector signed short vector bool short unsigned short vector bool short vector unsigned vector unsigned long* vector unsigned long int* unsigned 0.232 (F), 65535 -32768.32767 0.65536 Interpretation Contents unsigned char signed char unsigned char Components Represent Values 0.255 -128.127 0(F),
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Chapter High-Level Language Interface
Keywords
Table 2-1. AltiVec Data Types (Continued)
C/C++ Type vector signed vector signed long* vector signed long int* vector bool vector bool long* vector bool long int* vector float vector pixel float unsigned short IEEE-754 values 1/5/5/5 pixel unsigned (F), signed -231.231-1 Interpretation Contents Components Represent Values
*The vector types with long keyword deprecated will eliminated future version this document.
illustrations where algorithm could apply multiple types, vec_data represents these types. Introducing fundamental types permits compiler provide stronger type checking supports overloaded operations vector types.
Keywords
model introduces uses following
vector _vector pixel _pixel bool
simple type keywords. Among type used declaration, vector type must occur C++, remaining type freely intermixed order, possibly with other declaration syntax does allow typedef name type example, following allowed:
typedef signed short int16; vector int16 data;
These uses with their existing C++. There methods that used deal with this implementation AltiVec programming model choose either method.
2.2.1 Keyword Method
this method, _vector, _pixel, bool added keywords while vector pixel macros. bool already keyword C++. allow keyword, treated same C++. This means that language extended allow bool alone type Typically, this type will int.
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Alignment
accommodate with other uses vector pixel, user either #undef command line option remove
2.2.2 Context Sensitive Keyword Method
this method, _vector _pixel added keywords without regard context while uses vector, pixel, bool keywords only context type. Since vector must among type recognized type when type being scanned. uses pixel bool occur after vector been recognized. other contexts, vector, pixel, bool reserved. This avoids such class vector, typedef bool, allows vector, pixel, bool other uses.
Alignment
following paragraphs described AltiVec alignment requirements. When working with vector data, programmer must aware these alignment issues. Because AltiVec technology does generate exceptions, programmer must determine whether when vector data becomes unaligned.
2.3.1 Alignment Vector Types
data item vector data type memory always aligned 16-byte boundary. pointer vector data type always points 16-byte boundary. compiler responsible aligning vector data types 16-byte boundaries. Given that vector data correctly aligned, program incorrect attempts dereference pointer vector type pointer does contain 16-byte aligned address. AltiVec architecture, unaligned load/store does cause alignment exception that might lead (slow) loading bytes given address. Instead, low-order bits address quietly ignored.
2.3.2 Alignment Non-Vector Types
array components loaded into vector registers need aligned, will have accessed with attention alignment. Typically, this accomplished using either Load Vector Shift Right, vec_lvsr(), Load Vector Shift Left, vec_lvsl(), operation Vector Permute, vec_perm(), operation.
2.3.3 Alignment Aggregates Unions Containing Vector Types
Aggregates (structures arrays) unions containing vector types must aligned 16-byte boundaries their internal organization padded, necessary, that each internal vector type aligned 16-byte boundary. This extension ABIs (AIX, Apple, SVR4, EABI).
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Extensions C/C++ Operators Types
Extensions C/C++ Operators Types
Most C/C++ operators permit their arguments types. vector types pointer vector type. normal C/C++ operators extended include following operations.
2.4.1 sizeof()
operations sizeof(a) sizeof(*p) return
2.4.2 Assignment
either left hand side right hand side expression vector type, then both sides expression must same vector type. Thus, expression valid represents assignment same vector type neither vector type). Otherwise, expression invalid must signaled error compiler.
2.4.3 Address Operator
operation valid vector type. result operation pointer
2.4.4 Pointer Arithmetic
usual pointer arithmetic performed particular, pointer next vector after
2.4.5 Pointer Dereferencing
pointer vector type, implies either 128-bit vector load from address obtained clearing order bits equivalent instruction vec_ld(0, 128-bit vector store that address equivalent instruction vec_st(0, desired mark data accessed least-recently-used (LRU), explicit instruction vec_ldl(0,p) vec_stl(0, must used. Dereferencing pointer non-vector type produces standard behavior either load copy corresponding type. Accessing unaligned memory must carried explicitly
vec_ld(int, type operation, vec_ldl(int, type operation, vec_st(int, type operation vec_stl(int, type operation.
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Operators
2.4.6 Type Casting
Pointers types cast back forth each other. Casting pointer type represents unchecked assertion that address 16-byte aligned. Some operators provided provide equivalence casts data initialization. Casts from vector type another provided normal casts. These should needed frequently overloaded forms operators used. None casts performs conversion; pattern result same pattern argument that cast.
(vector (vector (vector (vector (vector (vector (vector (vector (vector (vector (vector signed char) vec_data signed short) vec_data signed int) vec_data unsigned char) vec_data unsigned short) vec_data unsigned int) vec_data bool char) vec_data bool short) vec_data bool int) vec_data float) vec_data pixel) vec_data
Casts between vector types scalar types illegal. copy data between these types, vec_lde() vec_ste() operations. alternative union consisting vector type equivalent array scalar type copy data using union.
Operators
operators introduced construct vector literals, adjust pointers, allow full access functionality provided AltiVec architecture.
2.5.1 Vector Literals
vector literal written parenthesized vector type followed parenthesized constant expressions. Vector literals used either initialization statements constants executable statements. Table lists formats descriptions vector literals. each, compiler generates code that either computes loads values into register.
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Operators
Table 2-2. Vector Literal Format Description
Notation
(vector unsigned char) (unsigned int)
Represents
unsigned 8-bit quantities which have value
specified integer. unsigned 8-bit quantities specified integers. signed 8-bit quantities that have value specified integer.
(vector unsigned char) (unsigned int, unsigned int) (vector signed char) (int)
(vector signed char) (int, int) (vector unsigned short) (unsigned int)
signed 8-bit quantities specified integers. eight unsigned 16-bit quantities which have value
specified unsigned integer. eight unsigned 16-bit quantities specified eight unsigned integers. eight signed 16-bit quantities which have value specified integer. eight signed 16-bit quantities specified eight integers. four unsigned 32-bit quantities which have value specified unsigned integer. four unsigned 32-bit quantities specified four unsigned integers. four signed 32-bit quantities which have value specified integer. four signed 32-bit quantities specified integers. four floating-point quantities which have value specified floating-point value. four floating-point quantities which have value specified four floating-point values.
(vector unsigned short) (unsigned int, unsigned int) (vector signed short) (int)
(vector signed short) (int, int)
(vector unsigned int) (unsigned int)
(vector unsigned int) (unsigned int, unsigned int) (vector signed int) (int)
(vector signed int) (int, int) (vector float) (float)
(vector float) (float, float)
2.5.2 Vector Literals Casts
combination vector casts vector literals complicate some parsers. implementation required support cast vector type vector cast vector literal when operand cast parenthesized expression. example, programmer write following:
(vector unsigned char)((vector unsigned int)(1, (vector signed char)((vector unsigned short) variable)
similar expressions below without parenthesized expression used conforming application
(vector unsigned char)(vector unsigned int)(1, (vector signed char)(vector unsigned short) variable
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Operators
2.5.3 Value Adjusting Pointers
compile time, vec_step(vec_data) produces integer value representing amount which pointer component AltiVec data should increment cause pointer increment increment bytes. example, vector unsigned short data type considered contain eight unsigned 2-byte values. pointer unsigned 2-byte values used stream through array unsigned 2-byte values full vector time should increment vec_step(vector unsigned short) Table provides summary values data type.
Table 2-3. Increment Value vec_step Data Type
vec_step Expression
vec_step(vector unsigned char) vec_step(vector signed char) vec_step(vector bool char) vec_step(vector unsigned short) vec_step(vector signed short) vec_step(vector bool short) vec_step(vector unsigned int) vec_step(vector signed int) vec_step(vector bool int) vec_step(vector pixel) vec_step(vector float)
Value
2.5.4 Operators Representing AltiVec Operations
operators introduced allow full access functionality provided AltiVec architecture. operators represented programming language language structures that parse like function calls. names associated with these operations with vec_. appearance these forms indicate following: generic AltiVec operation, like vec_add() AltiVec operation, like vec_addubm() predicate computed from AltiVec operation like vec_all_eq() Loading vector components, discussed Section 2.5.1,
Each AltiVec operator takes list arguments that represent input operands. order operands prescribed architecture includes returned result (possibly void). programming model restricts operand types permitted each AltiVec operation, whether generic. programmer override this constraint explicitly casting arguments permissible types.
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Programming Interface
operation, operand types determine whether operation acceptable within programming model type result. example, vec_vaddubm(vector signed char, vector signed char) acceptable programming model because represents reasonable modular addition with signed bytes, while vec_vaddubs(vector signed char, vector signed char) vec_vaddubh(vector signed char, vector signed char) acceptable. permitted, former operation would produce result which saturation treats operands unsigned; latter operation would produce result which adjacent pairs signed bytes treated signed halfwords. generic operation, operand types used determine whether operation acceptable, select particular operation according types arguments, determine type result. example, vec_add(vector signed char, vector signed char) will onto vec_vaddubm() return result type vector signed char, while vec_add(vector unsigned short, vector unsigned short) maps onto vec_vadduhm() return result type vector unsigned short. AltiVec operations that condition register (i.e., compare instructions) treated somewhat differently programming model. programmer access register names. Instead directly specifying compare instruction, programmer makes reference predicate that returns integer value derived from result compare instruction. this value used directly value true, false) condition branching. expected that compiler will produce minimum code needed condition. Predicates begin with vec_all_ vec_any_. Either true false state that compare instruction predicate. example, vec_all_gt(x,y) tests true value after executing some vcmpgt. instruction. complete coverage predicates, additional predicates exercise compare instructions with reversed duplicated arguments. examples, vec_all_lt(x,y) performs vcmpgtx.(y,x), vec_all_nan(x) mapped onto vcmpeqfp.(x,x). programmer wishes have both result compare instruction returned vector register value CR6, programmer operations. determine that these merged. AltiVec operations predicates listed Chapter Operations
Programming Interface
This document does prohibit require implementation provide include #pragma preprocessor commands. implementation requires that include used prior syntax described this document, suggested that include named <altivec.h>. implementation supports #pragma preprocessor commands, suggested that provide _ALTIVEC_ macro with nonzero value. suggested preprocessor command includes following:
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Programming Interface #pragma altivec_codegen
When this pragma compiler AltiVec instructions. When this pragma off, altivec_model pragma also off.
#pragma altivec_model
When this pragma compiler accepts syntax this document, altivec_codegen pragma also
#pragma altivec_vrsave allon
When this pragma compiler maintains VRSAVE register. With allon selected, compiler changes VRSAVE register have bits set. combined with #pragma altivec_vrsave having parent function work once setting value VRSAVE register with #pragma altivec_vrsave allon function calls uses setting #pragma altivec_vrsave off.
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Chapter Application Binary Interface (ABI)
Note: extensions described herein embedded applications still under review PowerPC EABI industry working group, subject change. any, will highlighted future revisions this document. AltiVec programming model extends existing PowerPC ABIs. This chapter extensions System Application Binary Interface PowerPC Processor Supplement (SVR4 ABI), PowerPC Embedded Application Binary Interface (EABI), Appendix PowerPC Compiler Guide (AIX ABI), Apple Macintosh ABI. SVR4 EABI both Big-Endian Little-Endian ABI. This extension independent endian mode.
Data Representation
vector data types 16-bytes long 16-byte aligned. ABIs extended similarly. Aggregates (structures arrays) unions containing vector types must aligned 16-byte boundaries their internal organization padded, necessary, that each internal vector type aligned 16-byte boundary. Apple specify maximum alignment aggregates unions 4-bytes; EABI maximum alignment 8-bytes. Increasing alignment 16-bytes creates opportunity padding holes parameter lists involving these aggregates described Section 3.4.2, Macintosh Parameter Passing without
Register Usage Conventions
register usage conventions vector register follows:
Table 3-1. AltiVec Registers
Register v0-v1 v2-v13 v14-v19 v20-v31 Intended General Parameters, general General General Behavior across call sites Volatile (Caller save) Volatile (Caller save) Volatile (Caller save) Non-volatile (Callee save)
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Stack Frame
Table 3-1. AltiVec Registers
Register VRSAVE Intended Special, Section 3.3, "The Stack Frame Behavior across call sites Non-volatile (Callee save)
VRSAVE special purpose register (SPR256, named vrsave assembly instructions) used inform operating system which vector registers (VRs) need saved reloaded across context switches. this register vector register needs saved restored across context switch. Otherwise, operating system return that register with value that does violate security after context switch. most 32-bit word EABI does VRSAVE special purpose, VRSAVE non-volatile register.
Stack Frame
stack pointer maintains 16-byte alignment SVR4 8-byte alignment EABI Apple Macintosh ABI. necessary align stack dynamically either SVR4 ABI, however, alignment padding space both. additions stack frame vector register save area, vrsave word, alignment padding space dynamically align stack quadword boundary. following additional requirements apply stack frame: Before function changes value vrsave, shall save value VRSAVE time entry function vrsave word. alignment padding space shall either bytes long that address vector register save area (and subsequent stack locations) quadword aligned. code establishing stack frame dynamically aligns stack pointer, shall update stack pointer atomically with stwux instruction. code assume stack pointer entry aligned 8-byte boundary. Before function changes value non-volatile vector register, shall save value word vector register save area bytes before low-addressed alignment padding space. Local variables vector data type which need saved memory will placed stack frame 16-byte alignment boundary same stack frame region used local variables other types.
denotes stack pointer (general purpose register called function after executed code establishing stack frame.
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Stack Frame
3.3.1 SVR4 EABI Stack Frame
size vector register save area presence VRSAVE word vary within function determined registers valid tag. Note: SVR4 ABI, registers valid most general describe stack frame. associated with frame frame valid tag. Figure shows SVR4 EABI stack frame.
High Address Back chain Floating-point register save area General register save area save word VRSAVE save word Alignment padding Vector register save area Local variable space Parameter list area save word Back chain Address
Figure 3-1. SVR4 EABI Stack Frame Table 3-2. Vector Registers Valid Format
Word Bits 0-17 18-29 Name RESERVED START_OFFSET number words between BASE nearest preceding Frame Frame Valid first instruction which this applies. each non-volatile vector register, v31,., v20, with signifying that register saved vector register save area. only VRSAVE word allocated register save area. Description
30-31 0-11
TYPE VECTOR_REGS
VRSAVE_AREA1
1.If more than Vector Registers Valid applies same Frame Frame Valid tag, they shall have same values VRSAVE_AREA
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Table 3-2. Vector Registers Valid Format
Word Bits 13-17 18-29 RANGE VRSAVE_REG SUBTYPE Name Description Size quadwords vector register save area. number words between first last instruction which this applies. only VRSAVE saved VRSAVE word.
1.If more than Vector Registers Valid applies same Frame Frame Valid tag, they shall have same values VRSAVE_AREA
code example below shows sample prologue epilogue code with full saves non-volatile (FPRs), general (GPRs), stack frame less than Kbytes. example aligns stack pointer dynamically, addresses incoming arguments r30, uses volatile maintains VRSAVE, does alter nonvolatile does dynamic stack allocation. Saving restoring updating vrsave occur either order. function that does need address incoming arguments does align stack pointer dynamically recover address original stack pointer with instruction such r11,0(sp). computation example whether addi align stack dynamically based size components frame. Starting with components higher addresses, value computed adding size save area, save area, save word, VRSAVE word. size alignment padding space then computed smallest number bytes needed make multiple example below, alignment padding space bytes. Consequently, used dynamically align stack increasing size alignment padding space either bytes. alignment padding space been bytes, addi would used align stack dynamically decreasing size alignment padding space either bytes. Continuing, value updated adding size vector register save area, local variable space, outgoing parameter list area, save word. size local variable space adjusted that overall value multiple following SVR4 EABI prologue epilogue sample code.
function: mflr rlwinm subfic stwux addi mflr addi r0,4(sp) r11,sp,0 r12,sp,0,28,28 r12,r12,-len sp,sp,r12 _savefpr_14 r11,r11,-144 _savegpr_14_g r30,r11,144 Save return address frame. Save save area based alignment stack length Establish aligned frame Save floating-point registers Compute save area Save gprs fetch Place Save here necessary Save pointer incoming
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Stack Frame arguments Save VRSAVE frame. v0-v10 v20-v31 (for example) Update VRSAVE Compute save area Save Body function Address save area Restore Fetch prior value VRSAVE Restore VRSAVE Address save area Restore gprs Address save area Restore fprs return
mfspr oris mtspr addi addi mtspr addi addi
r0,vrsave r0,-220(r30) r0,r0,0xff70 r0,r0,0x0fff vrsave,r0 r0,sp,len-224 _savevr20 r0,sp,len-224 _restvr20 r0,-220(r30) vrsave,r0 r11,r30,-144 _restgpr_14 r11,r11,144 _restfpr_14_x
3.3.2 Apple Macintosh Stack Frame
Figure shows Apple Macintosh stack frame
High Address Back chain Floating-point register save area General register save area VRSAVE save word Alignment padding Vector register save area Local variable space Parameter list area Saved Reserved Binders Reserved Compilers save word save word Back chain Address
Figure 3-2. Apple Macintosh Stack Frame
Apple Macintosh stack frame allow 220-byte area negative offset from stack pointer. This area used save non-volatile registers before stack pointer been updated. This size this area changed. Depending
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Stack Frame
number non-volatile registers saved, necessary update stack pointer before saving VRs. However, remains unnecessary update stack pointer before saving GPRs FPRs. size save area presence VRSAVE word determined traceback table entry. spare3 2-bit portion traceback table changed following: This 1-bit procedure saves non-volatile vector register save area, saves vrsave VRSAVE word, number vector parameters, uses AltiVec instructions. spare4 Reserved 1-bit When has_vec_info set, following optional traceback table present following position alloca_reg
has_vec_info
This 6-bit represents number non-volatile saved this procedure. Because last register saved always v31, value vr_saved indicates that saved. saves_vrsave this routine saves vrsave, this 1-bit set. VRSAVE word register save area must used restore prior value before returning from this procedure. has_varargs this function variable argument list, this 1-bit set. Otherwise, vectorparms This 7-bit records number vector parameters. non-zero value procedure with vector parameters that does have variable argument list. Otherwise, parmsonstk must set. vec_present This 1-bit AltiVec instructions performed within procedure. following code shows sample prologue epilogue code with full saves nonvolatile general, stack frame less than Kbytes. code example dynamically aligns stack pointer, addresses incoming arguments r31, uses volatile maintains VRSAVE, does alter non-volatile does dynamic stack allocation. Saving restoring updating vrsave register occur either order. function that does need address incoming arguments does align stack pointer dynamically recover address original stack pointer with instruction such r11,0(sp).
vr_saved
computation example whether addi align stack dynamically based size components frame. Starting with components higher addresses, value computed adding size register save area, general register save area, VRSAVE word. size alignment padding space then computed smallest number bytes
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Stack Frame
needed make multiple example below, alignment padding space bytes. Consequently, used align stack dynamically increasing size alignment padding space either bytes. alignment padding space been bytes, addi used align stack dynamically decreasing size alignment padding space either bytes. Continuing, value updated adding size vector register save area, local variable space, outgoing parameter list area, size link area. size local variable space adjusted that overall value multiple following Apple Macintosh prologue epilogue sample code.
function: mflr stmw rlwinm subfic stwux mfspr oris mtspr addi addi mtspr mtlr r0,8(sp) _savef14 r13,-220(sp) r31,sp,0 r12,sp,0,28,28 r12,r12,-len sp,sp,r12 r0,vrsave r0,-224(r31) r0,r0,0xff70 r0,r0,0x0fff vrsave,r0 r0,sp,len-224 _savev20 r0,sp,len-224 _restv20 r0,-224(r31) vrsave,r0 sp,r31 r13,-220(sp) r0,8(sp) _restf14 Save return address frame. Save floating-point registers. Save gprs save area Save here necessary Save pointer incoming arguments based alignment stack length Establish aligned frame Save VRSAVE frame. v0-v10 v20-v31 v20-v31 (for example) Update VRSAVE Compute VRSAVE area Save Body function Address VRSAVE area Restore Fetch prior value VRSAVE Restore Vrsave Restore Restore gprs Restore return address return from _restf14 Restore fprs return
3.3.3 Vector Register Saving Restoring Functions
vector register saving restoring functions described this section part ABI. They here only encourage uniformity among compilers code used save restore VRs. entry functions described this section, contains address word just beyond vector register save area, they leave undisturbed. They modify value r12. following code example saving vector register.
_savev20: addi stvx _savev21: addi r12,r0,-192 v20,r12,r0 r12,r0,-176 save
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Stack Frame stvx _savev22: addi stvx _savev23: addi stvx _savev24: addi stvx _savev25: addi stvx _savev26: addi stvx _savev27: addi stvx _savev28: addi stvx _savev29: addi stvx _savev30: addi stvx _savev31: addi stvx v21,r12,r0 r12,r0,-160 v22,r12,r0 r12,r0,-144 v23,r12,r0 r12,r0,-128 v24,r12,r0 r12,r0,-112 v25,r12,r0 r12,r0,-96 v26,r12,r0 r12,r0,-80 v27,r12,r0 r12,r0,-64 v28,r12,r0 r12,r0,-48 v29,r12,r0 r12,r0,-32 v30,r12,r0 r12,r0,-16 v31,r12,r0 save save save save save save save save save save save return prologue
following code shows restore vector register.
_restv20: addi _restv21: addi _restv22: addi _restv23: addi _restv24: addi _restv25: addi _restv26: addi _restv27: addi _restv28: addi _restv29: addi _restv30: addi _restv31: addi r12,r0,-192 v20,r12,r0 r12,r0,-176 v21,r12,r0 r12,r0,-160 v22,r12,r0 r12,r0,-144 v23,r12,r0 r12,r0,-128 v24,r12,r0 r12,r0,-112 v25,r12,r0 r12,r0,-96 v26,r12,r0 r12,r0,-80 v27,r12,r0 r12,r0,-64 v28,r12,r0 r12,r0,-48 v29,r12,r0 r12,r0,-32 v30,r12,r0 r12,r0,-16 v31,r12,r0 restore restore restore restore restore restore restore restore restore restore restore restore return prologue
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Function Calls
Function Calls
This section applies user functions. Note that intrinsic AltiVec operations treated function calls, these comments apply those operations. twelve vector parameters placed fewer vector type arguments passed, unneeded registers loaded contain values upon entry called function. Functions that declare vector data type return value place that return value function that returns vector type vector parameter requires prototype. This requirement enables compiler avoid shadowing GPRs.
3.4.1 SVR4 EABI Parameter Passing Varargs
SVR4 algorithm passing parameters considers arguments ordered from left argument) right, although order evaluation arguments vector arguments maintain their ordering. algorithm contain number next available vector register. INITIALIZE step, vr=2. SCAN loop, case next argument VECTOR_ARG follows: next argument variable portion parameter list, vr=14. This leaves portion variable argument list places variable portion memory. vr>13 (that there more available VRs), OTHER. Otherwise, load argument value into vector register vr+1, SCAN.
OTHER case only understand that vector arguments have 16-byte size alignment. Aggregates passed reference (i.e., converted pointer object), change needed deal with 16-byte aligned aggregates. va_list type unchanged, additional va_arg_type value named arg_VECTOR _va_arg() interface. Since vector parameters variable portion parameter list passed memory, _va_arg() routine access vector value from overflow_arg_area value va_list type.
3.4.2 Apple Macintosh Parameter Passing without Varargs
function does take variable argument list, non-vector parameters passed same registers stack locations they would vector parameters were present. only change that aggregates unions 16-byte aligned instead 4-byte aligned. This result words parameter list being skipped alignment (padding) left with value.
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malloc(), vec_malloc(),
twelve vector parameters placed These parameters shadowed GPRs. They allocated space memory argument list. additional vector parameters passed through memory program stack. They appear together, 16-byte aligned, after non-vector parameters.
3.4.3 Apple Macintosh Parameter Passing with Varargs
va_list type continues pointer memory location next parameter. va_arg() accesses vector type, va_list value must aligned 16-byte boundary. function that takes variable argument list parameters, including vector parameters, mapped argument area ordered aligned according their type. words argument area shadowed GPRs only they correspond variable portion parameter list. parameter word named stack offset 0x24. vector parameter must aligned 16-byte boundary. This means there cases where vector parameters passed GPRs. vector parameter passed PW2:PW5 (stack offset 0x32), value placed vector parameter passed PW6:PW9 (stack offset 0x48), value PW6:PW7 placed GPR9 GPR10 value PW8:PW9 placed stack. parameters after words argument area that correspond variable portion parameter list passed memory. portion parameter list, vector parameters placed provided stack location corresponding their position parameter list.
malloc(), vec_malloc(),
interest saving space, malloc(), calloc(), realloc() required return 16-byte aligned address. Instead, memory management functions introduced that return 16-byte aligned address. functions named vec_malloc(), vec_calloc(), vec_realloc(), vec_free(). sets memory management functions interchanged: memory allocated with malloc(), calloc(), realloc() only freed with free() reallocated with realloc(); memory allocated with vec_alloc(), vec_calloc(), vec_realloc() only freed with vec_free() reallocated with vec_realloc(). user must appropriate functions based alignment requirement type involved. case operator new, implementation required appropriate functions based alignment requirement type.
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setjmp() longjmp()
setjmp() longjmp()
context required saved restored setjmp(), longjmp(), related functions includes non-volatile vrsave. user types sigjmp_buf jmp_buf extended words. unused word existing jmp_buf used save VRSAVE.
Table 3-3. Specifications setjmp() longjmp()
Apple Macintosh SVR4 EABI jmp_buf Size VRSAVE Offset Offset
There complications implementing setjmp() longjmp(): user types must enlarged. Existing applications that these interfaces will have recompiled even though they make AltiVec instruction set. implementation that saves restores only assume that offset aligned 4-byte boundary. method where saved aligned location jmp_buf rejected because user types only 4-byte aligned copied value location with different alignment. implementation that saves restores vrsave uses instructions that exist non-AltiVec enabled PowerPC implementation. method testing whether AltiVec instructions operate privileged. solution interface that saves restores vrsave only AltiVec instructions exist enabled.
simple solution these complications setjmp(), longjmp() user types sigjmp_buf jmp_buf differently when compiled with AltiVec-enabled compiler (i.e., when _VEC_ These bindings result larger jmp_buf with 16-byte alignment. bindings setjmp() longjmp() unconditionally save restore vector state. Such implementation does save restore vector state when these interfaces compiled without AltiVec-enabled compiler. application must ensure that these sets bindings mixed.
Debugging Information
Extensions debugging information format required describe vector types vector register locations. While vector types described length arrays existing types, implementation should describe these fundamental types. Doing allows debugger provide mechanisms display vector values, assign vector values, create vector literals.
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printf() scanf() Control Strings
This section subject change. intended describe extensions standard debugging formats: xcoff stabstrings, DWARF version 1.1.0, DWARF version 2.0.0. Xcoff stabstrings used adopted Apple Macintosh support location objects GPRs FPRs. stabstring code describes parameter passed value given GPR; describes local variable residing given GPR. stabstring code describes parameter passed value given vector register; describes local variable residing given vector register. DWARF debugging DIEs support location objects machine register. SVR4 DWARF register number mapping. assigned register numbers VRSAVE SPR256 assigned register number 356.
printf() scanf() Control Strings
conversion control strings input functions (fscanf, scanf, sscanf) output functions (fprintf, printf, sprintf, vfprintf, vprintf, vsprintf) extended support vector types.
3.8.1 Output Conversion
output conversion have following general form:
where,
<flags> <flag-char> <std-flag-char> <c-sep> <width> <precision> <size> <vector-size> <conversion> <char-conv> <str-conv> <fp-conv> <int-conv> <misc-conv> ::=<flag-char> <flags><flag-char> ::=<std-flag-char> <c-sep> <decimal-integer> <width> <vector-size> <char-conv> <str-conv> <fp-conv> <int-conv> <misc-conv>
extensions output conversion vector types shown bold. <vector-size> indicates that single vector value converted. vector value displayed following general form:
value1 value2 valuen
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where separator character <c-sep> there output values depending <vector-size> each formatted according <conversion>, follows: <vector-size> consumes argument <int-conv> conversion; should type vector signed int, vector unsigned int, vector bool int; treated series four 4-byte components. <vector-size> consumes argument <int-conv> conversion; should type vector signed short, vector unsigned short, vector bool short, vector pixel; treated series eight 2-byte components. <vector-size> with <int-conv> <char-conv> consumes argument; should type vector signed char, vector unsigned char, vector bool char; treated series sixteen 1-byte components. <vector-size> with <fp-conv> consumes argument; should type vector float; treated series four 4-byte components. other combinations <vector-size> <conversion>
default value separator character space unless conversion being used. conversion default separator character null. Only separator character <flags>. Examples:
vector signed char vector signed vector unsigned short vector unsigned short(1,2,3,4,5,6,7,8); vector signed vector signed int(1, 99); vector float vector float(1.1, 2.2, 3.3, 4.39501); s8); s8); u16); s32); f32);
This code produces following output:
defghijklm,op a,b, ,d,e,f,g,h,i,j,k,l,m,,,o,p 3,99 1.10 ,2.20 ,3.30 ,4.40
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3.8.2 Input Conversion
input conversion have following general form:
where,
<flags> <c-sep> <width> <size> <vector-size> <conversion> <char-conv> <str-conv> <fp-conv> <int-conv> <misc-conv> <c-sep> <c-sep> <decimal-integer> <vector-size> <char-conv> <str-conv> <fp-conv> <int-conv> <misc-conv>
extensions input conversion vector types shown bold. <vector-size> indicates that single vector value scanned converted. vector value scanned following general form:
value1 value2 valuen
where separator sequence <c-sep> (the separator character optionally preceded whitespace characters) values scanned depending <vector-size> each value scanned according <conversion>, follows: <vector-size> consumes argument <int-conv> conversion; should type vector signed vector unsigned depending <int-conv> four values scanned. <vector-size> consumes argument <int-conv> conversion; should type vector signed vector unsigned short depending <int-conv> values scanned. <vector-size> with <int-conv> <char-conv> consumes argument; should type vector signed char vector unsigned char depending <int-conv> <char-conv> values scanned. <vector-size> with <fp-conv> consumes argument; should type vector float four values scanned. other combinations <vector-size> <conversion>
conversion default separator character null, separator sequence does include whitespace characters preceding separator character. other than
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conversions, default separator character space, separator sequence does include whitespace characters preceding separator character.
input stream reaches there between control string character read from input stream, input functions return assign their vector argument. When occurs, character causing remains unread processed next input operation. Examples:
&s8); &s8); &u16); &s32); ,2.20 ,3.30 ,&f32);
This equivalent
vector signed char vector signed vector unsigned short vector unsigned short(1,2,3,4,5,6,7,8); vector signed vector signed int(1, 99); vector float vector float(1.1, 2.2, 3.3, 4.4);
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Chapter AltiVec Operations Predicates
following three subsections provide some background information that helpful understanding descriptions provided each operation predicate. This followed detailed listing AltiVec operations followed separate section describing AltiVec predicates. subsection contains compiler notes handling predicates.
Vector Status Control Register
vector status control register (VSCR) special 32-bit vector register shown Figure 4-1.
Reserved
Figure 4-1. Vector Status Control Register (VSCR)
VSCR bits, AltiVec non-Java mode (NJ) (VSCR[15]) AltiVec saturation (SAT) (VSCR[31]); remaining bits reserved. vec_mfvscr operation moves VSCR vector register. When moved, 32-bit VSCR 128-bit vector register, upper bits vector register cleared, VSCR vector register looks shown Figure 4-2.
Reserved
Figure 4-2. VSCR Moved Vector Register
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Vector Status Control Register
VSCR settings shown Table 4-1.
Table 4-1. VSCR Field Descriptions
Bits
Name
Description Reserved. Software permitted write value such bit. subsequent reading returns value last written returns undefined value otherwise. Non-Java. mode control that determines whether AltiVec floating-point operations will performed Java-IEEE-C9X-compliant mode possibly faster non-Java/non-IEEE mode. Java-IEEE-C9X-compliant mode selected. Denormalized values handled specified Java, IEEE, standard. non-Java/non-IEEE-compliant mode selected. element source vector register contains denormalized value, value used instead. instruction causes underflow exception, corresponding element target cleared both cases same sign denormalized underflowing value. This mode described detail AltiVec Programming Environments Manual. Reserved. Software permitted write value such bit. subsequent reading returns value last written returns undefined value otherwise. Saturation. sticky status indicating that some field saturating instruction saturated since last time cleared. other words, when remains until cleared explicit instruction. Indicates saturation occurred, instruction explicitly clear this bit. AltiVec saturate instruction implicitly sets field when saturation occurred results AltiVec instructions vector operations having saturate name.
0-14
16-30
After vec_mfvscr executes, result target vector register architecturally precise. That updates that could have been made vector instructions logically preceding program further, does updates that made vector instructions logically following program Reading VSCR much slower than typical AltiVec instructions, therefore care must taken reading avoid performance problems. 16-bit elements result seventh element result contains high-order bits VSCR (including NJ). eighth element result contains low-order bits VSCR (including SAT). setting Non-Java mode (NJ) (VSCR[15]) affects some vector operations. other special (VSCR[31]) AltiVec Saturation (SAT) that when operation generates saturated result. Saturation with respect type resulting element result saturating value with respect type means:
(minimum(t), min(maximum(t), where minimum(t) algebraically smallest value representable number type maximum(t) algebraically largest value number type
each operation, where applicable, effects setting and/or effects described operation description.
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Byte Ordering
Byte Ordering
default mapping AltiVec PowerPC big-endian. endian support PowerPC architecture does address data element larger than double word; basic memory unit vectors quad word. Big-endian byte ordering shown Figure 4-3.
Quad Word
High-Order Word Low-Order High-Order Half Word Half Word Word Word High-Order Half Word Half Word HighOrder Byte Byte
Word
Word
Low-Order Word
Low-Order Half Word Half Word Half Word Half Word Half Word Half Word Half Word Half Word LowOrder Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
(HighOrder)
(LowOrder)
Figure 4-3. Big-Endian Byte Ordering Vector Register
shown Figure 4-3, vector register elements numbered using big-endian byte ordering. example, high-order most byte element numbered low-order least byte element numbered When high-order low-order elements vector register, careful confuse meaning based numbering. example, Figure high-order half word word would half word (bits low-order half word word would half word (bits
MOTOROLA
Chapter AltiVec Operations Predicates
Notation Conventions
Notation Conventions
Operation predicate functionality described this section semiformal pseudocode language. Table lists pseudocode notation conventions used throughout section.
Table 4-2. Notation Conventions
Notation/Convention Meaning Assignment Add, single-precision floating-point Subtract, single-precision floating-point subtract Multiply, single-precision floating-point multiply Integer division with non-negative remainder Less than, single-precision floating-point less than Less than equal, single-precision floating-point less than equal Greater than, single-precision floating-point greater than Greater than equal, single-precision floating-point greater than equal equal, floating-point equal Equal, floating-point equal Positive infinity, negative infinity Concatenation strings (e.g., same 010111) bit-wise operator bit-wise operator Exclusive-OR bit-wise operator logical operator (one's complement) number expressed binary format number expressed hexadecimal format These symbols represent whole operands AltiVec operation predicate. This typically vector, some operations represent specific length literal value. These symbols represent component elements vector respectively. Absolute value Borrow difference Align y-byte boundary. Carry smallest single-precision floating-point integer that greater than equal loop. following starting iterating Indenting shows range. "To" and/or "by" clauses specify incrementing iteration variable. "While" clauses give termination conditions. Indicates loop
!=fp 0bnnnn 0xnnnn a,b,c,d
ai,bi,ci,di ABS(x) BorrowOut(x BoundAlign(x,y) CarryOut(x Ceil(x)
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Notation Conventions
Table 4-2. Notation Conventions (Continued)
Notation/Convention Floor(x) Est(x) FPLog2Est(x) FPRecipEst(x) if.then.else. ISNaN(x) ISNUM(x) MAX(x,y) Meaning largest single-precision floating-point integer that less than equal 3-bit-accurate floating-point estimate 2**x 3-bit-accurate floating-point estimate log2(x) 12-bit-accurate floating-point estimate Conditional execution, indenting shows range, else optional. Result number (NaN) number Result number number (NaN) Returns larger floating-point values, following applies: maximum +0.0 -0.0 +0.0 maximum value QNaN Value memory location size bytes Returns smaller floating-point values, following applies: minimum +0.0 -0.0 -0.0 minimum value QNaN Remainder Number, non-numeric Result Result otherwise Result oherwise Result otherwise Result otherwise that propagates through most arithmetic operations without signalling exception Result 12-bit accurate single-precision floating-point estimate reciprocal square root single-precision floating-point integer that nearest value case tie, even single-precision floating-point value used). largest single-precision floating-point integer that less than equal smallest single-precision floating-point integer that greater than equal IEEE rounding nearest floating-point number Result rotating left bits Represents propagated sign figure Saturate(x) means saturate type Shift contents right left bits, clearing vacated bits (logical shift). This operation used shift instructions. Shift contents right bits, copying sign vacated bits (algebraic shift) Sign-extend left with sign bits (that with copies produce y-bit value; represented figures single Result converting signed integer y-bit floating-point value using Round-to-Nearest mode
MEM(x,y) MIN(x,y)
mod(x,y) NEG(x) NGE(x,y) NGT(x,y) NLE(x,y) NLT(x,y) QNaN RecipSQRTEst(x) RndToFPINear(x) RndToFPITrunc(x)
RndToFPNearest(x) ROTL(x,y) Saturate(x) ShiftRight(x,y) ShiftLeft(x,y) ShiftRightA(x,y) SignExtend(x,y) SIToFP(x,y)
MOTOROLA
Chapter AltiVec Operations Predicates
Notation Conventions
Table 4-2. Notation Conventions (Continued)
Notation/Convention UIToUImod(x,y) Undefined x{i} x[y:x]
Meaning Truncate unsigned integer y-bit unsigned integer undefined value. value vary from implementation another, from execution another same implementation. element vector where size type element determined type byte vector Bits through vector where equal referring single string zeros string ones string copies example, raised power
Precedence rules pseudocode operators summarized Table 4-3.
Table 4-3. Precedence Rules
Operators x{i}, x[y], x[y:z] function evaluation
Associativity Left right Right left Right left Left right Left right Left right Left right Left right Left right None
replication, exponentiation
unary *fp, +fp, =fp,!=,!=fp, <fp, >fp,
Operators higher Table applied before those lower table. Operators same level table associate from left right, from right left, all, shown. example, (unary minus) associates from left right, Parentheses used override evaluation order implied Table 4-3, increase clarity; parenthesized expressions evaluated before serving operands.
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Generic Specific AltiVec Operations
Generic AltiVec Operations
AltiVec operations organized alphabetically generic operation name with permitted generic AltiVec operations. operations listed alphabetical order mnemonic. Figure shows format each operation description page.
Operation mnemonic Operation name Pseudocode description operation
vec_cmpge
Vector Compare Greater Than Equal
vec_cmpge
vec_cmpge(a,b)
then else
Text description operation
Each element result corresponding element greaterthanor equal responding lement Otherwise, returns VSCR[NJ] everydenormalize floating operandelement uncated before thecomparison made. valid argument types correspon ding result type vec_cmpge(a,b) shown Figure4-31.
Figure showing operation usage mapping
Element->
vector bool
vector float
vector float
maps vcmpgefp d,a,b
Figure 4-31. Compare Greater-Than- or-E qual Four Float ing- Point Elements (32-Bit)
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Figure 4-4. Operation Description Format
Where possible, each description supported reference indicating data including table that lists: valid argument types that generic AltiVec operation, result type each argument types, AltiVec instruction(s) generated that arguments.
operation explicitly permitted this section prohibited.
MOTOROLA
Chapter AltiVec Operations Predicates
Generic Specific AltiVec Operations
vec_abs
Vector Absolute Value
vec_abs
vec_abs(a)
number elements ABS(ai)
Each element result absolute value corresponding element arithmetic modular integer types. vector float argument types, operation independent VSCR[NJ]. Programming note: Unlike other operations, vec_abs maps multiple instructions. programmer should consider alternatives. example, compute absolute difference vectors expression vec_abs(vec_sub(a,b)) expands four instructions. simpler method uses expression vec_sub(vec_max(a,b), vec_min(a,b)) that expands three instructions. valid combinations argument types corresponding result types vec_abs(a) shown Figure 4-5, Figure 4-6, Figure 4-7, Figure 4-8. necessary generic name since there operation vec_abs.
Element®
maps vspltisb vsububm t,z,a vmaxsb d,a,t
vector signed char
vector signed char
Figure 4-5. Absolute Value Sixteen Integer Elements (8-bit)
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Generic Specific AltiVec Operations
Element®
maps vspltisb vsubuhm t,z,a vmaxsh d,a,t
vector signed short
vector signed short
Figure 4-6. Absolute Value Eight Integer Elements (16-bit)
Element®
maps vsplisb vsubuwm t,z,a vmaxsw d,a,t
vector signed
vector signed
Figure 4-7. Absolute Value Four Integer Elements (32-bit)
Element®
maps vspltisw m,-1 vslw t,m,m vandc d,a,t
vector float
vector float
Figure 4-8. Absolute Value Four Floating-Point Elements (32-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
Generic Specific AltiVec Operations
vec_abss
Vector Absolute Value Saturated
vec_abss
vec_abss(a)
number elements Saturate(ABS(ai))
Each element result absolute value corresponding element arithmetic saturated integer types. saturation occurs, VSCR[SAT] (see Table 4-1). Programming note: Unlike other operations, vec_abss maps multiple instructions. programmer should consider alternatives. example, compute absolute difference vectors expression vec_abss(vec_subs(a,b)) expands four instructions. simpler method uses expression that expands three instructions. valid combinations argument types corresponding result types vec_abss(a) shown Figure 4-9, Figure 4-10, Figure 4-11. necessary generic name since there operation vec_abss.
Element®
maps vspltisb vsubsbs t,z,a vmaxsb d,a,t
vector signed char
vector signed char
Figure 4-9. Saturated Absolute Value Sixteen Integer Elements (8-bit)
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Generic Specific AltiVec Operations
Element®
maps vspltisb vsubshs t,z,a vmaxsh d,a,t
vector signed short
vector signed short
Figure 4-10. Saturated Absolute Value Eight Integer Elements (16-bit)
Element®
maps vsplisb vsubsws t,z,a vmaxsw d,a,t
vector signed
vector signed
Figure 4-11. Saturated Absolute Value Four Integer Elements (32-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-11
Generic Specific AltiVec Operations
vec_add
Vector
vec_add
vec_add(a,b) Integer add:
number elements
Floating-point add:
Each element added corresponding element Each placed corresponding element vector float argument types, VSCR[NJ] every denormalized operand element truncated same sign before operation carried out, each denormalized result element truncated same sign. valid combinations argument types corresponding result types vec_add(a,b) shown Figure 4-12, Figure 4-13, Figure 4-14, Figure 4-15.
Element®
vector unsigned char
vector unsigned char vector bool char vector unsigned char
maps
vector unsigned char
vector unsigned char vector bool char vector signed char
vaddubm d,a,b vector signed char vector bool char vector signed char vector signed char vector signed char vector bool char
Figure 4-12. Sixteen Integer Elements (8-bit)
4-12
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Generic Specific AltiVec Operations
Element®
vector unsigned short
vector unsigned short vector bool short vector unsigned short
maps
vector unsigned short
vector unsigned short vector bool short vector signed short
vadduhm d,a,b vector signed short vector bool short vector signed short vector signed short vector signed short vector bool short
Figure 4-13. Eight Integer Elements (16-bit)
Element®
vector unsigned
vector unsigned vector bool vector unsigned
maps
vector unsigned
vector unsigned vector bool vector signed
vadduwm d,a,b vector signed vector bool vector signed vector signed vector signed vector bool
Figure 4-14. Four Integer Elements (32-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-13
Generic Specific AltiVec Operations
Element®
vector float
vector float
vector float
maps vaddfp d,a,b
Figure 4-15. Four Floating-Point Elements (32-bit)
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Generic Specific AltiVec Operations
vec_addc
Vector Carryout Unsigned Word
vec_addc
vec_addc(a,b)
CarryOut(ai
Each element added corresponding element carry from each zero-extended placed into corresponding element CarryOut there carry, otherwise valid argument types corresponding result type vec_addc(a,b) shown Figure 4-16.
Element®
33-bit element (temp)
vector unsigned
vector unsigned
vector unsigned
maps vaddcuw d,a,b
Figure 4-16. Carryout Four Unsigned Integer Adds (32-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-15
Generic Specific AltiVec Operations
vec_adds
Vector Saturated
vec_adds
vec_adds(a,b)
number elements Saturate(ai
Each element added corresponding element saturation occurs, VSCR[SAT] (see Table 4-1). signed-integer result placed into corresponding element valid combinations argument types corresponding result types vec_adds(a,b) shown Figure 4-17, Figure 4-18, Figure 4-19.
Element®
vector unsigned char
vector unsigned char vector bool char vector unsigned char vector signed char vector bool char vector signed char
maps
vector unsigned char
vector unsigned char vector bool char vector signed char
vaddubs d,a,b
vector signed char
vector signed char vector bool char
vaddsbs d,a,b
Figure 4-17. Saturating Sixteen Integer Elements (8-bit)
4-16
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Generic Specific AltiVec Operations
Element®
vector unsigned short
vector unsigned short vector bool short vector unsigned short vector signed short vector bool short vector signed short
maps
vector unsigned short
vector unsigned short vector bool short vector signed short
vadduhs d,a,b
vector signed short
vector signed short vector bool short
vaddshs d,a,b
Figure 4-18. Saturating Eight Integer Elements (16-bit)
Element®
vector unsigned
vector unsigned vector bool vector unsigned vector signed vector bool vector signed
maps
vector unsigned
vector unsigned vector bool vector signed
vadduws d,a,b
vector signed
vector signed vector bool
vaddsws d,a,b
Figure 4-19. Saturating Four Integer Elements (32-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-17
Generic Specific AltiVec Operations
vec_and
Vector Logical
vec_and
vec_and(a,b)
Each result logical corresponding bits valid combinations argument types corresponding result types vec_and(a,b) shown Figure 4-20.
vector unsigned char
vector unsigned char vector unsigned char vector bool char vector signed char
vector unsigned char vector bool char vector unsigned char vector signed char vector bool char vector signed char vector bool char vector unsigned short vector bool short vector unsigned short vector signed short vector bool short vector signed short vector bool short vector unsigned vector bool vector unsigned vector signed vector bool vector signed vector bool vector float vector bool vector float
maps
vector signed char vector bool char vector unsigned short
vector signed char vector bool char vector bool char vector unsigned short vector unsigned short vector bool short vector signed short
vector signed short vector bool short vector unsigned
vector signed short vector bool short vector bool short vector unsigned vector unsigned vector bool vector signed
vand d,a,b
vector signed vector bool vector float
vector signed vector bool vector bool vector bool vector float vector float
Figure 4-20. Logical Bit-Wise
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Generic Specific AltiVec Operations
vec_andc
Vector Logical with Complement
vec_andc
vec_andc(a,b)
Each result logical corresponding one's complement corresponding valid combinations argument types corresponding result types vec_andc(a,b) shown Figure 4-21.
temp
Figure 4-21. Logical Bit-Wise with Complement
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Chapter AltiVec Operations Predicates
4-19
Generic Specific AltiVec Operations
vector unsigned char
vector unsigned char vector unsigned char vector bool char vector signed char
vector unsigned char vector bool char vector unsigned char vector signed char vector bool char vector signed char vector bool char vector unsigned short vector bool short vector unsigned short vector signed short vector bool short vector signed short vector bool short vector unsigned vector bool vector unsigned vector signed vector bool vector signed vector bool vector float vector bool vector float
maps
vector signed char vector bool char vector unsigned short
vector signed char vector bool char vector bool char vector unsigned short vector unsigned short vector bool short vector signed short
vector signed short vector bool short vector unsigned
vector signed short vector bool short vector bool short vector unsigned vector unsigned vector bool vector signed
vandc d,a,b
vector signed vector bool vector float
vector signed vector bool vector bool vector bool vector float vector float
Figure 4-21. Logical Bit-Wise with Complement
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Generic Specific AltiVec Operations
vec_avg
Vector Average
vec_avg
vec_avg(a,b)
number elements
Each element result rounded average corresponding elements Intermediate calculations limited element size. value added elements ensure result rounded valid combinations argument types corresponding result types vec_avg(a,b) shown Figure 4-22, Figure 4-23, Figure 4-24.
Element®
bits Temp bits
Temp
vector unsigned char vector signed char
vector unsigned char vector signed char
vector unsigned char vector signed char
maps vavgub d,a,b vavgsb d,a,b
Figure 4-22. Average Sixteen Integer Elements (8-bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-21
Generic Specific AltiVec Operations
Element®
bits
bits Temp
Temp
vector unsigned short vector signed short
vector unsigned short vector signed short
vector unsigned short vector signed short
maps vavguh d,a,b vavgsh d,a,b
Figure 4-23. Average Eight Integer Elements (16-bit)
Element®
bits Temp bits
Temp
vector unsigned vector signed
vector unsigned vector signed
vector unsigned vector signed
maps vavguw d,a,b vavgsw d,a,b
Figure 4-24. Average Four Integer Elements (32-bit)
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Generic Specific AltiVec Operations
vec_ceil
Vector Ceiling
vec_ceil
vec_ceil(a)
Ceil(ai)
Each single-precision element rounded single-precision integer using rounding mode Round toward placed into corresponding word element element corresponding element equals element corresponding element smallest represented value example, element 123.45, resulting integer would 124. VSCR[NJ] every denormalized operand element truncated before operation. valid argument types corresponding result type vec_ceil(a,b) shown Figure 4-25.
Element®
Ceil
Ceil
Ceil
Ceil
vector float
vector float
maps vrfip
Figure 4-25. Round Plus Infinity Four Floating-Point Integer Elements (32-Bit)
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Chapter AltiVec Operations Predicates
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Generic Specific AltiVec Operations
vec_cmpb
Vector Compare Bounds Floating-Point
vec_cmpb
vec_cmpb(a,b)
then else then else
di[0] di[0] di[1] di[1]
Each element compared corresponding element 2-bit result indicates whether element within bounds element each result element less than equal element (i.e., bounds high), otherwise (i.e., bounds high). 2-bit value element greater than equal negative element (i.e., bounds low), otherwise (i.e., bounds low). 2-bit result placed into high-order bits (bit corresponding element (which correspond bits respectively) remaining bits cleared. singleprecision word element negative; corresponding element bounds. element element NaN, high-order bits corresponding result both VSCR[NJ] every denormalized operand element truncated before comparison. valid argument types corresponding result type vec_cmpb(a,b) shown Figure 4-26.
Element®
(temp)
vector signed
vector float
vector float
maps vcmpbfp d,a,b
Figure 4-26. Compare Bounds Four Floating-Point Elements (32-Bit)
4-24 AltiVec Technology Programming Interface Manual MOTOROLA
Generic Specific AltiVec Operations
vec_cmpeq
Vector Compare Equal
vec_cmpeq
vec_cmpeq(a,b) Integer compare equal:
number elements number bits element (128/n) then else
Floating-point compare equal:
then else
Each element result ones corresponding element equal corresponding element Otherwise, returns zeros. vector float argument types, VSCR[NJ] every denormalized operand element truncated before comparison. valid combinations argument types corresponding result types vec_cmpeq(a,b) shown Figure 4-27, Figure 4-28, Figure 4-29, Figure 4-30.
Element®
vector bool char
vector unsigned char vector signed char
vector unsigned char vector signed char
maps vcmpequb d,a,b
Figure 4-27. Compare Equal Sixteen Integer Elements (8-bits)
MOTOROLA
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4-25
Generic Specific AltiVec Operations
Element®
vector bool short
vector unsigned short vector signed short
vector unsigned short vector signed short
maps vcmpequh d,a,b
Figure 4-28. Compare Equal Eight Integer Elements (16-Bit)
Element®
vector bool
vector unsigned vector signed
vector unsigned vector signed
maps vcmpequw d,a,b
Figure 4-29. Compare Equal Four Integer Elements (32-Bit)
Element®
vector bool
vector float
vector float
maps vcmpeqfp d,a,b
Figure 4-30. Compare Equal Four Floating-Point Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_cmpge
Vector Compare Greater Than Equal
vec_cmpge
vec_cmpge(a,b)
then else
Each element result ones corresponding element greater than equal corresponding element Otherwise, returns zeros. VSCR[NJ] every denormalized operand element truncated before comparison.
valid argument types corresponding result type Figure 4-31.
Element®
vec_cmpge(a,b) shown
vector bool
vector float
vector float
maps vcmpgefp d,a,b
Figure 4-31. Compare Greater-Than-or-Equal Four Floating-Point Elements (32-Bit)
MOTOROLA
Chapter AltiVec Operations Predicates
4-27
Generic Specific AltiVec Operations
vec_cmpgt
Vector Compare Greater Than
vec_cmpgt
vec_cmpgt(a,b) Integer compare greater than:
number elements number bits element (128/n) then else
Floating-point compare greater than:
then else
Each element result ones corresponding element greater than corresponding element Otherwise, returns zeros. vector float types, VSCR[NJ] every denormalized operand element truncated before comparison. valid combinations argument types corresponding result types vec_cmpgt(a,b) shown Figure 4-32, Figure 4-33, Figure 4-34, Figure 4-35.
Element®
vector bool char
vector unsigned char vector signed char
vector unsigned char vector signed char
maps vcmpgtub d,a,b vcmpgtsb d,a,b
Figure 4-32. Compare Greater-Than Sixteen Integer Elements (8-bits)
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Generic Specific AltiVec Operations
Element®
vector bool short
vector unsigned short vector signed short
vector unsigned short vector signed short
maps vcmpgtuh d,a,b vcmpgtsh d,a,b
Figure 4-33. Compare Greater-Than Eight Integer Elements (16-Bit)
Element®
vector bool
vector unsigned vector signed
vector unsigned vector signed
maps vcmpgtuw d,a,b vcmpgtsw d,a,b
Figure 4-34. Compare Greater-Than Four Integer Elements (32-Bit)
Element®
vector bool
vector float
vector float
maps vcmpgtfp d,a,b
Figure 4-35. Compare Greater-Than Four Floating-Point Elements (32-Bit)
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Chapter AltiVec Operations Predicates
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Generic Specific AltiVec Operations
vec_cmple
Vector Compare Less Than Equal
vec_cmple
vec_cmple(a,b)
then else
Each element result ones corresponding element less than equal corresponding element Otherwise, returns zeros. VSCR[NJ] every denormalized operand element truncated before comparison.
valid argument types corresponding result type vec_cmple(a,b) shown Figure 4-36. necessary generic name, since specific operation vec_vcmpgefp does reverse operands.
Element®
vector bool
vector float
vector float
maps vcmpgefp d,b,a
Figure 4-36. Compare Less-Than-or-Equal Four Floating-Point Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_cmplt
Vector Compare Less Than
vec_cmplt
vec_cmplt(a,b) Integer compare less than:
number elements number bits element (128/n) then else
Floating-point compare less than:
then else
Each element result ones corresponding element less than corresponding element Otherwise, returns zeros. vector float types, VSCR[NJ] every denormalized operand element truncated before comparison. valid combinations argument types corresponding result types vec_cmplt(a,b) shown Figure 4-37, Figure 4-38, Figure 4-39, Figure 4-40. necessary generic name, since operations reverse their operands.
Element®
vector bool char
vector unsigned char vector signed char
vector unsigned char vector signed char
maps vcmpgtub d,b,a vcmpgtsb d,b,a
Figure 4-37. Compare Less-Than Sixteen Integer Elements (8-bits)
MOTOROLA
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4-31
Generic Specific AltiVec Operations
Element®
vector bool short
vector unsigned short vector signed short
vector unsigned short vector signed short
maps vcmpgtuh d,b,a vcmpgtsh d,b,a
Figure 4-38. Compare Less-Than Eight Integer Elements (16-Bit)
Element®
vector bool
vector unsigned vector signed
vector unsigned vector signed
maps vcmpgtuw d,b,a vcmpgtsw d,b,a
Figure 4-39. Compare Less-Than Four Integer Elements (32-Bit)
Element®
vector bool
vector float
vector float
maps vcmpgtfp d,b,a
Figure 4-40. Compare Less-Than Four Floating-Point Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_ctf
Vector Convert from Fixed-Point Word
vec_ctf
vec_ctf(a,b)
SIToFP(ai)
Each element result closest representation number obtained dividing corresponding element power operation independent VSCR[NJ]. valid argument types corresponding result type vec_ctf(a,b) shown Figure 4-41.
Element®
SIToFP
SIToFP
SIToFP
SIToFP
vector float
vector unsigned vector signed
5-bit unsigned literal 5-bit unsigned literal
maps vcfux d,a,b vcfsx d,a,b
Figure 4-41. Convert Four Integer Elements Four Floating-Point Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_cts
Vector Convert Signed Fixed-Point Word Saturated
vec_cts
vec_cts(a,b)
Saturate(ai
Each element result saturated signed value obtained after truncating product corresponding element power VSCR[NJ] every denormalized operand element truncated before operation. saturation occurs, VSCR[SAT] (see Table 4-1). valid argument types corresponding result type vec_cts(a,b) shown Figure 4-42.
Element®
Saturate
Saturate
Saturate
Saturate
vector signed
vector float
5-bit unsigned literal
maps vctsxs d,a,b
Figure 4-42. Convert Four Floating-Point Elements Four Saturated Signed Integer Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_ctu
Vector Convert Unsigned Fixed-Point Word Saturated
vec_ctu
vec_ctu(a,b)
Saturate
Each element result saturated unsigned value obtained after truncating number obtained multiplying corresponding element power VSCR[NJ] every denormalized operand element truncated before operation. saturation occurs, VSCR[SAT] (see Table 4-1). valid argument types corresponding result type vec_ctu(a,b) shown Figure 4-43.
Element®
Saturate
Saturate
Saturate
Saturate
vector unsigned
vector float
5-bit unsigned literal
maps vctuxs d,a,b
Figure 4-43. Convert Four Floating-Point Elements Four Saturated Unsigned Integer Elements (32-Bit)
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Generic Specific AltiVec Operations
vec_dss
Vector Data Stream Stop
vec_dss
vec_dss(a)
DataStreamPrefetchControl
Each operation stops cache touches data stream associated with result void. valid argument type vec_dss(a) shown Table 4-4. result type void.
Table 4-4. Data Stream Stop Argument Types
2-bit unsigned literal maps
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Generic Specific AltiVec Operations
vec_dssall
Vector Stream Stop
vec_dssall
vec_dssall()
DataStreamPrefetchControl
operation stops cache touches data streams. argument result types vec_dssall() void. vec_dssall maps dssall instruction.
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Chapter AltiVec Operations Predicates
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Generic Specific AltiVec Operations
vec_dst
Vector Data Stream Touch
vec_dst
vec_dst(a,b,c)
addr[0:63] DataStreamPrefetchControl addr
Each operation initiates cache touches loads data stream associated with address using data block result type void. type also pointer type. Plain char excluded mapping type encoded 32-bit follows: Block size: b[3:7] b[3:7] otherwise Block count: b[8:15] b[8:15] otherwise Block stride: b[16:31] b[16:31] otherwise 32768
Block Size Block Count Block Stride
Figure 4-44. Format Type (32-bit)
type encoded 64-bit follows: Block size: b[35:39] b[35:39] otherwise Block count: b[40:47] b[40:47] otherwise Block stride: b[48:63] b[48:63] otherwise 32768
Block Size Block Count Block Stride
Figure 4-45. Format Type (64-bit)
type 2-bit unsigned literal used identify data stream. four streams with this mechanism. valid combinations argument types vec_dst(a,b,c) shown Table 4-5. result type void.
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Table 4-5. Data Stream Touch Argument Types
vector unsigned char vector signed char vector bool char vector unsigned short vector signed short vector bool short vector pixel vector unsigned vector signed vector bool vector float unsigned char signed char unsigned short short unsigned unsigned float integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal a,b,c maps
MOTOROLA
Chapter AltiVec Operations Predicates
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Generic Specific AltiVec Operations
vec_dstst
Vector Data Stream Touch Store
vec_dstst
vec_dstst(a,b,c)
addr[0:63] DataStreamPrefetchControl static addr
Each operation initiates cache touches stores data stream associated with address using data block result type void. type also pointer type. Plain char excluded mapping type encoded 32-bit follows: Block size: b[3:7] b[3:7] otherwise Block count: b[8:15] b[8:15] otherwise Block stride: b[16:31] b[16:31] otherwise 32768
Block Size Block Count Block Stride
Figure 4-46. Format Type (32-bit)
type encoded 64-bit follows: Block size: b[35:39] b[35:39] otherwise Block count: b[40:47] b[40:47] otherwise Block stride: b[48:63] b[48:63] otherwise 32768
Block Size Block Count Block Stride
Figure 4-47. Format Type (64-bit)
type 2-bit unsigned literal used identify data stream. four streams with this mechanism. valid combinations argument types vec_dstst(a,b,c) shown Table 4-6. result type void.
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Generic Specific AltiVec Operations
Table 4-6. Data Stream Touch Store Argument Types
vector unsigned char vector signed char vector bool char vector unsigned short vector signed short vector bool short vector pixel vector unsigned vector signed vector bool vector float unsigned char signed char unsigned short short unsigned unsigned float integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal dstst a,b,c maps
MOTOROLA
Chapter AltiVec Operations Predicates
4-41
Generic Specific AltiVec Operations
vec_dststt
Vector Data Stream Touch Store Transient
vec_dststt
vec_dststt(a,b,c)
addr[0:63] DataStreamPrefetchControl static addr
Each operation initiates cache touches transient stores data stream associated with address using data block result type void. type also pointer type. Plain char excluded mapping type encoded 32-bit follows: Block size: b[3:7] b[3:7] otherwise Block count: b[8:15] b[8:15] otherwise Block stride: b[16:31] b[16:31] otherwise 32768
Block Size Block Count Block Stride
Figure 4-48. Format Type (32-bit)
type encoded 64-bit follows: Block size: b[35:39] b[35:39] otherwise Block count: b[40:47] b[40:47] otherwise Block stride: b[48:63] b[48:63] otherwise 32768
Block Size Block Count Block Stride
Figure 4-49. Format Type (64-bit)
type 2-bit unsigned literal used identify data stream. four streams with this mechanism. valid combinations argument types vec_dststt(a,b,c) shown Table 4-7. result type void.
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Table 4-7. Data Stream Touch Store Transient Argument Types
vector unsigned char vector signed char vector bool char vector unsigned short vector signed short vector bool short vector pixel vector unsigned vector signed vector bool vector float unsigned char signed char unsigned short short unsigned unsigned float integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal dststt a,b,c maps
MOTOROLA
Chapter AltiVec Operations Predicates
4-43
Generic Specific AltiVec Operations
vec_dstt
Vector Data Stream Touch Transient
vec_dstt
vec_dstt(a,b,c)
addr[0:63] DataStreamPrefetchControl addr
Each operation initiates cache touches transient loads data stream associated with address using data block result type void. type also pointer type. Plain char excluded mapping type encoded 32-bit follows: Block size: b[3:7] b[3:7] otherwise Block count: b[8:15] b[8:15] otherwise Block stride: b[16:31] b[16:31] otherwise 32768
Block Size Block Count Block Stride
Figure 4-50. Format Type (32-bit)
type encoded 64-bit follows: Block size: b[35:39] b[35:39] otherwise Block count: b[40:47] b[40:47] otherwise Block stride: b[48:63] b[48:63] otherwise 32768
Block Size Block Count Block Stride
Figure 4-51. Format Type (64-bit)
type 2-bit unsigned literal used identify data stream. four streams with this mechanism. valid combinations argument types vec_dstt(a,b,c) shown Table 4-8. result type void.
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Table 4-8. Data Stream Touch Transient Argument Types
vector unsigned char vector signed char vector bool char vector unsigned short vector signed short vector bool short vector pixel vector unsigned vector signed vector bool vector float unsigned char signed char unsigned short short unsigned unsigned float integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type integral type 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned literal 2-bit unsigned
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