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ALTIVECPIM / D 6 / 1999 Rev. 0

AltiVec Technology Programming Interface Manual

ALTIVECPIM / D 6 / 1999 Rev. 0
AltiVec Technology Programming Interface Manual
DigitalDNA and Mfax are trademarks of Motorola, Inc. The PowerPC name and the PowerPC logotype are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
Overview
High-Level Language Interface
Application Binary Interface
AltiVec Operations and Predicates
AltiVec Instruction Set / Operations / Predicates Cross-Reference
Glossary of Terms and Abbreviations GLO
Index IND
Overview
High-Level Language Interface
Application Binary Interface
AltiVec Operations and Predicates
AltiVec Instruction Set / Operations / Predicates Cross-Reference
GLO Glossary of Terms and Abbreviations
Index
CONTENTS
Paragraph Number Title Page Number
Audience ....................................................... xvi Organization..................................................... xvi Suggested Reading............................................... xvii PowerPC Documentation........................................ xvii General Information............................................ xviii Chapter 1
Overview
1.1 1.2 High-Level Language Interface ...................................... 1-1 Application Binary Interface (ABI) ................................... 1-2 Chapter 2
High-Level Language Interface
2.1 2.2 2.2.1 2.2.2 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.6 Data Types ...................................................... 2-1 New Keywords................................................... 2-2 The Keyword and Predefine Method................................ 2-2 The Context Sensitive Keyword Method............................. 2-3 Alignment ...................................................... 2-3 Alignment of Vector Types ....................................... 2-3 Alignment of Non-Vector Types ................................... 2-3 Alignment of Aggregates and Unions Containing Vector Types .......... 2-3 Extensions of C / C++ Operators for the New Types ...................... 2-4 sizeof() ....................................................... 2-4 Assignment ................................................... 2-4 Address Operator ............................................... 2-4 Pointer Arithmetic.............................................. 2-4 Pointer Dereferencing ........................................... 2-4 Type Casting .................................................. 2-5 New Operators ................................................... 2-5 Vector Literals ................................................. 2-5 Vector Literals and Casts......................................... 2-6 Value for Adjusting Pointers ...................................... 2-7 New Operators Representing AltiVec Operations...................... 2-7 Programming Interface ............................................ 2-8 Chapter 3
Application Binary Interface (ABI)
3.1 3.2 Data Representation ............................................... 3-1 Register Usage Conventions ........................................ 3-1
MOTOROLA
Contents
CONTENTS
Paragraph Number 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.6 3.7 3.8 3.8.1 3.8.2 Title Page Number
AltiVec Operations and Predicates
4.1 4.2 4.3 4.4 4.5 Vector Status and Control Register................................... 4-1 Byte Ordering.................................................... 4-3 Notation and Conventions.......................................... 4-4 Generic and Specific AltiVec Operations.............................. 4-7 AltiVec Predicates .............................................. 4-133 Appendix A AltiVec Instruction Set / Operation / Predicate Cross-Reference
Glossary of Terms and Abbreviations Index
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ILLUSTRATIONS
Figure Number 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 Title Page Number
Illustrations vii
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ILLUSTRATIONS
AltiVec Technology Programming Interface Manual
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ILLUSTRATIONS
Figure Number 4-82 4-83 4-84 4-85 4-86 4-87 4-88 4-89 4-90 4-91 4-92 4-93 4-94 4-95 4-96 4-97 4-98 4-99 4-100 4-101 4-102 4-103 4-104 4-105 4-106 4-107 4-108 4-109 4-110 4-111 4-112 4-113 4-114 4-115 4-116 4-117 4-118 4-119 4-120 Title Page Number
Illustrations ix
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ILLUSTRATIONS
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ILLUSTRATIONS
Figure Number 4-162 4-163 4-164 4-165 4-166 4-167 4-168 4-169 4-170 4-171 4-172 4-173 4-174 4-175 4-176 4-177 4-178 4-179 4-180 4-181 4-182 4-183 4-184 4-185 4-186 4-187 4-188 4-189 4-190 4-191 4-192 4-193 4-194 4-195 4-196 4-197 4-198 4-199 4-200 4-201 4-202 4-203 4-204 Title Page Number
Illustrations xi
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ILLUSTRATIONS
Figure Page Title Number Number 4-205 Any Not Greater Than or Equal of Four Floating-Point Elements (32-Bit) ..................................................... 4-178 4-206 Any Not Greater Than of Four Floating-Point Elements (32-Bit) ............. 4-179 4-207 Any Not Less Than or Equal of Four Floating-Point Elements (32-Bit) ........ 4-180 4-208 Any Not Less Than of Four Floating-Point Elements (32-Bit) ................ 4-181 4-209 Any Numeric of Four Floating-Point Elements (32-Bit)..................... 4-182 4-210 Any Out of Bounds of Four Floating-Point Elements (32-Bit) ................ 4-183
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TABLES
Table Number 2-1 2-2 2-3 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 A-1 A-2 A-3 Title Page Number
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Tables
TABLES
Table Number Title Page Number
AltiVec Technology Programming Interface Manual
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About This Book
MOTOROLA
About This Book
Audience
This manual is intended for system software and application programmers who want to develop products using the AltiVec technology extension to the PowerPC processors in general. It is assumed that the reader understands operating systems, microprocessor system design, the basic principles of RISC processing, and the AltiVec Instruction Set.
Organization
AltiVec Technology Programming Interface Manual
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Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the AltiVec technology and PowerPC architecture.
PowerPC Documentation
MOTOROLA
About This Book
Additional literature on AltiVec technology and PowerPC implementations is being released as new processors become available. For a current list of AltiVec technology and PowerPC documentation, refer to the website at http://www.mot.com / SPS / PowerPC / .
General Information
xviii
AltiVec Technology Programming Interface Manual
MOTOROLA
Chapter 1 Overview
1.1 High-Level Language Interface
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Chapter 1. Overview
Application Binary Interface (ABI)
1.2 Application Binary Interface (ABI)
AltiVec Technology Programming Interface Manual
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Chapter 2 High-Level Language Interface
2.1 Data Types
The AltiVec programming model introduces a set of fundamental data types, as described in Table 2-1.
Table 2-1. AltiVec Data Types
New C / C++ Type vector unsigned char vector signed char vector bool char vector unsigned short 8 unsigned short vector unsigned short int vector signed short 8 signed short vector signed short int vector bool short 8 unsigned short vector bool short int vector unsigned int vector unsigned long vector unsigned long int 4 unsigned int 0..232 - 1 0 (F), 65535 (T) -32768..32767 0..65536 Interpretation of Contents 16 unsigned char 16 signed char 16 unsigned char Components Represent Values 0..255 -128..127 0(F), 255 (T)
MOTOROLA
Chapter 2. High-Level Language Interface
New Keywords
Table 2-1. AltiVec Data Types (Continued)
New C / C++ Type vector signed int vector signed long vector signed long int vector bool int vector bool long vector bool long int vector float vector pixel 4 float 8 unsigned short IEEE-754 values 1 / 5 / 5 / 5 pixel 4 unsigned int 0 (F), 232 - 1 (T) 4 signed int -231..231-1 Interpretation of Contents Components Represent Values
The vector types with the long keyword are deprecated and will be eliminated in a future version of this document.
2.2 New Keywords
typedef signed short int16 vector int16 data
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Alignment
2.2.2 The Context Sensitive Keyword Method
2.3 Alignment
The following paragraphs described AltiVec alignment requirements. When working with vector data, the programmer must be aware of these alignment issues. Because the AltiVec technology does not generate exceptions, the programmer must determine whether and when vector data becomes unaligned.
2.3.1 Alignment of Vector Types
2.3.2 Alignment of Non-Vector Types
2.3.3 Alignment of Aggregates and Unions Containing Vector Types
Aggregates (structures and arrays) and unions containing vector types must be aligned on 16-byte boundaries and their internal organization padded, if necessary, so that each internal vector type is aligned on a 16-byte boundary. This is an extension to all ABIs (AIX, Apple, SVR4, and EABI).
MOTOROLA
Chapter 2. High-Level Language Interface
Extensions of C / C++ Operators for the New Types
2.4 Extensions of C / C++ Operators for the New Types
Most C / C++ operators do not permit any of their arguments to be one of the new types. Let a and b be vector types and p be a pointer to a vector type. The normal C / C++ operators are extended to include the following operations.
2.4.1 sizeof()
The operations sizeof(a) and sizeof(p) return 16.
2.4.2 Assignment
2.4.3 Address Operator
The operation &a is valid if a is a vector type. The result of the operation is a pointer to a.
2.4.4 Pointer Arithmetic
The usual pointer arithmetic can be performed on p. In particular, p+1 is a pointer to the next vector after p.
2.4.5 Pointer Dereferencing
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New Operators
2.4.6 Type Casting
Pointers to old and new types may be cast back and forth to each other. Casting a pointer to a new type represents an unchecked assertion that the address is 16-byte aligned. Some new operators are provided to provide the equivalence of casts and data initialization. Casts from one vector type to another are provided by normal C casts. These should not be needed frequently if the overloaded forms of operators are used. None of the casts performs a conversion the bit pattern of the result is the same as the bit pattern of the argument that is cast.
2.5 New Operators
New operators are introduced to construct vector literals, adjust pointers, and allow full access to the functionality provided by the AltiVec architecture.
2.5.1 Vector Literals
A vector literal is written as a parenthesized vector type followed by a parenthesized set of constant expressions. Vector literals may be used either in initialization statements or as constants in executable statements. Table 2-2 lists the formats and descriptions of the vector literals. For each, the compiler generates code that either computes or loads the values into the register.
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Chapter 2. High-Level Language Interface
New Operators
Table 2-2. Vector Literal Format and Description
Notation
(vector unsigned char) (unsigned int)
Represents
A set of 16 unsigned 8-bit quantities which all have the value
specified by the integer. A set of 16 unsigned 8-bit quantities specified by the 16 integers. A set of 16 signed 8-bit quantities that all have the value specified by the integer.
(vector unsigned char) (unsigned int, .., unsigned int) (vector signed char) (int)
(vector signed char) (int, .., int) (vector unsigned short) (unsigned int)
A set of 16 signed 8-bit quantities specified by the 16 integers. A set of eight unsigned 16-bit quantities which all have the value
specified by the unsigned integer. A set of eight unsigned 16-bit quantities specified by the eight unsigned integers. A set of eight signed 16-bit quantities which all have the value specified by the integer. A set of eight signed 16-bit quantities specified by the eight integers. A set of four unsigned 32-bit quantities which all have the value specified by the unsigned integer. A set of four unsigned 32-bit quantities specified by the four unsigned integers. A set of four signed 32-bit quantities which all have the value specified by the integer. A set of four signed 32-bit quantities specified by the 4 integers. A set of four floating-point quantities which all have the value specified by the floating-point value. A set of four floating-point quantities which all have the value specified by the four floating-point values.
(vector unsigned short) (unsigned int, .., unsigned int) (vector signed short) (int)
(vector signed short) (int, .., int)
(vector unsigned int) (unsigned int)
(vector unsigned int) (unsigned int, .., unsigned int) (vector signed int) (int)
(vector signed int) (int, .., int) (vector float) (float)
(vector float) (float, .., float)
2.5.2 Vector Literals and Casts
The combination of vector casts and vector literals can complicate some parsers. An implementation is not required to support the cast to a vector type of a vector cast or vector literal when the operand of the cast is not a parenthesized expression. For example, the programmer may write the following:
(vector unsigned char)((vector unsigned int)(1, 2, 3, 4)) (vector signed char)((vector unsigned short) variable)
The similar expressions below without the parenthesized expression may not be used in a conforming application
(vector unsigned char)(vector unsigned int)(1, 2, 3, 4) (vector signed char)(vector unsigned short) variable
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New Operators
2.5.3 Value for Adjusting Pointers
Value 16
2.5.4 New Operators Representing AltiVec Operations
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Chapter 2. High-Level Language Interface
Programming Interface
2.6 Programming Interface
AltiVec Technology Programming Interface Manual
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Chapter 2. High-Level Language Interface
Programming Interface
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Chapter 3 Application Binary Interface (ABI)
3.1 Data Representation
3.2 Register Usage Conventions
Table 3-1. AltiVec Registers
Register v0-v1 v2-v13 v14-v19 v20-v31 Intended use General use Parameters, general General General Behavior across call sites Volatile (Caller save) Volatile (Caller save) Volatile (Caller save) Non-volatile (Callee save)
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Chapter 3. Application Binary Interface (ABI)
The Stack Frame
Table 3-1. AltiVec Registers
Register VRSAVE Intended use Special, see Section 3.3, "The Stack Frame Behavior across call sites Non-volatile (Callee save)
3.3 The Stack Frame
AltiVec Technology Programming Interface Manual
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The Stack Frame
3.3.1 SVR4 ABI and EABI Stack Frame
The size of the vector register save area and the presence of the VRSAVE word may vary within a function and are determined by a new registers valid tag. Note: In the SVR4 ABI, the registers valid tag is the most general way to describe a stack frame. It is associated with a frame or frame valid tag. Figure 3-1 shows an SVR4 and EABI stack frame.
High Address SP Back chain Floating-point register save area General register save area CR save word VRSAVE save word Alignment padding Vector register save area Local variable space Parameter list area LR save word Back chain Low Address NEW NEW NEW
Figure 3-1. SVR4 ABI and EABI Stack Frame Table 3-2. Vector Registers Valid Tag Format
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Chapter 3. Application Binary Interface (ABI)
The Stack Frame
Table 3-2. Vector Registers Valid Tag Format
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mfspr stw oris ori mtspr addi bl addi bl lwz mtspr addi bl addi bl
3.3.2 Apple Macintosh ABI and AIX ABI Stack Frame
Figure 3-2 shows how the Apple Macintosh ABI and AIX ABI stack frame is set up.
High Address SP Back chain Floating-point register save area General register save area VRSAVE save word Alignment padding Vector register save area Local variable space Parameter list area Saved TOC Reserved for Binders Reserved for Compilers LR save word CR save word Back chain Low Address NEW NEW NEW
Figure 3-2. Apple Macintosh ABI and AIX ABI Stack Frame
The Apple Macintosh ABI and AIX ABI stack frame allow the use of a 220-byte area at a negative offset from the stack pointer. This area can be used to save non-volatile registers before the stack pointer has been updated. This size of this area is not changed. Depending
MOTOROLA Chapter 3. Application Binary Interface (ABI) 3-5
The Stack Frame
AltiVec Technology Programming Interface Manual
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The Stack Frame
3.3.3 Vector Register Saving and Restoring Functions
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Chapter 3. Application Binary Interface (ABI)
The following code shows how to restore a vector register.
AltiVec Technology Programming Interface Manual
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Function Calls
3.4 Function Calls
3.4.1 SVR4 ABI and EABI Parameter Passing and Varargs
3.4.2 Apple Macintosh ABI and AIX ABI Parameter Passing without Varargs
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Chapter 3. Application Binary Interface (ABI)
3.4.3 Apple Macintosh ABI and AIX ABI Parameter Passing with Varargs
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setjmp() and longjmp()
3.6 setjmp() and longjmp()
Table 3-3. ABI Specifications for setjmp() and longjmp()
3.7 Debugging Information
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Chapter 3. Application Binary Interface (ABI)
printf() and scanf() Control Strings
3.8 printf() and scanf() Control Strings
where,
value1 C value2 C .. C valuen
AltiVec Technology Programming Interface Manual
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printf() and scanf() Control Strings
This code produces the following output:
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Chapter 3. Application Binary Interface (ABI)
printf() and scanf() Control Strings
where,
value1 C value2 C .. C valuen
AltiVec Technology Programming Interface Manual
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printf() and scanf() Control Strings
This is equivalent to:
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Chapter 3. Application Binary Interface (ABI)
printf() and scanf() Control Strings
AltiVec Technology Programming Interface Manual
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Chapter 4 AltiVec Operations and Predicates
4.1 Vector Status and Control Register
The vector status and control register (VSCR) is a special 32-bit vector register shown in Figure 4-1.
Figure 4-1. Vector Status and Control Register (VSCR)
Reserved 0 0 95 96 0 NJ 110 111 112 0
Figure 4-2. VSCR Moved to a Vector Register
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Chapter 4. AltiVec Operations and Predicates
Vector Status and Control Register
VSCR bit settings are shown in Table 4-1.
Table 4-1. VSCR Field Descriptions
Name -
For each operation, where applicable, the effects of the NJ bit setting and / or the effects on the SAT bit are described in the operation description.
AltiVec Technology Programming Interface Manual
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Byte Ordering
4.2 Byte Ordering
The default mapping for AltiVec ISA is PowerPC big-endian. The endian support of the PowerPC architecture does not address any data element larger than a double word the basic memory unit for vectors is a quad word. Big-endian byte ordering is shown in Figure 4-3.
Quad Word
High-Order Word 0 Low-Order High-Order Half Word for Half Word for Word 0 Word 0 High-Order Half Word Half Word 0 HighOrder Byte Byte 0
Word 1
Word 2
Low-Order Word 3
Low-Order Half Word Half Word 1 Half Word 2 Half Word 3 Half Word 4 Half Word 5 Half Word 6 Half Word 7 LowOrder Byte
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
(HighOrder)
(LowOrder)
Figure 4-3. Big-Endian Byte Ordering for a Vector Register
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Chapter 4. AltiVec Operations and Predicates
Notation and Conventions
4.3 Notation and Conventions
Operation and predicate functionality is described in this section by a semiformal pseudocode language. Table 4-2 lists the pseudocode notation and conventions used throughout the section.
Table 4-2. Notation and Conventions
+, +fp -, -fp , fp
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Notation and Conventions
Table 4-2. Notation and Conventions (Continued)