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M68060 User's Manual
Including MC68060, MC68LC060, MC68EC060
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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M68060 USER'S MANUAL
MOTOROLA
PREFACE
complete documentation package MC68060, MC68LC060, MC68EC060 (collectively called M68060) consists M68060UM/AD, M68060 User's Manual, M68000PM/AD, M68000 Family Programmer's Reference Manual. M68060 User's Manual describes capabilities, operation, programming M68060 superscalar 32-bit microprocessors. M68000 Family Programmer's Reference Manual contains complete instruction M68000 family. introduction this manual includes general information concerning MC68060 summarizes differences among M68060 family devices. Additionally, appendices provide detailed information these M68060 derivatives operate differently from MC68060. When reading this manual, disregard information concerning floating-point unit reference MC68LC060, disregard information concerning floating-point unit memory management unit reference MC68EC060. organization this manual follows: Section Section Section Section Section Section Section Section Section Section Section Section Section Appendix Appendix Appendix Appendix Introduction Signal Description Integer Unit Memory Management Unit Caches Floating-Point Unit Operation Exception Processing IEEE 1149.1 Test (JTAG) Debug Pipe Control Modes Instruction Timings Applications Electrical Thermal Characteristics Ordering Information Mechanical Data MC68LC060 MC68EC060 MC68060 Software Package M68060 Instructions
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MC68060 ACRONYM LIST
AGU-address generation unit ALU-arithmetic logic unit ATC-address translation cache BUSCR-bus control register CACR-cache control register CCR-condition code register CM-cache mode CPU-central processing unit DFC-destination function code DTTx-data transparent translation register DRAM-dynamic random access memory FPIAR-floating-point instruction address register FPCR-floating-point control register FPSP-floating-point software package FPSR-floating-point status register FPU-floating-point unit FP7-FP0-floating-point data registers FSLW-fault status long word IEE-integer execute unit IFP-instruction fetch pipeline IFU-instruction fetch unit IPU-instruction pipe unit ISP-interrupt stack pointer ITTR-instruction transparent translation register IU-integer unit JTAG-Joint Test Action Group MMU-memory management unit
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MC68060 Acronym List
MMUSR-memory management unit status register M68060SP-M68060 software package NANs-not-a-numbers NOP-no operation OEP-operand execution pipeline OPU-operand pipe unit PC-program counter PCR-processor configuration register PGI-page index field PI-pointer index field PLL-phase-locked loop pOEP-primary operand execution pipeline RI-root index field SFC-source function code SNAN-signaling not-a-number sOEP-secondary operand execution pipeline SP-stack pointer SR-status register SRP-supervisor root pointer register SSP-supervisor stack pointer TAP-test access port TCR-translation control register TTL-transistor-transistor logic TTR-transparent translation register UPA-user page attribute URP-user root pointer register USP-user stack pointer VBR-vector base register VLSI-very large-scale integration
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Section Introduction 1.1.1 1.1.2 1.1.2.1 1.1.2.2 1.4.1 1.4.2 1.4.2.1 1.4.2.2 1.4.2.3 1.4.2.4 1.4.2.5 1.4.2.6 1.4.2.6.1 1.4.2.6.2 1.4.3 1.10 Differences Among M68060 Family Members. MC68LC060. MC68EC060 Address Translation Differences Instruction Differences Features. Architecture. Processor Overview. Functional Blocks. Integer Unit Instruction Fetch Unit. Integer Unit Floating-Point Unit Memory Units Address Translation Caches Instruction Data Caches Cache Organization. 1-10 Cache Coherency. 1-10 Controller 1-10 Processing States 1-10 Programming Model. 1-11 Data Format Summary. 1-14 Addressing Capabilities Summary 1-14 Instruction Overview 1-15 Notational Conventions. 1-21 Section Signal Description 2.1.1 2.1.2 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5
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Address Control Signals Address (A31-A0) Cycle Long-Word Address (CLA) Data (D31-D0). Transfer Attribute Signals Transfer Cycle Type (TT1, TT0) Transfer Cycle Modifier (TM2-TM0) Transfer Line Number (TLN1, TLN0). User-Programmable Page Attributes (UPA1, UPA0). Read/Write (R/W)
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2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.4.1 2.4.2 2.4.3 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8.1 2.8.2 2.8.3 2.8.4 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.11.5 2.11.6 2.12 2.13 2.14
Transfer Size (SIZ1, SIZ0). Lock (LOCK). Lock (LOCKE). Cache Inhibit (CIOUT) Byte Select Lines (BS3-BS0). Master Transfer Control Signals Transfer Start (TS). Transfer Progress (TIP) Starting Termination Acknowledge Signal Sampling (SAS) Slave Transfer Control Signals Transfer Acknowledge (TA). Transfer Retry Acknowledge (TRA). Transfer Error Acknowledge (TEA) Transfer Burst Inhibit (TBI) Transfer Cache Inhibit (TCI) Snoop Control (SNOOP) Arbitration Signals. 2-10 Request (BR). 2-10 Grant (BG). 2-10 Grant Relinquish Control (BGR). 2-10 Tenure Termination (BTT). 2-10 Busy (BB) 2-11 Processor Control Signals 2-11 Cache Disable (CDIS) 2-11 Disable (MDIS). 2-12 Reset (RSTI). 2-12 Reset (RSTO) 2-12 Interrupt Control Signals 2-12 Interrupt Priority Level (IPL2-IPL0) 2-12 Interrupt Pending Status (IPEND) 2-12 Autovector (AVEC) 2-13 Status Clock Signals. 2-13 Processor Status (PST4-PST0). 2-13 MC68060 Processor Clock (CLK) 2-14 Clock Enable (CLKEN) 2-14 Test Signals 2-15 JTAG Enable (JTAG). 2-15 Test Clock (TCK) 2-15 Test Mode Select (TMS). 2-15 Test Data (TDI). 2-16 Test Data (TDO) 2-16 Test Reset (TRST) 2-16 Thermal Sensing Pins (THERM1, THERM0). 2-16 Power Supply Connections. 2-16 Signal Summary 2-16
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Section Integer Unit 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.2.2.1 3.2.2.2 3.2.2.3 3.2.2.4 3.2.2.5 Integer Unit Execution Pipelines Integer Unit Register Description Integer Unit User Programming Model Data Registers (D7-D0) Address Registers (A6-A0) User Stack Pointer (A7) Program Counter Condition Code Register Integer Unit Supervisor Programming Model. Supervisor Stack Pointer Status Register Vector Base Register. Alternate Function Code Registers. Processor Configuration Register. Section Memory Management Unit 4.1.1 4.1.2 4.1.3 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.3 4.2.4 4.2.4.1 4.2.4.2 4.2.4.3 4.2.4.4 4.2.5 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.6.1 Memory Management Programming Model. User Supervisor Root Pointer Registers Translation Control Register Transparent Translation Registers Logical Address Translation. Translation Tables Descriptors. 4-12 Table Descriptors. 4-12 Page Descriptors 4-12 Descriptor Field Definitions. 4-13 Translation Table Example 4-15 Variations Translation Table Structure. 4-16 Indirect Action 4-16 Table Sharing Between Tasks. 4-17 Table Paging 4-17 Dynamically Allocated Tables. 4-17 Table Search Accesses 4-19 Address Translation Protection. 4-20 Supervisor User Translation Tables 4-21 Supervisor Only 4-22 Write Protect 4-22 Address Translation Caches. 4-24 Transparent Translation. 4-27 Address Translation Summary. 4-28 RSTI MDIS Effect 4-28 Effect RSTI MMUs 4-28
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4.6.2 4.7.1 4.7.2 4.7.3
Effect MDIS Address Translation 4-30 Instructions. 4-30 MOVEC 4-30 PFLUSH 4-30 PLPA 4-30 Section Caches
5.4.1 5.4.1.1 5.4.1.2 5.4.2 5.4.3 5.5.1 5.5.2 5.5.3 5.5.4 5.7.1 5.7.2 5.10 5.11 5.12 5.12.1 5.12.2
Cache Operation. Cache Control Register Cache Management Caching Modes. Cachable Accesses Writethrough Mode Copyback Mode Cache-Inhibited Accesses Special Accesses Cache Protocol Read Miss. Write Miss. Read Hit. Write Hit. 5-10 Cache Coherency 5-10 Memory Accesses Cache Maintenance 5-11 Cache Filling. 5-11 Cache Pushes 5-13 Push Buffer 5-13 Store Buffer. 5-13 Push Buffer Store Buffer Operation. 5-14 Branch Cache 5-14 Cache Operation Summary 5-15 Instruction Cache. 5-15 Data Cache. 5-16 Section Floating-Point Unit
6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3
Floating-Point User Programming Model. Floating-Point Data Registers (FP7-FP0) Floating-Point Control Register (FPCR) Exception Enable Byte Mode Control Byte. Floating-Point Status Register (FPSR). Floating-Point Condition Code Byte Quotient Byte. Exception Status Byte
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6.1.3.4 6.1.4 6.3.1 6.3.2 6.4.1 6.4.2 6.5.1 6.5.2 6.5.3 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.4 6.6.4.1 6.6.4.2 6.6.5 6.6.5.1 6.6.5.2 6.6.6 6.6.6.1 6.6.6.2 6.6.7 6.6.7.1 6.6.7.2
Accrued Exception Byte Floating-Point Instruction Address Register (FPIAR) Floating-Point Data Formats Data Types. Computational Accuracy 6-11 Intermediate Result. 6-12 Rounding Result 6-13 Postprocessing Operation. 6-15 Underflow, Round, Overflow. 6-15 Conditional Testing 6-16 Floating-Point Exceptions 6-19 Unimplemented Floating-Point Instructions 6-19 Unsupported Floating-Point Data Types. 6-21 Unimplemented Effective Address Exception. 6-22 Floating-Point Arithmetic Exceptions 6-22 Branch/Set Unordered (BSUN). 6-24 Trap Disabled Results (FPCR BSUN Cleared) 6-24 Trap Enabled Results (FPCR BSUN Set) 6-24 Signaling Not-a-Number (SNAN) 6-25 Trap Disabled Results (FPCR SNAN Cleared) 6-25 Trap Enabled Results (FPCR SNAN Set) 6-26 Operand Error. 6-26 Trap Disabled Results (FPCR OPERR Cleared). 6-27 Trap Enabled Results (FPCR OPERR Set). 6-27 Overflow. 6-28 Trap Disabled Results (FPCR OVFL Cleared) 6-29 Trap Enabled Results (FPCR OVFL Set) 6-29 Underflow. 6-30 Trap Disabled Results (FPCR UNFL Cleared) 6-31 Trap Enabled Results (FPCR UNFL Set) 6-31 Divide-by-Zero 6-32 Trap Disabled Results (FPCR Cleared). 6-33 Trap Enabled Results (FPCR Set). 6-33 Inexact Result 6-33 Trap Disabled Results (FPCR INEX1 INEX2 Cleared. 6-34 Trap Enabled Results (Either FPCR INEX1 INEX2 Set). 6-34 Floating-Point State Frames 6-35 Section Operation
Characteristics Full-, Half-, Quarter-Speed Operation BCLK Acknowledge Termination Ignore State Capability Control Register. Data Transfer Mechanism. Misaligned Operands
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7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.8.1 7.8.1.1 7.8.1.2 7.8.1.3 7.8.2 7.8.2.1 7.9.1 7.9.2 7.9.3 7.10 7.11 7.11.1 7.11.2 7.11.3 7.12 7.13 7.14 7.14.1 7.14.2 7.14.3
Processor Data Transfers. 7-12 Byte, Word, Long-Word Read Transfer Cycles 7-12 Line Read Transfer. 7-15 Byte, Word, Long-Word Write Cycles. 7-20 Line Write Cycles. 7-25 Locked Read-Modify-Write Cycles 7-28 Emulating CAS2 Misaligned. 7-31 Using Increment 7-32 Acknowledge Cycles. 7-32 Interrupt Acknowledge Cycles 7-32 Interrupt Acknowledge Cycle (Terminated Normally) 7-35 Autovector Interrupt Acknowledge Cycle 7-35 Spurious Interrupt Acknowledge Cycle 7-35 Breakpoint Acknowledge Cycle 7-36 LPSTOP Broadcast Cycle 7-38 Exception Control Cycles 7-46 Errors. 7-46 Retry Operation 7-48 Double Fault 7-51 Synchronization 7-52 Arbitration 7-52 MC68040-Arbitration Protocol Protocol). 7-53 MC68060-Arbitration Protocol (BTT Protocol). 7-58 External Arbiter Considerations. 7-65 Snooping Operation. 7-68 Reset Operation. 7-71 Special Modes Operation 7-74 Acknowledge Termination Ignore State Capability. 7-74 Acknowledge Termination Protocol 7-76 Extra Data Write Hold Time Mode. 7-76 Section Exception Processing
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10
Exception Processing Overview Integer Unit Exceptions. Access Error Exception Address Error Exception. Instruction Trap Exception. Illegal Instruction Unimplemented Instruction Exceptions Privilege Violation Exception 8-10 Trace Exception. 8-10 Format Error Exception 8-11 Breakpoint Instruction Exception 8-11 Interrupt Exception 8-12 Reset Exception 8-14
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8.4.1 8.4.2 8.4.3 8.4.4 8.4.4.1 8.4.4.2 8.4.4.3 8.4.5 8.4.6 8.4.7
Exception Priorities 8-17 Return from Exceptions 8-19 Four-Word Stack Frame (Format 8-19 Six-Word Stack Frame (Format 8-20 Floating-Point Post-Instruction Stack Frame (Format 8-20 Eight-Word Stack Frame (Format $4). 8-21 Program Counter (PC). 8-21 Fault Address 8-22 Fault Status Long Word (FSLW). 8-22 Recovering from Access Error 8-25 Errors Pending Memory Writes 8-27 Branch Prediction Error 8-29 Section IEEE 1149.1 Test (JTAG) Debug Pipe Control Modes
9.1.1 9.1.2 9.1.2.1 9.1.2.2 9.1.2.3 9.1.2.4 9.1.2.5 9.1.2.6 9.1.2.7 9.1.2.8 9.1.3 9.1.3.1 9.1.3.2 9.1.3.3 9.1.4 9.1.5 9.1.6 9.2.1 9.2.2 9.2.3
IEEE 1149.1 Test Access Port (Normal JTAG) Mode Overview. JTAG Instruction Shift Register EXTEST. LPSAMPLE. Private Instructions SAMPLE/PRELOAD IDCODE. CLAMP HIGHZ. BYPASS JTAG Test Data Registers. Idcode Register Boundary Scan Register. Bypass Register 9-15 Restrictions 9-15 Disabling IEEE 1149.1 Standard Operation 9-15 Motorola MC68060 BSDL Description. 9-17 Debug Pipe Control Mode. 9-24 Debug Command Interface. 9-25 Debug Pipe Control Mode Commands 9-27 Emulator Mode 9-31 Switching between JTAG Debug Pipe ControlModes Operation. 9-33 Section Instruction Execution Timing
10.1 10.1.1 10.1.2
Superscalar Operand Execution Pipelines 10-1 Dispatch Test sOEP Opword Required Extension Words Valid 10-2 Dispatch Test Instruction Classification 10-2
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10.1.3 10.1.4 10.1.5 10.1.6 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16
Dispatch Test Allowable Effective Addressing Mode sOEP 10-8 Dispatch Test Allowable Operand Data Memory Reference 10-8 Dispatch Test Register Conflicts sOEP.AGU Resources 10-8 Dispatch Test Register Conflicts sOEP.IEE Resources 10-9 Timing Assumptions 10-10 Cache Performance Degradation Times 10-12 Instruction Miss 10-12 Data Miss 10-13 Instruction Cache Miss 10-13 Data Cache Miss 10-13 Effective Address Calculation Times 10-14 Move Instruction Execution Times. 10-14 Standard Instruction Execution Times 10-16 Immediate Instruction Execution Times. 10-17 Single-Operand Instruction Execution Times 10-18 Shift/Rotate Execution Times 10-19 Manipulation Field Execution Times. 10-19 Branch Instruction Execution Times 10-21 LEA, PEA, MOVEM Execution Times. 10-22 Multiprecision Instruction Execution Times. 10-22 Status Register, MOVES, Miscellaneous Instruction Execution Times. 10-22 Instruction Execution Times 10-24 Exception Processing Times 10-26 Section Applications Information
11.1 11.1.1 11.1.2 11.1.2.1 11.1.2.1.1 11.1.2.1.2 11.1.2.1.3 11.1.2.1.4 11.1.2.1.5 11.1.2.2 11.1.2.2.1 11.1.2.2.2 11.1.2.2.3 11.1.2.2.4 11.1.2.3 11.1.2.4 11.1.2.5 11.1.3
Guidelines Porting Software MC68060 11-1 User Code 11-1 Supervisor Code. 11-1 Initialization Code (Reset Exception Handler) 11-2 Processor Configuration Register (PCR) (MOVEC PCR). 11-2 Default Transparent Translation Register (MOVEC TCR) 11-2 MC68060 Software Package (M68060SP). 11-2 Cache Control Register (CACR) (MOVEC CACR). 11-3 Resource Checking (Access Error Handler) 11-3 Virtual Memory Software 11-3 Translation Control Register (MOVEC TCR). 11-3 Descriptors Cacheable Copyback Pages Prohibited. 11-4 Page Descriptor Faults (Access Error Handler). 11-4 PTEST, MOVEC MMUSR, PLPA. 11-4 Context Switch Interrupt Handlers. 11-5 Trace Handlers 11-5 Device Driver Software 11-5 Precise Imprecise Exception Mode 11-6
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11.1.4 11.2 11.2.1 11.2.1.1 11.2.1.1.1 11.2.1.1.2 11.2.1.2 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.3 11.4 11.5
Other Considerations. 11-6 Using MC68060 Existing MC68040 System 11-6 Power Considerations. 11-6 Voltage Conversion 11-6 Linear Voltage Regulator Solution. 11-7 Switching Regulator Solution. 11-7 Input Signals During Power-Up Requirement. 11-11 Output Hold Time Differences 11-11 Arbitration 11-13 Snooping. 11-13 Special Modes 11-13 Clocking 11-14 PSTx Encoding 11-14 Miscellaneous Pullup Resistors 11-15 Example DRAM Access. 11-15 Thermal Management. 11-17 Support Devices. 11-20 Section Electrical Thermal Characteristics
12.1 12.2 12.3 12.4 12.5 12.6 12.7
Maximum Ratings 12-1 Thermal Characteristics 12-1 Power Dissipation 12-1 Electrical Specifications (Vcc 12-2 Clock Input Specifications (Vcc 5%). 12-3 Output Timing Specifications (Vcc 12-4 Input Timing Specifications (Vcc 12-6 Section Ordering Information Mechanical Data
13.1 13.2 13.2.1 13.2.2 13.3
Ordering Information 13-1 Assignments 13-1 MC68060, MC68LC060, MC68EC060 Grid Array Suffix) 13-2 MC68060, MC68LC060, MC68EC060 Quad Flat Pack Suffix). 13-3 Mechanical Data 13-4 Appendix MC68LC060 Appendix MC68EC060
Address Translation Differences.B-1 Instruction Differences .B-1
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Appendix MC68060 Software Package C.2.1 C.2.2 C.2.2.1 C.2.2.2 C.2.2.3 C.2.3 C.3.1 C.3.2 C.3.2.1 C.3.2.2 C.3.2.2.1 C.3.2.2.2 C.3.2.2.3 C.3.2.2.4 C.3.2.3 C.3.2.3.1 C.3.2.3.2 C.3.2.3.3 C.3.2.3.4 C.3.2.3.5 C.3.2.4 C.3.2.4.1 C.3.2.4.2 C.3.3 C.3.4 C.4.1 C.4.2 C.5.1 C.5.2 C.5.3 C.5.4 Module Format.C-2 Unimplemented Integer Instructions .C-4 Integer Emulation Results .C-5 Module Unimplemented Integer Instruction Exception (MC68060ISP).C-5 Unimplemented Integer Instruction Exception Module Entry Points .C-6 Unimplemented Integer Instruction Exception Module Call-Outs .C-6 Misaligned Address CAS2 Emulation-Related Call-Outs Entry Points .C-6 Module Unimplemented Integer Instruction Library (MC68060ILSP) .C-9 Floating-Point Emulation Package (MC68060FPSP) .C-11 Floating-Point Emulation Results .C-13 Module Full Floating-Point Kernel .C-14 Full Floating-Point Kernel Module Entry Points .C-14 Full Floating-Point Kernel Module Call-Outs .C-14 F-Line Exception Call-Outs .C-14 System-Supplied Floating-Point Arithmetic Exception Handler Call-Outs .C-15 Exception-Related Call-Outs .C-15 Exit Point Call-Outs .C-15 Bypassing Module-Supplied Floating-Point Arithmetic Handlers .C-15 Overflow/Underflow .C-16 Signalling Not-A-Number, Operand Error.C-17 Inexact Exception .C-18 Divide-by-Zero Exception .C-19 Branch/Set Unordered Exception.C-19 Exceptions During Emulation .C-20 Trap-Disabled Operation .C-20 Trap-Enabled Operation.C-21 Module Partial Floating-Point Kernel .C-21 Module Floating-Point Library (M68060FPLSP).C-22 Operating System Dependencies .C-23 Instruction Data Fetches.C-23 Instructions Recommended .C-26 Installation Notes .C-27 Installing Library Modules.C-27 Installing Kernel Modules .C-27 Release Notes Module Offset Assignments .C-28 AESOP Electronic Bulletin Board .C-29 Appendix MC68060 Instructions
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4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 MC68060 Block Diagram Programming Model 1-12 Functional Signal Groups MC68060 Integer Unit Pipeline Integer Unit User Programming Model. Integer Unit Supervisor Programming Model Status Register. Processor Configuration Register Memory Management Unit Memory Management Programming Model Register Formats. Translation Control Register Format Transparent Translation Register Format Translation Table Structure Logical Address Format Detailed Flowchart Table Search Operation 4-10 Detailed Flowchart Descriptor Fetch Operation 4-11 Table Descriptor Formats. 4-12 Page Descriptor Formats 4-12 Example Translation Table. 4-15 Translation Table Using Indirect Descriptors 4-16 Translation Table Using Shared Tables 4-18 Translation Table with Nonresident Tables 4-19 Translation Table Structure Tasks 4-21 Logical Address with Shared Supervisor User Address Spaces. 4-22 Translation Table Using S-Bit W-Bit Protection 4-23 Organization. 4-24 Entry Fields 4-25 Address Translation Flowchart. 4-29 MC68060 Instruction Data Caches Instruction Cache Line Format Data Cache Line Format Caching Operation Cache Control Register Instruction Cache Line State Diagram. 5-16 Data Cache Line State Diagrams. 5-18 Floating-Point Unit Block Diagram Floating-Point User Programming Model Floating-Point Control Register Format.
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6-10 6-11 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37
Floating-Point Condition Code (FPSR) Floating-Point Quotient Byte (FPSR) Floating-Point Exception Status Byte (FPSR). Floating-Point Accrued Exception Byte (FPSR). Intermediate Result Format. 6-12 Rounding Algorithm Flowchart 6-14 Floating-Point State Frame 6-35 Status Word Contents 6-36 Signal Relationships Clocks. Full-Speed Clock. Half-Speed Clock Quarter-Speed Clock Control Register Format. Internal Operand Representation. Data Multiplexing. Byte Select Signal Generation Equation Example Misaligned Long-Word Transfer. 7-10 Example Misaligned Word Transfer 7-10 Misaligned Long-Word Read Cycle Timing. 7-11 Byte, Word, Long-Word Read Cycle Flowchart 7-13 Byte, Word, Long-Word Read Cycle Timing 7-14 Line Read Cycle Flowchart 7-17 Line Read Transfer Timing. 7-18 Burst-Inhibited Line Read Cycle Flowchart 7-20 Burst-Inhibited Line Read Cycle Timing. 7-21 Byte, Word, Long-Word Write Transfer Flowchart 7-22 Long-Word Write Cycle Timing 7-23 Line Write Cycle Flowchart 7-26 Line Write Burst-Inhibited Cycle Flowchart 7-27 Line Write Cycle Timing 7-28 Locked Cycle Instruction Timing. 7-30 Using High-Speed DRAM Design 7-33 Interrupt Pending Procedure 7-33 Assertion IPEND 7-34 Interrupt Acknowledge Cycle Flowchart. 7-36 Interrupt Acknowledge Cycle Timing 7-37 Autovector Interrupt Acknowledge Cycle Timing 7-38 Breakpoint Interrupt Acknowledge Cycle Flowchart. 7-39 Breakpoint Interrupt Acknowledge Cycle Timing 7-40 LPSTOP Broadcast Cycle Flowchart 7-41 LPSTOP Broadcast Cycle Timing, Negated 7-42 LPSTOP Broadcast Cycle Timing, Asserted 7-43 Exiting LPSTOP Mode Flowchart. 7-44 Exiting LPSTOP Mode Timing Diagram. 7-45 Word Write Access Cycle Terminated with Timing 7-48
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7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 9-10 9-11 9-12 9-13 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11
Line Read Access Cycle Terminated with Timing. 7-49 Retry Read Cycle Timing 7-50 Line Write Retry Cycle Timing. 7-51 MC68040-Arbitration Protocol State Diagram 7-57 MC68060-Arbitration Protocol State Diagram 7-64 Processor Request Timing. 7-67 Arbitration During Relinquish Retry Timing 7-68 Implicit Ownership Arbitration Timing. 7-69 Effect Locked Sequences. 7-70 Snooped Cycle. 7-71 Initial Power-On Reset Timing. 7-72 Normal Reset Timing. 7-73 Data Usage During Reset 7-74 Acknowledge Termination Ignore State Example 7-75 Extra Data Write Hold Example. 7-77 General Exception Processing Flowchart General Form Exception Stack Frame Interrupt Recognition Examples 8-13 Interrupt Exception Processing Flowchart. 8-15 Reset Exception Processing Flowchart. 8-16 Fault Status Long-Word Format 8-22 JTAG Test Logic Block Diagram JTAG Idcode Register Format. Output Cell (O.Pin). Observe-Only Input Cell (I.Obs). Input Cell (I.Pin) Output Control Cell (IO.Ctl) General Arrangement Bidirectional Cells 9-10 JTAG Bypass Register 9-15 Circuit Disabling IEEE Standard 1149.1. 9-16 Debug Command Interface Schematic 9-25 Interface Timing. 9-26 Transition from JTAG Debug Mode Timing Diagram 9-34 Transition from Debug JTAG Mode Timing Diagram 9-35 Linear Voltage Regulator Solution. 11-7 LTC1147 Voltage Regulator Solution. 11-8 LTC1148 Voltage Regulator Solution. 11-9 MAX767 Voltage Regulator Solution. 11-10 MC68040 Address Hold Time 11-11 MC68060 Address Hold Time 11-12 MC68060 Address Hold Time 11-12 Simple Generation. 11-14 Generic Generation 11-14 MC68040 BCLK CLKEN Relationship. 11-15 DRAM Timing Analysis. 11-15
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12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 13-1 13-2 C-10 C-11 C-12
Clock Input Timing Diagram. 12-3 Drive Levels Test Points Specifications 12-7 Reset Configuration Timing. 12-8 Read/Write Timing 12-9 Arbitration Timing. 12-10 Arbitration Timing (Continued) 12-11 Timing 12-12 Snoop Timing 12-13 Other Signals Timing. 12-14 Package Dimensions Suffix) 13-4 Package Dimensions Suffix) 13-5 Call-Out Dispatch Table Example .C-2 Example Pseudo-Assembly File .C-3 Module Call-In, Call-Out Example.C-4 CAS2 Call-Outs Entry Points .C-9 C-Code Representation Integer Library Routines .C-10 Instruction Call Example.C-11 CMP2 Instruction Call Example .C-11 SNAN/OPERR Exception Handler Pseudo-Code .C-18 Disabled Enabled Exception Actions.C-20 _mem_read Pseudo-Code .C-23 Register Usage {i,d}mem_{read,write}_{b,w,l} .C-25 Vector Table M68060SP Relationship .C-28
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6-10 6-11 6-12 6-13 6-14 6-15 6-16 Data Formats. 1-14 Effective Addressing Modes. 1-15 Instruction Summary 1-16 Notational Conventions 1-21 Signal Index. Transfer-Type Encoding. Normal MOVE16 Access Encoding. Alternate Access Encoding SIZx Encoding Data Byte Select Signals. PSTx Encoding. 2-14 Signal Summary 2-17 Updating U-Bit M-Bit Page Descriptors. 4-20 Values. 4-20 TLNx Encoding. 5-11 Instruction Cache Line State Transitions. 5-15 Data Cache Line State Transitions. 5-18 Encoding. PREC Encoding MC68060 Data Formats Data Types Single-Precision Real Format Summary Double-Precision Real Format Summary. Extended-Precision Real Format Summary 6-10 Packed Decimal Real Format Summary 6-11 Floating-Point Condition Code Encoding 6-16 Floating-Point Conditional Tests 6-18 Floating-Point Exception Vectors 6-19 Unimplemented Instructions. 6-20 Possible Operand Errors Exceptions 6-27 Overflow Rounding Mode Values. 6-29 Underflow Rounding Mode Values. 6-31 Possible Divide-by-Zero Exceptions. 6-33 Rounding Mode Values 6-34 Data Requirements Read Write Cycles Summary Access Types Signal Encoding. Memory Alignment Influence Noncachable Writethrough Cycles. 7-12 Interrupt Acknowledge Termination Summary 7-34 Termination Result Summary. 7-46 MC68040-Arbitration Protocol Transition Conditions 7-55
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7-10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 11-1 11-2 11-3 11-4
MC68040-Arbitration Protocol State Description 7-56 MC68060-Arbitration Protocol State Transition Conditions. 7-62 MC68060-Arbitration Protocol State Description 7-63 Special Mode IPLx Signals. 7-74 Exception Vector Assignments Interrupt Levels Mask Values. 8-12 Exception Priority Groups 8-17 JTAG States. JTAG Instructions. Boundary Scan Definitions. 9-10 Debug Command Interface Pins 9-25 Command Summary 9-28 Superscalar Dispatch Test Algorithm 10-4 MC68060 Superscalar Classification M680x0 Integer Instructions. 10-4 Superscalar Classification M680x0 Privileged Instructions. 10-7 Superscalar Classification M680x0 Floating-Point Instructions 10-7 Effective Address Calculation Times. 10-14 Move Byte Word Execution Times 10-15 Move Long Execution Times. 10-15 MOVE16 Execution Times 10-15 Standard Instruction Execution Time 10-16 Immediate Instruction Execution Times 10-17 Single-Operand Instruction Execution Times. 10-18 Clear (CLR) Execution Times 10-18 Shift/Rotate Execution Times. 10-19 Manipulation (Dynamic Count) Execution Times. 10-19 Manipulation (Static Count) Execution Times. 10-20 Field Execution Times. 10-20 Branch Execution Times 10-21 JMP, Execution Times. 10-21 Return Instruction Execution Times 10-21 LEA, PEA, MOVEM Instruction Execution Times 10-22 Multiprecision Instruction Execution Times 10-22 Status Register (SR) Instruction Execution Times 10-23 MOVES Execution Times. 10-23 Miscellaneous Instruction Execution Times 10-23 Floating-Point Instruction Execution Times. 10-24 Exception Processing Times. 10-26 With Heat Sink, Flow. 11-18 With Heat Sink, with Flow 11-18 Heat Sink 11-19 Support Devices Products. 11-20 Call-Out Dispatch Table Module Size .C-4 Comparison.C-12 Unimplemented Instructions.C-13
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Unimplemented Data Formats Data Types C-13 UNIX Operating System Calls C-23 Instructions Handled M68060SP C-26 Files Provided M68060SP Release. C-27 M68000 Family Instruction Processor Cross-Reference M68000 Family Instruction Set. Exception Vector Assignments M68000 Family. D-10
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SECTION INTRODUCTION
superscalar MC68060 represents line Motorola microprocessor products. first generation M68060 product line consists MC68060, MC68LC060, MC68EC060. three microprocessors offer superscalar integer performance over MIPS MHz. MC68060 comes fully equipped with both floating-point unit (FPU) memory management unit (MMU) high-performance embedded control desktop applications. cost-sensitive embedded control desktop applications where required, additional cost justified, MC68LC060 offers high-performance cost. Specifically designed low-cost embedded control applications, MC68EC060 eliminates both MMU, permitting designers leverage MC68060 performance while avoiding cost unnecessary features. Throughout this product brief, references MC68060 also refer MC68LC060 MC68EC060, unless otherwise noted. Leveraging many same performance enhancements used RISC designs well providing innovative architectural techniques, MC68060 harnesses levels performance M68000 family. Incorporating million transistors single piece silicon, MC68060 employs deep pipeline, dual issue superscalar execution, branch cache, high-performance floating-point unit (MC68060 only), eight Kbytes each on-chip instruction data caches, dual on-chip demand paging MMUs (MC68060 MC68LC060 only). MC68060 allows simultaneous execution integer instructions integer float instruction) branch instruction during each clock. MC68060 features full internal Harvard architecture. instruction data caches designed support concurrent instruction fetch, operand read operand write references every clock. Separate 8-Kbyte instruction 8-Kbyte data caches frozen prevent allocation over time-critical code data. independent nature caches allows instruction stream fetches, data-stream fetches, external accesses occur simultaneously with instruction execution. operand data cache four-way banked permit simultaneous read write access each clock. very high bandwidth internal memory system coupled with compact nature M68000 family code allows MC68060 achieve extremely high levels performance, even when operating from low-cost memory such 32-bit wide dynamic random access memory system. Instructions fetched from internal cache external memory four-stage instruction fetch pipeline. MC68060 variable-length instruction system internally decoded into fixed-length representation channeled into instruction buffer. instruction buffer acts FIFO which provides decoupling mechanism between instruction fetch
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unit operand execution units. Fixed format instructions dispatched dual fourstage pipelined RISC operand execution engines where they then executed. branch cache also plays major role achieving high performance levels MC68060. been implemented such that most branches executed zero cycles. Using technique known branch folding, branch cache allows instruction fetch pipeline detect change instruction prefetch stream before change flow affects instruction execution engines, minimizing need pipeline refill. addition substantial cost performance benefits, MC68060 also offers advantages power consumption power management. MC68060 automatically minimizes power dissipation using fully-static design, dynamic power management, low-voltage operation. automatically powers-down internal functional blocks that needed clock-by-clock basis. Explicitly MC68060 power consumption controlled from operating system. Although MC68060 operates lower operating voltage, directly interfaces both peripherals logic. Complete code compatibility with M68000 family allows designer draw existing code past experience bring products market quickly. There also broad base established development tools, including real-time kernels, operating systems, languages, applications, assist product design. functionality provided MC68060 makes ideal choice range high-performance embedded applications computing applications. With M68000 family code compatibility, MC68060 provides range upgrade opportunities virtually existing MC68040 application.
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DIFFERENCES AMONG M68060 FAMILY MEMBERS
Because functionality individual M68060 family members similar, this manual organized that reader will take following differences into account while reading rest this manual. Unless otherwise noted, references MC68060, with exception differences outlined below, will apply MC68060, MC68LC060, MC68EC060. following paragraphs describe MC68LC060 MC68EC060 differ from MC68060.
1.1.1 MC68LC060
MC68LC060 derivative MC68060. MC68LC060 same execution unit MC68060, FPU. MC68LC060 100% compatible with MC68060. Disregard information concerning when reading this manual. following difference exists between MC68LC060 MC68060: MC68LC060 does contain FPU. When floating-point instructions encountered, floating-point disabled exception taken.
1.1.2 MC68EC060
MC68EC060 derivative MC68060. MC68EC060 same execution unit MC68060, paged MMU, which embedded control applications generally require. Disregard information concerning when reading this manual. MC68EC060 compatible with MC68060. following differences exist between MC68EC060 MC68060: MC68EC060 does contain FPU. When floating-point instructions encountered, floating-point disabled exception taken. MDIS name been changed included boundary scan purposes only. 1.1.2.1 ADDRESS TRANSLATION DIFFERENCES. Although MC68EC060 paged MMU, four transparent translation registers (ITT0, ITT1, DTT0, DTT1) default transparent translation (defined certain bits translation control register (TCR)) operate normally still used assign cache modes supervisor write protection given address ranges. addresses mapped four transparent translation registers (TTRs) default transparent translation. 1.1.2.2 INSTRUCTION DIFFERENCES. PFLUSH PLPA instructions, supervisor root pointer (SRP) user root pointer (URP) registers, P-bits supported MC68EC060 must used. these instructions registers MC68EC060 exhibits poor programming practice since useful results achieved. functional anomalies that result from their will require system software modification remove offending instructions) achieve proper operation. PLPA instruction operates normally except that when address misses four TTRs, instead performing table search operation, access cache mode write protection properties defined default transparent translation bits TCR. address register contents never changed since addresses always transparently
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translated. PLPA instruction only generate access error exception only supervisor write protection violation cases. PFLUSH instruction operates virtual instruction. When MOVEC instruction used access registers P-bits TCR, exceptions reported. However, those bits undefined MC68EC060 must used.
FEATURES
main features MC68060 follows: 1.6-1.7 Times MC68040 Performance Same Clock Rate with Existing Compliers. 3.2-3.4 Times Performance MC68040. Harvard Architecture with Independent, Decoupled Fetch Execution Pipelines. Branch Prediction Logic with 256-Entry, 4-Way Set-Associative, Virtual-Mapped Branch Cache Improved Branch Instruction Performance. Superscalar Pipeline Dual Integer Execution Units Achieving Simultaneous, Out-of-Order Instruction Execution. IEEE Standard, MC68040- MC68881-/MC68882-Compatible FPU. MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry Address Translation Caches Dual 8-Kbyte Caches (Instruction Cache Data Cache) Flexible, High-Bandwidth Synchronous Interface User Object-Code Compatible with Earlier M68000 Microprocessors
ARCHITECTURE
instruction fetch unit (IFU) four-stage pipeline prefetching instructions. dual operand execution pipelines (OEPs) (named primary" (pOEP) secondary (sOEP)) four-stage pipelines decoding instructions, fetching required operand(s), then performing actual execution instructions. Since decoupled first-in-first-out (FIFO) instruction buffer, able prefetch instructions advance their actual OEPs. MC68060 designed maximize OEP's efficiency through superscalar pipeline architecture. This architectural advance improves processor performance dramatically exploiting instruction-level parallelism. term superscalar denotes ability detect, dispatch, execute, return results from more than instruction during each machine cycle from otherwise conventional instruction stream. result, multiple instructions executed single machine cycle. Since dual OEPs perform lock-step mode operation, multiple instruction execution performed simultaneously, out-of-order. effect software-invisible pipeline architecture capable sustained execution rates machine cycle instruction M68000 instruction set.
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Architectural highlights MC68060 include: Four-Stage Instruction Fetch Unit (IFU) 64-Entry Instruction Address Translation Cache (ATC), Organized 4-Way SetAssociative, Fast Virtual-to-Physical Address Translations Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache -256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache, Which Predicts Direction Branches Based Their Past Execution History -96-Byte FIFO Instruction Buffer Allow Decoupling OEPs Four-Stage Execution Pipelines Featuring Primary Pipeline (pOEP), Secondary Pipeline (sOEP), Register File (RGF) Containing Program-Visible General Registers 64-Entry Operand Data ATC, Organized 4-Way Set-Associative, Fast Virtualto-Physical Address Translations Kbyte, 4-Way Set-Associative, Physically-Mapped Operand Data Cache Operand Data Cache Organized Banked Structure Allow Simultaneous Read/Write Accesses Integer Execute Engines Optimized Perform Most Instruction Executions Single Machine Cycle -Floating-Point Execute Engine, with Floating-Point Register File, Optimized Performance with Extended-Precision-Wide Internal Datapaths. -Four-Entry Store Buffer One-Entry Push Buffer That Provide Performance Feature Decoupling Processor Pipeline from External Memory Certain Cache Modes Operation. This pipeline architecture supports extremely high data transfer rates within MC68060 processor. on-chip instruction operand data caches provide MBytes/sec pipelines, while integer execute engines support sustained transfer rates GBytes/sec.
PROCESSOR OVERVIEW
following paragraphs provide general description MC68060.
1.4.1 Functional Blocks
Figure illustrates simplified block diagram MC68060.
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architecture MC68060 processor implemented following major blocks: Execution Unit -Instruction Fetch Unit -Integer Unit -FPU Memory Units -Instruction Memory Unit Instruction Instruction Cache Instruction Cache Controller -Data Memory Unit Data Data Cache Data Cache Controller Controller These major units execute concurrently maximize sustained performance. Note that caches reside separate buses allowing concurrent instruction fetch, data read, data write operations (internal Harvard architecture).
EXECUTION UNIT INSTRUCTION FETCH UNIT CALCULATE INSTRUCTION FETCH EARLY DECODE
BRANCH CACHE
INSTRUCTION
INSTRUCTION CACHE ADDRESS
INSTRUCTION CACHE CONTROLLER INSTRUCTION MEMORY UNIT
INSTRUCTION BUFFER pOEP FLOATINGPOINT UNIT FETCH EXECUTE DECODE CALCULATE FETCH EXECUTE sOEP DECODE CALCULATE FETCH EXECUTE
DATA DATA CACHE DATA CACHE CONTROLLER
DATA
INTEGER UNIT
CONTROL
DATA AVAILABLE WRITE-BACK
DATA MEMORY UNIT
OPERAND DATA
Figure 1-1. MC68060 Block Diagram
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integer unit implements subset MC68040 instruction set. implements subset MC68881/2 coprocessor instruction set. instruction data memory units manage ATCs instruction data caches. ATCs provide on-chip storage paged MMU's most recently used address translations. data instruction caches include logic necessary read, write, update, invalidate, flush caches. controller manages interface between MMUs external bus. Snoop invalidation supported maintain cache consistency monitoring external when processor current master.
1.4.2 Integer Unit
MC68060's integer unit carries logical arithmetic operations. integer unit contains instruction fetch controller, instruction execution controller, branch target cache. superscalar design MC68060 provides dual execution pipelines instruction execution controller, providing simultaneous execution. superscalar operation integer unit disabled software, turning second execution pipeline debugging. Disabling superscalar operation also lowers performance power consumption. 1.4.2.1 INSTRUCTION FETCH UNIT. instruction fetch unit contains instruction fetch pipeline logic that interfaces branch cache. instruction fetch pipeline consists four stages, providing ability prefetch instructions advance their actual instruction execution controller. continuous fetching instructions keeps instruction execution controller busy greatest possible performance. Every instruction passes through each four stages before entering instruction execution controller. four stages instruction fetch pipeline are: Instruction Address Calculation (IAG)-The virtual address instruction determined. Instruction Fetch (IC)-The instruction fetched from memory. Early Decode (IED)-The instruction pre-decoded pipeline control information. Instruction Buffer (IB)-The instruction pipeline control information buffered until integer execution pipeline ready process instruction. branch cache plays major role achieving performance levels MC68060. concept branch cache provide mechanism that allows instruction fetch pipeline detect change instruction stream before change flow affects instruction execution controller. branch cache examined valid branch entry after each instruction fetch address generated instruction fetch pipeline. does occur branch target cache, instruction fetch pipeline continues fetch instructions sequentially. occurs branch cache, indicating branch taken instruction, current instruction stream discarded instruction stream fetched starting location indicated branch cache.
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1.4.2.2 INTEGER UNIT. integer unit contains dual integer execution pipelines, interface logic FPU, control logic data written data cache MMU. superscalar design dual integer execution pipelines provide simultaneous instruction execution, which allows processing more than instruction during each machine clock cycle. effect this software invisible pipeline capable sustained execution rates less than machine clock cycle instruction M68000 instruction set. integer unit's control logic pulls instruction pair from instruction buffer every machine clock cycle, stopping only instruction information available integer execution pipeline hold condition exists. stages dual integer execution pipelines are: Decode (DS)-The instruction fully decoded. Effective Address Calculation (AG)-If instruction calls data from memory, location data calculated. Effective Address Fetch (OC)-Data fetched from memory location. Integer Execution (EX)-The data manipulated during execution. Data Available (DA)-The result available. Write-Back (WB)-The resulting data written back on-chip caches external memory. MC68060 optimized most integer instructions execute machine clock cycle. during instruction decode stage, instruction determined floatingpoint instruction, will passed after effective address calculate stage. data written either on-chip caches external memory after instruction execution, write-back stage holds data until memory ready receive 1.4.2.3 FLOATING-POINT UNIT. Floating-point math distinguished from integer math, which deals only with whole numbers fixed decimal point locations. IEEE-compatible MC68060's computes numeric calculations with variable decimal point location. Consolidating on-chip speeds overall processing eliminates interfacing overhead associated with external accelerators. MC68060's operates parallel with integer unit. performs numeric calculations while integer unit continues integer processing. been optimized most frequently used instructions data types provide highest possible performance. also disabled software reduce system power consumption.
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MC68060 compatible with ANSI/IEEE Standard Binary Floating-Point Arithmetic. MC68060's been optimized execute most commonly used subset MC68881/MC68882 instruction sets. Software emulates floating-point instructions directly supported hardware. Refer Appendix MC68060 Software Package details software emulation. MC68060FPSP provides following features: Arithmetic Transcendental Instructions IEEE-Compliant Exception Handlers Unimplemented Data Type Data Format Handlers 1.4.2.4 MEMORY UNITS. MC68060 contains independent instruction data memory units. Each memory unit consists 8-Kbyte cache, cache controller, ATC. full addressing range MC68060 Gbytes. Even though most MC68060 systems implement much smaller physical memory, using virtual memory techniques, system appear have full Gbytes memory available each user program. Each fully supports demand-paged virtual-memory operating systems with either 8Kbyte page sizes. Each protects supervisor areas from accesses user programs provides write protection page-by-page basis. maximum efficiency, each operates parallel with other processor activities. MMUs disabled emulator debugging support. 1.4.2.5 ADDRESS TRANSLATION CACHES. 64-entry, four-way, set-associative ATCs store recently used logical-to-physical address translation information page descriptors instruction data accesses. Each initiates address translation searching descriptor containing address translation information ATC. descriptor does reside ATC, performs external cycles through controller search translation tables physical memory. After being located, page descriptor loaded into ATC, address correctly translated access. 1.4.2.6 INSTRUCTION DATA CACHES. Studies have shown that typical programs spend much their execution time main routines tight loops. Earlier members M68000 family took advantage this locality-of-reference phenomenon varying degrees. MC68060 takes further advantage cache technology with two, independent, on-chip physical caches, instructions data. caches reduce processor's external activity increase throughput lowering effective memory access time. typical system design, large caches MC68060 yield very high rate, providing substantial increase system performance. autonomous nature caches allows instruction-stream fetches, data-stream fetches, external accesses occur simultaneously with instruction execution. example, MC68060 requires both instruction access external peripheral access instruction resident on-chip cache, peripheral access proceeds unimpeded rather than being queued behind instruction fetch. data operand also required resident data cache, accessed without hindering either instruction access external peripheral access. parallelism inherent MC68060 also allows multiple instructions that require external accesses exe-
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cute concurrently while processor performing external access previous instruction. Each MC68060 cache Kbytes, accessed physical addresses. data cache configured write-through deferred copyback page basis. This choice allows optimizing system design high performance deferred copyback used. Cachability data each memory page controlled bits page descriptor. Cachable pages either write-through copyback, with write-allocate misses write-through pages. MC68060 implements four-entry store buffer that maximizes system performance decoupling integer pipeline from external system bus. When needed, store buffer allows pipeline generate writes every clock cycle until full, even system runs slower speed than processor. 1.4.2.6.1 Cache Organization. instruction data caches each organized four-way associative, with 16-byte lines. Each line data associated with address state information that shows line's validity. data cache, state information indicates whether line invalid, valid, dirty. 1.4.2.6.2 Cache Coherency. MC68060 ability watch snoop external during accesses other masters, maintaining coherency between MC68060's caches external memory systems. External cycles flagged snoopable nonsnoopable. When external cycle marked snoopable, snooper checks caches invalidates matching data. Although integer execution units snooper circuit have access on-chip caches, snooper priority over execution units.
1.4.3 Controller
implemented nonmultiplexed, fully synchronous protocol that clocked rising edge input clock. controller operates concurrently with other functional units MC68060 maximize system throughput. timing fully configurable match external memory requirements.
PROCESSING STATES
processor always three states: normal processing, exception processing, halted. normal processing state when executing instructions, fetching instructions operands, storing instruction results. Exception processing transition from program processing system, interrupt, exception handling. Exception processing includes fetching exception vector, stacking operations, refilling instruction pipe caused after exception. processor enters exception processing when exceptional internal condition arises such tracing instruction, instruction results trap, executing specific instructions. External conditions, such interrupts access errors, also cause exceptions. Exception processing ends when first instruction exception handler begins execute.
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processor halts when receives access error generates address error while exception processing state. example, during exception processing access error another access error occurs, MC68060 unable complete transition normal processing cannot save internal state machine. processor assumes that system operational halts. Only external reset restart halted processor. Note that when processor executes STOP LPSTOP instruction, special type normal processing state, without cycles. processor stops, does halt restored interrupt reset.
PROGRAMMING MODEL
MC68060 programming model separated into privilege modes: supervisor user. integer unit identifies logical address accessing either supervisor user address space, maintaining differentiation between supervisor user modes. MMUs indicated privilege mode control translate memory accesses, protecting supervisor code, data, resources from user program accesses. Refer 1.1.2.1 Address Translation Differences details concerning MC68EC060 address translation. Programs access registers based indicated mode. User programs only access registers specific user mode; whereas, system software executing supervisor mode access registers, using control registers perform supervisory functions. User programs thus restricted from accessing privileged information, operating system performs management service tasks user programs coordinating their activities. This difference allows supervisor mode protect system resources from uncontrolled accesses. Most instructions execute either mode, some instructions that have important system effects privileged only execute supervisor mode. instance, user programs cannot execute STOP RESET instructions. prevent user program from entering supervisor mode, except controlled manner, instructions that alter S-bit status register (SR) privileged. TRAP instructions provide controlled access operating system services user programs. S-bit set, processor executes instructions supervisor mode. Because processor performs exception processing supervisor mode, cycles generated during exception processing supervisor references, stack accesses active supervisor stack pointer. S-bit clear, processor executes instructions user mode. cycles instruction executed user mode user references. values transfer modifier pins indicate either supervisor user accesses. processor utilizes user mode user programming model when normal processing. During exception processing, processor changes from user supervisor mode. Exception processing saves current value active supervisor stack then sets S-bit, forcing processor into supervisor mode. return user mode, system routine must execute following instructions: MOVE ANDI EORI RTE, which execute supervisor mode,
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modifying S-bit After these instructions execute, instruction pipeline flushed refilled from appropriate address space. MC68060 integrates functions integer unit, FPU, MMU. registers depicted programming model (see Figure 1-2) provide operand storage control these three units. registers partitioned into levels privilege modes: user supervisor. user programming model same user programming model MC68040, which consists general-purpose 32-bit registers, control registers, eight 80-bit floating-point data registers, floating-point control register, floating-point status register, floating-point instruction address register.
CONTROL REGISTER STATUS REGISTER INSTRUCTION ADDRESS REGISTER USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL FPCR FPSR FPIAR
DATA REGISTERS
FLOATING-POINT DATA REGISTERS
ADDRESS REGISTERS
A7/USP
A7/SSP (CCR) CACR DTT0 DTT1 ITT0 ITT1 BUSCR PROCESSOR CONFIGURATION REGISTER SUPERVISOR STACK POINTER STATUS REGISTER (CCR ALSO SHOWN USER PROGRAMMING MODEL) VECTOR BASE REGISTER SOURCE FUNCTION CODE DESTINATION FUNCTION CODE CACHE CONTROL REGISTER USER ROOT POINTER REGISTER SUPERVISOR ROOT POINTER REGISTER TRANSLATION CONTROL REGISTER DATA TRANSPARENT TRANSLATION REGISTER DATA TRANSPARENT TRANSLATION REGISTER INSTRUCTION TRANSPARENT TRANSLATION REGISTER INSTRUCTION TRANSPARENT TRANSLATION REGISTER CONTROL REGISTER SUPERVISOR PROGRAMMING MODEL
Figure 1-2. Programming Model Only system programmers supervisor programming model implement operating system functions, control, memory management subsystems. This supervisor/
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user distinction M68000 family architecture allows writing application software that executes user mode migrates MC68060 from M68000 family platform without modification. supervisor programming model contains control features that system designers need modify system software when porting design. example, only supervisor software read write TTRs MC68060. existence TTRs does affect programming resources user application programs. user programming model includes eight data registers, seven address registers, stack pointer register. address registers stack pointer used base address registers software stack pointers, registers used index registers. control registers available user mode-the program counter (PC), which usually contains address instruction that MC68060 executing, lower byte which accessible condition code register (CCR). contains condition codes that reflect results previous operation used conditional instruction execution program. supervisor programming model includes upper byte which contains operation control information. vector base register (VBR) contains base address exception vector table, which used exception processing. source function code (SFC) destination function code (DFC) registers contain 3-bit function codes. These function codes considered extensions 32-bit logical address. processor automatically generates function codes select address spaces data program accesses user supervisor modes. Some instructions alternate function code registers specify function codes various operations. processor configuration register (PCR) contains bits which control internal pipelines MC68060 design. control register (BUSCR) used control software emulation locked transactions. cache control register (CACR) controls enabling on-chip instruction data caches MC68060. supervisor root pointer (SRP) user root pointer (URP) registers point root address translation table tree used supervisor user mode accesses. translation control register (TCR) enables logical-to-physical address translation selects either 8-Kbyte page sizes. There four TTRs, instruction accesses data accesses. These registers allow portions logical address space transparently mapped accessed without resident descriptors ATC. user programming model also access entire floating-point programming model. eight 80-bit floating-point data registers analogous integer data registers. 32-bit floating-point control register (FPCR) contains exception enable byte that enables disables traps each class floating-point exceptions mode byte that sets user-selectable rounding precision modes. floating-point status register (FPSR) contains condition code byte, quotient byte, exception status byte, accrued exception
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byte. floating-point exception handler address 32-bit floating-point instruction address register (FPIAR) locate floating-point instruction that caused exception. Instructions that modify FPIAR used read FPIAR exception handler without changing previous value.
DATA FORMAT SUMMARY
MC68060 supports basic data formats M68000 family. Some data formats apply only integer unit, some only FPU, some both. addition, instruction supports operations other data formats such memory addresses. operand data formats supported integer unit standard twos-complement data formats defined M68000 family architecture plus data format (16-byte block) MOVE16 instruction. Registers, memory, instructions themselves contain integer unit operands. operand size each instruction either explicitly encoded instruction implicitly defined instruction operation. Whenever integer used floating-point operation, automatically converts extended-precision floating-point number before using integer. implements single-, double-, extended-precision floating-point data formats defined IEEE standard. does directly support packed decimal real format. However, software emulation supports this format unimplemented data format vector. Additionally, each data format special encoding that represents five data types: normalized numbers, denormalized numbers, zeros, infinities, not-a-numbers (NANs). Table lists data formats both integer unit FPU. Refer M68000PM/ M68000 Family Programmer's Reference Manual, details data format organization registers memory. Table 1-1. Data Formats
Operand Data Format Field Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer 16-Byte Single-Precision Real Double-Precision Real Extended-Precision Real Size Supported Notes Integer Unit 1-32 Bits Integer Unit Field Consecutive Bits Bits Integer Unit Packed: Digits/Byte; Unpacked: Digit/Byte Bits Integer Unit, Bits Integer Unit, Bits Integer Unit, Bits Integer Unit Memory Only, Aligned 16-Byte Boundary Bits 1-Bit Sign, 8-Bit Exponent, 23-Bit Fraction Bits 1-Bit Sign, 11-Bit Exponent, 52-Bit Fraction Bits 1-Bit Sign, 15-Bit Exponent, 64-Bit Mantissa
ADDRESSING CAPABILITIES SUMMARY
MC68060 supports basic addressing modes M68000 family. register indirect addressing modes support postincrement, predecrement, offset, indexing, which particularly useful handling data structures common sophisticated applications high-level languages. program counter indirect mode also indexing offset capabilities. This addressing mode typically required support position-independent software. Besides these addressing modes, MC68060 provides index sizing scaling features.
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instruction's addressing mode specify value operand, register containing operand, derive effective address operand memory. Each addressing mode assembler syntax. Some instructions imply addressing mode operand. These instructions include appropriate fields operands that only addressing mode. Table lists summary effective addressing modes MC68060. Refer M68000PM/AD, M68000 Family Programmer's Reference Manual, details instruction format addressing modes. Table 1-2. Effective Addressing Modes
Addressing Modes Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address Register Indirect with Index 8-Bit Displacement Base Displacement Memory Indirect Postindexed Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index 8-Bit Displacement Base Displacement Program Counter Memory Indirect Postindexed Preindexed Absolute Data Addressing Short Long Immediate Syntax (An) (An)+ -(An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #<xxx>
INSTRUCTION OVERVIEW
instruction tailored support high-level languages optimized those instructions most commonly executed. floating-point instructions MC68060 commonly used subset MC68881/MC68882 instruction with arithmetic instructions explicitly select single- double-precision rounding. remaining unimplemented instructions less frequently used efficiently emulated MC68060FPSP, maintaining compatibility with MC68881/MC68882 floating-point coprocessors. MC68060 instruction includes MOVE16 which allows high-speed transfers 16-byte blocks between external devices such memory memory coprocessor memory. Table provides alphabetized listing MC68060 instruction set's opcode, operation, syntax. Refer Table notations used Table 1-3. left operand syntax always source operand, right operand destination operand. Refer M68000PM/AD, M68000 Family Programmer's Reference Manual, details instructions used MC68060.
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Table 1-3. Instruction Summary
Opcode ABCD ADDA ADDI ADDQ ADDX ANDI Operation Source Destination Destination Source Destination Destination Source Destination Destination Immediate Data Destination Destination Immediate Data Destination Destination Source Destination Destination Source Destination Destination Immediate Data Destination Destination supervisor state then Source else TRAP Destination Shifted count Destination condition true then ~(bit number Destination) ~(bit number Destination) (bit number) Destination ~(bit number Destination) number Destination ~(bit field Destination) field Destination field Destination field Source offset Source offset Source Scan field Destination field Destination field Destination breakpoint acknowledge cycle; TRAP illegal instruction ~(bit number Destination) number Destination (SP); -(bit number Destination) Destination Compare Operand Update Operand Destination else Destination Compare Operand CAS2 Destination Compare Destination Compare Update Destination Update Destination else Destination Compare Destination Compare Source then TRAP then TRAP supervisor state then invalidate selected cache lines else TRAP Syntax ABCD Dy,Dx ABCD -(Ay),-(Ax) <ea>,Dn Dn,<ea> ADDA <ea>,An ADDI #<data>,<ea> ADDQ #<data>,<ea> ADDX Dy,Dx ADDX -(Ay),-(Ax) <ea>,Dn Dn,<ea> ANDI #<data>,<ea> ANDI #<data>,CCR ANDI #<data>,SR Dx,Dy1 #<data>,Dy <ea> <label> BCHG Dn,<ea> BCHG #<data>,<ea> BCLR Dn,<ea> BCLR #<data>,<ea> BFCHG <ea>{offset:width} BFCLR <ea>{offset:width} BFEXTS <ea>{offset:width},Dn BFEXTU <ea>{offset:width},Dn BFFFO <ea>{offset:width},Dn BFINS Dn,<ea>{offset:width} BFSET <ea>{offset:width} BFTST <ea>{offset:width} BKPT #<data> <label> BSET Dn,<ea> BSET #<data>,<ea> <label> BTST Dn,<ea> BTST #<data>,<ea> Dc,Du,<ea>
ANDI Source ANDI ASL, BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BSET BTST CAS8
CAS22
CAS2 Dc1-Dc2,Du1-Du2,(Rn1)- (Rn2)
CHK22 CINV
<ea>,Dn CHK2 <ea>,Rn CINVL <caches>, (An) CINVP <caches>, (An) CINVA <caches>
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Table 1-3. Instruction Summary (Continued)
Opcode CMPA CMPI CMPM CMP22 CPUSH Operation Destination Destination Source Destination Source Destination Immediate Data Destination Source Compare Condition Codes supervisor state then data cache push selected dirty data cache lines; invalidate selected cache lines else TRAP condition false then (Dn-1 then Syntax <ea> <ea>,Dn CMPA <ea>,An CMPI #<data>,<ea> CMPM (Ay)+,(Ax)+ CMP2 <ea>,Rn CPUSHL <caches>, (An) CPUSHP <caches>, (An) CPUSHA <caches> DBcc Dn,<label> DIVS.W <ea>,Dn32 16r:16q DIVS.L <ea>,Dq32 DIVS.L <ea>,Dr:Dq64 32r:32q2 DIVSL.L <ea>,Dr:Dq 32r:32q DIVU.W <ea>,Dn32 16r:16q DIVU.L <ea>,Dq32 DIVU.L <ea>,Dr:Dq64 32r:32q2 DIVUL.L <ea>,Dr:Dq32 32r:32q Dn,<ea> EORI #<data>,<ea> EORI #<data>,CCR EORI #<data>,SR Dx,Dy Ax,Ay Dx,Ay Ay,Dx EXT.W Dnextend byte word EXT.L Dnextend word long word EXTB.L extend byte long word FABS.<fmt> <ea>,FPn FABS.X FPm,FPn FABS.X FrABS.<fmt> <ea>,FPn3 FrABS.X FPm,FPn3 FrABS.X FPn3 FADD.<fmt> <ea>,FPn FADD.X FPm,FPn FrADD.<fmt> <ea>,FPn3 FrADD.X FPm,FPn3 FBcc.SIZE <label> FCMP.<fmt> <ea>,FPn FCMP.X FPm,FPn
DBcc
DIVS, DIVSL Destination Source Destination
DIVU, DIVUL Destination Source Destination Source Destination Destination EORI Immediate Data Destination Destination EORI Source supervisor state EORI then Source else TRAP EXTB
Destination Sign Extended Destination
FABS
Absolute Value Source
FADD
Source condition true then Source condition true then operation else then else execute next instruction Source
FBcc FCMP
FDBcc2
FDBcc Dn,<label>
FDIV
FDIV.<fmt> <ea>,FPn FDIV.X FPm,FPn FrDIV.<fmt> <ea>,FPn3 FrDIV.X FPm,FPn3
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Table 1-3. Instruction Summary (Continued)
Opcode FINT FINTRZ Floating-Point Integer Part Floating-Point Integer Part, Round-to-Zero Operation Syntax FINT.<fmt><ea>,FPn FINT.X FPm,FPn FINT.X FINTRZ.<fmt><ea>,FPn FINTRZ.X FPm,FPn FINTRZ.X FMOVE.<fmt> <ea>,FPn FMOVE.<fmt> FPm,<ea> FMOVE.P FPm,<ea>{Dn} FMOVE.P FPm,<ea>{#k} FrMOVE.<fmt> <ea>,FPn3 FMOVE.L <ea>,FPcr FMOVE.L FPcr,<ea> FMOVEM.X <list>,<ea>4 FMOVEM.X Dn,<ea> FMOVEM.X <ea>,<list>4 FMOVEM.X <ea>,Dn FMOVEM.L <list>,<ea>5 FMOVEM.L <ea>,<list>5 FMUL.<fmt> <ea>,FPn FMUL.X FPm,FPn FrMUL<fmt> <ea>,FPn3 FrMUL.X FPm,FPn3 FNEG.<fmt> <ea>,FPn FNEG.X FPm,FPn FNEG.X FrNEG.<fmt> <ea>,FPn3 FrNEG.X FPm,FPn3 FrNEG.X FPn3 FNOP FRESTORE <ea> FSAVE <ea> FScc.SIZE <ea> FSGLDIV.<fmt> <ea>,FPn FSGLDIV.X FPm,FPn FSGMUL.<fmt> <ea>,FPn FSGLMUL.X FPm, FSQRT.<fmt> <ea>,FPn FSQRT.X FPm,FPn FSQRT.X FrSQRT.<fmt> <ea>,FPn3 FrSQRT FPm,FPn3 FrSQRT FPn3 FSUB.<fmt> <ea>,FPn FSUB.X FPm,FPn FrSUB.<fmt> <ea>,FPn3 FrSUB.X FPm,FPn3 FTRAPcc FTRAPcc.W #<data> FTRAPcc.L #<data> FTST.<fmt> <ea> FTST.X ILLEGAL <ea>
FMOVE
Source Destination
FMOVE
Source Destination Register List Destination Source Register List Register List Destination Source Register List Source
FMOVEM
FMOVEM9
FMUL
FNEG
-(Source)
FNOP FRESTORE FSAVE FScc2 FSGLDIV FSGLMUL
None supervisor state then State Frame Internal State else TRAP supervisor state then Internal State State Frame else TRAP condition true then Destination else Destination Source Source
FSQRT
Square Root Source
FSUB
Source condition true then TRAP Condition Codes Operand FPCC SSP; Vector Offset (SSP); SSP; (SSP); SSP; (SSP); Illegal Instruction Vector Address Destination Address
FTRAPcc2 FTST ILLEGAL
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Table 1-3. Instruction Summary (Continued)
Opcode LINK Operation (SP) Destination Address <ea> (SP) SP+d supervisor state immediate data broadcast cycle STOP else TRAP Destination Shifted count Destination Source Destination Source Destination Destination Source Syntax <ea> <ea>,An LINK An,dn
LPSTOP
LPSTOP #<data> Dx,Dy1 #<data>,Dy1 <ea>1 MOVE <ea>,<ea> MOVEA <ea>,An MOVE CCR,<ea> MOVE <ea>,CCR MOVE SR,<ea> MOVE <ea>,SR MOVE USP,An MOVE An,USP MOVE16 (Ax)+, (Ay)+6 MOVE16 (xxx).L, (An) MOVE16 (An), (xxx).L MOVE16 (An)+, (xxx).L MOVEC Rc,Rn MOVEC Rn,Rc MOVEM <list>,<ea>4 MOVEM <ea>,<list>4 MOVEP Dx,(dn,Ay) MOVEP (dn,Ay),Dx MOVEQ #<data>,Dn MOVES Rn,<ea> MOVES <ea>,Rn MULS.W <ea>,Dn MULS.L <ea>,Dl MULS.L <ea>,Dh-Dl MULU.W <ea>,Dn MULU.L <ea>,Dl MULU.L <ea>,Dh-Dl NBCD <ea> <ea> NEGX <ea> <ea> <ea>,Dn Dn,<ea> #<data>,<ea> #<data>,CCR
LSL, MOVE MOVEA MOVE from MOVE MOVE from
supervisor state then Destination else TRAP supervisor state MOVE then Source else TRAP supervisor state MOVE then else TRAP MOVE16 Source block Destination block supervisor state then else TRAP Registers Destination Source Registers Source Destination Immediate Data Destination supervisor state then Destination [DFC] Source [SFC] else TRAP Source Destination Destination Source Destination Destination (Destination10) Destination (Destination) Destination (Destination) Destination None Destination Destination Source Destination Destination Immediate Data Destination Destination Source
MOVEC MOVEM MOVEP2 MOVEQ MOVES
MULS
MULU NBCD NEGX
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Table 1-3. Instruction Summary (Continued)
Opcode PACK PFLUSH7 Operation supervisor state then Source else TRAP Source (Unpacked BCD) adjustment Destination (Packed BCD) <ea> (SP) supervisor state then invalidate instruction data entries destination address else TRAP supervisor state then logical address translate physical address else TRAP supervisor state then Assert RSTO Line else TRAP Destination Rotated count Destination Syntax #<data>,SR PACK -(Ax),-(Ay),#(adjustment) PACK Dx,Dy,#(adjustment) <ea> PFLUSH (An) PFLUSHN (An) PFLUSHA PFLUSHAN PLPAR (An) PLPAW (An) RESET
Rx,Dy1
PLPA
RESET ROL,
ROXL, ROXR Destination Rotated with count Destination (SP) supervisor state then (SP) (SP) restore state deallocate stack according (SP) else TRAP (SP) CCR; (SP) (SP) Destination10 Source10 Destination condition true then Destination else Destination supervisor state then Immediate Data STOP else TRAP Destination Source Destination Destination Source Destination Destination Immediate Data Destination Destination Immediate Data Destination Destination Source Destination Register 31-16 Register 15-0 Destination Tested Condition Codes; Destination SSP; Format Offset (SSP); SSP; (SSP); SSP; (SSP); Vector Address then TRAP
ROXd Dx,Dy1 ROXd #<data>,Dy1 ROXd <ea>1 #(dn)
SBCD STOP SUBA SUBI SUBQ SUBX SWAP TRAP TRAPcc TRAPV UNLK UNPK
SBCD Dx,Dy SBCD -(Ax),-(Ay) <ea> STOP #<data> <ea>,Dn Dn,<ea> SUBA <ea>,An SUBI #<data>,<ea> SUBQ #<data>,<ea> SUBX Dx,Dy SUBX -(Ax),-(Ay) SWAP <ea> TRAP #<vector> TRAPcc TRAPcc.W #<data> TRAPcc.L #<data> TRAPV <ea> UNLK UNPACK -(Ax),-(Ay),#(adjustment) UNPACK Dx,Dy,#(adjustment)
then TRAP Destination Tested Condition Codes (SP) Source (Packed BCD) adjustment Destination (Unpacked BCD)
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Table 1-3. Instruction Summary (Continued)
Opcode Operation Syntax NOTES: 1.Where direction, left right. 2.Emulation support only, supported hardware. 3.Where rounding precision, single double precision. 4.List refers register. 5.List refers control registers only. 6.MOVE16 (ax)+,(ay)+ functionally same MOVE16 (ax),(ay)+ when address register only incremented once, line copied over itself rather than next line. 7.Not available MC68EC060. 8.Emulation support misaligned operands. 9.Emulation support FMCVEM with dynamic register list.
1.10 NOTATIONAL CONVENTIONS
Table lists notation conventions used throughout this manual. Table 1-4. Notational Conventions
<op> <operand>tested sign-extended Single- Double-Operand Operations Arithmetic addition postincrement indicator. Arithmetic subtraction predecrement indicator. Arithmetic multiplication. Arithmetic division conjunction symbol. Invert; operand logically complemented. Logical Logical Logical exclusive Source operand moved destination operand. operands exchanged. double-operand operation. Operand compared zero condition codes appropriately. bits upper portion made equal high-order lower portion. Other Operations Equivalent Format Offset Word (SSP); SSP; (SSP); SSP; (SSP); SSP; (Vector) Enter stopped state, waiting interrupts. operand BCD; operations performed decimal. Test condition. true, operations after "then" performed. condition false optional "else" clause present, operations after "else" performed. condition false else omitted, instruction performs operation. Refer instruction description example. Register Specification Address Register (example: address register Source destination address registers, respectively. Base Register-An, suppressed. Data register D7-D0, used during compare. Data registers high- low-order bits product. Data Register (example: data register Data register's remainder quotient divide. Data register D7-D0, used during update. Source destination data registers, respectively. Memory Register
TRAP STOP <operand>10 <condition> then <operations> else <operations>
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Table 1-4. Notational Conventions (Continued)
<fmt> #<xxx> #<data> SCALE SIZE {offset:width} <ea> <label> <list> Address Data Register source destination registers, respectively. Index Register-An, suppressed. Data Format Type Positive Infinity Operand Data Format: Byte (B), Word (W), Long (L), Single (S), Double (D), Extended (X), Packed (P). Specifies signed integer data type (twos complement) byte, word, long word. Double-precision real data format bits). twos complement signed integer (-64 +17) specifying number's format stored packed decimal format. Packed real data format bits, bytes). Single-precision real data format bits). Extended-precision real data format bits, bits unused). Negative Infinity Subfields Qualifiers Immediate data following instruction word(s). Identifies indirect address register. Identifies indirect address memory. Base Displacement Displacement Value, Bits Wide (example: 16-bit displacement). Least Significant Least Significant Word Most Significant Most Significant Word Outer Displacement scale factor no-word, word, long-word, quad-word scaling, respectively). index register's size word, long word). field selection. Register Codes General Case. Carry Condition Codes from Function Code Negative Undefined, Reserved Motorola Use. Overflow Extend Zero Affected Applicable. Miscellaneous Effective Address Assemble Program Label List registers, example D3-D0. Lower Bound Operand Bits through Operand Upper Bound
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SECTION SIGNAL DESCRIPTION
This section contains brief descriptions MC68060 signals their functional groups (see Figure 2-1). Each signal's function briefly explained, referencing other sections containing detailed information about signal related operations. Table lists MC68060 signal names, mnemonics, functional descriptions signals. Timing specifications these signals found Section Electrical Thermal Characteristics. NOTE
Assertion negation used specify forcing signal particular state. Assertion assert refer signal that active true. Negation negate refer signal that inactive false. These terms used independently voltage level (high low) that they represent.
Table 2-1. Signal Index
Signal Name Address Cycle Long-Word Address Data Transfer Type Transfer Modifier Transfer Line Number User-Programmable Attributes Read/Write Transfer Size Lock Lock Cache Inhibit Byte Select Transfer Start Transfer Progress Starting Termination Acknowledge Signal Sampling Transfer Acknowledge Mnemonic A31-A0 D31-D0 Function 32-bit address used address 4-Gbytes. Controls operation during cycles.
32-bit data used transfer bits data transfer. Indicates general transfer type: normal, MOVE16, alternate logical function TT1,TT0 code, acknowledge. TM2-TM0 Indicates supplemental information about access. TLN1,TLN0 Indicates which cache line being pushed loaded current line transfer cycle. UPA1,UPA0 User-defined signals, controlled corresponding user attribute bits from address translation entry. Identifies transfer read write. Indicates data transfer size. These signals, together with SIZ1,SIZ0 define active sections data bus. Alternately, BS3-BS0 used this function. Indicates cycle part read-modify-write operation that LOCK sequence cycles should interrupted. LOCKE Indicates current cycle last locked sequence cycles. CIOUT Indicates processor will cache current transfer information. BS3-BS0 Indicate which bytes within long word selected which data bytes valid. Indicates beginning cycle. Asserted duration cycle. Indicates MC68060 will begin sampling termination acknowledge signals. Asserted acknowledge transfer.
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Table 2-1. Signal Index (Continued)
Signal Name Transfer Retry Acknowledge Transfer Error Acknowledge Transfer Cycle Burst Inhibit Transfer Cache Inhibit Snoop Control Request Grant Grant Relinquish Control Tenure Termination Busy Cache Disable Disable Reset Reset Interrupt Priority Level Interrupt Pending Autovector Processor Status Processor Clock Clock Enable JTAG Enable Test Clock Test Mode Select Test Data Input Test Data Output Test Reset Thermal Resistor Connections Power Supply Ground Mnemonic SNOOP Function Indicates need rerun cycle. Indicates error condition exists transfer. Indicates slave cannot handle line burst access.
Indicates current transfer should cached. Indicates MC68060 should snoop activity while master. Asserted processor request mastership. Asserted arbiter grant mastership privileges processor. Qualifies indicating degree necessity relinquishing ownerBGR ship when negated. Indicates MC68060 relinquished response external arBTT biter's negation Asserted current master indicate assumed ownership bus. CDIS Dynamically disables internal caches assist emulator support. MDIS Disables translation mechanism MMUs. RSTI Processor reset. RSTO Asserted during execution RESET instruction reset external devices. IPL2-IPL0 Provides encoded interrupt level processor. IPEND Indicates interrupt pending. Used during interrupt acknowledge transfer request internal generation AVEC vector number. PST4-PST0 Indicates internal processor status. Clock input used internal logic timing. Defines speed system clock full, 1/2, speed CLKEN processor clock. Selects between IEEE 1149.1 compliance operation emulation mode operJTAG ation. Clock signal IEEE P1149.1 test access port (TAP). Selects principal operations test-support circuitry. Serial data input TAP. Serial data output TAP. TRST Provides asynchronous reset controller. THERM1, Provides thermal sensing information. THERM0 Power supply. Ground connection.
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Signal Description
ADDRESS CONTROL
A31-A0
SNOOP
SNOOP CONTROL
DATA
D31-D0
ARBITRATION CONTROL
TLN1 TLN0 UPA1 UPA0 TRANSFER ATTRIBUTES SIZ1 SIZ0 LOCK LOCKE CIOUT
CDIS MDIS RSTI RSTO IPL2 IPL1 IPL0 IPEND AVEC PST4 PST3 PST2 PST1 PST0 CLKEN JTAG TRST
PROCESSOR CONTROL
INTERRUPT CONTROL
MC68060
STATUS CLOCKS
MASTER TRANSFER CONTROL
TEST
SLAVE TRANSFER CONTROL
THERM1 THERM0
THERMAL RESISTOR CONNECTIONS POWER SUPPLY
Figure 2-1. Functional Signal Groups
ADDRESS CONTROL SIGNALS
following paragraphs describe MC68060 address control signals.
2.1.1 Address (A31-A0)
These three-state bidirectional signals provide address first item transfer (except interrupt acknowledge transfers) when MC68060 master. When alternate master controlling asserts SNOOP signal, address sig-
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nals examined determine whether processor should invalidate matching cache entries maintain cache coherency.
2.1.2 Cycle Long-Word Address (CLA)
This active-low input signal controls operation during cycles. Following each clock-enabled clock edge which asserted, long-word address each four transfers encoded will increment circular wraparound fashion. negated during clock-enabled clock edge, values will change. necessary synchronize with
DATA (D31-D0)
These three-state bidirectional signals provide general-purpose data path between MC68060 other devices. data transfer bits data transfer. During burst cycle, bits line information transferred using four 32-bit transfers.
TRANSFER ATTRIBUTE SIGNALS
following paragraphs describe transfer attribute signals, which provide additional information about transfer cycle. Refer Section Operation detailed information about relationship transfer attribute signals operation.
2.3.1 Transfer Cycle Type (TT1, TT0)
processor drives these three-state signals indicate type access current cycle. During cycle transfers alternate master when processor allowed snoop transactions, sampled. Only normal MOVE16 accesses snooped. Table lists definition encoding. acknowledge access (TT1 used interrupt acknowledge, breakpoint acknowledge, lowpower stop broadcast cycles. Table 2-2. Transfer-Type Encoding
Transfer Type Normal Access MOVE16 Access Alternate Logical Function Code Access, Debug Access Acknowledge Access, Low-Power Stop Broadcast
2.3.2 Transfer Cycle Modifier (TM2-TM0)
These three-state outputs provide supplemental information each transfer cycle type. Table lists encoding normal (TTx MOVE16 (TTx transfers, Table lists encoding alternate access transfers (TTx 10). interrupt acknowledge transfers, signals carry interrupt level being acknowledged. breakpoint
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Signal Description
acknowledge transfers low-power stop broadcast cycles, signals negated. When MC68060 master, signals high-impedance state.
MOTOROLA
M68060 USER'S MANUAL
Signal Description
Table 2-3. Normal MOVE16 Access Encoding
Transfer Modifier Data Cache Push Access User Data Access* User Code Access Table Search Data Access Table Search Code Access Supervisor Data Access* Supervisor Code Access Reserved *MOVE16 accesses only these encodings.
Table 2-4. Alternate Access Encoding
Transfer Modifier Logical Function Code Debug Access Reserved Logical Function Code Logical Function Code Debug Pipe Control Mode Access Debug Pipe Control Mode Access Logical Function Code
2.3.3 Transfer Line Number (TLN1, TLN0)
These three-state outputs indicate which line four data instruction cache lines being accessed normal push line data read accesses. TLNx signals undefined other accesses placed high-impedance state when processor master. TLNx signals used high-performance systems build external snoop filter with duplicate cache tags. TLNx signals address provide direct indication state data caches used help maintain duplicate store. TLNx signals indicate correct number when instruction cache burst fill occurs.
2.3.4 User-Programmable Page Attributes (UPA1, UPA0)
UPAx signals three-state outputs. These signals only valid normal code, data, MOVE16 accesses. other accesses (including table search cache line push accesses), UPAx signals low. When MC68060 master, these signals placed high-impedance state. During normal MOVE16 accesses, transparent translation register (TTR) enabled address attributes match values, UPAx signals defined logical values bits TTR. enabled translation control register (TCR) address attributes result address translation cache (ATC) hit, UPAx signals defined logical values bits entry. given logical address mapped TTRs address translation disabled,
M68060 USER'S MANUAL
MOTOROLA
Signal Description
then MC68060 invokes default transparent translation. cache mode, user page attributes, other fields default translation defined contents TCR. more information about UPAx signals, refer Section Memory Management Unit.
2.3.5 Read/Write (R/W)
This three-state output signal defines data transfer direction current cycle. high (logic one) level indicates read cycle, (logic zero) level indicates write cycle. This signal placed high-impedance state when MC68060 master.
2.3.6 Transfer Size (SIZ1, SIZ0)
These three-state output signals indicate data size cycle. These signals placed high-impedance state when MC68060 master. Table shows definitions SIZx encoding. Table 2-5. SIZx Encoding
SIZ1 SIZ0 Transfer Size Long Word Bytes) Byte Word Bytes) Line Bytes)
2.3.7 Lock (LOCK)
This three-state output indicates that current cycle part sequence locked cycles. external arbiter LOCK with control alternate master's prevent alternate master from gaining control accessing same operand between processor accesses locked sequence transfers. Although LOCK indicates that processor requests that locked, processor will relinquish external arbiter negates asserts BGR. When MC68060 master, LOCK signal high-impedance state. MC68060 relinquishes while LOCK asserted, LOCK will negated full clock-enabled clock cycle then three-stated clock-enabled clock cycle after address idled. LOCK already negated clock cycle which MC68060 relinquishes bus, will three-stated same clock cycle address idled. Refer Section Operation information locked transfers.
2.3.8 Lock (LOCKE)
This three-state output indicates that current cycle last sequence locked cycles (except case which retry termination indicated last write read-modify-write sequence). When MC68060 master, LOCKE signal high-impedance state. MC68060 relinquishes while LOCKE asserted, LOCKE will negated
MOTOROLA
M68060 USER'S MANUAL
Signal Description
full BCLK cycle then three-stated BCLK cycle after address idled. LOCKE already negated BCLK cycle which MC68060 relinquishes bus, will three-stated same BCLK cycle address idled. LOCKE provided help make MC68060 compatible with MC68040-style protocol; however, designs, external arbitration logic simplified with instead LOCKE. LOCKE. LOCKE protocol breaks integrity locked read-modifywrite sequence possible retry last write read-modify-write operation. reason that when LOCKE asserted, arbiter grant alternate master when current cycle finished (before retry attempted). arbitrated away, last write's retry deferred until returned processor. meantime, alternate master access same location where write should have taken place. Hence, integrity locked read-modify-write sequence compromised this situation.
2.3.9 Cache Inhibit (CIOUT)
When asserted, this three-state output indicates that MC68060 will cache current information internal caches. Refer Section Memory Management Unit more information CIOUT function. When MC68060 master, CIOUT signal placed high-impedance state.
2.3.10 Byte Select Lines (BS3-BS0)
These three-state outputs indicate which bytes within long-word transfer being selected which bytes data will used transfer. refers D31- D24, refers D23-D16, refers D15-D8, refers D7-D0. These signals generated provide byte data select signals which decoded from SIZx, signals shown Table 2-6. These signals placed high-impedance state when MC68060 master. Table 2-6. Data Byte Select Signals
Transfer Size Byte Byte Byte Byte Word Word Long Word Line SIZ1 SIZ0 D31-D24 D23-D16 D15-D8 D7-D0
MASTER TRANSFER CONTROL SIGNALS
following signals provide control functions cycles when MC68060 master. Refer Section Operation detailed information about relationship cycle control signals operation.
M68060 USER'S MANUAL
MOTOROLA
Signal Description
2.4.1 Transfer Start (TS)
processor asserts this three-state bidirectional signal clock-enabled clock period indicate start each cycle. During alternate master accesses, processor monitors SNOOP detect start each cycle which snooped. placed high-impedance state when MC68060 master. properly maintain internal state information, masters must have their signals tied together.
2.4.2 Transfer Progress (TIP)
This three-state output asserted indicate that cycle progress negated during idle cycles still granted processor. remains asserted during time between back-to-back cycles. MC68060 relinquishes while asserted, will negated clock period after completion final transfer then goes high-impedance state clock period after address idled. Note that this clock period which driven negated refers MC68060 processor clock period, full clock-enabled clock period. already negated clock period which MC68060 relinquishes bus, will placed high-impedance state same clock period that address becomes idle.
2.4.3 Starting Termination Acknowledge Signal Sampling (SAS)
This three-state output asserted clock-enabled clock period indicate that MC68060 will begin sampling TEA, TRA, TBI, TCI, AVEC, spurious interrupt indication next rising edge clock-enabled clock. negated other times while MC68060 master. When MC68060 relinquishes bus, driven negated clock-enabled clock period then three-stated clock-enabled clock period after address idled. When MC68060 newly gains ownership immediately starts cycle with assertion remains three-stated until clock-enabled clock period after asserted.
SLAVE TRANSFER CONTROL SIGNALS
following signals provide control functions transfers when MC68060 master. Refer Section Operation detailed information about relationship cycle control signals operation.
2.5.1 Transfer Acknowledge (TA)
This input indicates completion requested data transfer operation. During transfers MC68060, input signal from referenced slave device indicating completion transfer. MC68060 accept transfer successful with transfer acknowledge, must negated when asserted.
2.5.2 Transfer Retry Acknowledge (TRA)
native-MC68060-style (non-MC68040-style) acknowledge termination, this input signal asserted current slave first transfer cycle indicate need
MOTOROLA
M68060 USER'S MANUAL
Signal Description
rerun current cycle. assertion transfer other than first transfer ignored. assertion precedence over does have precedence over TEA. MC68060 processor used with MC68040-style acknowledge termination, then must held negated. this case, does have precedence over slave must assert both first transfer cycle cause retry current cycle. assertion transfer other than first will interpreted MC68060 only been asserted, which immediately terminates cycle with error indication.
2.5.3 Transfer Error Acknowledge (TEA)
current slave asserts this input signal indicate error condition current transfer immediately terminate cycle. assertion precedence over native-MC68060-style acknowledgment termination. MC68040-style acknowledge termination, must asserted with negated cause current cycle immediately terminate with error indication. MC68040-style acknowledge termination, must held negated.
2.5.4 Transfer Burst Inhibit (TBI)
This input signal indicates processor that device cannot support burst mode accesses that requested line transfer cycle should divided into individual longword cycles. Asserting with terminates first data transfer line access, causing processor terminate burst cycle access remaining data line three successive long-word transfer cycles.
2.5.5 Transfer Cache Inhibit (TCI)
This input signal inhibits line read data from being loaded into MC68060 instruction data caches. ignored during writes after first data transfer both burst line reads burst-inhibited line reads. also ignored during alternate master transfers.
SNOOP CONTROL (SNOOP)
This input signal controls operation MC68060 internal snoop logic. MC68060 examines SNOOP when asserted alternate master controlling bus. snooping disabled (i.e., SNOOP negated) during clock when asserted, MC68060 will snoop transaction. snooping enabled (i.e., SNOOP asserted) during clock when asserted, MC68060 will snoop access invalidate matching cache lines either read write cycles without external indication that cache entry been invalidated upon cache snoop hits. Section Caches provides information about relationship SNOOP caches, Section Operation discusses relationship SNOOP operation.
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Signal Description
ARBITRATION SIGNALS
following control signals support mastership control external arbiter over MC68060. Refer Section Operation detailed information about relationship arbitration signals operation.
2.7.1 Request (BR)
This output signal indicates external arbiter that processor needs become master more cycles. negated when MC68060 begins access external with other internal accesses pending, remains negated until another internal request occurs. assertion negation independent activity there some situations which MC68060 asserts then negates without having cycle; this disregard request condition. Refer Section Operation details about this state.
2.7.2 Grant (BG)
This input signal from external arbiter indicates that available MC68060 soon current cycle completes. MC68060 assumes ownership when asserted negated, when asserted TS-BTT pair asserted, followed asserted) occurred past without another assertion when asserted negated. MC68060 indicates ownership asserting When external arbiter negates MC68060 relinquishes soon current cycle complete unless locked sequence cycles progress with negated. this case, MC68060 will complete entire sequence locked cycles then indicate that relinquishing asserting negating
2.7.3 Grant Relinquish Control (BGR)
This input signal qualifier indicates MC68060 degree necessity relinquishing ownership when negated external arbiter. controls MC68060 behavior when negated during sequences locked cycles (LOCK asserted). When external arbiter negates during series locked cycles, assertion will cause MC68060 relinquish last transfer current cycle, even though MC68060 intended series locked. remains negated when negated during locked transfers, then MC68060 will relinquish until series locked cycles complete.
2.7.4 Tenure Termination (BTT)
This three-state bidirectional signal asserted clock-enabled clock period negated clock-enabled clock period indicate that MC68060 relinquished tenure following negation external arbiter. other times, high-impedance state. When alternate master controlling bus, MC68060 samples input maintain internal state information monitor when MC68060 become master. properly maintain this internal state information, masters must have their signals tied together their signals tied together MC68060 keep track TS-BTT pairs.
MOTOROLA
M68060 USER'S MANUAL
2-11
Signal Description
MC68060 provides signal protocol provide compatibility with MC68040style buses. Either signal protocol signal protocol (but both) should used. unused signal, either must pulled with pullup resistor tied VCC. signal protocol yields higher performance full speed high operating frequencies. associated protocol recommended full speeds. protocol discussed detail Section Operation.
2.7.5 Busy (BB)
This three-state bidirectional signal indicates that currently owned. monitored processor input determine when alternate master released control bus. MC68060 samples availability each clock-enabled clock edge. must asserted both must negated (indicating free) before MC68060 asserts (with first assertion output assume ownership bus. processor keeps asserted until external arbiter negates processor completes cycle progress. When releasing bus, processor negates clock period, then places high-impedance state begins sample input. Note that clock period which negated MC68060 processor clock period, full clock-enabled clock period. MC68060 provides signal protocol support compatibility with MC68040style buses. Either signal protocol signal protocol (but both) should used. unused signal, either must pulled through pullup resistor tied VCC. signal protocol yields higher performance full speed high operating frequencies. associated protocol recommended full speeds. protocol discussed detail Section Operation.
PROCESSOR CONTROL SIGNALS
following signals control caches MMUs support processor external device initialization.
2.8.1 Cache Disable (CDIS)
When asserted, this input signal dynamically disables on-chip caches next internal cache access boundary. caches enabled next boundary after CDIS negated. CDIS does flush data instruction caches. Cache entries remain unaltered become available after CDIS negated, unless cache invalidate instructions (CINVA, CINVP, CINVL) executed. execution cache invalidate instructions invalidate entries even caches have been disabled with this signal. assertion CDIS does affect snooping. Refer Section Caches information about caches.
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MOTOROLA
Signal Description
2.8.2 Disable (MDIS)
When asserted, this input signal dynamically disables MC68060 internal operand data instruction MMUs next internal access boundary. While MDIS asserted, accesses bypass ATCs, thus translate transparently. execution flush instructions (PFLUSHA, PFLUSHAN, PFLUSH, PFLUSHN) cause deletion entries, even been disabled this signal. MMUs enabled next boundary after MDIS negated. Refer Section Memory Management Unit description address translation.
2.8.3 Reset (RSTI)
assertion this input signal causes MC68060 enter reset exception processing. RSTI signal asynchronous input that internally synchronized next rising clock-enabled clock (CLK) edge. three-state signals will eventually highimpedance state when RSTI recognized. assertion RSTI does affect test pins. Refer Section Operation description reset operation Section Exception Processing information about reset exception.
2.8.4 Reset (RSTO)
MC68060 asserts this output during execution RESET instruction initialize external devices. cycles MC68060 suspended prior assertion RSTO, arbitration snooping still function. Refer Section Operation description reset operation.
INTERRUPT CONTROL SIGNALS
following signals control interrupt functions.
2.9.1 Interrupt Priority Level (IPL2-IPL0)
These input signals provide indication interrupt condition with interrupt level from peripheral external prioritizing circuitry encoded. IPL2 most significant level number. example, since IPLx signals active low, IPL2-IPL0 corresponds interrupt request interrupt priority level IPL2-IPL0 (level highest priority interrupt cannot internally masked. IPL2-IPL0 (level indicates interrupt requested. IPLx signals asynchronous inputs that internally synchronized rising clock (CLK) edges. During processor reset, levels IPLx lines registered used configure various operating modes MC68060 bus. Refer Section Operation more information operating modes Section Exception Processing information interrupts.
2.9.2 Interrupt Pending Status (IPEND)
This output signal indicates that interrupt request been recognized internally processor exceeds current interrupt priority mask status register (SR). External devices (other masters) IPEND predict processor operation next instruction boundaries. IPEND intended interrupt acknowledge exter-
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M68060 USER'S MANUAL
2-13
Signal Description
peripheral devices. Refer Section Operation information related interrupts Section Exception Processing interrupt information.
2.9.3 Autovector (AVEC)
This input signal asserted with during interrupt acknowledge cycle request internal generation vector number. Refer Section Operation more information about automatic vectors.
2.10 STATUS CLOCK SIGNALS
following paragraphs describe signals that provide timing internal processor status.
2.10.1 Processor Status (PST4-PST0)
These outputs indicate internal execution unit status. timing synchronous with MC68060 processor clock (CLK), status have nothing with current transfer. Table lists definition PSTx encodings. encodings $16, $17, indicate present status reflect specific stage pipe. These encodings persist long processor stays indicated state. default encoding indicated none above conditions apply. Most other encodings indicate that instruction last instruction execution stage. These encodings exist only period instruction mutually exclusive. general, PSTx bits indicate following information: PST4 Supervisor Mode PST3 Branch Instruction PST2 Taken Branch Instruction PST1, PST0 Number Instructions Completed that Cycle
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MOTOROLA
Signal Description
Table 2-7. PSTx Encoding
PST4 PST3 PST2 PST1 PST0 Internal Processor Status Continue Execution User Mode Complete Instruction User Mode Complete Instructions User Mode Emulator Mode Entry Exception Processing Complete Taken Branch User Mode Complete Taken Branch Plus Instruction User Mode Cycle Branch Vector, Emulator Entry Exception Complete Taken Branch User Mode Complete Taken Branch Plus Instruction User Mode Complete Taken Branch Plus Instructions User Mode Continue Execution Supervisor Mode Complete Instruction Supervisor Mode Complete Instructions Supervisor Mode Complete Instruction Supervisor Mode Low-Power Stopped State; Waiting Interrupt Reset MC68060 Stopped Waiting Interrupt MC68060 Processing Exception Complete Taken Branch Supervisor Mode Complete Taken Branch Plus Instruction Supervisor Mode Cycle Branch Vector, Exception Processing MC68060 Halted Complete Taken Branch Supervisor Mode Complete Taken Branch Plus Instruction Supervisor Mode Complete Taken Branch Plus Instructions Supervisor Mode
2.10.2 MC68060 Processor Clock (CLK)
synchronous clock MC68060. This signal used internally clock sequence internal logic MC68060 processor qualified with CLKEN clock external signals. Since MC68060 designed static operation, gated lower power dissipation (e.g., during low-power stopped states). Refer Section Operation more information low-power stopped states.
2.10.3 Clock Enable (CLKEN)
This input signal qualifier MC68060 processor clock (CLK) provided support lower frequency MC68060 designs. internal MC68060 interface controller will sample, assert, negate, three-state signals (except which three-
MOTOROLA
M68060 USER'S MANUAL
2-15
Signal Description
state rising edge regardless state CLKEN) only those rising edges which spanned assertion CLKEN. CLKEN used allow external speed MC68060 processor clock which controls internal operations. MC68060 interface controller will detect those rising edges which spanned with negation CLKEN. operate external speed CLK, CLKEN must asserted stable during rising edges which coincide with system clock running frequency MC68060 processor clock. CLKEN must negated stable during other rising edges
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