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QADC QUEUED ANALOG-TO-DIGITAL CONVERTER REFERENCE MANUAL

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc..
QADC QUEUED ANALOG-TO-DIGITAL CONVERTER REFERENCE MANUAL
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Freescale Semiconductor, Inc. PREFACE
This manual describes the capabilities, operation, and functions of the queued analogto-digital converter (QADC). The following conventions are used throughout the manual. Logic level one is the voltage that corresponds to Boolean true (1) state. Logic level zero is the voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one on the bit or bits. To clear a bit or bits means to establish logic level zero on the bit or bits. A signal that is asserted is in its active logic state. An active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. A signal that is negated is in its inactive logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out. A specific bit or signal within a range is referred to by mnemonic and number. For example, ADDR15 is bit 15 of the address bus. A range of bits or signals is referred to by mnemonic and the numbers that define the range. For example, DATA7:0 form the low byte of the data bus.
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QADC REFERENCE MANUAL
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Freescale Semiconductor, Inc. TABLE OF CONTENTS
Paragraph Title SECTION 1 OVERVIEW 1.1 1.2 1.3 Block Diagram .............................................. 1-1 QADC Features ............................................. 1-2 Memory Map ............................................... 1-2 SECTION 2 SIGNAL DESCRIPTIONS 2.1 2.1.1 2.1.2 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Port A Pin Functions ......................................... 2-2 Port A Analog Input Pins .................................. 2-2 Port A Digital Input / Output Pins ............................. 2-2 Port B Pin Functions ......................................... 2-2 Port B Analog Input Pins .................................. 2-2 Port B Digital Input Pins .................................. 2-2 External Trigger Input Pins .................................... 2-3 Multiplexed Address Output Pins ............................... 2-3 Multiplexed Analog Input Pins .................................. 2-3 Voltage Reference Pins ....................................... 2-4 Dedicated Analog Supply Pins ................................. 2-4 External Digital Supply Pin .................................... 2-4 Internal Digital Supply Pins .................................... 2-4 SECTION 3 CONFIGURATION AND CONTROL 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.5 3.5.1 3.5.2 QADC Bus Interface Unit ..................................... 3-1 QADC Bus Accessing ........................................ 3-1 Module Configuration ........................................ 3-3 Low Power Stop Mode ................................... 3-3 Freeze Mode ........................................... 3-4 Supervisor / Unrestricted Address Space ...................... 3-4 Interrupt Arbitration Priority ................................ 3-5 QADC Module Configuration Register ....................... 3-5 QADC Test Register ......................................... 3-6 General-Purpose I / O Port Operation ............................. 3-6 Port Data Register ....................................... 3-6 Port Data Direction Register ............................... 3-7 SECTION 4 EXTERNAL MULTIPLEXING 4.1 4.2 External Multiplexing Operation ................................ 4-1 Module Version Options ...................................... 4-3 Page
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QADC REFERENCE MANUAL
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TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com QADC REFERENCE MANUAL
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MOTOROLA vi
Freescale Semiconductor, Inc. TABLE OF CONTENTS
Paragraph 7.7 7.8 (Continued) Title Page
Conversion Command Word Table ............................. 7-26 Result Word Table .......................................... 7-32 SECTION 8 INTERRUPTS
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Interrupt Operation .......................................... 8-1 Polled and Interrupt-Driven Operation ............................ 8-1 Interrupt Sources ............................................ 8-2 QADC Interrupt Register ...................................... 8-2 Interrupt Priority ............................................. 8-3 Interrupt Arbitration .......................................... 8-4 Interrupt Vectors ............................................ 8-4 Initializing the QADC for Interrupt Driven Operation ................. 8-5 Interrupt Processing Summary ................................. 8-6 SECTION 9 QUEUE PRIORITY EXAMPLES
Queue Priority Schemes ...................................... 9-1 APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B REGISTER SUMMARY
B.1 B.2 B.2.1 B.2.2 B.2.3 B.2.4 B.2.5 B.2.6 B.2.7 B.2.8 B.2.9
Address Map .............................................. B-1 QADC Registers ............................................ B-1 QADC Module Configuration Register ....................... B-1 QADC Test Register ..................................... B-2 QADC Interrupt Register ................................. B-2 Port A / B Data Register ................................... B-3 Port Data Direction Register ............................... B-3 QADC Control Registers ................................. B-4 QADC Status Register ................................... B-7 Conversion Command Word Table ......................... B-8 Result Registers ....................................... B-11 APPENDIX C CONVERSION ACCURACY DEFINITIONS
C.1 C.2 C.3 C.4 C.5 C.6
Transfer Curve ............................................. C-1 Offset Error ................................................ C-2 Quantizing Error ............................................ C-2 Monotonicity ............................................... C-2 Gain Error (Slope Error) ...................................... C-2 Integral Non-Linearity ........................................ C-3
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Paragraph C.7 (Continued) Title Page
Differential Non-Linearity (Related to Monotonicity) ................. C-4 INDEX
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Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS
Figure 1-1 2-1 3-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 C-1 Title Page
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QADC REFERENCE MANUAL
Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS
Figure C-2 C-3 C-4 C-5 (Continued) Title Page
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Freescale Semiconductor, Inc. LIST OF TABLES
Table 1-1 2-1 4-1 5-1 5-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 9-1 9-2 A-1 A-2 A-3 A-4 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 Title Page
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QADC Address Map ............................................... 1-3 Multiplexed Analog Input Channels .................................... 2-3 Analog Input Channels ............................................. 4-3 External Circuit Settling Time (10-Bit Conversions)....................... 5-9 Error Resulting From Input Leakage (IOFF) ............................ 5-10 QADC Clock Programmability ....................................... 7-12 Prescaler Clock High Times ........................................ 7-15 Prescaler Clock Low Times ......................................... 7-16 Queue 1 Operating Modes ......................................... 7-17 Queue 2 Operating Modes ......................................... 7-18 Queue Status.................................................... 7-24 Input Sample Times............................................... 7-30 Nonmultiplexed Channel Assignments and Pin Designations ............... 7-31 Multiplexed Channel Assignments and Pin Designations.................. 7-32 QADC Status Flags and Interrupt Sources.............................. 8-2 Trigger Events .................................................... 9-1 Status Bits....................................................... 9-2 QADC Maximum Ratings ........................................... A-1 QADC DC Electrical Characteristics (Operating) ......................... A-2 QADC AC Electrical Characteristics (Operating) ......................... A-3 QADC Conversion Characteristics (Operating)........................... A-4 QADC Address Map............................................... B-1 Prescaler Clock High Times ......................................... B-4 Prescaler Clock Low Times.......................................... B-5 Queue 1 Operating Modes .......................................... B-5 Queue 2 Operating Modes .......................................... B-6 Queue Status .................................................... B-8 Input Sample Times ............................................... B-9 Nonmultiplexed Channel Assignments and Pin Designations............... B-10 Multiplexed Channel Assignments and Pin Designations .................. B-10
QADC REFERENCE MANUAL
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QADC REFERENCE MANUAL
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SECTION 1 OVERVIEW
The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive approximation converter. A maximum of 16 analog input channels can be supported using internal multiplexing. A maximum of 44 input channels can be supported in the expanded, externally multiplexed mode. The actual number of channels depends upon the number of pins available to the QADC module. 1.1 Block Diagram Figure 1-1 displays the major components of the QADC module. The QADC consists of an analog front-end and a digital control subsystem, which includes an intermodule bus (IMB) interface block.
EXTERNAL TRIGGERS EXTERNAL MUX ADDRESS UP TO 16 ANALOG INPUT PINS REFERENCE INPUTS ANALOG POWER INPUTS
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ANALOG INPUT MULTIPLEXER AND DIGITAL PIN FUNCTIONS
DIGITAL CONTROL
10-BIT ANALOG TO DIGITAL CONVERTER
QUEUE OF 10-BIT CONVERSION COMMAND WORDS (CCW), 40 WORDS
10-BIT RESULT TABLE, 40 WORDS
INTERMODULE BUS INTERFACE
10-BIT TO 16-BIT RESULT ALIGNMENT
QADC BLOCK
Figure 1-1 QADC Block Diagram The analog section includes input pins, an analog multiplexer, and two sample and hold analog circuits. The analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a high-gain comparator. The digital control section contains control logic to sequence the conversion process, channel select logic, and a successive approximation register (SAR). Also included are the periodic / interval timer, control and status registers, the conversion command word (CCW) table RAM, and the result word table RAM.
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QADC REFERENCE MANUAL
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Table 1-1 QADC Address Map
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other information about the operation of the QADC. Refer to APPENDIX B REGISTER SUMMARY for more information. The QADC has three global registers for configuring module operation: the module configuration register (QADCMCR), the interrupt register (QADCINT), and a test register (QADCTEST). The global registers are always defined to be in supervisor-only data space. When the CPU supports the supervisor / user address data space designations, software can establish the global registers to be in supervisor data space and the remaining registers and tables to be in user space. All QADC analog channel / port pins that are not used for analog input channels can be used as digital port pins. Port values are read / written by accessing the port A and B data registers (PORTQA and PORTQB). The digital port pins are specified as inputs or outputs by programming the port data direction register (DDRQA). Only port A uses open drain pull-down output drivers. The remaining four registers in the control register block control the operation of the queuing mechanism, and provide a means of monitoring the operation of the QADC. Control register 0 (QACR0) contains hardware configuration information. Control register 1 (QACR1) is associated with queue 1, and control register 2 (QACR2) is associated with queue 2. The status register (QASR) provides visibility on the status of each queue and the particular conversion that is in progress. Following the register block in the address map is the CCW table. There are 40 words to hold the desired analog conversion sequences. Each CCW is a 16-bit word, with ten implemented bits in four fields. Refer to APPENDIX B REGISTER SUMMARY for more information. The final block of address space belongs to the result word table, which appears in three places in the memory map. Each result word table location holds one 10-bit conversion value. The software selects one of three data formats, which map the 10-bit result onto the 16-bit data bus by reading the address which produces the desired alignment. The first address block presents the result data in right justified format, the second block is presented in left justified signed format, and the third is presented in left justified unsigned format. Refer to APPENDIX B REGISTER SUMMARY for more information.
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SECTION 2 SIGNAL DESCRIPTIONS
The QADC uses a maximum of 21 external pins. There are 16 channel / port pins that can support up to 44 channels when external multiplexing is used (including internal channels). All of the channel pins can also be used as general-purpose digital port pins. In addition, there are also two analog reference pins, two analog submodule power pins, and one VSSE pin for the open drain output drivers on port A. The QADC allows external trigger inputs and the multiplexer outputs to be combined onto some of the channel pins. All of the channel pins are used for at least two functions, depending on the modes in use. The following paragraphs describe QADC pin functions. Figure 2-1 displays the QADC module pins.
INTERNAL DIGITAL POWER (SHARED W / OTHER MODULES) ANALOG POWER ANALOG REFERENCES OUTPUT DRIVER POWER V SSI VDDI VSSA VDDA V RH VRL VSSE
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PORT B ANALOG INPUTS, EXT MUX INPUTS, DIGITAL INPUTS
PORT A ANALOG INPUTS, EXT TRIGGER INPUTS, EXT MUX ADDRESS OUTPUTS, DIGITAL I / O
AN0 / ANW / PQB0 AN1 / ANX / PQB1 AN2 / ANY / PQB2 AN3 / ANZ / PQB3 AN48 / PQB4 AN49 / PQB5 AN50 / PQB6 AN51 / PQB7 AN52 / MA0 / PQA0 AN53 / MA1 / PQA1 AN54 / MA2 / PQA2 AN55 / ETRIG1 / PQA3 AN56 / ETRIG2 / PQA4 AN57 / PQA5 AN58 / PQA6 AN59 / PQA7
PORT B
ANALOG MULTIPLEXER PORT A
ANALOG CONVERTER
DIGITAL RESULTS AND CONTROL
PORT A PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS.
QADC PINOUT
Figure 2-1 QADC Input and Output Signals
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the input of a synchronizer during reads and may be used as general-purpose digital inputs when the applied voltages meet VIH and VIL requirements. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information on voltage requirements. Since port B pins are input only, a data direction register is not necessary. The digital input signal states are read by the software in the lower half of the port data register. Refer to APPENDIX B REGISTER SUMMARY for more information. 2.3 External Trigger Input Pins The QADC uses two external trigger pins (ETRIG2:1). The external trigger inputs are included in two multifunction port A pins (PQA4:3), which are normally used as analog channel input pins. Each of the two input external trigger pins is associated with one of the scan queues, queue 1 and queue 2. When a queue is in an external trigger mode, the corresponding external trigger pin is configured as a digital input and the software programmed input / output direction for the external trigger pins in the data direction register (DDRQA) is ignored. Refer to paragraph 7.7 in SECTION 7 DIGITAL CONTROL for more information. 2.4 Multiplexed Address Output Pins In the non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer which routes the analog signals into the internal A / D converter. In the externally multiplexed mode, the QADC allows automatic channel selection through up to four external 8-to-1 selector chips. The QADC provides a 3-bit multiplexed address output to the external multiplex chips to allow selection of one of eight inputs. The multiplexed address output signals (MA2:0) can be used as multiplex address output bits, or as general I / O. MA2:0 are used as the address inputs for up to four 8-channel multiplexer chips (for example, the MC14051 and the MC74HC4051). Since the MA2:0 pins are digital outputs in the multiplexed mode, the software programmed input / output direction for the multiplex address pins in the data direction register is ignored. Refer to paragraph 7.7 in SECTION 7 DIGITAL CONTROL for more information on the use of multiplexed address output pins in the external multiplexed mode. 2.5 Multiplexed Analog Input Pins In the external multiplexed mode, four of the port B pins are redefined to each represent eight input channels. Refer to Table 2-1. Table 2-1 Multiplexed Analog Input Channels
Multiplexed Analog Input ANw ANx ANy ANz Channels Even numbered channels from 0 to 14 Odd numbered channels from 1 to 15 Even channels from 16 to 30 Odd channels from 17 to 31
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Refer to paragraph 7.7 in SECTION 7 DIGITAL CONTROL for more information.
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2.6 Voltage Reference Pins VRH and VRL are the dedicated input pins for the high and low reference voltages. Separating the reference inputs from the power supply pins allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. 2.7 Dedicated Analog Supply Pins VDDA and VSSA pins supply power to the analog subsystems of the QADC module. Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information.
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2.8 External Digital Supply Pin Each port A pin includes a digital open drain output driver, as well as an analog input signal path and a digital input synchronizer. The VSSE pin provides the ground level for the drivers on the port A pins. Since the QADC output pins have open drain type drivers, a dedicated VDDE pin is not needed. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. 2.9 Internal Digital Supply Pins VDDI and VSSI pins provide the power for the digital portions of the QADC, and for all other digital modules on the microcontroller chip. Since these pins are common to all modules, they are not counted as QADC pins. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information.
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SECTION 3 CONFIGURATION AND CONTROL
The QADC module communicates with other microcontroller modules via the intermodule bus (IMB). The QADC bus interface unit (BIU) coordinates IMB activity with internal QADC bus activity. This section describes the operation of the BIU, IMB read / write accesses to QADC memory locations, module configuration, and general-purpose I / O operation. 3.1 QADC Bus Interface Unit The BIU is designed to act as a slave device on the IMB. The BIU has the following functions: to respond with the appropriate bus cycle termination, and to supply IMB interface timing to all internal module signals. BIU components consist of IMB buffers, address match and module select logic, interrupt and arbitration logic, the BIU state machine, clock prescaler logic, data bus routing logic, and the interface to the internal module data bus. The QADC responds to all IMB operations and signals, allowing byte, word, and long word addressable read and write operations in any addressable space. NOTE Normal accesses to the QADC require two clocks. However, if the CPU tries to access locations that are also accessible by the QADC while the QADC is accessing them, the QADC produces wait states. From one to four CPU wait states may be inserted by the QADC in the process of reading and writing. 3.2 QADC Bus Accessing The QADC permits software access to 8-bit, 16-bit words, and 32-bit long words, at even and odd addresses, however, coherency (ensuring that all samples are taken consecutively in one scan) is not provided for accesses that require more than one bus cycle. For example, if a read of two consecutive word locations in a result area are made, the QADC could change one word in the result area between the bus cycles. There is no holding register for the second word. Refer to paragraph 7.6.3 in SECTION 7 DIGITAL CONTROL for more information on coherency. All read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. These accesses include misaligned and long word accesses. NOTE CPU32 does not support word access or long word access to an odd address. Both of these are considered misaligned accesses. The CPU16 supports misaligned and long word accesses.
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Figure 3-1 shows the three bus cycles which are implemented by the QADC. The following paragraphs describe how the three types of accesses are used, including misaligned and long word accesses.
INTERMODULE BUS
DATA15:8
DATA7:0 00
QADC LOCATION
DATA15:8
DATA7:0
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INTERMODULE BUS
DATA15:8 00
DATA7:0
QADC LOCATION
DATA15:8
DATA7:0
INTERMODULE BUS
DATA15:8
DATA7:0
QADC LOCATION
DATA15:8
DATA7:0
QADC BUS CYC ACC
Figure 3-1 Bus Cycle Accesses Byte accesses to an even address read or write bits 15 through 8 of a QADC location, as shown in the top illustration of Figure 3-1. In the case of write cycles, bits 7 through 0 of the addressed QADC register are not disturbed. In the case of read cycles, the QADC provides zeros to the IMB for bits 7 through 0. Byte accesses to an odd address read or write bits 7 through 0 of a QADC location, as shown in the center illustration of Figure 3-1. In the case of write cycles, bits 15 through 8 of the addressed QADC location are not disturbed. In the case of read cycles, the QADC provides zeros to the IMB for bits 15 through 8. Word accesses to an even address read or write bits 15 through 0 of a QADC location, as shown in the lower illustration of Figure 3-1. A full 16 bits of data is written to and read from the QADC location with each access.
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15 STOP RESET: 0 14 FRZ 0 13 12 11 10 NOT USED 9 8 7 SUPV 1 6 5 NOT USED 4 3 2 IARB 0 0 0 0
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3.5 General-Purpose I / O Port Operation Each of the port pins, when used as a general-purpose input, is conditioned by a synchronizer with an enable feature. The synchronizer is not enabled until the QADC decodes an IMB bus cycle which addresses the port data register to minimize the highcurrent effect of mid-level signals on the inputs used for analog signals. Digital input signals must meet the input low voltage (VIL) or input high voltage (VIH) specifications in APPENDIX A ELECTRICAL CHARACTERISTICS. If an analog input pin does not meet the digital input pin specifications when a digital port read operation occurs, an indeterminate state is read. During a port data register read, the actual value of the pin is reported when its corresponding bit in the data direction register defines the pin to be an input (port A only). When the data direction bit specifies the pin to be an output, the content of the port data register is read. By reading the latch which drives the output pin, software instructions that read data, modify it, and write the result, like bit manipulation instructions, work correctly. When a reduced number of digital port pins are implemented on a particular microcontroller version, the unused bit positions are read as a zero and write operations do not have any effect. There are two special cases to consider for the digital I / O port operation. When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are ignored for the bits corresponding to PQA2:0, the three multiplexed address (MA2:0) output pins. The MA2:0 pins are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs are driven. The data returned during a port data register read is the value of the multiplexed address latches which drive MA2:0, regardless of the data direction setting. Similarly, when an external trigger queue operating mode is selected, the data direction setting for the corresponding pins, PQA3 or PQA4, is ignored. The port pins are forced to be digital inputs for ETRIG1 and / or ETRIG2. The data driven during a port data register read is the actual value of the pin, regardless of the data direction setting. 3.5.1 Port Data Register QADC ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB).
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8 PQA0 U AN52 7 PQB7 U AN51 6 PQB6 U AN50 5 PQB5 U AN49 4 PQB4 U AN48 3 PQB3 U AN3 2 PQB2 U AN2 1 PQB1 U AN1 0 PQB0 U AN0
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15 14 13 12 11 PQA7 PQA6 PQA5 PQA4 PQA3 RESET: U U U U U ANALOG CHANNEL: AN59 AN58 AN57 AN56 AN55 EXTERNAL TRIGGER INPUTS: ETRIG2 ETRIG1 MULTIPLEXED ADDRESS OUTPUTS: MULTIPLEXED ANALOG INPUTS:
10 PQA2 U AN54
9 PQA1 U AN53
MA0 ANz ANy ANx ANw
3.5.2 Port Data Direction Register The port data direction register (DDRQA) is associated with the port A digital I / O pins. The bidirectional pins have somewhat higher leakage and capacitance specifications. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. The software is responsible for ensuring that DDR bits are not set to one on pins used for analog inputs. When the DDR bit is set to one and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. NOTE Caution should be exercised when mixing digital and analog inputs. This should be isolated as much as possible. Rise and fall times should be as large as possible to minimize AC coupling effects. Since port B is input-only, a data direction register is not needed. Therefore, the lower byte of the port data direction register is not implemented. Read operations on the reserved bits return zeros, and writes have no effect.
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DDRQA - Port Data Direction Register
15 14 13 12 11 10 9 8 DDQA7 DDQA6 DDQA5 DDQA4 DDQA3 DDQA2 DDQA1 DDQA0 RESET: 0 0 0 0 0 0 0 0 7 6 5 4 3 RESERVED 0 0 2
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SECTION 4 EXTERNAL MULTIPLEXING
External multiplexer chips concentrate a number of analog signals onto a few inputs to the analog converter. This is helpful in applications that need to convert more analog signals than the A / D converter can normally provide. External multiplexing also puts the multiplex chip closer to the signal source. This minimizes the number of analog signals that need to be shielded due to the close proximity to noisy high speed digital signals at the microcontroller chip. For example, four 8-input multiplexer chips can be put at the connector where the analog signals first arrive on the computer board. As a result, only four analog signals need to be shielded from noise as they approach the microcontroller chip, rather than having to protect 32 analog signals. However, external multiplexer chips may introduce additional noise and errors if not properly utilized. Therefore, it is necessary to maintain low "on" resistance (the impedance of an analog switch when active within a multiplex chip) and insert a low pass filter (R / C) on the input side of the multiplex chip. 4.1 External Multiplexing Operation The QADC can use from one to four external multiplexer chips to expand the number of analog signals that may be converted. Up to 32 analog channels can be converted through external multiplexer selection. The externally multiplexed channels are automatically selected from the channel field of the conversion command word (CCW) table, the same as internally multiplexed channels. Refer to paragraph 7.7 in SECTION 7 DIGITAL CONTROL for additional information on channel number assignments. All of the automatic queue features are available for externally and internally multiplexed channels. The software selects the external multiplexed mode by setting the MUX bit in control register 0 (QACR0). Figure 4-1 shows the maximum configuration of four external multiplexer chips connected to the QADC. The external multiplexer chips select one of eight analog inputs and connect it to one analog output, which becomes an input to the QADC. The QADC provides three multiplexed address signals - MA0, MA1, and MA2, to select one of eight inputs. These inputs are connected to all four external multiplexer chips. The analog output of the four multiplex chips are each connected to four separate QADC inputs - ANw, ANx, ANy, and ANz.
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AN0 AN2 AN4 AN6 AN8 AN10 AN11 AN12
VSSA VDDA V RH VRL VSSE
ANALOG POWER ANALOG REFERENCES
AN1 AN3 AN5 AN7 AN9 AN11 AN13 AN15
MUX AN0 / ANW / PQB0 AN1 / ANX / PQB1 AN2 / ANY / PQB2 AN3 / ANZ / PQB3 AN48 / PQB4 AN49 / PQB5 AN50 / PQB6 AN51 / PQB7 AN52 / MA0 / PQA0 AN53 / MA1 / PQA1 AN54 / MA2 / PQA2 AN55 / ETRIG1 / PQA3 AN56 / ETRIG2 / PQA4 AN57 / PQA5 AN58 / PQA6 AN59 / PQA7
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AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31
EXTERNAL TRIGGERS
PORT A
AN16 AN18 AN20 AN22 AN24 AN26 AN28 AN30
PORT B
ANALOG MULTIPLEXER
ANALOG CONVERTER
DIGITAL RESULTS AND CONTROL
PORT A PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS.
QADC EXT MUX CONN
Figure 4-1 Example of External Multiplexing When the external multiplexed mode is selected, the QADC automatically creates the MA open drain output signals from the channel number in each CCW. The QADC also converts the proper input channel (ANw, ANx, ANy, and ANz) by interpreting the CCW channel number. As a result, up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals. The software simply puts the channel number of externally multiplexed channels into CCWs. Refer to Table 7-9 in SECTION 7 DIGITAL CONTROL which shows the channel numbers for the externally multiplexed channels that are assigned the range of channel 0 to channel 31. Figure 4-1 shows that the three MA signals may also be analog input pins. When external multiplexing is selected, none of the MA pins can be used for analog or digital inputs. They become multiplexed address outputs.
MOTOROLA 4-2
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4.2 Module Version Options The number of available analog channels varies, depending on whether or not external multiplexing is used. A maximum of 16 analog channels are supported by the internal multiplexing circuitry of the converter. Table 4-1 shows the total number of analog input channels supported with zero to four external multiplexer chips. The QADC uses 21 pins which allow a maximum of 41 analog channels to be converted. Table 4-1 Analog Input Channels
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NOTES: 1. The above assumes that the external trigger inputs are shared with two analog input pins. 2. When external multiplexing is used, three input channels become multiplexed address outputs, and for each external multiplexer chip, one input channel becomes a multiplexed analog input.
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MOTOROLA 4-3
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MOTOROLA 4-4
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SECTION 5 PIN CONNECTION CONSIDERATIONS
The QADC requires accurate, noise-free input signals for proper operation. This section discusses the design of external circuitry to maximize QADC performance. 5.1 Analog Reference Pins No A / D converter can be more accurate than its analog reference. Any noise in the reference can result in at least that much error in a conversion. The reference for the QADC, supplied by pins VRH and VRL, should be low-pass filtered from its source to obtain a noise-free, clean signal. In many cases, simple capacitive bypassing may suffice. In extreme cases, inductors or ferrite beads may be necessary if noise or RF energy is present. Series resistance is not advisable since there is an effective DC current requirement from the reference voltage by the internal resistor string in the RC DAC array. External resistance may introduce error in this architecture under certain conditions. Any series devices in the filter network should contain a minimum amount of DC resistance. For accurate conversion results, the analog reference voltages must be within the limits defined by VDDA and VSSA, as explained in the following subsection. 5.2 Analog Power Pins The analog supply pins (VDDA and VSSA) define the limits of the analog reference voltages (VRH and VRL) and of the analog multiplexer inputs. Figure 5-1 is a diagram of the analog input circuitry.
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MOTOROLA 5-1
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SAMPLE AMP 8 CHANNELS TOTAL RC DAC ARRAY
COMPARATOR
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TWO SAMPLE AMPS EXIST ON THE QADC WITH 8 CHANNELS
ON EACH SAMPLE AMP.
QADC 8CH SAMPLE AMP
Figure 5-1 Analog Input Circuitry Since the sample amplifier is powered by VDDA and VSSA, it can accurately transfer input signal levels up to but not exceeding VDDA and down to but not below VSSA. If the input signal is outside of this range, the output from the sample amplifier is clipped. In addition, VRH and VRL must be within the range defined by VDDA and VSSA. As long as VRH is less than or equal to VDDA and VRL is greater than or equal to VSSA and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by VRL and VRH. If VRH is greater than VDDA, the sample amplifier can never transfer a full-scale value. If VRL is less than VSSA, the sample amplifier can never transfer a zero value. Figure 5-2 shows the results of reference voltages outside the range defined by VDDA and VSSA. At the top of the input signal range, VDDA is 10 mV lower than VRH. This results in a maximum obtainable 10-bit conversion value of 3FE. At the bottom of the signal range, VSSA is 15 mV higher than VRL, resulting in a minimum obtainable 10-bit conversion value of three.
MOTOROLA 5-2
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3FF 3FE 3FD 3FC 3FB 10-BIT RESULT 3FA 8 7 6
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QADC CLIPPING
Figure 5-2 Errors Resulting from Clipping 5.3 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding. Generally, digital circuits use bypass capacitors on every VDD / VSS pin pair. This applies to analog subsystems or submodules also. Equally important as bypassing is the distribution of power and ground. Analog supplies should be isolated from digital supplies as much as possible. This necessity stems from the higher performance requirements often associated with analog circuits. Therefore, deriving an analog supply from a local digital supply is not recommended. However, if for economic reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned. For example, an RC low pass filter could be used to isolate the digital and analog supplies when generated by a common regulator. If multiple high precision analog circuits are locally employed (i.e. two A / D converters), the analog supplies should be isolated from each other as sharing supplies introduces the potential for interference between analog circuits. Grounding is the most important factor influencing analog circuit performance in mixed signal systems (or in standalone analog systems). Close attention must be paid not to introduce additional sources of noise into the analog circuitry. Common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately.
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ANALOG POWER SUPPLY
DIGITAL POWER SUPPLY
VDDA VSS VDD
QADC POWER SCHEM
Figure 5-3 Star-Ground at the Point of Power Supply Origin Another approach is to star-point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the non-analog grounds to the analog ground. The small traces are meant only to accommodate DC differences, not AC transients. NOTE This star-point scheme still requires adequate grounding for digital and analog subsystems in addition to the star-point ground.
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Other suggestions for PCB layout in which the QADC is employed include: · Analog ground must be low impedance to all analog ground points in the circuit. · Bypass capacitors should be as close to the power pins as possible. · The analog ground should be isolated from the digital ground. This can be done by cutting a separate ground plane for the analog ground. · Non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground / power points. · Minimum distance for trace runs when possible. 5.4 Accommodating Positive / Negative Stress Conditions Positive or negative stress refers to conditions which exceed nominally defined operating limits. Examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply / reference ranges) or causing currents into or out of the pin which exceed normal limits. QADC specific considerations are voltages greater than VDDA, VRH or less than VSSA applied to an analog input which cause excessive currents into or out of the input. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information on exact magnitudes. Both stress conditions can potentially disrupt conversion results on neighboring inputs. Parasitic devices, associated with CMOS processes, can cause an immediate disruptive influence on neighboring pins. Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate (VSSI / VSSA ground). Under stress conditions, current introduced on an adjacent pin can cause errors on adjacent channels by developing a voltage drop across the adjacent external channel source impedances. Figure 5-4 shows an active parasitic bipolar when an input pin is subjected to negative stress conditions. Positive stress conditions do not activate a similar parasitic device.
NEGATIVE STRESS VOLTAGE + VDD RADJACENT
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RSTRESS IOUT 10K IIN
PIN UNDER STRESS PARASITIC DEVICE ADJACENT PINS
QADC PAR STRESS CONN
Figure 5-4 Input Pin Subjected to Negative Stress The current out of the pin (IOUT) under negative stress is determined by the following equation:
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kR EXTERNAL VOLTAGE
R TO DEVICE
QADC NEG STRESS CONN
Figure 5-5 Voltage Limiting Diodes in a Negative Stress Circuit Another method for minimizing the impact of stress conditions on the QADC is to strategically allocate QADC inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. Finally, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. 5.5 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. Figure 5-6 shows the connection of eight typical analog signal sources to one QADC analog input pin through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC analog input channel is displayed.
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ANALOG SIGNAL SOURCE
FILTERING AND INTERCONNECT
R FILTER2 0.1 µF1
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R SOURCE2
TYPICAL MUX CHIP (MC54HC4051, MC74HC4051, MC54HC4052, MC74HC4052, MC54HC4053, ETC.)
INTERCONNECT
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXIN
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXIN
R MUXOUT
C MUXIN
C SOURCE
R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXOUT
C MUXIN
C SAMPLE
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXIN
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXIN
C SOURCE R SOURCE2
C FILTER R FILTER2 0.1 µF1
C MUXIN
C SOURCE
C FILTER
C MUXIN
R SOURCE2
R FILTER2 0.1 µF1
C SOURCE
C FILTER
NOTES: 1. TYPICAL VALUE 2. RFILTER TYPICALLY 10K-20K.
C SAMPLE
QADC EXT MUX EX
Figure 5-6 External Multiplexing Of Analog Signal Sources
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5.6 Analog Input Pins Analog inputs should have low AC impedance at the pins. Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part. Ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high frequency characteristics). This capacitor has two effects: · It helps attenuate any noise that may exist on the input. · It sources charge during the sample period when the analog signal source is a high-impedance source. Series resistance can be used with the capacitor on an input pin to implement a simple RC filter. The maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input. Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured. (refer to 5.6.2 Error Resulting from Leakage). In some cases, the size of the capacitor at the pin may be very small. Figure 5-7 is a simplified model of an input channel. Refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the QADC.
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EXTERNAL CIRCUIT S1 RF
INTERNAL CIRCUIT MODEL S2 AMP S3 S4
QADC SAMPLE AMP MODEL
Figure 5-7 Electrical Model of an A / D Input Pin In Figure 5-7, RF and CF comprise the external filter circuit. CS is the internal sample capacitor. Each channel has its own capacitor. CS is never precharged it retains the value of the last sample. VI is an internal voltage source used to precharge the DAC
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Filter Capacitor (CF)
1 µF .1 µF .01 µF .001 µF 100 pF
100 760 µs 76 µs 7.6 µs 760 ns 76 ns
Source Resistance (RF) 1 k 10 k 7.6 ms 76 ms 760 µs 7.6 ms 76 µs 760 µs 7.6 µs 76 µs 760 ns 7.6 µs
100 k 760 ms 76 ms 7.6 ms 760 µs 76 µs
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Source Impedance 1 k 10 k 100 k 10 nA - - 0.2 counts Leakage Value (10-bit Conversions) 50 nA 100 nA - - 0.1 counts 0.2 counts 1 count 2 counts 1000 nA 0.2 counts 2 counts 20 counts
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SECTION 6 ANALOG SUBSYSTEM
This section describes the QADC analog subsystem, which includes the front-end analog multiplexer, digital to analog converter (DAC) array, the comparator, and the successive approximation register (SAR). 6.1 Analog-to-Digital Converter Operation The analog subsystem consists of the path from the input pins through the input multiplexing circuitry, into the DAC array, and through the analog comparator. The output of the comparator feeds into the SAR and is considered the boundary between the analog and digital subsystems of the QADC. Figure 6-1 shows a block diagram of the QADC analog submodule.
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CHARGE PUMP AND BIAS
CHAN. MUX 16: 2
EXTERNAL TRIGGERS
PORT PQB INPUT
ADDRESS DECODE
SAMPLE / HOLD PQA0 PQB7 MUX 4: 1 CONTROL REGISTERS AND CONTROL LOGIC SAMPLE / HOLD
SAMPLE TIMER
PERIODIC TIMER
CLOCK PRESCALER
CLOCK BUS INTERFACE
PQB0 VRH DUMMY DAC VRL VDDA COMPARATOR VSSA
DATA 10-BIT RC-DAC CCW TABLE 10-BIT, 40-WORD RAM SUCCESSIVE APPROXIMATION REGISTER RESULT TABLE 10-BIT, 40-WORD RAM ADDRESS DECODE RESULT ALIGNMENT ADDR IMB INTERMODULE BUS
QADC DETAIL BLOCK
Figure 6-1 QADC Module Block Diagram
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6.1.1 Conversion Cycle Times Total conversion time is made up of initial sample time, transfer time, final sample time, and resolution time. Initial sample time refers to the time during which the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. During the transfer period, the sample capacitor is disconnected from the multiplexer, and the stored voltage is buffered and transferred to the RC DAC array. During the final sampling period, the sample capacitor and amplifier are bypassed, and the multiplexer input charges the RC DAC array directly. During the resolution period, the voltage in the RC DAC array is converted to a digital value and stored in the SAR. Initial sample time is fixed at two QCLKs and the transfer time at four QCLKs. Final sample time can be 2, 4, 8, or 16 ADC clock cycles, depending on the value of the IST field in the CCW. Resolution time is ten cycles. Transfer and resolution require a minimum of 18 QCLK clocks (8.6 µs with a 2.1-MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total conversion time is 15.2 µs (with a 2.1-MHz QCLK). Figure 6-2 illustrates the timing for conversions. This diagram assumes a final sampling period of two QCLKs.
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INITIAL SAMPLE TIME 2 CYCLES TRANSFER TIME 4 CYCLES
FINAL SAMPLE TIME N CYCLES: (2, 4, 8, 16)
RESOLUTION TIME 10 CYCLES
SAMPLE AND TRANSFER TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
QADC CONVERSION TIM
Figure 6-2 Conversion Timing 6.1.1.1 Amplifier Bypass Mode Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the CCW, the timing changes to that shown in Figure 6-3. Refer to paragraph 7.7 in SECTION 7 DIGITAL CONTROL for more information on the BYP field. The initial sample time and the transfer time are eliminated reducing the potential conversion time by six QCLKs. However, due to internal RC effects, a minimum final samMOTOROLA 6-2 ANALOG SUBSYSTEM For More Information On This Product, Go to: www.freescale.com QADC REFERENCE MANUAL
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ple time of four QCLKs must be allowed. This results in a savings of four QCLKs. When using the bypass mode, the external circuit should be of low source impedance (typically less than 10 k). Also, the loading effects of the external circuitry by the QADC need to be considered, since the benefits of the sample amplifier are not present.
SAMPLE TIME N CYCLES: (2, 4, 8, 16)
RESOLUTION TIME 10 CYCLES
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SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
QADC BYP CONVERSION TIM
Figure 6-3 Bypass Mode Conversion Timing 6.2 Front-End Analog Multiplexer The internal multiplexer selects one of the 16 analog input pins or one of three special internal reference channels for conversion. The following are the three special channels: · VRH - Reference Voltage High · VRL - Reference Voltage Low · VDDA / 2 - Mid-Analog Supply Voltage The selected input is connected to one side of the DAC capacitor array. The other side of the DAC array is connected to the comparator input. The multiplexer also includes positive and negative stress protection circuitry, which prevents other channels from affecting the current conversion when voltage levels are applied to the other channels. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for specific voltage level limits. 6.3 Digital to Analog Converter Array The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider chain. The array serves two purposes: · The array holds the sampled input voltage during conversion. · The resistor-capacitor array provides the mechanism for the successive approximation A / D conversion. · Resolution begins with the most significant bit (MSB) and works down to the least significant bit (LSB). The switching sequence is controlled by the digital logic.
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6.4 Comparator The comparator is used during the approximation process to sense whether the digitally selected arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The comparator output feeds into the SAR which accumulates the A / D conversion result sequentially, starting with the MSB. 6.5 Successive Approximation Register The input of the successive approximation register (SAR) is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time, starting with the MSB. After accumulating the 10 bits of the conversion result, the SAR data is transferred to the appropriate result location, where it may be read from the IMB by user software.
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MOTOROLA 6-4
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SECTION 7 DIGITAL CONTROL
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Figure 7-1 shows the CCW format and an example of using pause to create subqueues. Queue 1 is shown with four CCWs in each subqueue and queue 2 has two CCWs in each subqueue.
CONVERSION COMMAND WORD (CCW) TABLE 0 0 0 1 0 0 0 1 PAUSE PAUSE BEGIN QUEUE 1 CHANNEL SELECT, SAMPLE, HOLD, AND A / D CONVERSION RESULT WORD TABLE 00
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QADC CQP
END OF QUEUE 1 BEGIN QUEUE 2 PAUSE PAUSE PAUSE
Figure 7-1 QADC Queue Operation With Pause The queue operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the subqueues within queue 1. Similarly, the queue operating mode for queue 2 determines the type of trigger event required to execute each of the subqueues within queue 2. For example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there are six subqueues within queue 1, a separate rising edge is required on the external trigger pin after every pause to begin the execution of each subqueue (refer to Figure 7-1). Refer to 7.3 Scan Modes for more information on different scan modes. The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue. Once a subqueue is initiated, each CCW is executed sequentially until the last CCW in the subqueue is executed and the pause state is entered.
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· The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6. · The pause is in CCW39. · During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21. Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW and the pause flag is not set. The QADC sets the completion flag and the queue status becomes idle. Examples of this situation are: · The pause bit is set in CCW10 and EOQ is programmed into CCW10. · During queue 1 operation, the pause bit set in CCW32, which is also BQ2.
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The interval timer generates a trigger event whenever the time interval elapses. The trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. Once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to count again. The interval timer single-scan mode can be used in applications which need coherent results, for example: · When it is necessary that all samples are guaranteed to be taken during the same scan of the analog pins. · When the interrupt rate in the periodic timer continuous-scan mode would be too high. · In sensitive battery applications, where the single-scan mode uses less power than the software initiated continuous-scan mode.
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7.3.3 Continuous-Scan Modes When the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is selected. By programming the MQ1 field in QACR1, the following software initiated modes can be selected for queue 1: · Software initiated continuous-scan mode · External trigger rising edge continuous-scan mode · External trigger falling edge continuous-scan mode In addition to the above modes, queue 2 can also be programmed for the periodic timer continuous-scan mode, where a scan is initiated at a selectable time interval using the on-chip periodic / interval timer. The queue operating mode for queue 2 is selected by the MQ2 field in QACR2. When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. As soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. In the case of the software initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other single-scan queue operating modes, the selected trigger event must occur before the queue can start. A trigger overrun is recorded if a trigger event occurs during queue execution i