QADC QUEUED ANALOG-TO-DIGITAL CONVERTER REFERENCE MANUAL Motorola
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QADC QUEUED ANALOG-TO-DIGITAL CONVERTER REFERENCE MANUAL
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA Motorola logo registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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Freescale Semiconductor, Inc. PREFACE
This manual describes capabilities, operation, functions queued analogto-digital converter (QADC). following conventions used throughout manual. Logic level voltage that corresponds Boolean true state. Logic level zero voltage that corresponds Boolean false state. bits means establish logic level bits. clear bits means establish logic level zero bits. signal that asserted active logic state. active signal changes from logic level logic level zero when asserted, active high signal changes from logic level zero logic level one. signal that negated inactive logic state. active signal changes from logic level zero logic level when negated, active high signal changes from logic level logic level zero. means least significant bits. means most significant bits. References high bytes spelled out. specific signal within range referred mnemonic number. example, ADDR15 address bus. range bits signals referred mnemonic numbers that define range. example, DATA[7:0] form byte data bus.
QADC REFERENCE MANUAL
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Freescale Semiconductor, Inc. TABLE CONTENTS
Paragraph Title SECTION OVERVIEW Block Diagram QADC Features Memory SECTION SIGNAL DESCRIPTIONS 2.1.1 2.1.2 2.2.1 2.2.2 Port Functions Port Analog Input Pins Port Digital Input/Output Pins Port Functions Port Analog Input Pins Port Digital Input Pins External Trigger Input Pins Multiplexed Address Output Pins Multiplexed Analog Input Pins Voltage Reference Pins Dedicated Analog Supply Pins External Digital Supply Internal Digital Supply Pins SECTION CONFIGURATION CONTROL 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.5.1 3.5.2 QADC Interface Unit QADC Accessing Module Configuration Power Stop Mode Freeze Mode Supervisor/Unrestricted Address Space Interrupt Arbitration Priority QADC Module Configuration Register QADC Test Register General-Purpose Port Operation Port Data Register Port Data Direction Register SECTION EXTERNAL MULTIPLEXING External Multiplexing Operation Module Version Options Page
QADC REFERENCE MANUAL
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Paragraph (Continued) Title SECTION CONNECTION CONSIDERATIONS 5.6.1 5.6.2 Analog Reference Pins Analog Power Pins Analog Supply Filtering Grounding Accommodating Positive/Negative Stress Conditions Analog Input Considerations Analog Input Pins Settling Time External Circuit Error Resulting from Leakage 5-10 SECTION ANALOG SUBSYSTEM 6.1.1 6.1.1.1 Analog-to-Digital Converter Operation Conversion Cycle Times Amplifier Bypass Mode Conversion Timing Front-End Analog Multiplexer Digital Analog Converter Array Comparator Successive Approximation Register SECTION DIGITAL CONTROL 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.6.1 7.6.2 7.6.3 7.6.4 Queue Priority Boundary Conditions Scan Modes Disabled Mode Reserved Mode Single-Scan Modes Software Initiated Single-Scan Mode External Trigger Single-Scan Mode Interval Timer Single-Scan Mode Continuous-Scan Modes Software Initiated Continuous-Scan Mode External Trigger Continuous-Scan Mode Periodic Timer Continuous-Scan Mode QADC Clock (QCLK) Generation Periodic/Interval Timer 7-13 Control Status Registers 7-14 Control Register 7-14 Control Register 7-16 Control Register 7-17 Status Register 7-20
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Freescale Semiconductor, Inc. TABLE CONTENTS
Paragraph (Continued) Title Page
Conversion Command Word Table 7-26 Result Word Table 7-32 SECTION INTERRUPTS
Interrupt Operation Polled Interrupt-Driven Operation Interrupt Sources QADC Interrupt Register Interrupt Priority Interrupt Arbitration Interrupt Vectors Initializing QADC Interrupt Driven Operation Interrupt Processing Summary SECTION QUEUE PRIORITY EXAMPLES
Queue Priority Schemes APPENDIX ELECTRICAL CHARACTERISTICS APPENDIX REGISTER SUMMARY
B.2.1 B.2.2 B.2.3 B.2.4 B.2.5 B.2.6 B.2.7 B.2.8 B.2.9
Address QADC Registers QADC Module Configuration Register QADC Test Register QADC Interrupt Register Port Data Register Port Data Direction Register QADC Control Registers QADC Status Register Conversion Command Word Table Result Registers B-11 APPENDIX CONVERSION ACCURACY DEFINITIONS
Transfer Curve Offset Error Quantizing Error Monotonicity Gain Error (Slope Error) Integral Non-Linearity
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QADC REFERENCE MANUAL
Freescale Semiconductor, Inc. TABLE CONTENTS
Paragraph (Continued) Title Page
Differential Non-Linearity (Related Monotonicity) INDEX
MOTOROLA viii
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Freescale Semiconductor, Inc. LIST ILLUSTRATIONS
Figure 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 Title Page
QADC Block Diagram QADC Input Output Signals Cycle Accesses Example External Multiplexing Analog Input Circuitry Errors Resulting from Clipping Star-Ground Point Power Supply Origin Input Subjected Negative Stress Voltage Limiting Diodes Negative Stress Circuit External Multiplexing Analog Signal Sources Electrical Model Input QADC Module Block Diagram Conversion Timing Bypass Mode Conversion Timing QADC Queue Operation With Pause QADC Clock Subsystem Functions 7-10 QADC Clock Programmability Examples 7-12 Queue Status Transition 7-25 QADC Conversion Queue Operation 7-27 QADC Interrupt Flow Diagram QADC Interrupt Vector Format Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Priority Situation Freeze Situation Freeze Situation Freeze Situation Freeze Situation Freeze Situation Freeze Situation Freeze Situation Freeze Situation 9-10 Transfer Curve Ideal 10-Bit Converter .C-1
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QADC REFERENCE MANUAL
Freescale Semiconductor, Inc. LIST ILLUSTRATIONS
Figure (Continued) Title Page
Transfer Curve Non-Monotonic 10-Bit Converter .C-2 Transfer Curve 10-Bit Converter with Gain Error .C-3 Transfer Curve 10-Bit Converter With Integral .C-4 Transfer Curve 10-Bit Converter With Differential Linearity .C-5
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Freescale Semiconductor, Inc. LIST TABLES
Table Title Page
QADC Address Multiplexed Analog Input Channels Analog Input Channels External Circuit Settling Time (10-Bit Conversions). Error Resulting From Input Leakage (IOFF) 5-10 QADC Clock Programmability 7-12 Prescaler Clock High Times 7-15 Prescaler Clock Times 7-16 Queue Operating Modes 7-17 Queue Operating Modes 7-18 Queue Status. 7-24 Input Sample Times. 7-30 Nonmultiplexed Channel Assignments Designations 7-31 Multiplexed Channel Assignments Designations. 7-32 QADC Status Flags Interrupt Sources. Trigger Events Status Bits. QADC Maximum Ratings QADC Electrical Characteristics (Operating) QADC Electrical Characteristics (Operating) QADC Conversion Characteristics (Operating). QADC Address Map. Prescaler Clock High Times Prescaler Clock Times. Queue Operating Modes Queue Operating Modes Queue Status Input Sample Times Nonmultiplexed Channel Assignments Designations. B-10 Multiplexed Channel Assignments Designations B-10
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QADC REFERENCE MANUAL
SECTION OVERVIEW
queued analog-to-digital converter (QADC) 10-bit, unipolar, successive approximation converter. maximum analog input channels supported using internal multiplexing. maximum input channels supported expanded, externally multiplexed mode. actual number channels depends upon number pins available QADC module. Block Diagram Figure displays major components QADC module. QADC consists analog front-end digital control subsystem, which includes intermodule (IMB) interface block.
EXTERNAL TRIGGERS EXTERNAL ADDRESS ANALOG INPUT PINS REFERENCE INPUTS ANALOG POWER INPUTS
ANALOG INPUT MULTIPLEXER DIGITAL FUNCTIONS
DIGITAL CONTROL
10-BIT ANALOG DIGITAL CONVERTER
QUEUE 10-BIT CONVERSION COMMAND WORDS (CCW), WORDS
10-BIT RESULT TABLE, WORDS
INTERMODULE INTERFACE
10-BIT 16-BIT RESULT ALIGNMENT
QADC BLOCK
Figure QADC Block Diagram analog section includes input pins, analog multiplexer, sample hold analog circuits. analog conversion performed digital-to-analog converter (DAC) resistor-capacitor array high-gain comparator. digital control section contains control logic sequence conversion process, channel select logic, successive approximation register (SAR). Also included periodic/interval timer, control status registers, conversion command word (CCW) table RAM, result word table RAM.
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interface unit (BIU) allows QADC operate with applications software through environment. QADC Features Sample hold analog input channels using internal multiplexing Directly supports four external multiplexers (for example, MC14051) total input channels with internal external multiplexing Programmable input sample time various source impedances conversion command queues variable length Sub-queues possible using pause mechanism Queue complete pause software interrupts available both queues Automated queue modes initiated External trigger Periodic/interval timer, within QADC module Software command Single-scan continuous-scan queues result registers Output data readable three formats: Right-justified unsigned Left-justified signed Left-justified unsigned Unused analog channels used digital ports Memory QADC occupies bytes, words, address space. Nine words control, port, status registers, words table, words result word table which occupy address locations because result data readable three data alignment formats. remaining words reserved expansion. Table displays QADC memory map. Each register address Table consists 15-bit base address plus 9-bit offset. offset represents nine order bits register address. "$####" represents 15-bit base address plus high order offset. (For example, both LJUR RJUR registers represented $####B0-$####FE, even though they represent different addresses since each register different most significant their offset). precise locations these registers, refer appropriate microcontroller unit (MCU) manual. column labeled "Access" specifies which address space designated supervisor data space unrestricted data space. Remember that determined bit.
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Table QADC Address
Access S/U2 Address $####00 $####02 $####04 $####06 $####08 $####0A $####0C $####0E $####10 $####12- $####2E $####30- $####7E $####80- $####AE $####B0- $####FE $####00- $####2E $####30- $####7E $####80- $####AE $####B0- $####FE Offset $000 $002 $004 $006 $008 $00A $00C $00E $010 $012- $02E $030- $07E $080- $0AE $0B0- $0FE $100- $12E $130- $17E $180- $1AE $1B0- $1FE MODULE CONFIGURATION REGISTER (QADCMCR) TEST REGISTER (QADCTEST) INTERRUPT REGISTER (QADCINT) PORT DATA (PORTQA) PORT DATA (PORTQB) PORT DATA DIRECTION REGISTER (DDRQA) CONTROL REGISTER (QACR0) CONTROL REGISTER (QACR1) CONTROL REGISTER (QACR2) STATUS REGISTER (QASR) RESERVED CONVERSION COMMAND WORD (CCW) TABLE RESERVED RESULT WORD TABLE RIGHT JUSTIFIED, UNSIGNED RESULT REGISTER (RJURR) RESERVED RESULT WORD TABLE LEFT JUSTIFIED, SIGNED RESULT REGISTER (LJSRR) RESERVED RESULT WORD TABLE LEFT JUSTIFIED, UNSIGNED RESULT REGISTER (LJURR)
NOTES: Supervisor only Unrestricted supervisor depending state SUPV QADCMCR.
Access supervisor-only data space permitted only when software operating supervisor access mode. Assignable data space either restricted supervisor-only access unrestricted both supervisor user data space addresses. SUPV module configuration register designates assignable space supervisor unrestricted. Attempts read supervisor-only data space when supervisor access mode causes value $0000 returned. Attempts read assignable data space unrestricted access mode when space programmed supervisor space causes value $FFFF returned. Attempts write supervisor-only supervisor-assigned data space when unrestricted access mode effect. CPU32 indicates supervisor user space access with function code signal bus. CPU16 does support supervisor/user space selection, always supervisor access mode. such cases, SUPV meaning effect. first block address contains nine words used control, status, port, test information. control registers permit software initialize QADC desired configuration queue operating mode. Also included status bits that software read identify interrupt source determine
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other information about operation QADC. Refer APPENDIX REGISTER SUMMARY more information. QADC three global registers configuring module operation: module configuration register (QADCMCR), interrupt register (QADCINT), test register (QADCTEST). global registers always defined supervisor-only data space. When supports supervisor/user address data space designations, software establish global registers supervisor data space remaining registers tables user space. QADC analog channel/port pins that used analog input channels used digital port pins. Port values read/written accessing port data registers (PORTQA PORTQB). digital port pins specified inputs outputs programming port data direction register (DDRQA). Only port uses open drain pull-down output drivers. remaining four registers control register block control operation queuing mechanism, provide means monitoring operation QADC. Control register (QACR0) contains hardware configuration information. Control register (QACR1) associated with queue control register (QACR2) associated with queue status register (QASR) provides visibility status each queue particular conversion that progress. Following register block address table. There words hold desired analog conversion sequences. Each 16-bit word, with implemented bits four fields. Refer APPENDIX REGISTER SUMMARY more information. final block address space belongs result word table, which appears three places memory map. Each result word table location holds 10-bit conversion value. software selects three data formats, which 10-bit result onto 16-bit data reading address which produces desired alignment. first address block presents result data right justified format, second block presented left justified signed format, third presented left justified unsigned format. Refer APPENDIX REGISTER SUMMARY more information.
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SECTION SIGNAL DESCRIPTIONS
QADC uses maximum external pins. There channel/port pins that support channels when external multiplexing used (including internal channels). channel pins also used general-purpose digital port pins. addition, there also analog reference pins, analog submodule power pins, VSSE open drain output drivers port QADC allows external trigger inputs multiplexer outputs combined onto some channel pins. channel pins used least functions, depending modes use. following paragraphs describe QADC functions. Figure displays QADC module pins.
INTERNAL DIGITAL POWER (SHARED OTHER MODULES) ANALOG POWER ANALOG REFERENCES OUTPUT DRIVER POWER VDDI VSSA VDDA VSSE
PORT ANALOG INPUTS, INPUTS, DIGITAL INPUTS
PORT ANALOG INPUTS, TRIGGER INPUTS, ADDRESS OUTPUTS, DIGITAL I/O*
AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 AN51/PQB7 AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN58/PQA6 AN59/PQA7
PORT
QADC
ANALOG MULTIPLEXER PORT
ANALOG CONVERTER
DIGITAL RESULTS CONTROL
PORT PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS.
QADC PINOUT
Figure QADC Input Output Signals
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Port Functions eight port pins used analog inputs, bidirectional 8-bit digital input/output port. Refer following paragraphs more information. 2.1.1 Port Analog Input Pins When used analog inputs, eight port pins referred AN[59:52]. digital output drivers associated with port analog characteristics port different from those port Refer APPENDIX REGISTER SUMMARY more information analog signal characteristics. analog signal input pins used least other purpose. 2.1.2 Port Digital Input/Output Pins Port pins referred PQA[7:0] when used bidirectional 8-bit digital input/ output port. These eight pins used general-purpose digital input signals digital open drain pull-down output signals. Port pins connected digital input synchronizer during reads used general purpose digital inputs when applied voltages meet high voltage input (VIH) voltage input (VIL) requirements. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information voltage requirements. Each port configured input output programming upper half port data direction register (DDRQA). digital input signal states read software upper half port data register when port data direction register specifies that pins inputs. digital data port data register driven onto port pins when corresponding port data direction register specifies output. Refer APPENDIX REGISTER SUMMARY more information. Since outputs open drain drivers minimize effects analog function pins), active external pull-up provisions must made when output used drive another integrated circuit. Port Functions eight port pins used analog inputs, 8-bit digital input only port. Refer following paragraphs more information. 2.2.1 Port Analog Input Pins When used analog inputs, eight port pins referred AN[51:48]/ AN[3:0]. Since port functions analog digital input only, analog characteristics different from those port Refer APPENDIX ELECTRICAL CHARACTERISTICS more information analog signal characteristics. analog signal input pins used least other purpose. 2.2.2 Port Digital Input Pins Port pins referred PQB[7:0] when used 8-bit digital input only port. addition functioning analog input pins, port pins also connected
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input synchronizer during reads used general-purpose digital inputs when applied voltages meet requirements. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information voltage requirements. Since port pins input only, data direction register necessary. digital input signal states read software lower half port data register. Refer APPENDIX REGISTER SUMMARY more information. External Trigger Input Pins QADC uses external trigger pins (ETRIG[2:1]). external trigger inputs included multifunction port pins (PQA[4:3]), which normally used analog channel input pins. Each input external trigger pins associated with scan queues, queue queue When queue external trigger mode, corresponding external trigger configured digital input software programmed input/output direction external trigger pins data direction register (DDRQA) ignored. Refer paragraph SECTION DIGITAL CONTROL more information. Multiplexed Address Output Pins non-multiplexed mode, channel pins connected internal multiplexer which routes analog signals into internal converter. externally multiplexed mode, QADC allows automatic channel selection through four external 8-to-1 selector chips. QADC provides 3-bit multiplexed address output external multiplex chips allow selection eight inputs. multiplexed address output signals (MA[2:0]) used multiplex address output bits, general I/O. MA[2:0] used address inputs four 8-channel multiplexer chips (for example, MC14051 MC74HC4051). Since MA[2:0] pins digital outputs multiplexed mode, software programmed input/output direction multiplex address pins data direction register ignored. Refer paragraph SECTION DIGITAL CONTROL more information multiplexed address output pins external multiplexed mode. Multiplexed Analog Input Pins external multiplexed mode, four port pins redefined each represent eight input channels. Refer Table 2-1. Table Multiplexed Analog Input Channels
Multiplexed Analog Input Channels Even numbered channels from numbered channels from Even channels from channels from
Refer paragraph SECTION DIGITAL CONTROL more information.
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Voltage Reference Pins dedicated input pins high reference voltages. Separating reference inputs from power supply pins allows additional external filtering, which increases reference voltage precision stability, subsequently contributes higher degree conversion accuracy. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information. Dedicated Analog Supply Pins VDDA VSSA pins supply power analog subsystems QADC module. Dedicated power required isolate sensitive analog circuitry from normal levels noise present digital power supply. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information.
External Digital Supply Each port includes digital open drain output driver, well analog input signal path digital input synchronizer. VSSE provides ground level drivers port pins. Since QADC output pins have open drain type drivers, dedicated VDDE needed. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information. Internal Digital Supply Pins VDDI VSSI pins provide power digital portions QADC, other digital modules microcontroller chip. Since these pins common modules, they counted QADC pins. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information.
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SECTION CONFIGURATION CONTROL
QADC module communicates with other microcontroller modules intermodule (IMB). QADC interface unit (BIU) coordinates activity with internal QADC activity. This section describes operation BIU, read/ write accesses QADC memory locations, module configuration, general-purpose operation. QADC Interface Unit designed slave device IMB. following functions: respond with appropriate cycle termination, supply interface timing internal module signals. components consist buffers, address match module select logic, interrupt arbitration logic, state machine, clock prescaler logic, data routing logic, interface internal module data bus. QADC responds operations signals, allowing byte, word, long word addressable read write operations addressable space. NOTE Normal accesses QADC require clocks. However, tries access locations that also accessible QADC while QADC accessing them, QADC produces wait states. From four wait states inserted QADC process reading writing. QADC Accessing QADC permits software access 8-bit, 16-bit words, 32-bit long words, even addresses, however, coherency (ensuring that samples taken consecutively scan) provided accesses that require more than cycle. example, read consecutive word locations result area made, QADC could change word result area between cycles. There holding register second word. Refer paragraph 7.6.3 SECTION DIGITAL CONTROL more information coherency. read write accesses that require more than 16-bit access complete occur more independent cycles. These accesses include misaligned long word accesses. NOTE CPU32 does support word access long word access address. Both these considered misaligned accesses. CPU16 supports misaligned long word accesses.
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Figure shows three cycles which implemented QADC. following paragraphs describe three types accesses used, including misaligned long word accesses.
INTERMODULE
DATA[15:8]
DATA[7:0]
QADC LOCATION
DATA[15:8]
DATA[7:0]
8-BIT ACCESS EVEN ADDRESS (ISIZ
INTERMODULE
DATA[15:8]
DATA[7:0]
QADC LOCATION
DATA[15:8]
DATA[7:0]
8-BIT ACCESS ADDRESS (ISIZ ISIZ
INTERMODULE
DATA[15:8]
DATA[7:0]
QADC LOCATION
DATA[15:8]
DATA[7:0]
16-BIT ALIGNED ACCESS (ISIZ
QADC
Figure Cycle Accesses Byte accesses even address read write bits through QADC location, shown illustration Figure 3-1. case write cycles, bits through addressed QADC register disturbed. case read cycles, QADC provides zeros bits through Byte accesses address read write bits through QADC location, shown center illustration Figure 3-1. case write cycles, bits through addressed QADC location disturbed. case read cycles, QADC provides zeros bits through Word accesses even address read write bits through QADC location, shown lower illustration Figure 3-1. full bits data written read from QADC location with each access.
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Word accesses address require cycles; half different 16-bit QADC locations accessed. first cycle treated QADC 8-bit read write address. second cycle 8-bit read write even address. QADC address space organized into 16-bit even address locations, 16-bit read write address obtains provides lower half QADC location, upper half following QADC location. Long word (32-bit) accesses even address require cycles complete access, full QADC locations accessed. first cycle reads writes addressed 16-bit QADC location second cycle reads writes following 16-bit location. Long word accesses address require three cycles. Portions three different QADC locations accessed. first cycle treated QADC 8-bit access address, second cycle 16-bit aligned access, third cycle 8-bit access even address. QADC address space organized into 16-bit even address locations, 32-bit read write address provides lower half QADC location, full 16-bit content following QADC location, upper half third QADC location. Module Configuration module configuration register (QADCMCR) contains parameters which allow QADC interface with other modules. register defines freeze stop mode operation, supervisor-only access protection, QADC software interrupt arbitration priority number. implemented fields read written. Unimplemented locations read zero writes have effect. They typically written once when software initializes QADC, changed afterwards. 3.3.1 Power Stop Mode When STOP QADCMCR set, clock signal converter disabled, effectively turning analog circuitry. This results static, power consumption, idle condition. stop mode aborts conversion sequence progress. Because bias currents analog circuits turned stop mode, QADC requires some recovery time (TSR APPENDIX ELECTRICAL CHARACTERISTICS) stabilize analog circuits after stop enable cleared. stop mode, state machine logic shut down, QADCMCR, interrupt register (QADCINT), test register (QADCTEST) fully accessible reset. data direction register (DDRQA), port data register (PORTQA/PORTQB), control register (QACR0) reset read-only accessible. reset accessible. Control register (QACR1), control register (QACR2), status register (QASR) reset read-only accessible. addition, QADC clock (QCLK) periodic/interval timer held reset during stop mode. STOP clear, stop mode disabled.
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3.3.2 Freeze Mode Freeze mode occurs when background debug mode enabled device integration module breakpoint encountered. This indicated assertion internal FREEZE line IMB. QADCMCR determines whether QADC responds internal FREEZE signal assertion. Freeze very useful when debugging application. When set, QADC finishes current conversion then freezes. Depending when asserted, there three possible queue "freeze" scenarios: When queue executing, QADC freezes immediately. When queue executing, QADC completes current conversion then freezes. during execution current conversion, queue operating mode active queue changed, queue abort occurs, QADC freezes immediately. When QADC enters freeze mode while queue active, current location queue pointer saved. During freeze, analog clock held reset clocked. Although QCLK unaffected, periodic/interval timer held reset. External trigger events that occur during freeze mode recorded. remains active allow access QADC registers RAM. Although QADC saves pointer next current queue, software force QADC execute different writing queue operating modes normal operation. QADC looks queue operating modes, current queue pointer, pending trigger events decide which execute. clear, internal FREEZE signal ignored. 3.3.3 Supervisor/Unrestricted Address Space QADC memory divided into segments: supervisor-only data space assignable data space. Access supervisor-only data space permitted only when software operating supervisor access mode. Assignable data space either restricted supervisor-only access unrestricted both supervisor user data space accesses. SUPV QADCMCR designates assignable space supervisor unrestricted. Attempts read supervisor-only data space when supervisor access mode causes value $0000 returned. Attempts read assignable data space unrestricted access mode when space programmed supervisor space causes value $FFFF returned. Attempts write supervisor-only supervisor-assigned data space when unrestricted access mode effect. indicates supervisor user space access with function code bits (FC[2:0]) bus.
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NOTE Some CPUs support supervisor/user space selection, always supervisor access mode. such cases, SUPV meaning effect. supervisor-only data space segment contains QADC global registers, which include QADCMCR, QADCTEST, QADCINT. supervisor/unrestricted space designation table, result word table, remaining QADC registers programmable. 3.3.4 Interrupt Arbitration Priority Each module that generate interrupts, including QADC, IARB (interrupt arbitration number) field QADCMCR. Each IARB field must have different value. During interrupt acknowledge cycle, IARB permits arbitration among simultaneous interrupts same priority level. reset value IARB QADCMCR This prevents QADC interrupts from being discarded. Initialization software must IARB field lower value range (highest priority) (lowest priority) lower priority interrupts arbitrated. Refer SECTION INTERRUPTS more information. 3.3.5 QADC Module Configuration Register QADCMCR contains fields bits that control freeze stop modes determines privilege level required access most registers. also contains IARB field. QADCMCR Module Configuration Register
STOP RESET: USED SUPV USED IARB
$####00
STOP Stop Enable Disable stop mode. Enable stop mode. Freeze Enable Ignores internal FREEZE signal. Finish current conversion, then freeze SUPV Supervisor/Unrestricted Data Space Only module configuration register, test register, interrupt register designated supervisor-only data space. Access other locations unrestricted. QADC registers tables designated supervisor-only data space.
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IARB[3:0] Interrupt Arbitration Number IARB determines QADC interrupt arbitration priority. IARB field assigned value from %0001 (lowest priority) %1111 (highest value). Refer SECTION INTERRUPTS more information. QADC Test Register QADCTEST QADC Test Register QADCTEST used only during factory testing MCU. $####02
General-Purpose Port Operation Each port pins, when used general-purpose input, conditioned synchronizer with enable feature. synchronizer enabled until QADC decodes cycle which addresses port data register minimize highcurrent effect mid-level signals inputs used analog signals. Digital input signals must meet input voltage (VIL) input high voltage (VIH) specifications APPENDIX ELECTRICAL CHARACTERISTICS. analog input does meet digital input specifications when digital port read operation occurs, indeterminate state read. During port data register read, actual value reported when corresponding data direction register defines input (port only). When data direction specifies output, content port data register read. reading latch which drives output pin, software instructions that read data, modify write result, like manipulation instructions, work correctly. When reduced number digital port pins implemented particular microcontroller version, unused positions read zero write operations have effect. There special cases consider digital port operation. When (externally multiplexed) QACR0, data direction register settings ignored bits corresponding PQA[2:0], three multiplexed address (MA[2:0]) output pins. MA[2:0] pins forced digital outputs, regardless data direction setting, multiplexed address outputs driven. data returned during port data register read value multiplexed address latches which drive MA[2:0], regardless data direction setting. Similarly, when external trigger queue operating mode selected, data direction setting corresponding pins, PQA3 PQA4, ignored. port pins forced digital inputs ETRIG1 and/or ETRIG2. data driven during port data register read actual value pin, regardless data direction setting. 3.5.1 Port Data Register QADC ports accessed through 8-bit port data registers (PORTQA PORTQB).
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Port pins referred PQA[7:0] when used bidirectional 8-bit input/output port that used general-purpose digital input signals digital open drain pull-down output signals. Port also used analog inputs (AN[59:52], external trigger inputs (ETRIG[2:1]), external multiplexer address outputs (MA[2:0]). Port pins referred PQB[7:0] when used input-only 8-bit digital port that used general-purpose digital input signals. Data PQB[7:0] accessed lower half QPDR. Port also used nonmultiplexed (AN[51:48]/AN[3:0]) multiplexed (ANz, ANy, ANx, ANw) analog inputs. PORTQA PORTQB unaffected reset. PORTQA Port Data Register PORTQB Port Data Register $####06 $####07
PQA0 AN52 PQB7 AN51 PQB6 AN50 PQB5 AN49 PQB4 AN48 PQB3 PQB2 PQB1 PQB0
PQA7 PQA6 PQA5 PQA4 PQA3 RESET: ANALOG CHANNEL: AN59 AN58 AN57 AN56 AN55 EXTERNAL TRIGGER INPUTS: ETRIG2 ETRIG1 MULTIPLEXED ADDRESS OUTPUTS: MULTIPLEXED ANALOG INPUTS:
PQA2 AN54
PQA1 AN53
3.5.2 Port Data Direction Register port data direction register (DDRQA) associated with port digital pins. bidirectional pins have somewhat higher leakage capacitance specifications. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information. this register configures corresponding output. this register cleared zero configures corresponding input. software responsible ensuring that bits pins used analog inputs. When selected analog conversion, voltage sampled that output digital driver influenced load. NOTE Caution should exercised when mixing digital analog inputs. This should isolated much possible. Rise fall times should large possible minimize coupling effects. Since port input-only, data direction register needed. Therefore, lower byte port data direction register implemented. Read operations reserved bits return zeros, writes have effect.
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DDRQA Port Data Direction Register
DDQA7 DDQA6 DDQA5 DDQA4 DDQA3 DDQA2 DDQA1 DDQA0 RESET: RESERVED
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SECTION EXTERNAL MULTIPLEXING
External multiplexer chips concentrate number analog signals onto inputs analog converter. This helpful applications that need convert more analog signals than converter normally provide. External multiplexing also puts multiplex chip closer signal source. This minimizes number analog signals that need shielded close proximity noisy high speed digital signals microcontroller chip. example, four 8-input multiplexer chips connector where analog signals first arrive computer board. result, only four analog signals need shielded from noise they approach microcontroller chip, rather than having protect analog signals. However, external multiplexer chips introduce additional noise errors properly utilized. Therefore, necessary maintain "on" resistance (the impedance analog switch when active within multiplex chip) insert pass filter (R/C) input side multiplex chip. External Multiplexing Operation QADC from four external multiplexer chips expand number analog signals that converted. analog channels converted through external multiplexer selection. externally multiplexed channels automatically selected from channel field conversion command word (CCW) table, same internally multiplexed channels. Refer paragraph SECTION DIGITAL CONTROL additional information channel number assignments. automatic queue features available externally internally multiplexed channels. software selects external multiplexed mode setting control register (QACR0). Figure shows maximum configuration four external multiplexer chips connected QADC. external multiplexer chips select eight analog inputs connect analog output, which becomes input QADC. QADC provides three multiplexed address signals MA0, MA1, MA2, select eight inputs. These inputs connected four external multiplexer chips. analog output four multiplex chips each connected four separate QADC inputs ANw, ANx, ANy, ANz.
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AN10 AN11 AN12
VSSA VDDA VSSE
ANALOG POWER ANALOG REFERENCES
AN11 AN13 AN15
AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 AN51/PQB7 AN52/MA0/PQA0* AN53/MA1/PQA1* AN54/MA2/PQA2* AN55/ETRIG1/PQA3* AN56/ETRIG2/PQA4* AN57/PQA5* AN58/PQA6* AN59/PQA7*
AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31
EXTERNAL TRIGGERS
PORT
AN16 AN18 AN20 AN22 AN24 AN26 AN28 AN30
PORT
QADC
ANALOG MULTIPLEXER
ANALOG CONVERTER
DIGITAL RESULTS CONTROL
PORT PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS.
QADC CONN
Figure Example External Multiplexing When external multiplexed mode selected, QADC automatically creates open drain output signals from channel number each CCW. QADC also converts proper input channel (ANw, ANx, ANy, ANz) interpreting channel number. result, externally multiplexed channels appear conversion queues directly connected signals. software simply puts channel number externally multiplexed channels into CCWs. Refer Table SECTION DIGITAL CONTROL which shows channel numbers externally multiplexed channels that assigned range channel channel Figure shows that three signals also analog input pins. When external multiplexing selected, none pins used analog digital inputs. They become multiplexed address outputs.
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Module Version Options number available analog channels varies, depending whether external multiplexing used. maximum analog channels supported internal multiplexing circuitry converter. Table shows total number analog input channels supported with zero four external multiplexer chips. QADC uses pins which allow maximum analog channels converted. Table Analog Input Channels
Number Analog Input Channels Available Directly Connected External Multiplexed Total Channels1, External External External Three External Four External Chips Chip Chips Chips Chips
NOTES: above assumes that external trigger inputs shared with analog input pins. When external multiplexing used, three input channels become multiplexed address outputs, each external multiplexer chip, input channel becomes multiplexed analog input.
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SECTION CONNECTION CONSIDERATIONS
QADC requires accurate, noise-free input signals proper operation. This section discusses design external circuitry maximize QADC performance. Analog Reference Pins converter more accurate than analog reference. noise reference result least that much error conversion. reference QADC, supplied pins VRL, should low-pass filtered from source obtain noise-free, clean signal. many cases, simple capacitive bypassing suffice. extreme cases, inductors ferrite beads necessary noise energy present. Series resistance advisable since there effective current requirement from reference voltage internal resistor string array. External resistance introduce error this architecture under certain conditions. series devices filter network should contain minimum amount resistance. accurate conversion results, analog reference voltages must within limits defined VDDA VSSA, explained following subsection. Analog Power Pins analog supply pins (VDDA VSSA) define limits analog reference voltages (VRH VRL) analog multiplexer inputs. Figure diagram analog input circuitry.
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VDDA
SAMPLE CHANNELS TOTAL ARRAY
COMPARATOR
VSSA
SAMPLE AMPS EXIST QADC WITH CHANNELS
EACH SAMPLE AMP.
QADC SAMPLE
Figure Analog Input Circuitry Since sample amplifier powered VDDA VSSA, accurately transfer input signal levels exceeding VDDA down below VSSA. input signal outside this range, output from sample amplifier clipped. addition, must within range defined VDDA VSSA. long less than equal VDDA greater than equal VSSA sample amplifier accurately transferred input signal, resolution ratiometric within limits defined VRH. greater than VDDA, sample amplifier never transfer full-scale value. less than VSSA, sample amplifier never transfer zero value. Figure shows results reference voltages outside range defined VDDA VSSA. input signal range, VDDA lower than VRH. This results maximum obtainable 10-bit conversion value 3FE. bottom signal range, VSSA higher than VRL, resulting minimum obtainable 10-bit conversion value three.
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10-BIT RESULT
.010 .020 .030 5.100 5.110 5.120 INPUT VOLTS (VRH 5.120 5.130
QADC CLIPPING
Figure Errors Resulting from Clipping Analog Supply Filtering Grounding important factors influencing performance analog integrated circuits supply filtering grounding. Generally, digital circuits bypass capacitors every VDD/ pair. This applies analog subsystems submodules also. Equally important bypassing distribution power ground. Analog supplies should isolated from digital supplies much possible. This necessity stems from higher performance requirements often associated with analog circuits. Therefore, deriving analog supply from local digital supply recommended. However, economic reasons digital analog power derived from common regulator, filtering analog power recommended addition bypassing supplies already mentioned. example, pass filter could used isolate digital analog supplies when generated common regulator. multiple high precision analog circuits locally employed (i.e. converters), analog supplies should isolated from each other sharing supplies introduces potential interference between analog circuits. Grounding most important factor influencing analog circuit performance mixed signal systems standalone analog systems). Close attention must paid introduce additional sources noise into analog circuitry. Common sources noise include ground loops, inductive coupling, combining digital analog grounds together inappropriately.
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problem when combine digital analog grounds arises from large transients which digital ground must handle. digital ground able handle large transients, current from large transients return ground through analog ground. excess current overflowing into analog ground which causes performance degradation developing differential voltage between true analog ground microcontroller's ground pin. result that ground observed analog circuit longer true ground often ends skewed results. similar approaches designed improve eliminate problems associated with grounding excess transient currents involve star-point ground systems. approach star-point different grounds power supply origin, thus keeping ground isolated. Refer Figure 5-3.
ANALOG POWER SUPPLY
DIGITAL POWER SUPPLY
AGND
PGND
VSSA
VDDA
QADC
QADC POWER SCHEM
Figure Star-Ground Point Power Supply Origin Another approach star-point different grounds near analog ground microcontroller using small traces connecting non-analog grounds analog ground. small traces meant only accommodate differences, transients. NOTE This star-point scheme still requires adequate grounding digital analog subsystems addition star-point ground.
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Other suggestions layout which QADC employed include: Analog ground must impedance analog ground points circuit. Bypass capacitors should close power pins possible. analog ground should isolated from digital ground. This done cutting separate ground plane analog ground. Non-minimum traces should utilized connecting bypass capacitors filters their corresponding ground/power points. Minimum distance trace runs when possible. Accommodating Positive/Negative Stress Conditions Positive negative stress refers conditions which exceed nominally defined operating limits. Examples include applying voltage exceeding normal limit input (for example, voltages outside suggested supply/reference ranges) causing currents into which exceed normal limits. QADC specific considerations voltages greater than VDDA, less than VSSA applied analog input which cause excessive currents into input. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information exact magnitudes. Both stress conditions potentially disrupt conversion results neighboring inputs. Parasitic devices, associated with CMOS processes, cause immediate disruptive influence neighboring pins. Common examples parasitic devices diodes substrate bipolar devices with base terminal tied substrate (VSSI/VSSA ground). Under stress conditions, current introduced adjacent cause errors adjacent channels developing voltage drop across adjacent external channel source impedances. Figure shows active parasitic bipolar when input subjected negative stress conditions. Positive stress conditions activate similar parasitic device.
NEGATIVE STRESS VOLTAGE RADJACENT
RSTRESS IOUT
UNDER STRESS PARASITIC DEVICE ADJACENT PINS
QADC STRESS CONN
Figure Input Subjected Negative Stress current (IOUT) under negative stress determined following equation:
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STRESS STRESS where: VSTRESS Adjustable voltage source Parasitic bipolar base/emitter voltage (refer VNEGCLAMP APPENDIX ELECTRICAL CHARACTERISTICS) RSTRESS Source impedance (10K resistor Figure stressed channel)
current into (IIN) neighboring determined 1/KN (Gain) parasitic bipolar transistor (1/KN<<1). minimize impact stress conditions QADC apply voltage limiting circuits such diodes supply ground. However, leakage from such circuits potential influence sampled voltage converted must considered. Refer Figure 5-5.
EXTERNAL VOLTAGE
DEVICE
QADC STRESS CONN
Figure Voltage Limiting Diodes Negative Stress Circuit Another method minimizing impact stress conditions QADC strategically allocate QADC inputs that lower accuracy inputs adjacent inputs most likely stress conditions. Finally, suitable source impedances should selected meet design goals minimize effect stress conditions. Analog Input Considerations source impedance analog signal measured intermediate filtering should considered whether external multiplexing used not. Figure shows connection eight typical analog signal sources QADC analog input through separate multiplexer chip. Also, example analog signal source connected directly QADC analog input channel displayed.
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ANALOG SIGNAL SOURCE
FILTERING INTERCONNECT
FILTER2
SOURCE2
TYPICAL CHIP (MC54HC4051, MC74HC4051, MC54HC4052, MC74HC4052, MC54HC4053, ETC.)
INTERCONNECT
QADC
SOURCE SOURCE2
FILTER FILTER2
MUXIN
SOURCE SOURCE2
FILTER FILTER2
MUXIN
MUXOUT
MUXIN
SOURCE
SOURCE2
FILTER FILTER2
MUXOUT
MUXIN
SAMPLE
SOURCE SOURCE2
FILTER FILTER2
CSAMPLE
SOURCE SOURCE2
FILTER FILTER2
MUXIN
SOURCE SOURCE2
FILTER FILTER2
MUXIN
SOURCE SOURCE2
FILTER FILTER2
MUXIN
SOURCE
FILTER
MUXIN
SOURCE2
FILTER2
SOURCE
FILTER
NOTES: TYPICAL VALUE RFILTER TYPICALLY 10K-20K.
SAMPLE
QADC
Figure External Multiplexing Analog Signal Sources
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Analog Input Pins Analog inputs should have impedance pins. impedance realized placing capacitor with good high frequency characteristics input part. Ideally, that capacitor should large possible (within practical range capacitors that still have good high frequency characteristics). This capacitor effects: helps attenuate noise that exist input. sources charge during sample period when analog signal source high-impedance source. Series resistance used with capacitor input implement simple filter. maximum level filtering input pins application dependent based bandpass characteristics required accurately track dynamic characteristics input. Simple filtering limited source impedance transducer circuit supplying analog signal measured. (refer 5.6.2 Error Resulting from Leakage). some cases, size capacitor very small. Figure simplified model input channel. Refer this model following discussion interaction between external circuitry circuitry inside QADC.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT MODEL
VSRC
CDAC
VSRC SOURCE VOLTAGE FILTER IMPEDANCE (SOURCE IMPEDANCE INCLUDED) FILTER CAPACITOR INTERNAL CAPACITANCE (FOR BYPASSED CHANNEL, THIS CDAC CAPACITANCE) CDAC CAPACITOR ARRAY INTERNAL VOLTAGE SOURCE PRECHARGE (VDDA/2)
QADC SAMPLE MODEL
Figure Electrical Model Input Figure 5-7, comprise external filter circuit. internal sample capacitor. Each channel capacitor. never precharged; retains value last sample. internal voltage source used precharge
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capacitor array (CDAC) before each sample. value this supply VDDA/2, volts 5-volt operation. following paragraphs provide simplified description interaction between QADC user's external circuitry. This circuitry assumed simple low-pass filter passing signal from source QADC input pin. following simplifying assumptions made: source impedance included with series resistor filter. external capacitor perfect leakage, significant dielectric absorption characteristics, etc.) parasitic capacitance associated with input included value external capacitor. Inductance ignored. "on" resistance internal switches zero ohms "off" resistance infinite. 5.6.1 Settling Time External Circuit values user's external circuitry determine length time required charge source voltage level (VSRC). time Figure closes. open, disconnecting internal circuitry from external circuitry. Assume that initial voltage across zero. charges, voltage across determined following equation, where total charge time:
When voltage across approaches infinity, will equal VSRC. (This assumes internal leakage.) With 10-bit resolution, count equal 1/2048 full-scale value. Assuming worst case (VSRC full scale), Table shows required time charge within count actual source voltage during 10-bit conversions. Table based network Figure 5-7. NOTE following times completely independent converter architecture (assuming QADC affecting charging). Table External Circuit Settling Time (10-Bit Conversions)
Filter Capacitor (CF)
.001
Source Resistance (RF)
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external circuit described Table low-pass filter. user interested measuring component external signal must take characteristics this filter into account. 5.6.2 Error Resulting from Leakage series resistor limits current pin, therefore input leakage acting through large source impedance degrade accuracy. maximum input leakage current specified APPENDIX ELECTRICAL CHARACTERISTICS. Input leakage greatest high operating temperatures general rule decreases half each decrease temperature. Assuming 5.12 count (assuming 10-bit resolution) corresponds input voltage. typical input leakage acting through external series resistance results error less than count (5.0 mV). source impedance typical leakage present, error counts introduced. addition internal junction leakage, external leakage (e.g., external clamping diodes used) charge sharing effects with internal capacitors also contribute total leakage current. Table illustrates effect different levels total leakage accuracy different values source impedance. error listed terms 10-bit counts. CAUTION Leakage from part obtainable only within limited temperature range. Table Error Resulting From Input Leakage (IOFF)
Source Impedance counts Leakage Value (10-bit Conversions) counts counts count counts 1000 counts counts counts
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SECTION ANALOG SUBSYSTEM
This section describes QADC analog subsystem, which includes front-end analog multiplexer, digital analog converter (DAC) array, comparator, successive approximation register (SAR). Analog-to-Digital Converter Operation analog subsystem consists path from input pins through input multiplexing circuitry, into array, through analog comparator. output comparator feeds into considered boundary between analog digital subsystems QADC. Figure shows block diagram QADC analog submodule.
PQA7
CHARGE PUMP BIAS
CHAN.
EXTERNAL TRIGGERS
PORT
PORT INPUT
ADDRESS DECODE
SAMPLE/ HOLD PQA0 PQB7 CONTROL REGISTERS CONTROL LOGIC SAMPLE/ HOLD
SAMPLE TIMER
PERIODIC TIMER
CLOCK PRESCALER
CLOCK INTERFACE
PQB0 DUMMY VDDA COMPARATOR VSSA
DATA 10-BIT RC-DAC TABLE 10-BIT, 40-WORD SUCCESSIVE APPROXIMATION REGISTER RESULT TABLE 10-BIT, 40-WORD ADDRESS DECODE RESULT ALIGNMENT ADDR INTERMODULE
QADC DETAIL BLOCK
Figure QADC Module Block Diagram
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6.1.1 Conversion Cycle Times Total conversion time made initial sample time, transfer time, final sample time, resolution time. Initial sample time refers time during which selected input channel connected sample capacitor input sample buffer amplifier. During transfer period, sample capacitor disconnected from multiplexer, stored voltage buffered transferred array. During final sampling period, sample capacitor amplifier bypassed, multiplexer input charges array directly. During resolution period, voltage array converted digital value stored SAR. Initial sample time fixed QCLKs transfer time four QCLKs. Final sample time clock cycles, depending value field CCW. Resolution time cycles. Transfer resolution require minimum QCLK clocks (8.6 with 2.1-MHz QCLK). maximum final sample time period QCLKs selected, total conversion time 15.2 (with 2.1-MHz QCLK). Figure illustrates timing conversions. This diagram assumes final sampling period QCLKs.
INITIAL SAMPLE TIME CYCLES TRANSFER TIME CYCLES
FINAL SAMPLE TIME CYCLES:
RESOLUTION TIME CYCLES
QCLK
SAMPLE TRANSFER TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
QADC CONVERSION
Figure Conversion Timing 6.1.1.1 Amplifier Bypass Mode Conversion Timing amplifier bypass mode enabled conversion setting amplifier bypass (BYP) field CCW, timing changes that shown Figure 6-3. Refer paragraph SECTION DIGITAL CONTROL more information field. initial sample time transfer time eliminated reducing potential conversion time QCLKs. However, internal effects, minimum final samMOTOROLA ANALOG SUBSYSTEM More Information This Product, www.freescale.com QADC REFERENCE MANUAL
time four QCLKs must allowed. This results savings four QCLKs. When using bypass mode, external circuit should source impedance (typically less than Also, loading effects external circuitry QADC need considered, since benefits sample amplifier present.
SAMPLE TIME CYCLES:
RESOLUTION TIME CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
QADC CONVERSION
Figure Bypass Mode Conversion Timing Front-End Analog Multiplexer internal multiplexer selects analog input pins three special internal reference channels conversion. following three special channels: Reference Voltage High Reference Voltage VDDA/2 Mid-Analog Supply Voltage selected input connected side capacitor array. other side array connected comparator input. multiplexer also includes positive negative stress protection circuitry, which prevents other channels from affecting current conversion when voltage levels applied other channels. Refer APPENDIX ELECTRICAL CHARACTERISTICS specific voltage level limits. Digital Analog Converter Array digital analog converter (DAC) array consists binary-weighted capacitors resistor-divider chain. array serves purposes: array holds sampled input voltage during conversion. resistor-capacitor array provides mechanism successive approximation conversion. Resolution begins with most significant (MSB) works down least significant (LSB). switching sequence controlled digital logic.
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Comparator comparator used during approximation process sense whether digitally selected arrangement array produces voltage level higher lower than sampled input. comparator output feeds into which accumulates conversion result sequentially, starting with MSB. Successive Approximation Register input successive approximation register (SAR) connected comparator output. sequentially receives conversion value time, starting with MSB. After accumulating bits conversion result, data transferred appropriate result location, where read from user software.
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SECTION DIGITAL CONTROL
digital control subsystem includes control logic sequence conversion activity, channel select logic, clock periodic/interval timer, control status registers, conversion command word table RAM, result word table RAM. central element control QADC conversions 40-entry conversion command word (CCW) table. Each specifies conversion input channel. Depending application, queues established table. queue scan sequence more input channels. using pause mechanism, subqueues created queues. Each queue operated using several different scan modes. scan modes queue queue programmed QACR1 QACR2 (control registers Once queue been started trigger event (any ways cause QADC begin executing CCWs queue subqueue), QADC performs sequence conversions places results result word table. Queue Priority Queue priority over queue execution. following cases show conditions under which queue asserts priority: When queue active, trigger event queue queue causes corresponding queue execution begin. When queue active trigger event occurs queue queue cannot begin execution until queue reaches completion paused state. status register records trigger event reporting queue status trigger pending. Additional trigger events queue which occur before execution begin, recorded trigger overruns. When queue active trigger event occurs queue current queue conversion aborted. status register reports queue status suspended. trigger events occurring queue while queue suspended recorded trigger overruns. Once queue reaches completion paused state, queue begins executing again. programming resume QACR2 determines which executed queue Refer 7.6.3 Control Register more information. When simultaneous trigger events occur queue queue queue begins execution queue status changed trigger pending. Subqueues that paused. pause feature used divide queue and/or queue into multiple subqueues. subqueue defined setting pause last subqueue.
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Figure shows format example using pause create subqueues. Queue shown with four CCWs each subqueue queue CCWs each subqueue.
CONVERSION COMMAND WORD (CCW) TABLE PAUSE PAUSE BEGIN QUEUE CHANNEL SELECT, SAMPLE, HOLD, CONVERSION RESULT WORD TABLE
PAUSE QUEUE
QADC
QUEUE BEGIN QUEUE PAUSE PAUSE PAUSE
Figure QADC Queue Operation With Pause queue operating mode selected queue determines what type trigger event causes execution each subqueues within queue Similarly, queue operating mode queue determines type trigger event required execute each subqueues within queue example, when external trigger rising edge continuous-scan mode selected queue there subqueues within queue separate rising edge required external trigger after every pause begin execution each subqueue (refer Figure 7-1). Refer Scan Modes more information different scan modes. choice single-scan continuous-scan applies full queue, applied each subqueue. Once subqueue initiated, each executed sequentially until last subqueue executed pause state entered.
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Execution only continue with next CCW, which beginning next subqueue. subqueue cannot executed second time before overall queue execution been completed. Refer 7.6.3 Control Register more information. Trigger events which occur during execution subqueue ignored, except that trigger overrun flag set. When continuous-scan mode selected, trigger event occurring after completion last subqueue (after queue completion flag set), causes execution continue with first subqueue, starting with first queue. When QADC encounters with pause set, queue enters paused state after completing conversion specified with pause bit. pause flag pause software interrupt optionally issued. status queue shown paused, indicating completion subqueue. QADC then waits another trigger event again begin execution next subqueue. Boundary Conditions following queue operation boundary conditions: first queue contains channel end-of-queue (EOQ) code. queue becomes active first read. end-of-queue recognized, completion flag set, queue becomes idle. conversion performed. (beginning queue beyond table (40-63) trigger event occurs queue Refer 7.6.3 Control Register information BQ2. end-of-queue condition recognized immediately, completion flag set, queue becomes idle. conversion performed. CCW0 trigger event occurs queue After reading CCW0, end-of-queue condition recognized, completion flag set, queue becomes idle. conversion performed. NOTE Multiple end-of-queue conditions recognized simultaneously, although there change QADC behavior. example, CCW0, CCW0 contains code, trigger event occurs queue QADC reads CCW0 detects both end-of-queue conditions. completion flag queue becomes idle. Boundary conditions also exist combinations pause end-of-queue. case when pause end-of-queue condition next CCW. conversion specified with pause completes normally. pause flag set. However, since end-of-queue condition recognized, completion flag also queue status becomes idle, paused. Examples this situation include:
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pause CCW5 channel (EOQ) code CCW6. pause CCW39. During queue operation, pause CCW20 points CCW21. Another pause end-of-queue boundary condition occurs when pause end-of-queue condition occur same CCW. Both pause end-of-queue conditions recognized simultaneously. end-of-queue condition precedence conversion performed pause flag set. QADC sets completion flag queue status becomes idle. Examples this situation are: pause CCW10 programmed into CCW10. During queue operation, pause CCW32, which also BQ2.
Scan Modes QADC queuing mechanism allows application utilize different requirements automatically scanning input channels. single-scan mode, single pass through sequence conversions defined queue performed. continuous-scan mode, multiple passes through sequence conversions defined queue executed. following paragraphs describe single-scan continuous-scan operations. 7.3.1 Disabled Mode Reserved Mode When disabled mode reserved mode selected, queue active. Trigger events cannot initiate queue execution. When both queue queue disabled, wait states encountered accesses RAM. When both queues disabled, safe change prescaler values. 7.3.2 Single-Scan Modes When application software wants execute single pass through sequence conversions defined queue, single-scan queue operating mode selected. programming field QACR1, following modes selected queue Software initiated single-scan mode External trigger rising edge single-scan mode External trigger falling edge single-scan mode addition above modes, queue also programmed interval timer single-scan mode, using periodic/interval timer. queue operating mode queue selected field QACR2. single-scan queue operating modes, software must also enable queue begin execution writing single-scan enable queue's control register. single-scan enable bits, SSE1 SSE2, provided queue queue respectively.
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Until single-scan enable set, trigger events that queue ignored. single-scan enable during write cycle, which selects single-scan queue operating mode. single-scan enable written zero, always read zero. completion flag, completion interrupt, queue status used determine when queue completed. After single-scan enable set, trigger event causes QADC begin execution with first queue. single-scan enable remains until queue completed. After queue reaches completion, QADC resets singlescan enable zero. single-scan enable written zero software before queue scan complete, queue affected. However, software changes queue operating mode, queue operating mode value single-scan enable recognized immediately. current conversion aborted queue operating mode takes effect. software initiated single-scan mode, writing single-scan enable causes QADC internally generate trigger event queue execution begins immediately. other single-scan queue operating modes, once single-scan enable written, selected trigger event must occur before queue start. trigger overrun recorded trigger event occurs during queue execution external trigger single-scan mode interval timer single-scan mode. When pause encountered during queue scan single-scan mode, another trigger event required queue execution continue. Software involvement needed enable queue execution continue from paused state. singlescan enable allows entire queue scanned once. software initiated single-scan mode, trigger event generated internally soon conversion complete with pause set. pause QCLKs. external trigger single-scan mode, queue remains paused until another trigger edge received external trigger pin. interval timer single-scan mode, next expiration timer trigger event queue. After queue execution complete, queue status shown idle. software restart queue setting single-scan enable one. Queue execution begins with first queue. 7.3.2.1 Software Initiated Single-Scan Mode Software initiate execution scan sequence queue selecting software initiated single-scan mode, writing single-scan enable QACR1 QACR2. trigger event generated internally QADC immediately begins execution first queue. pause encountered, queue execution ceases momentarily while another trigger event generated internally, then execution continues. QADC automatically performs conversions queue until end-of-queue condition encountered. queue remains idle until software again sets single-scan enable bit. While time internally generate trigger event
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very short, software momentarily read status conditions, indicating that queue paused. trigger overrun flag never while software initiated single-scan mode. software initiated single-scan mode useful following applications: Allows software complete control queue execution. Allows software easily alternate between several queue sequences. 7.3.2.2 External Trigger Single-Scan Mode external trigger single-scan mode variation external trigger continuousscan mode, also available with both queue queue software programs polarity external trigger edge that detected, either rising falling edge. software must enable scan occur setting single-scan enable queue. first external trigger edge causes queue executed time. Each read indicated conversions performed until end-of-queue condition encountered. After queue completed, QADC clears single-scan enable bit. Software single-scan enable again allow another scan queue initiated next external trigger edge. external trigger single-scan mode useful when input trigger rate exceed queue execution rate. Analog samples taken sync with external event, even though software interested data taken from every edge. software start external trigger single-scan mode data, later time, start queue again next samples. external trigger single-scan mode also useful when software needs change polarity external trigger that both rising falling edges cause queue execution. 7.3.2.3 Interval Timer Single-Scan Mode Queue also periodic/interval timer single-scan queue operating mode. timer interval range from 128K QCLK cycles binary multiples. When interval timer single-scan mode selected software sets singlescan enable QACR2, timer begins counting. When time interval expires, internal trigger event created start queue. timer reloaded begins counting again. Meanwhile, QADC begins execution with first queue QADC automatically performs conversions queue until pause end-of-queue condition encountered. When pause occurs, queue execution stops until timer interval expires again, queue execution continues. When queue execution reaches queue situation, timer held reset singlescan enable cleared. Software single-scan enable again, allowing another scan queue initiated interval timer.
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interval timer generates trigger event whenever time interval elapses. trigger event cause queue execution continue following pause, considered trigger overrun. Once queue execution completed, single-scan enable must again enable timer count again. interval timer single-scan mode used applications which need coherent results, example: When necessary that samples guaranteed taken during same scan analog pins. When interrupt rate periodic timer continuous-scan mode would high. sensitive battery applications, where single-scan mode uses less power than software initiated continuous-scan mode.
7.3.3 Continuous-Scan Modes When application software wants execute multiple passes through sequence conversions defined queue, continuous-scan queue operating mode selected. programming field QACR1, following software initiated modes selected queue Software initiated continuous-scan mode External trigger rising edge continuous-scan mode External trigger falling edge continuous-scan mode addition above modes, queue also programmed periodic timer continuous-scan mode, where scan initiated selectable time interval using on-chip periodic/interval timer. queue operating mode queue selected field QACR2. When queue programmed continuous-scan mode, single-scan enable queue control register does have meaning effect. soon queue operating mode programmed, selected trigger event initiate queue execution. case software initiated continuous-scan mode, trigger event generated internally queue execution begins immediately. other single-scan queue operating modes, selected trigger event must occur before queue start. trigger overrun recorded trigger event occurs during queue execution external trigger continuous-scan mode periodic timer continuous-scan mode. When pause encountered during scan, another trigger event required queue execution continue. Software involvement needed enable queue execution continue from paused state. software initiated continuous-scan mode, trigger event generated internally soon conversion complete with pause set. pause QCLKs. external trigger continuous-scan mode, queue remains paused until another trigger edge received external trigger pin. periodic timer continuous-scan mode, next expiration timer trigger event queue.
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After queue execution complete, queue status shown idle. Since continuous-scan queue operating modes allow entire queue scanned multiple times, software involvement needed enable queue execution continue from idle state. next trigger event causes queue execution begin again, starting with first queue. NOTE possible guarantee coherent samples since relationship between conversion time other conversion variable (due programmable trigger events, queue priorities, on). 7.3.3.1 Software Initiated Continuous-Scan Mode When software initiated continuous-scan mode programmed, trigger event generated automatically QADC. Queue execution begins immediately. pause encountered, queue execution ceases QCLKs, while another trigger event generated internally, then execution continues. When end-of-queue reached, another internal trigger event generated, queue execution begins again from beginning queue. While time internally generate trigger event very short, software momentarily read status conditions, indicating that queue paused idle. trigger overrun flag never while software initiated continuous-scan mode. software initiated continuous-scan mode keeps result registers updated more frequently than other queue operating modes. software always read result table latest converted value each channel. channels scanned kept date QADC without software involvement. Software read result value time. NOTE possible guarantee coherent samples since relationship between conversion time other conversion variable (due programmable trigger events, queue priorities, on). software initiated continuous-scan mode chosen either queue, normally used only with queue When software initiated continuous-scan mode chosen queue that queue operates continuously queue being lower priority, never gets executed. short interval time between queue pause internally generated trigger event, between queue completion subsequent trigger event sufficient allow queue execution begin. software initiated continuous-scan mode useful choice with queue converting channels that need synchronized anything, slow-tochange analog channels. Interrupts normally used with software initiated continuous-scan mode. Rather, software reads latest conversion result from
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result table time. Once initiated, software action needed sustain conversions channel. 7.3.3.2 External Trigger Continuous-Scan Mode QADC provides external trigger pins both queues. When external trigger software initiated continuous-scan mode selected, transition associated external trigger initiates queue execution. polarity external trigger signal programmable, that software choose begin queue execution rising falling edge. Each read indicated conversions performed until end-of-queue condition encountered. When next external trigger edge detected, queue execution begins again automatically. Software initialization needed between trigger events.
Some applications need synchronize sampling analog channels external events. There cases when possible software initiation queue scan sequence, since interrupt response times vary. 7.3.3.3 Periodic Timer Continuous-Scan Mode QADC includes dedicated periodic/interval timer initiating scan sequence queue only. Software selects programmable timer interval ranging from 128K times QCLK period binary multiples. QCLK period prescaled down from intermodule (IMB) clock. When periodic timer continuous-scan mode selected, timer begins counting. After programmed interval elapses, timer generated trigger event starts queue. timer then reloaded begins counting again. Meanwhile, QADC automatically performs conversions queue until end-of-queue condition pause encountered. When pause occurs, QADC waits periodic interval expire again, then continues with queue. After end-of-queue been detected, next trigger event causes queue execution begin again with first queue periodic timer generates trigger event whenever time interval elapses. trigger event cause queue execution continue following pause queue completion, considered trigger overrun. with continuous-scan queue operating modes, software action needed between trigger events. Software enables completion interrupt when using periodic timer continuousscan mode. When interrupt occurs, software knows that periodically collected analog results have just been taken. software periodic interrupt obtain non-analog inputs well, such contact closures, part periodic look inputs. QADC Clock (QCLK) Generation Figure block diagram clock subsystem. QCLK provides timing converter state machine which controls timing conversion. QCLK also input 17-stage binary divider which implements periodic/inQADC REFERENCE MANUAL DIGITAL CONTROL More Information This Product, www.freescale.com MOTOROLA
terval timer. retain specified analog conversion accuracy, QCLK frequency (FQCLK) must within tolerance specified APPENDIX ELECTRICAL CHARACTERISTICS. Before using QADC, software must initialize prescaler with values that QCLK within specified range. Though most software applications initialize prescaler once change write operations prescaler fields permitted. CAUTION change prescaler value while conversion progress likely corrupt result from conversion progress. Therefore, prescaler write operation should done only when both queues disabled modes.
ZERO DETECT
RESET QCLK
SYSTEM CLOCK (FSYS)
5-BIT DOWN COUNTER
LOAD
CLOCK GENERATE
QCLK
PRESCALER RATE SELECTION (FROM CONTROL REGISTER HIGH TIME CYCLES (PSH) TIME CYCLES (PSL) HALF CYCLE HIGH (PSA)
ONE'S COMPLEMENT COMPARE
QCLK
QADC CLOCK
INPUT SAMPLE TIME (FROM CCW)
CONVERTER STATE MACHINE
CONTROL SAR[9:0]
BINARY COUNTER QUEUE MODE RATE SELECTION (FROM CONTROL REGISTER
PERIODIC/INTERVAL TIMER SELECT
PERIODIC/INTERVAL TRIGGER EVENT
QADC CLOCK BLOCK
Figure QADC Clock Subsystem Functions
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accommodate wide variations main clock frequency (IMB system clock FSYS), QCLK generated programmable prescaler which divides system clock frequency within specified QCLK tolerance range. allow conversion time maximized across spectrum system clock frequencies, QADC prescaler permits frequency QCLK software selectable. also allows duty cycle QCLK waveform programmable. software establishes basic high phase QCLK waveform with (prescaler clock high time) field QACR0, selects basic phase QCLK with (prescaler clock time) field. duty cycle QCLK further modified with (prescaler clock tic) QACR0. combination parameters establishes frequency QCLK.
Figure shows that prescaler essentially variable pulse width signal generator. 5-bit down counter, clocked system clock rate, used create both high phase phase QCLK signal. beginning high phase, 5-bit counter loaded with 5-bit value. When zero detector finds that high phase finished, QCLK reset. 3-bit comparator looks one's complement match with 3-bit value, which phase QCLK. allows QCLK high-to-low transition delayed half cycle input clock. following sequence summarizes process determining what values into prescaler fields QACR0: Choose system clock frequency (FSYS). Choose first-try values PSH, PSL, PSA, then skip step Choose different values PSH, PSL, PSA. High QCLK Time less than TPSH (QADC Clock Duty Cycle Minimum High Phase Time), return step Refer APPENDIX ELECTRICAL CHARACTERISTICS more information TPSH. NOTE High QCLK Time 1000 (PSH PSA) FSYS MHz) QCLK Time less than TPSL (QADC Clock Duty Cycle Minimum Phase Time), return step Refer APPENDIX ELECTRICAL CHARACTERISTICS more information TPSL. NOTE QCLK Time 1000 (PSL PSA) FSYS MHz) Calculate QCLK frequency (FQCLK). NOTE FQCLK MHz) 1000 (High QCLK Time QCLK Time) Choose number input sample cycles typical input channel. calculated conversion times sufficient, return step
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Code selected PSH, PSL, values into prescaler fields QACR0. Figure Table show examples QCLK programmability. examples include conversion times based following assumptions: System clock (FSYS) 20.97 MHz. Input sample time fast possible (IST QCLK cycles). Figure Table also show conversion time calculated single conversion queue. other system clock frequencies other input sample times, same calculations made.
SYSTEM CLOCK
FSYS QCLK EXAMPLES
CYCLES
QADC QCLK
Figure QADC Clock Programmability Examples
Table QADC Clock Programmability
Control Register Information Example Number FSYS 20.97 Input Sample Time (IST) QCLK Conversion Time (MHz) (µs) 18.0 18.0
system clock frequency basis QADC timing. QADC requires that system clock frequency least twice QCLK frequency. Refer APPENDIX ELECTRICAL CHARACTERISTICS information minimum maximum allowable QCLK frequencies. QCLK frequency established combination parameters QACR0. 5-bit field selects number system clock cycles high phase QCLK wave. 3-bit field selects number system clock cycles phase QCLK wave. Example Figure shows that when QCLK remains high four cycles system clock. also shows that when QCLK remains four system clock cycles. example equation QCLK high cycles value plus one, equation QCLK cycles value plus one.
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Refer APPENDIX ELECTRICAL CHARACTERISTICS information minimum QCLK high time (TPSH) minimum QCLK time (TPSL). order able tune QCLK close possible fastest conversion time given system clock frequency, QADC permits more programmable control QCLK high time. parameter QACR0 allows QCLK high phase stretched half cycle system clock, correspondingly, QCLK phase shortened half cycle system clock. Example Figure same Example except that set. QCLK high phase system clock cycles; QCLK phase system clock cycles. following equations calculating QCLK high phases:
High QCLK Time 1000 (PSH PSA) FSYS QCLK Time 1000 (PSL PSA) FSYS FQCLK 1000 (High QCLK Time QCLK Time) MHz) Where: prescaler QCLK high cycles QACR0 prescaler QCLK cycles QACR0 prescaler QCLK half cycle QACR0 FSYS System clock frequency FQCLK QCLK frequency Periodic/Interval Timer on-chip periodic/interval timer enabled generate trigger events programmable interval, initiating execution queue periodic/interval timer stays reset under following conditions: Queue programmed queue operating mode which does periodic/interval timer Interval timer single-scan mode selected, single-scan enable zero system reset master reset asserted Stop mode selected Freeze mode selected other conditions which cause pulsed reset timer are: Roll over timer counter queue operating mode change from periodic/interval timer mode another periodic/interval timer mode During stop mode, periodic/interval timer held reset. Since stop mode causes QACR2 initialized zero, valid periodic interval timer mode must written QACR2 after stop mode exited release timer from reset. When internal FREEZE line asserted periodic interval timer mode
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selected, timer counter reset after current conversion completes. When periodic interval timer mode been enabled (the timer counting), trigger event been issued, freeze mode takes effect immediately, timer held reset. When internal FREEZE line negated, timer counter starts counting from beginning. Refer paragraph 3.3.2 SECTION CONFIGURATION CONTROL more information. Control Status Registers following paragraphs describe control status registers. QADC three control registers status register. 7.6.1 Control Register Control register establishes QCLK with prescaler parameter fields defines whether external multiplexing enabled. implemented control register fields read written, reserved locations read zero writes have effect. They typically written once when software initializes QADC, changed afterwards. QACR0 Control Register
RESET: RESERVED
$####0A
Externally Multiplexed Mode allows software select externally multiplexed mode, which affects interpretation channel numbers forces MA0, pins outputs. Internally multiplexed, possible channels. Externally multiplexed, possible channels. PSH[8:4] Prescaler Clock High Time field selects QCLK high time prescaler. Refer APPENDIX ELECTRICAL CHARACTERISTICS information QADC operating clock frequency (FQCLK) values. keep QCLK within specified range, field selects high time QCLK, which range from system clock cycles. minimum high time QCLK specified TPSH. Table displays bits field which enable range QCLK high times.
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Table Prescaler Clock High Times
PSH[8:4] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 QCLK High Time System Clock Cycle System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles
01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Prescaler Clock adds system clock QCLK high time prescaler. fields establish FQCLK. field does change frequency clock, however, does change duty cycle tic, half system clock period. modifies QCLK duty cycle adding system clock high time subtracting system clock from time. QCLK high times modified. system clock half cycle high time QCLK subtract system clock half cycle from time.
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PSL[2:0] Prescaler Clock Time field selects QCLK time prescaler. Refer APPENDIX ELECTRICAL CHARACTERISTICS information FQCLK values. keep QCLK within specified range, field selects time QCLK, which range from eight system clock cycles. minimum time clock specified TPSL. Table displays bits field which enable range QCLK times. Table Prescaler Clock Times
PSL[2:0] QCLK Time System Clock Cycle System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles System Clock Cycles
7.6.2 Control Register Control register mode control register operation queue applications software defines queue operating mode queue, enable completion and/or pause interrupt. control register fields read/write data. However, SSE1 always reads zero unless test mode enabled. Most bits typically written once when software initializes QADC, changed afterwards. QACR1 Control Register
CIE1 RESET: PIE1 SSE1 USED USED
$####0C
CIE1 Queue Completion Interrupt Enable CIE1 enables interrupt upon completion queue interrupt request initiated when conversion complete queue Disable queue completion interrupt associated with queue Enable interrupt after conversion sample requested last queue PIE1 Queue Pause Interrupt Enable PIE1 enables interrupt when queue enters pause state. interrupt request initiated when conversion complete that pause set. Disable pause interrupt associated with queue Enable interrupt after conversion sample requested queue which pause set.
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SSE1 Queue Single-Scan Enable SSE1 enables single-scan queue start after trigger event occurs. SSE1 during same write cycle when bits single-scan queue operating modes. single-scan enable written zero, always read zero, unless test mode selected. SSE1 enables trigger event initiate queue execution single-scan operation queue QADC clears SSE1 when single-scan complete. Trigger events accepted single-scan modes. Accept trigger event start queue single-scan mode. MQ1[10:8] Queue Operating Mode field selects queue operating mode queue Table shows bits field which enable different queue operating modes. Table Queue Operating Modes
MQ1[10:8] Operating Modes Disabled mode, conversions occur Software triggered single-scan mode (started with SSE1) External trigger rising edge single-scan mode ETRIG1 pin) External trigger falling edge single-scan mode ETRIG1 pin) Reserved mode, conversions occur Continuous-scan software triggered mode External trigger rising edge continuous-scan mode ETRIG1 pin) External trigger falling edge continuous-scan mode ETRIG1 pin)
7.6.3 Control Register Control register mode control register operation queue Software specifies queue operating mode queue enable completion and/or pause interrupt. control register fields read/write data, except SSE2 bit, which readable only when test mode enabled. Most bits typically written once when software initializes QADC, changed afterwards. QACR2 Control Register
CIE2 RESET: PIE2 SSE2 USED
$####0E
CIE2 Queue Completion Software Interrupt Enable CIE2 enables interrupt upon completion queue interrupt request initiated when conversion complete queue Disable queue completion interrupt associated with queue Enable interrupt after conversion sample requested last queue
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PIE2 Queue Pause Software Interrupt Enable PIE2 enables interrupt when queue enters pause state. interrupt request initiated when conversion complete that pause set. Disable pause interrupt associated with queue Enable interrupt after conversion sample requested queue which pause set. SSE2 Queue Single-Scan Enable SSE2 enables single-scan queue start after trigger event occurs. SSE2 during same write cycle when bits single-scan queue operating modes. single-scan enable written zero, always read zero, unless test mode selected. SSE2 enables trigger event initiate queue execution single-scan operation queue QADC clears SSE2 when single-scan complete. Trigger events accepted single-scan modes. Accept trigger event start queue single-scan mode. MQ2[12:8] Queue Operating Mode field selects queue operating mode queue Table shows bits field which enable different queue operating modes. Table Queue Operating Modes
MQ2[12:8] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 Operating Modes Disabled mode, conversions occur Software triggered single-scan mode (started with SSE2) External trigger rising edge single-scan mode ETRIG2 pin) External trigger falling edge single-scan mode ETRIG2 pin) Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Interval timer single-scan mode: time QCLK period Reserved mode Reserved mode Continuous-scan software triggered mode External trigger rising edge continuous-scan mode ETRIG2 pin) External trigger falling edge continuous-scan mode ETRIG2 pin) Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period
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Table Queue Operating Modes (Continued)
MQ2[12:8] 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Operating Modes Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Periodic timer continuous-scan mode: time QCLK period Reserved mode
Queue Resume selects queue resumption point after suspension queue changed during execution queue change recognized until endof-queue condition reached, queue operating mode queue changed. primary reason selecting re-execution entire queue subqueue guarantee that samples taken consecutively scan (coherency). When subqueues used, queue execution restarts after suspension with first queue When pause previously occurred queue execution, queue execution restarts after suspension with first current subqueue. subqueue considered stand-alone sequence conversions. Once pause flag been report subqueue completion, that subqueue repeated until CCWs queue executed. example using resume when frequency queue trigger events prohibit queue completion. rate queue execution high, best queue execution continue with that being converted when queue suspended. This allows queue eventually complete execution. After suspension, begin execution with first queue current subqueue. After suspension, begin execution with aborted queue BQ2[5:0] Beginning Queue field indicates location where queue begins. allow length queue queue vary, programmable pointer identifies table location where queue begins. field also serves end-of-queue condition queue Software defines beginning queue programming field QACR2. usually programmed before same time queue operating mode queue selected. greater, queue does have entries, entire table dedicated queue entire table
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dedicated queue special case, when queue operating mode queue selected trigger event occurs queue with queue execution terminated after CCW0 read. Conversions occur. pointer changed dynamically, alternate between queue scan sequences. change while queue active does take effect until endof-queue condition recognized, until queue operating mode queue changed. example, scan sequences could defined follows: first sequence starts CCW10, with pause after CCW11 programmed CCW15; second sequence starts CCW16, with pause after CCW17 programmed CCW39. With CCW10 continuous-scan mode selected, queue execution begins. When pause encountered CCW11, software interrupt routine redefine CCW16. Therefore, after end-of-queue recognized CCW15, internal retrigger event generated execution restarts CCW16. When pause software interrupt occurs again, software change back CCW10. After end-of-queue recognized CCW39, internal retrigger event created execution restarts CCW10. changed while queue active, effect end-of-queue indication queue immediate. NOTE assigned that queue currently working then that conversion completed before takes effect. Each time read queue location compared with current value pointer detect possible end-of-queue condition. example, changed CCW3 while queue converting CCW2, queue terminated after conversion completed. However, changed CCW1 while queue converting CCW2, QADC would recognize end-of-queue condition until queue execution reached CCW1 again, presumably next pass through queue. 7.6.4 Status Register status register contains information about state each queue current conversion. Except four flag bits (CF1, PF1, CF2, PF2) trigger overrun bits (TOR1 TOR2), status register fields contain read-only data. four flag bits trigger overrun bits cleared writing zero after previously read one. QASR Status Register
RESET: TOR1 TOR2
$####10
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Queue Completion Flag indicates that queue scan been completed. scan completion flag QADC when input channel sample requested last queue converted, result stored result table. queue identified when execution complete location prior that pointed BQ2, when current contains end-of-queue code instead valid channel number, when currently completed last location RAM. When interrupts enabled that queue completion flag, QADC asserts interrupt request level specified IRL1 interrupt register (QADCINT). software reads completion flag during interrupt service routine identify interrupt request. interrupt request cleared when software writes zero completion flag bit, when previously read one. Once set, only software reset clear CF1. maintained QADC regardless whether corresponding interrupt enabled. software polls set. This allows software recognize that QADC finished with queue scan. software acknowledges that detected completion flag being writing zero completion flag after read one. Refer SECTION INTERRUPTS more information. Queue scan complete. Queue scan complete. Queue Pause Flag indicates that queue scan reached pause. QADC when current queue pause set, selected input channel been converted, result been stored result table. Once set, queue enters paused state waits trigger event allow queue execution continue. However, with pause last queue, queue execution complete. queue status becomes idle, paused, both pause completion flags set. When interrupts enabled corresponding queue, QADC asserts interrupt request level specified IRL1 interrupt register. software read during interrupt service routine identify interrupt request. interrupt request cleared when software writes zero PF1, when previously read one. Once set, only software reset clear PF1. maintained QADC regardless whether corresponding interrupts enabled. software poll find when QADC reached pause scanning queue. software acknowledges that detected pause flag being writing zero after last read one. Queue reached pause. Queue reached pause.
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Queue Completion Flag indicates that queue scan been completed. QADC when input channel sample requested last queue converted, result stored result table. queue identified when current contains end-of-queue code instead valid channel number, when currently completed last location RAM. When interrupts enabled that queue completion flag, QADC asserts interrupt request level specified IRL2 interrupt register (QADCINT). software reads during interrupt service routine identify interrupt request. interrupt request cleared when software writes zero bit, when previously read one. Once set, only software reset clear CF2. maintained QADC regardless whether corresponding interrupts enabled. software polls set. This allows software recognize that QADC finished with queue scan. software acknowledges that detected completion flag being writing zero completion flag after read one. Refer SECTION INTERRUPTS more information. Queue scan complete. Queue scan complete. Queue Pause Flag indicates that queue scan reached pause. QADC when current queue pause set, selected input channel been converted, result been stored result table. Once set, queue enters paused state waits trigger event allow queue execution continue. However, with pause last queue, queue execution complete. queue status becomes idle, paused, both pause completion flags set. When interrupts enabled corresponding queue, QADC asserts interrupt request level specified IRL2 interrupt register. software reads during interrupt service routine identify interrupt request. interrupt request cleared when software writes zero PF2, when previously read one. Once set, only software reset clear PF2. maintained QADC regardless whether corresponding interrupts enabled. software poll find when QADC reached pause scanning queue. software acknowledges that detected pause flag being writing zero after last read one. Queue reached pause. Queue reached pause.
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TOR1 Queue Trigger Overrun TOR1 indicates that unexpected trigger event occurred queue TOR1 only while queue active state. trigger event generated transition external trigger periodic/ interval timer recorded trigger overrun. TOR1 only occur when using external trigger mode. TOR1 cannot occur when software initiated single-scan mode software initiated continuous-scan mode selected. TOR1 occurs when trigger event received while queue executing before scan completed paused. TOR1 also occur when trigger event occurred queue, execution begun. TOR1 effect queue execution.
After trigger event occurred queue before scan completed paused, additional queue trigger events retained. Such trigger events considered unexpected, QADC sets TOR1 error status bit. unexpected trigger event system overrun situation, indicating system loading mismatch. software acknowledges that detected trigger overrun being writing zero trigger overrun, after read one. Once set, only software reset clear TOR1. unexpected queue trigger events have occurred. least unexpected queue trigger event occurred. TOR2 Queue Trigger Overrun TOR2 indicates that unexpected trigger event occurred queue TOR2 when queue active, suspended, trigger pending states. TOR2 trigger overrun only occur when using external trigger mode periodic/interval timer mode. Trigger overruns cannot occur when software initiated single-scan mode software initiated continuous-scan mode selected. TOR2 occurs when trigger event received while queue executing before scan completed paused. TOR2 also occurs when trigger event occurred queue, execution begun. TOR2 effect queue execution. trigger event that causes trigger overrun retained since considered unexpected. After trigger event occurred queue before scan completed paused, additional queue trigger events retained, considered unexpected. Also, when queue trigger event pending, queue active, additional queue trigger events considered unexpected. both cases, QADC sets TOR2 error status bit. unexpected trigger event system overrun situation, indicating system loading mismatch. software acknowledges that detected trigger overrun being writing zero trigger overrun, after read one. Once set, only software reset clear TOR2. unexpected queue trigger events have occurred. least unexpected queue trigger event occurred.
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MOTOROLA 7-23
QS[9:6] Queue Status 4-bit read-only field indicates current condition queue queue following five queue status conditions: Idle Active Paused Suspended Trigger pending most significant bits associated primarily with queue remaining bits associated with queue Since priority scheme between queues causes status interlinked, status bits considered 4-bit field.
Table shows bits field they affect status queue queue Refer SECTION QUEUE PRIORITY EXAMPLES, which shows 4-bit queue status field transitions typical situations. Table Queue Status
QS[9:6] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Queue 1/Queue States Queue idle, Queue idle Queue idle, Queue paused Queue idle, Queue active Queue idle, Queue trigger pending Queue paused, Queue idle Queue paused, Queue paused Queue paused, Queue active Queue paused, Queue trigger pending Queue active, Queue idle Queue active, Queue paused Queue active, Queue suspended Queue active, Queue trigger pending Reserved Reserved Reserved Reserved
both queues idle state. When queue idle, CCWs being executed that queue, queue pause state, there trigger pending. idle state occurs when queue disabled, when queue reserved mode, when queue valid queue operating mode awaiting trigger event initiate queue execution. queue active state when valid queue operating mode selected, when selected trigger event occurred, when QADC performing conversion specified from that queue.
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Only queue active time. Either both queues paused state. queue paused when previous executed from that queue pause set. QADC does execute CCWs from paused queue until trigger event occurs. Consequently, QADC service queue while queue paused. Only queue suspended state. When trigger event occurs queue while queue executing, current queue conversion aborted. queue status reported suspended. Queue transitions back active state when queue becomes idle paused. trigger pending state required since both queues cannot active same time. status queue changed trigger pending when trigger event occurs queue while queue active. opposite case, when trigger event occurs queue while queue active, queue aborted status reported queue active, queue suspended. priority scheme, only queue trigger pending state. There transition cases which cause queue status trigger pending before queue shown active state. When queue active there trigger pending queue after queue completes pauses, queue continues trigger pending state clock cycles. following fleeting status conditions: Queue idle with queue trigger pending. Queue paused with queue trigger pending. Figure displays status conditions queue status field QADC goes through transition from queue a
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