Modular Microcontroller Family !MOTOROLA Modular Microcontro
|
|
|
Top Searches for this datasheet
CTMRM/D
Modular Microcontroller Family
!MOTOROLA
Modular Microcontroller Family CREFERENCE MANUAL
CCONFIGURABLE TIMER MODULE
REFERENCE MANUAL
More Information This Product, www.freescale.com
!MOTOROLA
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. FUNCTIONAL OVERVIEW INTERFACE UNIT SUBMODULE (BIUSM) INTERRUPTS COUNTER PRESCALER SUBMODULE (CPSM) FREE-RUNNING COUNTER SUBMODULE (FCSM) MODULUS COUNTER SUBMODULE (MCSM) SINGLE ACTION SUBMODULE (SASM) DOUBLE ACTION SUBMODULE (DASM) PULSE WIDTH MODULATION SUBMODULE (PWMSM) ELECTRICAL SPECIFICATIONS REGISTER SUMMARY CEXAMPLE CTM2 GLOSSARY INDEX
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. FUNCTIONAL OVERVIEW INTERFACE UNIT SUBMODULE (BIUSM) INTERRUPTS COUNTER PRESCALER SUBMODULE (CPSM) FREE-RUNNING COUNTER SUBMODULE (FCSM) MODULUS COUNTER SUBMODULE (MCSM) SINGLE ACTION SUBMODULE (SASM) DOUBLE ACTION SUBMODULE (DASM) PULSE WIDTH MODULATION SUBMODULE (PWMSM) ELECTRICAL SPECIFICATIONS REGISTER SUMMARY CEXAMPLE CTM2 GLOSSARY INDEX
More Information This Product, www.freescale.com
CConfigurable Timer Module
Reference Manual
Trade Marks recognized. This document contains information products. Specifications information herein subject change without notice.
products sold Motorola's Terms Conditions Supply. ordering product covered this document Customer agrees bound those Terms Conditions nothing contained this document constitutes forms part contract (with exception contents this Notice). copy Motorola's Terms Conditions Supply available request.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals", must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola !are registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Customer should ensure that most date version document contacting local Motorola office. This document supersedes earlier documentation relating products referred herein. information contained this document current date publication. subsequently updated, revised withdrawn.
MOTOROLA LTD., 1997
GJL-ekb
More Information This Product, www.freescale.com
Conventions
Where abbreviations used text, explanation found glossary, back this document. Register mnemonics defined paragraphs describing them. horizontal over signal name indicates that signal active-low, e.g. RESET. Unless stated otherwise, shaded cells register diagram indicate that bits either unimplemented bits reserved, always read zero. register diagrams, indicates that state reset undefined. When `set', value (one). When `clear', value (zero). When `reset', default value, which
Reference documents
CPU16 Central Processor Unit Reference Manual (CPU16RM/D) CPU32 Central Processor Unit Reference Manual (CPU32RM/AD) General Purpose Timer Reference Manual (GPTRM/AD) introduction HC16 HC11 users (AN461/D)
More Information This Product, www.freescale.com
CTMLOP
-this line does form part document-
11/Nov/97@15:52
CUSTOMER FEEDBACK QUESTIONNAIRE (CTMRM)
Motorola wishes continue improve quality documentation. would welcome your feedback publication have just received. Having used document, please complete this card photocopy prefer). would rate quality document? Check each category. Excellent Organization Readability Understandability Accuracy Illustrations Comments: Poor Tables Table contents Index Page size/binding Overall impression Excellent Poor
What your intended this document? more than option applies, please rank them Selection device application System design Training purposes Other Please specify:
well does this manual enable perform task(s) outlined question Completely Comments:
along this line remove
easy find information looking for? Easy Difficult Comments:
level technical detail following sections sufficient allow understand device functions? little detail Table Contents/List Figures/List Tables SECTION SECTION SECTION SECTION SECTION SECTION SECTION SECTION SECTION SECTION APPENDIX APPENDIX APPENDIX APPENDIX Comments: FUNCTIONAL OVERVIEW INTERFACE UNIT SUBMODULE (BIUSM) INTERRUPTS COUNTER PRESCALER SUBMODULE (CPSM) FREE-RUNNING COUNTER SUBMODULE (FCSM) MODULUS COUNTER SUBMODULE (MCSM) SINGLE ACTION SUBMODULE (SASM) DOUBLE ACTION SUBMODULE (DASM) PULSE WIDTH MODULATION SUBMODULE (PWMSM) ELECTRICAL SPECIFICATIONS REGISTER SUMMARY CEXAMPLE CTM2 GLOSSARY INDEX much detail
Have found errors? please comment:
From your point view, anything missing from document? please what:
More Information This Product, www.freescale.com
11/Nov/97@15:52
-this line does form part document-
CTMLOP
could improve this document?
would rate Motorola's documentation? Excellent general Against other semiconductor suppliers Poor
Which semiconductor manufacturer provides best technical documentation? Which company field) provides best technical documentation? many years have worked with microprocessors? Less than year years years More than years
Second fold back along this line
mail avion
IBRS NUMBER PHQ-B/207/G CCRI NUMERO PHQ-B/207/G
AFFRANCHIR
STAMP REQUIRED
First fold back along this line
along this line remove
REPONSE PAYEE GRANDE-BRETAGNE
SECTION
MOTOROLA LTD. Semiconductor Products Sector
Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, 8BR. GREAT BRITAIN. F.A.O. Technical Publications Manager (re: CTMRM/D)
Third fold back along this line
Currently there some discussion semiconductor industry regarding move towards providing data sheets electronic form. have opinion this subject, please comment.
would grateful would supply following information your discretion), attach your card. Name: Position: Department: Company: Address: Phone
Thank helping improve documentation, Graham Livey, Technical Publications Manager, Motorola Ltd., Scotland.
More Information This Product, www.freescale.com GoLast tuck this edge into opposite flap
TABLE CONTENTS
Paragraph Number Title Page Number
FUNCTIONAL OVERVIEW
1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.10 Cfeatures .1-1 Cdescription .1-2 Byte/word/long word accesses .1-3 8-bit (byte) accesses .1-3 16-bit (word) aligned accesses .1-4 16-bit (word) misaligned accesses.1-4 32-bit (long word) aligned accesses .1-5 32-bit (long word) misaligned accesses .1-5 3-byte accesses .1-5 time base system.1-5 descriptions .1-6 Input capture (IC) concepts .1-6 Output compare (OC) concepts.1-7 Pulse accumulator (PA) concepts .1-8 Pulse width modulation (PWM) concepts .1-9 Using clearing flag bits .1-10
INTERFACE UNIT SUBMODULE (BIUSM)
2.5.1 2.5.2 2.5.3 BIUSM description.2-1 Freeze action BIUSM.2-1 LPSTOP action BIUSM.2-1 STOP WAIT action BIUSM .2-2 BIUSM registers .2-2 BIUMCR BIUSM module configuration register .2-2 BIUTEST BIUSM test configuration register .2-4 BIUTBR BIUSM time base register .2-5
CREFERENCE
More Information This Product, www.freescale.com
TABLE CONTENTS
MOTOROLA
Paragraph Number Page Number
Title
INTERRUPTS
Interrupt levels IMB.3-1 Arbitration .3-2 Cdaisy-chain priority.3-2
COUNTER PRESCALER SUBMODULE (CPSM)
CPSM description.4-1 Freeze action CPSM.4-2 CPSM registers .4-2 4.3.1 CPCR CPSM control register.4-2 4.3.2 CPTR CPSM test register .4-3
FREE-RUNNING COUNTER SUBMODULE (FCSM)
5.3.1 5.7.1 5.7.2 FCSM description.5-1 FCSM counter .5-1 FCSM clock sources.5-2 FCSM external event counting.5-2 FCSM time base driver.5-3 FCSM interrupts .5-3 Freeze action FCSM.5-3 FCSMSIC FCSM status/interrupt/control register .5-4 FCSMCNT FCSM counter register .5-6
MODULUS COUNTER SUBMODULE (MCSM)
MCSM description .6-1 MCSM modulus latch .6-2 MCSM counter .6-2 6.3.1 Loading MCSM counter register .6-2 6.3.1.1 Using MCSM free-running counter.6-3 MCSM clock sources.6-3 6.4.1 MCSM external event counting.6-3 MCSM time base driver .6-4
MOTOROLA
More Information This Product, www.freescale.com
TABLE CONTENTS
CREFERENCE
Paragraph Number Page Number
Title
MCSM interrupts.6-4 Freeze action MCSM .6-4 MCSM registers .6-4 6.8.1 MCSMSIC MCSM status/interrupt/control register.6-5 6.8.2 MCSMCNT MCSM counter register .6-7 6.8.3 MCSMML MCSM modulus latch register .6-8
SINGLE ACTION SUBMODULE (SASM)
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.5.1 7.5.2 7.5.3 7.5.4 SASM description .7-1 SASM modes operation.7-2 Clearing using FLAG bits .7-2 Input capture (IC) mode .7-4 Output compare (OC) mode .7-4 Output compare toggle (OCT) mode .7-5 Output port (OP) mode .7-5 SASM interrupts .7-6 Freeze action SASM .7-6 SASM registers.7-6 SICA SASM status/interrupt/control register A.7-7 SDATA SASM data register A.7-10 SICB SASM status/interrupt/control register B.7-10 SDATB SASM data register .7-11
DOUBLE ACTION SUBMODULE (DASM)
DASM description .8-2 32-bit coherent access .8-3 DASM modes operation.8-3 8.3.1 Disable (DIS) mode.8-4 8.3.2 Input pulse width measurement (IPWM) mode.8-4 8.3.3 Input period measurement (IPM) mode .8-5 8.3.4 Input capture (IC) mode .8-7 8.3.5 Output compare (OCB OCAB) modes .8-7 8.3.5.1 Single shot output pulse operation .8-8 8.3.5.2 Single output compare operation .8-9 8.3.5.3 Output port operation .8-9 8.3.6 Output pulse width modulation (OPWM) mode.8-10 DASM interrupts .8-12 Freeze action DASM.8-13
CREFERENCE
More Information This Product, www.freescale.com
TABLE CONTENTS
MOTOROLA
Paragraph Number Page Number
Title
DASM registers .8-13 8.6.1 DASMSIC DASM status/interrupt/control register .8-14 8.6.2 DASMA DASM data register .8-18 8.6.3 DASMB DASM data register .8-18 DASM examples .8-20 8.7.1 mode example.8-20 8.7.2 mode example .8-21 8.7.3 mode example.8-22 8.7.4 mode example.8-24
PULSE WIDTH MODULATION SUBMODULE (PWMSM)
PWMSM features .9-1 PWMSM description.9-2 9.2.1 Output flip-flop pin.9-2 9.2.2 Clock selection.9-2 9.2.3 PWMSM counter (PWMC).9-3 9.2.4 PWMSM period registers comparator.9-4 9.2.5 PWMSM pulse width registers comparator.9-4 9.2.5.1 100% `pulses' .9-5 9.2.6 PWMSM coherency .9-5 9.2.7 PWMSM interrupts.9-6 9.2.8 Freeze action PWMSM .9-6 frequency, pulse width resolution.9-6 9.3.1 frequency .9-7 9.3.2 pulse width .9-7 9.3.3 period pulse width register values.9-8 PWMSM register registers.9-9 9.4.1 PWMSIC Status, interrupt control register .9-9 9.4.2 PWMA period register .9-12 9.4.3 PWMB pulse width register .9-13 9.4.4 PWMC counter register .9-14
ELECTRICAL SPECIFICATIONS
10.1 10.2 10.3 10.4 FCSM MCSM timing information .10-1 SASM timing information.10-6 DASM timing information .10-9 PWMSM timing information .10-12
MOTOROLA
More Information This Product, www.freescale.com
TABLE CONTENTS
CREFERENCE
Paragraph Number Page Number
Title
APPENDIX REGISTER SUMMARY
BIUSM registers bits. A.1.1 BIUMCR BIUSM module configuration register A.1.1.1 STOP Stop enable. A.1.1.2 Freeze enable. A.1.1.3 VECT7, VECT6 Interrupt vector base number bits. A.1.1.4 IARB[2:0] Interrupt arbitration identification bits A.1.1.5 TBRS1, TBRS0 Time base register select bits A.1.2 BIUTEST BIUSM test configuration register A.1.3 BIUTBR BIUSM time base register CPSM registers bits. A.2.1 CPCR CPSM control register. A.2.1.1 PRUN Prescaler running A.2.1.2 DIV23 Divide divide bit. A.2.1.3 PSEL1, PSEL0 Prescaler division ratio select bits A.2.2 CPTR CPSM test register FCSM registers bits A.3.1 FCSMSIC FCSM status/interrupt/control register A.3.1.1 Counter overflow flag A.3.1.2 IL[2:0] Interrupt level bits A.3.1.3 IARB3 Interrupt arbitration A.3.1.4 DRVA, DRVB Drive time base bits A.3.1.5 Input status bit. A.3.1.6 CLK[2:0] Counter clock select bits. A.3.2 FCSMCNT FCSM counter register MCSM registers bits A.4.1 MCSMSIC MCSM status/interrupt/control register. A.4.1.1 Counter overflow flag A.4.1.2 IL[2:0] Interrupt level bits A.4.1.3 IARB3 Interrupt arbitration A.4.1.4 DRVA, DRVB Drive time base bits A.4.1.5 Clock input status A.4.1.6 Modulus load input status bit. A.4.1.7 EDGEN, EDGEP Modulus load edge sensitivity bits. A.4.1.8 CLK[2:0] Counter clock select bits. A.4.2 MCSMCNT MCSM counter register. A.4.3 MCSMML MCSM modulus latch register SASM registers bits A.5.1 SICA SASM status/interrupt/control register A.5.1.1 FLAG Event flag bit. A.5.1.2 IL[2:0] Interrupt level bits A.5.1.3 IARB3 Interrupt arbitration A.5.1.4 Interrupt enable bit. A.5.1.5 Time base select A-10
MOTOROLA
More Information This Product, www.freescale.com
TABLE CONTENTS
CREFERENCE
Paragraph Number Page Number
Title
A.5.1.6 Input status bit. A-10 A.5.1.7 FORCE Force compare control A-10 A.5.1.8 EDOUT Edge detect output level bit. A-10 A.5.1.9 MODE1, MODE0 SASM operating mode select bits. A-10 A.5.2 SDATA SASM data register A-11 A.5.3 SICB SASM status/interrupt/control register A-11 A.5.3.1 FLAG Event flag bit. A-11 A.5.3.2 Time base select A-11 A.5.3.3 Input status bit. A-11 A.5.3.4 FORCE Force compare control A-12 A.5.3.5 EDOUT Edge detect output level bit. A-12 A.5.3.6 MODE1, MODE0 SASM operating mode select bits. A-12 A.5.4 SDATB SASM data register A-12 DASM registers bits. A-13 A.6.1 DASMSIC DASM status/interrupt/control register A-13 A.6.1.1 FLAG Flag status A-13 A.6.1.2 IL[2:0] Interrupt level bits A-13 A.6.1.3 IARB3 Interrupt arbitration A-13 A.6.1.4 Wired-OR A-13 A.6.1.5 select A-14 A.6.1.6 Input status bit. A-14 A.6.1.7 FORCA Force bit. A-14 A.6.1.8 FORCB Force bit. A-14 A.6.1.9 EDPOL Edge polarity bit. A-14 A.6.1.10 MODE[3:0] Mode select bits. A-15 A.6.2 DASMA DASM data register A-15 A.6.3 DASMB DASM data register A-16 PWMSM registers bits A-17 A.7.1 PWMSIC PWMSM status, interrupt control register. A-17 A.7.1.1 FLAG Period completion status A-17 A.7.1.2 IL[2:0] Interrupt level bits A-17 A.7.1.3 IARB3 Interrupt arbitration A-17 A.7.1.4 Output status bit. A-17 A.7.1.5 LOAD Period pulse width register load control A-18 A.7.1.6 Output polarity control bit. A-18 A.7.1.7 PWMSM enable control A-18 A.7.1.8 CLK[2:0] Clock rate selection bits. A-19 A.7.2 PWMA period register A-19 A.7.3 PWMB pulse width register A-19 A.7.4 PWMC counter register A-20
MOTOROLA
More Information This Product, www.freescale.com
TABLE CONTENTS
CREFERENCE
Paragraph Number Page Number
Title
APPENDIX CEXAMPLE CTM2
CTM2 registers B.1.1 CTM2 interface unit submodule registers. B.1.2 CTM2 counter prescaler submodule registers B.1.3 CTM2 free-running counter submodule registers B.1.4 CTM2 modulus counter submodule registers B.1.5 CTM2 double action submodule registers
APPENDIX GLOSSARY APPENDIX INDEX
CREFERENCE
More Information This Product, www.freescale.com
TABLE CONTENTS
MOTOROLA
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA viii
More Information This Product, www.freescale.com
TABLE CONTENTS
CREFERENCE
LIST FIGURES
Figure Number 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 Title Page Number
Carchitecture block diagram.1-2 8-bit (byte) access (even addresses).1-3 8-bit (byte) access (odd addresses) .1-4 16-bit (word) aligned access.1-4 Simplified block diagram 16-bit input capture .1-7 Simplified block diagram 16-bit output compare.1-7 Simplified block diagram typical pulse accumulator .1-8 example waveforms .1-9 Simplified block diagram typical 16-bit system .1-10 CPSM block diagram .4-1 FCSM block diagram .5-2 MCSM block diagram .6-1 SASM block diagram .7-1 SASM block diagram (channel A).7-3 DASM block diagram .8-1 Input pulse width measurement example .8-5 Input period measurement example .8-6 DASM input capture example .8-7 Single-shot output pulse example .8-9 Single shot output transition example.8-10 DASM output pulse width modulation example .8-11 Pulse width modulation submodule block diagram.9-3 FCSM MCSM time base timing diagram example.10-3 FCSM MCSM clock counter timing diagram .10-4 MCSM load counter timing diagram .10-4 FCSM MCSM timing diagram.10-5 FCSM MCSM interrupt request timing diagram .10-5 SASM input capture timing diagram .10-7 SASM timing diagram.10-7 SASM output compare timing diagram.10-8 SASM FLAG interrupt request timing diagram .10-8 DASM input capture timing diagram .10-10 DASM timing diagram.10-10
CREFERENCE
More Information This Product, www.freescale.com
LIST FIGURES
MOTOROLA
Figure Number 10-12 10-13 10-14 10-15 10-16 10-17 Page Number
Title
DASM output compare timing diagram. 10-11 DASM FLAG interrupt request timing diagram 10-11 PWMSM minimum output pulse example timing diagram 10-13 PWMSM CPSM enable output timing diagram 10-13 PWMSM enable output timing diagram 10-14 PWMSM FLAG interrupt request timing diagram 10-14 Configurable timer module (CTM2) .B-2
MOTOROLA
More Information This Product, www.freescale.com
LIST FIGURES
CREFERENCE
LIST TABLES
Table Number 10-1 10-2 10-3 10-4 10-5 Title Page Number
BIUSM register .2-2 Csubmodule interrupt vector number convention.3-3 CPSM register .4-2 FCSM register .5-4 MCSM register map.6-5 SASM register .7-7 DASM modes operation.8-3 DASM example output frequencies/resolutions fSYS MHz.8-12 DASM register .8-13 pulse frequency ranges using option (16.78 MHz).9-6 pulse frequency ranges using option (16.78 MHz).9-7 PWMSM register .9-9 PWMSM output polarity selection.9-11 PWMSM clock rate selection .9-13 FCSM timing characteristics.10-1 MCSM timing characteristics .10-2 SASM timing characteristics.10-6 DASM timing characteristics.10-9 PWMSM timing characteristics.10-12 Time base allocation. CTM2 interrupt priority, vector allocation allocation CTM2 register map. BIUSM register CPSM register FCSM register MCSM register map. DASM register
CREFERENCE
More Information This Product, www.freescale.com
LIST TABLES
MOTOROLA
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
More Information This Product, www.freescale.com
LIST TABLES
CREFERENCE
FUNCTIONAL OVERVIEW
configurable timer module (CTM) integral module Motorola's family modular microcontrollers. Members this family normally composed several modules, interconnected means intermodule (IMB). unusual sense that itself, modular composed submodules, making easily configurable different kinds applications.
Cfeatures
Modular architecture Counter submodules: Clock prescaler 16-bit free-running counter 16-bit modulus counter
Action submodules: Single action input capture/output compare channels Double action input capture/output compare channels, with (pulse width modulation) mode channels
each input capture/output compare Output-only each channel External clock input capability Interrupt capability capture/compare/PWM channels counter overflow conditions Two, three four time base buses, allowing great flexibility Cconfiguration
CREFERENCE
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
MOTOROLA
Cdescription
highly modular architecture illustrated Figure 1-1. Submodules located either side CTM's internal submodule (SMB). data control signals within Care passed over this bus. connected outside world special Csubmodule, known interface unit submodule (BIUSM), which connected intermodule (IMB) hence main CPU. This configuration allows access data control registers each Csubmodule SMB.
Time base (TBBA) Time base (TBBB)
Submodule Submodule (SMB)
Submodule Time base (TBB3)
Submodule Time base (TBB1) Time base (TBB2)
Submodule
Submodule
Submodule
interface unit submodule (BIUSM)
Intermodule (IMB)
Figure Carchitecture block diagram
Four local time base buses (TBB1 TBB4) arranged such that each Csubmodule connected them. seen Figure 1-1, Csubmodules numbered connected TBB3 TBB4 Csubmodules connected TBB1 TBB2. Control bits within each Csubmodule allow software connect submodule desired time base bus(es). During design Cmodule, four local time base
MOTOROLA
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
CREFERENCE
Time base (TBB4)
buses connected together shown dotted lines Figure 1-1) form time base buses TBBA (TBB1/TBB4) TBBB (TBB2/TBB3). time base buses each 16-bits wide used transfer timing information from counters action submodules. Each Csubmodule either clock source module (and drive time base buses) action submodule (and read react timing information time base buses). Every Cmodule implementation must include least BIUSM some form clock submodule. other submodules optional would selected from library Csubmodules design stage, required user meet needs application.
Byte/word/long word accesses
Cregisters data buses bits wide. Consequently, 16-bit (word) accesses normal case. 8-bit 32-bit accesses also permitted; however, there pipelining CTM, 8-bit coherency supported.
1.3.1
8-bit (byte) accesses
8-bit accesses illustrated Figure even addresses Figure addresses.
Read ($00) DATA
Cregister
DATA
Write
Read DATA 15:8 DATA 15:8
Read DATA 15:8
Write
Write
Figure 8-bit (byte) access (even addresses)
1.3.2
16-bit (word) aligned accesses
16-bit aligned access normal case such accesses counter action submodule registers coherent. This illustrated Figure 1-4.
CREFERENCE
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
DATA
MOTOROLA
Read
Read DATA
Cregister
DATA
Write
Write
Read ($00) DATA 15:8 DATA 15:8 DATA 15:8 Cregister DATA 15:0
Write
Figure 8-bit (byte) access (odd addresses)
DATA 15:0
Read write
DATA 15:0
Read write
Figure 16-bit (word) aligned access
1.3.3
16-bit (word) misaligned accesses
16-bit misaligned access consists 8-bit accesses, first address (see Figure 1-3), second following even address (see Figure 1-2). 16-bit misaligned access treated 8-bit address access. then responsibility master access following byte. case 8-bit access, since there pipelining, coherency supported.
Note:
Neither CPU16 CPU32 (see section reference documents beginning this document) support 16-bit misaligned accesses.
MOTOROLA
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
DATA
CREFERENCE
1.3.4 32-bit (long word) aligned accesses
long word aligned access consists 16-bit aligned accesses (see Figure 1-4). When long word access attempted, signal line activated during access high order byte. This allows Carchitecture compatible with submodules supporting long word coherency.
1.3.5
32-bit (long word) misaligned accesses
long word misaligned access consists three accesses: first byte access address (see Figure 1-3), followed 16-bit aligned access following even address (see Figure 1-4), followed byte access remaining even address (see Figure 1-2). Note that latter accesses (16-bit aligned access followed byte access even address) represent what called 3-byte access. there pipelining, coherency supported.
Note:
Neither CPU16 CPU32 support 32-bit misaligned accesses.
1.3.6
3-byte accesses
3-byte access normally part long word misaligned access. consists 16-bit aligned access (see Figure 1-4), followed byte access remaining even address (see Figure 1-2). 3-byte access treated BIUSM 16-bit aligned access. then responsibility master access following byte. there pipelining, coherency supported.
time base system
time base system composed four 16-bit buses: TBB1, TBB2, TBB3 TBB4 (see Figure 1-1). Typically, TBB2 TBB3 tied together form global (TBBB) while TBB1 TBB4 remain partial buses (collectively called TBBA). submodules connected these time base buses different each Cconfiguration. This shown generically Figure 1-1, where counter action submodules right half diagram (numbered from M-1) connected TBB3 and/or TBB4, submodules left half diagram (numbered from connected TBB1 and/or TBB2. example time base buses configured submodules connected them practical Cmodule (CTM2) provided Appendix time base buses precharge/discharge type buses with wired-OR capability, that hardware damage occurs when several counters driving same same time.
CREFERENCE
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
MOTOROLA
Depending software options, counter action submodules located left half Figure (submodules connected buses TBB1 TBB2, while counter action submodules located right half Figure (submodules M-1) connected buses TBB3 TBB4.
descriptions
Input/output requirements specific each Csubmodule; allocation functionality described relevant sections this document.
Input capture (IC) concepts
typical 16-bit input capture function shown Figure 1-5. three basic parts: edge select logic, 16-bit input capture latch 16-bit free-running counter. edge select logic determines input signal transition (rising falling) that triggers input capture circuitry. When selected transition occurs, contents counter latched into input capture latch. This action sets status flag indicating that input capture occurred. interrupt generated enabled. value count latched `captured' time event. Because this value stored input capture register when actual event occurs, user software respond this event later time determine actual time event. However, this must done prior another input capture same pin; otherwise, previous time value will lost. recording times successive edges incoming signal, software determine period and/or pulse width signal. measure period, successive edges same polarity captured. measure pulse width, consecutive edges opposing polarity captured. example, measure high time pulse, input transition time captured rising edge subtracted from time captured subsequent falling edge. When period pulse width less than full 16-bit counter overflow period, measurement very straightforward. practice, however, software usually must keep track number overflows 16-bit counter order extend range. Another typical input capture function establish time reference. this case used conjunction with output compare function same timer. example, consider case where required generate output signal transition specific number clock cycles after detecting event (edge). input capture function used record time which event occurred. number corresponding desired delay then added this captured value stored output compare register. Because input capture output compare functions referenced same 16-bit counter, delay controlled resolution free-running counter, independent software latencies.
MOTOROLA
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
CREFERENCE
Clock 16-bit free-running counter
Event
Edge select logic
Input capture latch
Data
Figure Simplified block diagram 16-bit input capture
Output compare (OC) concepts
Output compare functions used cause events occur specific times, i.e. cause signal transitions occur output pin. typical 16-bit output compare function shown Figure 1-6; comprises 16-bit compare register, 16-bit comparator 16-bit free-running counter. When value stored compare register matches value free-running counter, comparator sets output compare flag. Other events occur when output compare flag set: interrupt generated interrupts enabled) logic levels pins associated with output compare function change.
Clock 16-bit free running counter
16-bit comparator
Output match
16-bit output compare register
Figure Simplified block diagram 16-bit output compare
output compare function generate output specific duration polarity. 16-bit value corresponding time when state change will occur written output
CREFERENCE
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
MOTOROLA
compare register. output compare function configured generate high output automatically pin, toggle state pin, when match occurs. output compare register loaded with value after compare occurs. Typically, more than output compare function associated with each pin; because state changes occur automatically specific values free-running counter, pulse width controlled resolution free-running counter independent software latencies. periodic pulse specific frequency duty cycle generated repeating above steps.
Pulse accumulator (PA) concepts
Pulse accumulator systems usually based bits. typical 16-bit pulse accumulator shown Figure 1-7; consists 16-bit counter edge select logic, modes operation: event counting mode gated mode. event counting mode, counter incremented each time event occurs. gated mode, internal clock source increments counter while selected level present input (the gate). When signal input negated, counter stopped. status flags available: indicate occurrence event, other indicate counter overflow. Either these flags cause processor interrupted.
Clock
Event 16-bit counter Event Event counting mode
16-bit counter
Gated time accumulator mode
Figure Simplified block diagram typical pulse accumulator
pulse accumulator used, example, count number items going conveyor belt number teeth that have gone crankshaft timing gear. each item tooth detected, counter incremented (event counting mode). counter therefore contains number items teeth). flag indicates occurrence event item tooth went by). interrupts enabled, interrupt generated. Software read counter this time.
MOTOROLA
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
CREFERENCE
gated mode operation used measure pulse width period input signal. When input pulse accumulator active, counter begins counting input clock. When signal negated stops counting. counter zero before pulse starts, count value multiplied clock period gives width input pulse nearest clock period. This could used determine long stimulus present. 8-bit pulse accumulator only events counted before counter overflows; overflow flag used extend counter range beyond this value required.
Pulse width modulation (PWM) concepts
waveform created when mark-to-space ratio periodic rectangular signal varied. waveform incrementally changed 1/65536 period, bits resolution (see Figure 1-8).
65536 increments
1/65536 32768/65536
Figure example waveforms
typical 16-bit system (Motorola's General Purpose Timer, GPT) shown Figure 1-9. Each time counter overflows from $FFFF $0000, zero detector sets output latch (output high state). zero detector used reference start high time. counter incremented, counter value compared with contents pulse width register. When comparator detects match, latch reset. changing value pulse width register, duty cycle continuously variable 1/65536 increments. pulse width register contains $0000, output latch will always reset condition (output state). pulse width register loaded with $0001, output latch will count before being reset remainder period. register contains $8000 (32768 decimal), latch will 32768 counts timer before being reset, resulting duty cycle 50%. Provision usually made allow 100% duty cycle (output latch always set; output always high) generated. Varying input clock frequency counter also varies period signal.
CREFERENCE
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
MOTOROLA
16-bit pulse width register
Output
Latch
16-bit comparator
Zero detector
Clock
Output compare register
Figure Simplified block diagram typical 16-bit system
Typically, systems provided with increased flexibility additional features such output polarity selection, variable resolution variable pulse periods.
1.10
Using clearing flag bits
clear flag CTM, software must first read register containing flag question (usually register), then write zero flag bit. These steps have done consecutive instructions. Writing flag effect.
Note:
flag clearing mechanism will work only flag setting event occurs between read write operations; flag setting event occurs between read write operations, flag will cleared.
MOTOROLA 1-10
More Information This Product, www.freescale.com
FUNCTIONAL OVERVIEW
CREFERENCE
INTERFACE UNIT SUBMODULE (BIUSM)
BIUSM description
BIUSM connects CTM's allows Csubmodules communicate with master (usually CPU). BIUSM also communicates interrupt requests, from Csubmodules IMB, transfers interrupt level, arbitration vector number during interrupt acknowledge cycle. BIUSM contains module configuration register, time base register test register (for factory testing only).
Freeze action BIUSM
When freeze condition detected, BIUSM module configuration register determines whether freeze condition passed other Csubmodules. freeze condition ignored; BIUSM passes FREEZE signal from through Csubmodules. Each Csubmodule then reacts FREEZE signal defined internal circuitry control bits.
LPSTOP action BIUSM
When stopped LPSTOP instruction (from CPU32 CPU16), system clock (fSYS) stopped, thereby shutting down dependent modules, including CTM, until low-power STOP mode exited.
CREFERENCE
More Information This Product, www.freescale.com
INTERFACE UNIT SUBMODULE (BIUSM)
MOTOROLA
STOP WAIT action BIUSM
When STOP instruction CPU32 WAIT instruction CPU16 executed, only stopped; Ccontinues operate normal. stop Coperation selectively, refer description STOP Section 2.5.1).
BIUSM registers
BIUSM register comprises four 16-bit register locations. shown Table 2-1, register block contains three BIUSM registers reserved register. BIUSM register block always occupies first four register locations Cregister space cannot relocated within Cstructure. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations effect.
Note:
BIUSM register addresses this section specified offsets from base address CTM.
Table BIUSM register
Address BIUSM module configuration register (BIUMCR) BIUSM test register (BIUTEST) BIUSM time base register (BIUTBR)
Offset from base address CTM.
2.5.1
BIUMCR BIUSM module configuration register
BIUMCR register contains nine defined bits that allow software control five functions CTM: enabling/disabling module, response FREEZE, vector base address, interrupt arbitration number access time base buses (via time base register).
Bit: BIUMCR Reset: TBRS1 TBRS0
STOP
VECT7 VECT6 IARB2 IARB1 IARB0
Offset from base address CTM.
MOTOROLA
INTERFACE UNIT SUBMODULE (BIUSM)
More Information This Product, www.freescale.com
CREFERENCE
STOP Stop enable STOP bit, while asserted, activates FREEZE signal regardless state FREEZE signal IMB. This completely stops operation CTM. Note that some submodules validate this signal with internal enable bits. BIUSM continues operate allow access submodule's registers. FREEZE signal remains active until reset until STOP negated (via IMB). STOP cleared reset. (set) Stops operation CTM. Allows operation CTM.
(clear)
Freeze enable bit, while asserted, activates FREEZE signal when FREEZE signal active. This completely stops operation CTM. Note that some submodules validate this signal with internal enable bits. BIUSM continues operate allow access submodule's registers. FREEZE signal remains active until cleared FREEZE signal negated. cleared reset. (set) Halts Csub module when FREEZE signal appears IMB. Ignores FREEZE signal IMB.
(clear)
VECT7, VECT6 Interrupt vector base number bits interrupt vector base number bits select interrupt vector base number CTM. bits necessary vector number definition, least significant bits programmed hardware submodule basis, while remaining bits provided VECT7 VECT6. This places Cvectors four possible positions interrupt vector table, follows.
VECT7
VECT6
Resulting vector base number
Note:
reader should refer also Section relevant reference manuals more detailed information interrupt vector tables.
CREFERENCE
More Information This Product, www.freescale.com
INTERFACE UNIT SUBMODULE (BIUSM)
MOTOROLA
IARB[2:0] Interrupt arbitration identification bits
interrupt arbitration field (IARB), composed IARB[2:0] BIUMCR IARB3 within each submodule, provides fifteen different arbitration identification numbers that used arbitrate between interrupt requests occurring with same interrupt priority level. IARB field defaults zero reset, thus preventing module from arbitrating during interrupt arbitration acknowledge cycle (IACK). arbitration takes place during IACK cycle spurious interrupt vector generated (system integration module). This tells system that interrupt arbitration number been initialized. seven levels interrupt primary means which interrupt priority established. 4-bit interrupt arbitration number secondary priority, allowing requests each primary level. During IACK cycle request with highest arbitration number gets serviced (binary 1111 highest priority binary 0001 lowest). Many modules have software assignable arbitration number whole module. Callows different arbitration numbers used providing each submodule with IARB3 (which cleared software). Once IARB[2:0] assigned BIUSM, they apply Cinterrupt requests. Therefore, Csubmodule interrupts interleaved priority with requests from other modules same interrupt level. IARB[2:0] cleared reset. TBRS1, TBRS0 Time base register select bits These bits specify which time base accessed when time base register (BIUTBR) read.
TBRS1 TBRS0
Time base TBB1 TBB2 TBB3 TBB4
2.5.2
BIUTEST BIUSM test configuration register
BIUTEST register located Cbase address offsets reserved factory testing CTM.
MOTOROLA
INTERFACE UNIT SUBMODULE (BIUSM)
More Information This Product, www.freescale.com
CREFERENCE
2.5.3 BIUTBR BIUSM time base register
normal operation, BIUTBR read-only register used read value present time base buses. time base being accessed determined TBRS1 TBRS0 BIUMCR. Writing BIUTBR effect, except certain test modes.
Bit: BIUTBR Reset:
Offset from base address CTM.
CREFERENCE
More Information This Product, www.freescale.com
INTERFACE UNIT SUBMODULE (BIUSM)
MOTOROLA
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
INTERFACE UNIT SUBMODULE (BIUSM)
More Information This Product, www.freescale.com
CREFERENCE
INTERRUPTS
This section describes interrupt functions Cand submodules these interrupts passed IMB. Interrupt requests from Care treated exceptions dealt with CPU's exception processing routines. more detailed description exception processing based microprocessors, please refer following Motorola publications:
CPU16 Central Processor Unit Reference Manual (CPU16RM/D) CPU32 Central Processor Unit Reference Manual (CPU32RM/AD)
Interrupt levels
Cand submodules capable generating interrupts eight different levels intermodule (IMB). Interrupt levels, arbitration hardwired daisy-chain priority system submodules Callow each many interrupt sources uniquely identified have unique vector address. Each Csubmodule contains interrupt control register that sets interrupt priority submodule eight levels (IL[2:0]). Level highest priority level level disables interrupts. (Note that CPSM BIUSM have capability generate interrupts have interrupt vectors associated with them.) When interrupt requested higher level than current interrupt level interrupt exception level mask CPU's status register, starts interrupt acknowledge (IACK) cycle. Ccompares interrupt level requested with interrupt level acknowledged during IACK cycle. levels match, arbitration with other modules requesting service same interrupt level begins. interrupt same level CPU's current interrupt exception level mask cannot executed until mask level reduces below that level, except level interrupts. Level maskable exception processing this level will interrupted other level interrupts. higher level exception will interrupt lower level exception routine, which must then wait until exception mask returns original level before continuing.
CREFERENCE
More Information This Product, www.freescale.com
INTERRUPTS
MOTOROLA
Arbitration
interrupt exception processing system family devices very similar that used M68000 microprocessor family architecture, designed support very large number interrupt sources. Within each eight interrupt request levels, defined IL[2:0], there sixteen different arbitration priority levels, defined IARB[3:0], available each module. Level highest arbitration priority level level lowest. Level special case treated spurious interrupt. Interrupting modules present their arbitration (IARB[3:0]) module with highest wins.
Note:
Simultaneous interrupts same interrupt level arbitrated basis four arbitration bits IARB[3:0]. Consequently, modules have same IARB field value.
CTM, IARB[2:0] contained within BIUSM module configuration register (BIUMCR) common Csubmodules, each Csubmodule contains IL[2:0] IARB3 bits. This allows each Csubmodule request interrupts with arbitration levels available interrupt levels. example, IARB[2:0] bits BIUMCR 101, each submodule have arbitration priority level 0101 1101 (13), depending state IARB3 bit.
Cdaisy-chain priority
allow resolution between Csubmodule interrupts same interrupt level (IL[2:0]) with same arbitration priority (IARB3), hardwired vector bits (VECT[5:0]) each submodule provide hardware system priority, daisy-chain, within CTM. submodules daisy-chained descending order their vector numbers, i.e. submodule highest position daisy-chain will over other submodules generating simultaneous interrupts same level with same arbitration. position each submodule daisy-chain specific each different Cvariant. This shown generically Table 3-1. example daisy-chain structure specific Cimplementation, CTM2, Appendix
MOTOROLA
More Information This Product, www.freescale.com
INTERRUPTS
CREFERENCE
Interrupt vector number vector address
Cwins arbitration sequence, generates uniquely coded 8-bit interrupt vector number that indicates which timer submodule requesting service. highest order bits (VECT[7:6]) interrupt vector number come from BIUMCR establish vector base number $00, $40, $C0. remaining bits interrupt vector number (VECT[5:0]) hardwired into each Csubmodule unique each interrupt source. vector address obtained multiplying vector base number two. (See Table 3-1.)
Note:
Some Csubmodules, e.g. SASM, have more than interrupt source therefore have corresponding number vectors uniquely coded vector base numbers.
Table Csubmodule interrupt vector number convention
Submodule number Interrupt vector number (VBN vect[5:0]) Daisy-chain priority Highest
Lowest
$00, $3F, depending state VECT[7:6] bits BIUSM.
CREFERENCE
More Information This Product, www.freescale.com
INTERRUPTS
MOTOROLA
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
More Information This Product, www.freescale.com
INTERRUPTS
CREFERENCE
COUNTER PRESCALER SUBMODULE (CPSM)
CPSM description
counter prescaler submodule (CPSM) programmable divider system that provides Ccounters with choice clock signals (PCLKx) derived from main system clock (fSYS). first counter prescaler stage generates PCLK1 dividing fSYS output this first counter then applied 8-bit prescaler which divides clock signal further produce PCLK2, PCLK3, PCLK4 PCLK5 (respectively). division ratio PCLK6 software selectable (using PSEL[1:0] control bits counter prescaler control register) from divide 256. block diagram CPSM given Figure 4-1. clock division ratios available PCLKx also shown table Section 4.3.1. These clock signals provided used Csubmodules.
First CPSM prescaler fSYS
PCLK1
fSYS
fSYS
PCLK2 PCLK3 PCLK4 PCLK5
fSYS fSYS fSYS fSYS
fSYS fSYS fSYS fSYS
8-bit prescaler
/128 /256
Select
PCLK6
fSYS fSYS /128 fSYS /256 fSYS /512
fSYS fSYS /192 fSYS /384 fSYS /768
DIV23 PRUN DIV23 PSEL1 PSEL0 CPCR
DIV23
Figure CPSM block diagram
CREFERENCE
More Information This Product, www.freescale.com
COUNTER PRESCALER SUBMODULE (CPSM)
MOTOROLA
Freeze action CPSM
When FREEZE signal recognized, CPSM counters stop counting remain their current values. When FREEZE signal negated, counters start incrementing from their current values, nothing happened. registers accessible during freeze.
CPSM registers
CPSM register comprises four 16-bit register locations. shown Table 4-1, register block contains CPSM registers reserved registers. CPSM register block always immediately follows BIUSM register block CPSM register map. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations effect.
Note:
CPSM register addresses this section specified offsets from base address CTM.
Table CPSM register
Address CPSM control register (CPCR) CPSM test register (CPTR)
Offset from base address CTM.
4.3.1
Bit: CPCR Reset:
CPCR CPSM control register
PRUN DIV23 PSEL1 PSEL0
Offset from base address CTM.
PRUN Prescaler running PRUN read/write control that allows software switch prescaler counter off.
MOTOROLA
COUNTER PRESCALER SUBMODULE (CPSM)
More Information This Product, www.freescale.com
CREFERENCE
(set) Prescaler running. Prescaler divider held reset running.
(clear)
This allows counters various Csubmodules synchronized. cleared reset. DIV23 Divide divide DIV23 read/write control that selects division ratio first prescaler counter. changed software time cleared reset. (set) First prescaler stage divides First prescaler stage divides
(clear)
PSEL1, PSEL0 Prescaler division ratio select bits These control bits select division ratio programmable prescaler output signal, PCLK6.
Prescaler control register bits Prescaler division ratio PRUN DIV23 PSEL1 PSEL0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6
4.3.2
CPTR CPSM test register
This test register located Caddress offsets reserved factory testing CPSM.
MOTOROLA
COUNTER PRESCALER SUBMODULE (CPSM)
More Information This Product, www.freescale.com
CREFERENCE
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
COUNTER PRESCALER SUBMODULE (CPSM)
More Information This Product, www.freescale.com
CREFERENCE
FREE-RUNNING COUNTER SUBMODULE (FCSM)
FCSM description
free-running counter submodule (FCSM) provides multipurpose `fixed' time base wide range applications, such input capture, output compare signal generation. FCSM also configured operate event counter; this case, flag after predefined number events (internal clocks external events). block diagram FCSM shown Figure 5-1. main components FCSM 16-bit loadable free-running up-counter, clock selector, time base driver interrupt interface.
Note:
order able count, FCSM requires CPSM clock signals present. coming reset, FCSM will count internal external events until prescaler CPSM starts running (when software sets PRUN bit). This allows counters Csubmodules synchronized.
FCSM counter
FCSM counter section comprises 16-bit register 16-bit up-counter. Reading register transfers contents counter data bus, while write register loads counter with value. Overflow counter defined transition from $FFFF $0000. overflow condition causes flag FCSMSIC register set.
Note:
Reset presets counter register $0000. Writing $0000 counter register while counter's value $FFFF does flag does generate interrupt request.
CREFERENCE
More Information This Product, www.freescale.com
FREE-RUNNING COUNTER SUBMODULE (FCSM)
MOTOROLA
TBBA Time base buses TBBB clocks (PCLKx) from prescaler select
DRVA DRVB
Control register bits Clock select Overflow 16-bit counter Interrupt control
Input CTMC
Edge detect
CLK2 CLK1 CLK0 IARB3
Control register bits Submodule
Control register bits
Figure FCSM block diagram
FCSM clock sources
user choose from eight software selectable counter clock sources: prescaler outputs (PCLKx) input rising edge detection input CTMC input falling edge detection input CTMC
clock source selected CLK[2:0] bits FCSM status, interrupt control register FCSMSIC (see Section 5.7.1). When CLK[2:0] bits being changed, internal circuitry ensures that spurious edges occurring CTMC affect FCSM. Note that read-only FCSMSIC register reflects state input CTMC. input Schmitt triggered synchronized with system clock (fSYS).
5.3.1
FCSM external event counting
When external clock source input pin) selected, FCSM event counter mode. counter simply count number events occurring input pin. Alternatively, FCSM programmed generate interrupt when predefined number events have been counted; this done presetting counter with two's complement value
MOTOROLA
FREE-RUNNING COUNTER SUBMODULE (FCSM)
More Information This Product, www.freescale.com
CREFERENCE
desired number events. When using external clock source, maximum guaranteed external frequency fSYS/4.
FCSM time base driver
DRVA DRVB bits FCSMSIC register select time base buses driven (see Section 5.7.1). Which time base buses driven depends where FCSM physically placed particular Cimplementation. Section more information structure time base buses. examples FCSM waveforms timings, please refer Section 10.1. Warning: recommended that time base buses driven same time.
FCSM interrupts
valid FCSM interrupt generated when FCSMSIC register result counter overflowing). interrupt priority level FCSM non-zero, defined three bits FCSMSIC register, valid interrupt request will occur IMB.
Freeze action FCSM
When FREEZE signal recognized, FCSM counter stops counting remains current value. When FREEZE signal negated, counter starts incrementing from current value, nothing happened. registers accessible during freeze. During freeze, FCSMSIC register continues reflect state signal input CTMC (see Section 5.7.1).
CREFERENCE
More Information This Product, www.freescale.com
FREE-RUNNING COUNTER SUBMODULE (FCSM)
MOTOROLA
FCSM registers
FCSM register comprises four 16-bit register locations. shown Table 5-1, register block contains FCSM registers reserved registers. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations effect. Cimplementations featuring multiple FCSMs, each FCSM registers.
Note:
register addresses this section offsets from base address FCSM.
Address
Table FCSM register
Status, interrupt control register (FCSMSIC) Counter register(FCSMCNT)
Offset from base address FCSM submodule.
5.7.1
Bit: FCSMSIC Reset:
FCSMSIC FCSM status/interrupt/control register
IARB3
DRVA DRVB
CLK2 CLK1 CLK0
Offset from base address FCSM submodule.
Counter overflow flag This status flag indicates whether counter overflow occurred. overflow defined transition counter from $FFFF $0000. field non-zero, interrupt request generated when set. (set) Counter overflow occurred. Counter overflow occurred.
(clear)
This flag only hardware cleared only software system reset. clear flag, software must first read `one') then write `zero' bit.
Note:
flag clearing mechanism will work only flag setting event occurs between read write operations; setting event occurs between read write operations, will cleared.
MOTOROLA
FREE-RUNNING COUNTER SUBMODULE (FCSM)
More Information This Product, www.freescale.com
CREFERENCE
IL[2:0] Interrupt level bits three interrupt level bits read/write control bits that select priority level interrupt requests made FCSM. These bits read written time cleared reset.
Selected level Interrupt disabled Interrupt level (lowest) Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level (highest)
IARB3 Interrupt arbitration read/write IARB3 works conjunction with IARB[2:0] field BIUSM module configuration register. Each module that generates interrupt requests must have unique value arbitration field (IARB). This interrupt arbitration identification number used arbitrate when modules generate simultaneous interrupts same priority (see Section IARB3 cleared reset. DRVA, DRVB Drive time base bits DRVA DRVB read/write bits that control connection FCSM time base buses These bits cleared reset. (See Section information time base buses.)
DRVA DRVB selected Neither time base time base driven Time base driven Time base driven Both time base time base driven
Warning: recommended that time base buses driven same time. Input status This read-only status reflects logic state FCSM input CTMC. Writing `zero' `one' this effect. Reset effect this bit.
CREFERENCE
More Information This Product, www.freescale.com
FREE-RUNNING COUNTER SUBMODULE (FCSM)
MOTOROLA
CLK[2:0] Counter clock select bits These read/write control bits select internal clock signals (PCLKx) external conditions input (rising edge falling edge). maximum frequency external clock signals fSYS/4.
CLK2 CLK1 CLK0 Free running counter clock source Prescaler output Prescaler output Prescaler output /12) Prescaler output (/16 /24) Prescaler output (/32 /48) Prescaler output (/64 /512 /768) CTMC input, negative edge CTMC input, positive edge
5.7.2
Bit: FCSMCNT Reset:
FCSMCNT FCSM counter register
Offset from base address FCSM submodule.
FCSM counter register read/write register; cleared reset.
MOTOROLA
FREE-RUNNING COUNTER SUBMODULE (FCSM)
More Information This Product, www.freescale.com
CREFERENCE
MODULUS COUNTER SUBMODULE (MCSM)
MCSM description
MCSM versatile timer submodule capable performing complex counting timing functions, including modulus counting, wide range applications. MCSM also configured event counter, allowing overflow flag after predefined number events (internal clocks external events), variable time source generation. Note that MCSM also operate free running counter; this case behaves exactly like FCSM. block diagram MCSM shown Figure 6-1.
TBBA Time base buses TBBB clocks (PCLKx) from prescaler Clock input CTMC select Edge detect Clock select
DRVA DRVB
Control register bits
CLK2 CLK1 CLK0
Control register Modulus load input CTML Edge detect
Control register bits Modulus control
16-bit counter
Overflow
Interrupt control
Modulus register
Write both
EDGEN EDGEP IARB3
Control register bits
Submodule
Control register bits
Figure MCSM block diagram
CREFERENCE
More Information This Product, www.freescale.com
MODULUS COUNTER SUBMODULE (MCSM)
MOTOROLA
main components MCSM 16-bit modulus latch, 16-bit loadable up-counter, counter loading logic, clock selector, time base driver interrupt interface.
Note:
order able count, MCSM requires CPSM clock signals present. coming reset, MCSM will count internal external events until prescaler CPSM starts running (when software sets PRUN bit). This allows counters Csubmodules synchronized.
MCSM modulus latch
16-bit modulus latch read/write register that used reload counter automatically with predetermined value. contents modulus latch register read time. Writing register loads modulus latch with value. This value then transferred counter register next hardware load that counter. However, writing corresponding counter register loads modulus latch counter register immediately with value. modulus latch register cleared $0000 reset.
MCSM counter
counter composed 16-bit read/write register associated with 16-bit incrementer. Reading counter transfers contents counter register data bus; writing counter loads modulus latch counter register immediately with value. counter clocked with different clock sources (see Section 6.4).
Note:
Reset presets counter register $0000. Writing $0000 counter register while value $FFFF does flag does generate interrupt.
6.3.1
Loading MCSM counter register
counter register loaded writing directly counter register also loaded from modulus latch each time counter overflow occurs flag MCSM status/interrupt/control register (MCSMSIC) set.
Note:
When modulus latch loaded with $FFFF, overflow flag every counter clock pulse.
MOTOROLA
MODULUS COUNTER SUBMODULE (MCSM)
More Information This Product, www.freescale.com
CREFERENCE
Loading counter register from modulus register also triggered external event modulus load CTML. edge CTML that triggers loading counter register selected bits EDGEN EDGEP MCSMSIC register. Hardware provided prevent occurrence spurious edges while changing EDGEN EDGEP bits. Reset clears EDGEN EDGEP bits zero, thereby preventing signal CTML from loading counter register until EDGEN EDGEP have been initialized software. modulus load input CTML Schmitt triggered synchronized system clock (fSYS).
Note:
read-only MCSMSIC reflects state input CTML.
6.3.1.1
Using MCSM free-running counter
MCSM modulus counter. However made behave like free-running counter loading modulus register with value $0000.
MCSM clock sources
User choose from eight software selectable counter clock sources: prescaler outputs (PCLKx) input rising edge detection input CTMC input falling edge detection input CTMC
clock source selected CLK[2:0] bits MCSM status, interrupt control register MCSMSIC (see Section 6.8.1). When CLK[2:0] bits being changed, internal circuitry ensures that spurious edges occurring CTMC affect MCSM. clock input CTMC Schmitt triggered synchronized with system clock (fSYS).
Note:
read-only MCSMSIC register reflects state input CTMC.
6.4.1
MCSM external event counting
When external clock source CTMC input pin) selected, MCSM event counter mode. counter simply count number events occurring input pin. Alternatively, MCSM programmed generate interrupt when predefined number events have been counted; this done presetting counter with two's complement value desired number events. When using external clock source, maximum external guaranteed frequency fSYS/4.
CREFERENCE
More Information This Product, www.freescale.com
MODULUS COUNTER SUBMODULE (MCSM)
MOTOROLA
MCSM time base driver
DRVA DRVB bits MCSMSIC register select time base buses driven (see Section 6.8.1). Which time base buses driven depends where MCSM physically placed particular Cimplementation. Section information structure time base buses. examples MCSM waveforms timings, please refer Section 10.1. Warning: recommended that time base buses driven same time.
MCSM interrupts
valid MCSM interrupt generated when MCSMSIC register result counter overflowing. interrupt priority level MCSM non-zero, defined three bits MCSMSIC register, valid interrupt request will occur IMB.
Freeze action MCSM
When FREEZE signal recognized, MCSM counter stops counting remains last value. When FREEZE signal negated, counter starts incrementing from last value, nothing happened. registers accessible during freeze. During freeze, bits MCSMSIC continue reflect states signals input pins (see Section 6.8.1).
MCSM registers
MCSM register comprises four 16-bit register locations. shown Table 6-1, register block contains three FCSM registers reserved register. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations effect. Cimplementations featuring multiple MCSMs, each MCSM registers.
Note:
register addresses this section specified offsets from base address MCSM.
MOTOROLA
MODULUS COUNTER SUBMODULE (MCSM)
More Information This Product, www.freescale.com
CREFERENCE
Table MCSM register
Address MCSM status/interrupt/control register (MCSMSIC) MCSM counter (MCSMCNT) MCSM modulus latch (MCSMML)
Offset from base address MCSM submodule.
6.8.1
Bit: MCSMSIC Reset:
MCSMSIC MCSM status/interrupt/control register
IARB3
DRVA DRVB
EDGEN EDGEP
CLK2 CLK1 CLK0
Offset from base address MCSM submodule.
Counter overflow flag This status flag indicates whether counter overflow occurred. overflow MCSM counter defined transition counter from $FFFF $xxxx, where $xxxx value contained modulus latch. field non-zero, interrupt request generated when set. (set) Counter overflow occurred. Counter overflow occurred.
(clear)
This flag only hardware cleared only software system reset. clear flag, software must first read `one') then write `zero' bit.
Note:
flag clearing mechanism will work only flag setting event occurs between read write operations; setting event occurs between read write operations, will cleared.
CREFERENCE
More Information This Product, www.freescale.com
MODULUS COUNTER SUBMODULE (MCSM)
MOTOROLA
IL[2:0] Interrupt level bits three interrupt level bits read/write control bits that select priority level interrupt requests made MCSM. These bits read written time cleared reset.
Selected level Interrupt disabled Interrupt level (lowest) Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level (highest)
IARB3 Interrupt arbitration read/write IARB3 works conjunction with IARB[2:0] field BIUSM module configuration register. Each module that generates interrupt requests must have unique value arbitration field (IARB). This interrupt arbitration identification number used arbitrate when modules generate simultaneous interrupts same priority (see Section IARB3 cleared reset. DRVA, DRVB Drive time base bits DRVA DRVB read/write bits that control connection MCSM time base buses These bits cleared reset. (See Section information time base buses.)
DRVA DRVB selected Neither time base time base driven Time base driven Time base driven Both time base time base driven
Warning: recommended that time base buses driven same time. Clock input status This read-only status reflects logic state clock input CTMC. Writing this effect. Reset effect this bit.
MOTOROLA
MODULUS COUNTER SUBMODULE (MCSM)
More Information This Product, www.freescale.com
CREFERENCE
Modulus load input status This read-only status reflects logic state modulus load input CTML. Writing this effect. Reset effect this bit. EDGEN, EDGEP Modulus load edge sensitivity bits These read/write bits select sensitivity edge detection circuitry modulus load CTML.
EDGEN EDGEP edge detector sensitivity None Positive edge only Negative edge only Positive negative edge
CLK[2:0] Counter clock select bits These read/write control bits select internal clock signals (PCLKx) external conditions input (rising edges falling edges). maximum frequency external clock signals fSYS/4.
CLK2 CLK1 CLK0 Free running counter clock source Prescaler output Prescaler output Prescaler output /12) Prescaler output (/16 /24) Prescaler output (/32 /48) Prescaler output (/64 /768) CTMC input, negative edge CTMC input, positive edge
6.8.2
Bit: MCSMCNT Reset:
MCSMCNT MCSM counter register
Offset from base address MCSM submodule.
MCSM counter register read/write register.
MOTOROLA
MODULUS COUNTER SUBMODULE (MCSM)
More Information This Product, www.freescale.com
CREFERENCE
6.8.3
Bit: MCSMML Reset:
MCSMML MCSM modulus latch register
Offset from base address MCSM submodule.
MCSM modulus latch register read/write register.
MOTOROLA
MODULUS COUNTER SUBMODULE (MCSM)
More Information This Product, www.freescale.com
CREFERENCE
SINGLE ACTION SUBMODULE (SASM)
Single action channel
FLAG
IARB3
Interrupt control
FLAG
Single action channel
Submodule Ctime base buses
Figure SASM block diagram
SASM description
dual-channel SASM provides identical single-action channels, each having input/output sharing same interrupt circuitry (see Figure 7-1). Each channel configured independently software perform either input capture output compare. single action submodule called because each SASM channel perform single timing action (input capture output compare) before some software intervention required. Each channel also work simple pin.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA
more detailed block diagram SASM channel shown Figure 7-2. Each channel comprises: time base selector (which selects time base used that channel timing functions), 16-bit data register (which read software time which used both input capture output compare functions), 16-bit comparator (which continuously compares 16-bit value data register with time base bus), output flip-flop (which holds logic level sent output when successful output compare occurs), input edge detector (which detects rising falling edge that will trigger input capture function), several status control bits status/interrupt/control register SICA SICB, interrupt section. During reset output output flip-flop cleared (i.e. `zero').
Note:
SASM modes operation
Each SASM channel operate four different modes: Input capture (IC) (i.e. either input capture rising falling edge read-only input port) Output compare (OC) Output compare toggle (OCT) Output port (OP)
Note:
channel operating mode, register reflects logic state corresponding input (after being Schmitt triggered synchronized). When channel operating mode, register reflects logic state output output flip-flop.
7.2.1
Clearing using FLAG bits
clear FLAG bit, software must first read channel's register, then write zero FLAG bit. These steps have done consecutive instructions. This clearing sequence must used every mode operation. Writing FLAG effect.
MOTOROLA
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
TBBA time base buses TBBB select
FORCE EDOUT
16-bit comparator
Output flip-flop
Output buffer Interrupt control
16-bit register
Edge detect
MODE1 MODE0
FLAG
IARB3
Control register bits Submodule
Control register bits
Figure SASM block diagram (channel
Warning: avoid spurious interrupts, make sure that FLAG according newly selected mode, following sequence operations should adopted when changing mode: Disable SASM interrupts Change mode Reset corresponding FLAG Re-enable SASM interrupts desired)
Note:
When changing between output modes (OP, OCT), necessary follow this procedure, these modes FLAG merely indicates software that compare value updated.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA
7.2.2 Input capture (IC) mode
mode, 16-bit counter value selected time base `captured' when triggering event occurs channel's input pin. Triggering input capture circuitry done rising falling edge input pin; polarity triggering edge selected EDOUT bit. logic level input read software channel's register.
Note:
mode, input Schmitt triggered input signal synchronized system clock (fSYS). reflects state present input (after being Schmitt triggered synchronized).
When input capture occurs, count value selected time base latched into channel's 16-bit data register. same time, FLAG register indicate that input capture occurred. FLAG must reset software (see Section 7.2.1). interrupt serviced, FLAG should cleared servicing routine before returning from that routine. subsequent input capture event occurs while FLAG set, captured counter value latched, FLAG remains unchanged.
Note:
mode, value EDOUT permanently transferred output flip-flop. This value will output when mode changed output modes.
7.2.3
Output compare (OC) mode
mode, state output changed when successful output compare occurs; interrupt also generated. output compare circuitry performs comparison between 16-bit register selected time base bus. When match found, EDOUT value transferred output flip-flop. same time, FLAG indicate processor that match occurred. Depending state bit, interrupt generated when FLAG set. FLAG must reset software (see Section 7.2.1). interrupt serviced, FLAG should cleared servicing routine before returning from that routine. subsequent output compare occurs while FLAG set, output compare function occurs normally, FLAG remains set. output compare match simulated software writing FORCE bit. Setting FORCE forces EDOUT value onto output compare occurred. this case, FLAG affected. Only genuine output compare occurs while doing force, will FLAG signify that compare occurred.
Note:
mode, value reflects logic state output output flip-flop.
MOTOROLA
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
7.2.4 Output compare toggle (OCT) mode
mode, state output toggled each time successful output compare occurs; interrupt also generated. output compare circuitry performs comparison between 16-bit register selected time base bus. When match found, output flip-flop toggled opposite state. same time, FLAG indicate processor that output compare occurred. Depending state bit, interrupt generated when FLAG set. FLAG must reset software (see Section 7.2.1). interrupt serviced, FLAG should cleared servicing routine before returning from that routine. subsequent output compare occurs while FLAG set, output toggles, FLAG remains set. output compare match simulated software writing FORCE bit. Setting FORCE forces output flip flop toggle output compare occurred. this case, FLAG affected. Only genuine output compare occurs while doing force, will FLAG signify that compare occurred.
Note:
mode, reflects logic state output output flip-flop.
7.2.5
Output port (OP) mode
mode channel's input/output used single output port pin. output compare function still available, internal operation only, does affect state output pin. interrupt also generated when compare occurs. state output always reflects value EDOUT channel's register. Reading EDOUT returns last value written internal compare feature compares 16-bit register with selected time base bus. output compare circuitry performs comparison between 16-bit register selected time base bus. When match found, FLAG indicate processor that output compare occurred. Depending state bit, interrupt generated when FLAG set. FLAG must reset software (see Section 7.2.1). interrupt serviced, FLAG should cleared servicing routine before returning from that routine. subsequent output compare occurs while FLAG set, internal output compare functions normally, FLAG remains set.
Note:
mode, value reflects logic state output output flip-flop.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA
SASM interrupts
Each channel dual-channel SASM separately enabled initiated interrupts they each have their unique vector number address. However, they both assigned same interrupt level arbitration priority IL[2:0] IARB3 bits SICA register. valid SASM interrupt recognized when FLAG set, corresponding interrupt level defined bits IL[2:0] equal zero. FLAG status that indicates, when set, that input capture output compare occurred corresponding single action channel. relative priority these sources interrupt fixed channel higher priority than channel
Freeze action SASM
When FREEZE signal recognized, SASM input capture output compare functions halted. soon FREEZE signal negated, SASM actions resume nothing happened. During freeze, bits registers (SICA SICB) readable return levels present input pins input mode operation, output value output mode operation (see Section 7.5.1 Section 7.5.3). When output modes operation, force output function remains available, allowing software output desired level useful feature debugging). SASM registers accessible during freeze.
SASM registers
SASM register comprises eight 16-bit register locations. shown Table 7-1, register block contains SASM registers each channel four reserved registers. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations meaning effect. register addresses this section specified offsets from base address SASM. Cimplementations featuring multiple SASMs, each SASM registers.
MOTOROLA
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
Table SASM register
Address SASM status/interrupt/control register (SICA) SASM data register (SDATA) SASM status/interrupt/control register (SICB) SASM data register (SDATB)
Offset from base address SASM submodule.
7.5.1
SICA SASM status/interrupt/control register
This register contains control, interrupt enable status bits SASM channel also contains interrupt priority level bits IL[2:0] arbitration priority IARB3 whole SASM (i.e. common channels
Bit: SICA Reset: FLAG IARB3
FORCE EDOUT
MODE1 MODE0
Offset from base address SASM submodule.
FLAG Event flag FLAG whenever input capture output compare event occurs. This flag only hardware cleared only software system reset. field non-zero, set, interrupt request generated when FLAG set. (set) input capture output compare event occurred. input capture output compare event occurred.
(clear)
mode, subsequent input capture event occurs while FLAG set, value latched FLAG remains set. mode, subsequent output compare event occurs while FLAG set, compare occurs normally FLAG remains set. mode, subsequent output compare event occurs while FLAG set, toggle output signal occurs normal FLAG remains set. mode, subsequent internal compare event occurs while FLAG set, compare occurs normally FLAG remains set.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA
clear flag, software must first read `one') then write `zero' bit.
Note:
flag clearing mechanism will work only flag setting event occurs between read write operations; FLAG setting event occurs between read write operations, FLAG will cleared.
IL[2:0] Interrupt level bits three interrupt level bits read/write control bits that select priority level interrupt requests made SASM. These bits read written time cleared reset.
Note:
These bits affect both SASM channels, just channel
Selected level Interrupt disabled Interrupt level (lowest) Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level (highest)
IARB3 Interrupt arbitration read/write IARB3 works conjunction with IARB[2:0] field BIUSM module configuration register. Each module that generates interrupt requests must have unique value arbitration field (IARB). This interrupt arbitration identification number used arbitrate when modules generate simultaneous interrupts same priority (see Section IARB3 cleared reset.
Note:
This affects both SASM channels, just channel
Interrupt enable This control enables interrupts channel when FLAG IL[2:0] field non-zero. This cleared reset. (set) Interrupts enabled. Interrupts disabled.
(clear)
MOTOROLA
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
Time base select This control selects time base connected SASM channel This cleared reset. (set) Time base selected. Time base selected.
(clear)
Input status input mode (IC), reflects logic state present corresponding input (after being Schmitt triggered synchronized). output modes (OC, OP), value reflects state output output flip-flop. read-only bit; writing effect. Reset effect this bit. FORCE Force compare control modes, FORCE used writing effect. modes, FORCE used software cause output flip-flop (and output pin) behave though output compare occurred. mode, setting FORCE causes value EDOUT transferred output output flip-flop; mode, setting FORCE causes output flip-flop toggle. Internal synchronization ensures that correct level appears output when value written EDOUT FORCE same time. (set) Force output flip-flop behave output compare just occurred. action.
(clear)
FORCE cleared reset always reads zero.
Note:
FLAG affected FORCE bit.
EDOUT Edge detect output level mode, EDOUT used select edge that will trigger input capture circuitry. (set) Input capture rising edge. Input capture falling edge.
(clear)
mode, EDOUT used latch value output next output compare match when FORCE set. Internal synchronization ensures that correct level appears output when value written EDOUT FORCE same time. Reading EDOUT returns previous value written.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA
mode, EDOUT effect. However, force function still available will force value EDOUT appear output pin. mode, value EDOUT output corresponding pin. Reading EDOUT returns previous value written. EDOUT cleared reset. MODE1, MODE0 SASM operating mode select bits These control bits select mode operation SASM channel, shown following table. MODE1 MODE0 cleared reset.
7.5.2
MODE1
MODE0
SASM channel operating mode Input capture (IC) Output port (OP) Output compare (OC) Output compare toggle (OCT)
SDATA SASM data register
SDATA 16-bit read-write register associated with channel mode, SDATA contains last captured value. modes, loaded with value next output compare. SDATA affected reset.
Bit: SDATA Reset:
Offset from base address SASM submodule.
7.5.3
SICB SASM status/interrupt/control register
This register contains control status bits SASM channel bits contains identical those SICA, with exception IL[2:0], IARB3 which apply both
MOTOROLA 7-10
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
channels simultaneously which included only SICA. descriptions bits, please refer Section 7.5.1).
Bit: SICB Reset: FLAG
FORCE EDOUT
MODE1 MODE0
Offset from base address SASM submodule.
7.5.4
SDATB SASM data register
SDATB 16-bit read-write register associated with channel mode, SDATB contains last captured value. modes, loaded with value next output compare. SDATB affected reset.
Bit: SDATB Reset:
Offset from base address SASM submodule.
CREFERENCE
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
MOTOROLA 7-11
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA 7-12
More Information This Product, www.freescale.com
SINGLE ACTION SUBMODULE (SASM)
CREFERENCE
DOUBLE ACTION SUBMODULE (DASM)
TBBA time base buses TBBB select
FORCA FORCB
16-bit comparator
Output flip-flop
Output buffer
16-bit register
EDPOL
16-bit register Register 16-bit register
Edge detect
Interrupt control
16-bit comparator
MODE3 MODE2
MODE1 MODE0
FLAG
IARB3
Control register bits Submodule
Control register bits
Figure DASM block diagram
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA
DASM description
DASM timer submodule designed specifically integrated into Csystems used Motorola's M68300 M68HC16 family MCUs. contains timing channels associated with same input/output pin. dual action submodule called because timing channel configuration allows events (input capture output compare) occur before some software intervention required. operating modes allow software DASM's input capture output compare functions perform pulse width measurement, period measurement, single pulse generation continuous pulse width generation, well standard input capture output compare. DASM also work single (see Table 8-1). DASM composed timing channels output flip-flop, input edge detector, some control logic interrupt section (see Figure 8-1). control status bits contained DASMSIC register. Channel comprises 16-bit data register 16-bit comparator. Channel also appears user consist 16-bit data register 16-bit comparator, however, internally, channel data registers operating mode determines which register accessed software: input capture modes (IPWM, IC), registers used hold captured values; these modes, register used temporary latch channel output compare modes (OCA OCAB), registers used define output pulse; register used these modes. output pulse width modulation mode (OPWM), registers used primary registers hidden register used double buffer channel
Register contents always transferred automatically correct time that minimum pulse (measurement generation) just time base count. data registers always read/write registers, accessible CTM's submodule bus. input capture modes, edge detect circuitry triggers capture whenever rising falling edge defined EDPOL bit) applied input pin. signal input Schmitt triggered synchronized with system clock (fSYS). disabled mode (DIS) input modes, reflects state present input (after being Schmitt triggered synchronized). output modes reflects value present output output flip-flop. output flip-flop used output modes hold logic level applied output pin. time base selector common input output functions; connects DASM time base controlled software select DASMSIC register.
MOTOROLA
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
32-bit coherent access
IPWM modes, 32-bit coherent access data registers supported (see Section 1.3.4). 32-bit coherent access consists doing long word aligned access data register this case, register accessed first, immediately followed next cycle) register access. During this time, flag setting data transfer from hidden register deferred until coherent access ended. When 32-bit access ended, DASM finishes pending action resumes normal operation.
DASM modes operation
mode operation DASM determined mode select bits MODE[3:0] DASMSIC register (see Table 8-1). Table DASM modes operation
MODE[3:0] 0000 0001 0010 0011 0100 0101 1xxx Mode IPWM OCAB OPWM Description mode Disabled Input high impedance; gives state input pin. Input pulse width measurement Capture leading edge trailing edge input pulse. Input period measurement Capture consecutive rising/falling edges. Input capture Capture when designated edge detected. Output compare, flag compare Generate leading trailing edges output pulse flag. Output compare, flag compare Generate leading trailing edges output pulse flag. Output pulse width modulation Generate continuous output with bits resolution.
Warning: avoid spurious interrupts, make sure that FLAG according newly selected mode, following sequence operations should adopted when changing mode: Disable DASM interrupts Change mode Reset corresponding FLAG Re-enable DASM interrupts desired)
Note:
When changing between output modes (OP, OCT), necessary follow this procedure, these modes FLAG merely indicates software that compare value updated.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA
8.3.1 Disable (DIS) mode
mode selected making MODE[3:0] 0000. this mode, input capture output compare functions DASM disabled FLAG maintained reset state, input port function remains available. associated becomes high impedance input input level this reflected state DASMSIC register. control interrupt bits remain accessible, allowing software prepare future mode selection. Data registers accessible consecutive addresses. Writing data register stores same value registers Warning: When changing modes, imperative through mode order reset DASM's internal functions properly. Failure this could lead invalid unexpected output compare input capture results, flags being incorrectly.
8.3.2
Input pulse width measurement (IPWM) mode
IPWM mode selected making MODE[3:0] 0001. This mode allows width positive negative pulse determined capturing leading edge pulse channel trailing edge pulse channel successive captures done consecutive edges opposite polarity. edge sensitivity selected EDPOL DASMSIC register. This mode also allows software determine logic level input time reading DASMSIC register. channel input capture function remains disabled until first rising edge triggers first input capture channel When this rising edge detected, count value time base selected latched 16-bit data register FLAG affected. When next falling edge detected, count value time base latched into 16-bit data register and, same time, FLAG contents register transferred register Reading data register returns value register subsequent input capture events occur while FLAG set, data registers will updated with latest captured values FLAG will remain set. 32-bit coherent operation progress when falling edge detected, transfer from deferred until coherent operation completed. Operation DASM then continues channels previously described. input pulse width calculated subtracting value data register from value data register Figure provides example DASM used input pulse width measurement.
MOTOROLA
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
Mode selection; EDPOL
FLAG reset software
FLAG reset software
Input signal Time base FLAG DASMA captured value captured value value
$0500
$1000
$1100
$1250
$1525
$16A0
$xxxx $xxxx $xxxx
$xxxx $1000 $xxxx
$1100 $1000 $1000
$1100 $1250 $1000
$1525 $1250 $1250
$1525 $16A0 $1250
Notes: These values accessible software. These values internal accessible.
Figure Input pulse width measurement example
8.3.3
Input period measurement (IPM) mode
mode selected making MODE[3:0] 0010. This mode allows period input signal determined capturing consecutive rising edges consecutive falling edges; successive input captures done consecutive edges same polarity. edge polarity defined EDPOL DASMSIC register. This mode also allows software determine logic level input time reading DASMSIC register. When first edge having selected polarity detected, time base value latched into 16-bit data register data register transferred data register finally data register transferred register this first capture FLAG set. second subsequent captures, FLAG immediately before data register transferred register When second edge same polarity detected, time base value latched into data register data register transferred data register FLAG signify that beginning points complete period have been captured, finally data register transferred register This sequence events repeated each subsequent capture. Reading data register returns value register 32-bit coherent operation progress when edge detected, transfer data from deferred until coherent operation completed. time, input level present input read bit.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA
input pulse period calculated subtracting value data register from value data register Figure provides example DASM used input period measurement.
Mode selection; EDPOL
FLAG reset software
FLAG reset software
Input signal Time base FLAG DASMA captured value value value $0500 $1000 $1100 $1250 $1525 $16A0
$xxxx $xxxx $xxxx
$1000 $1000 $xxxx
$1250 $1250 $1000
$16A0 $16A0 $1250
Notes: These values accessible software. These values internal accessible.
Figure Input period measurement example
MOTOROLA
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
8.3.4 Input capture (IC) mode
mode selected making MODE[3:0] 0011. This mode identical input period measurement mode (IPM) described above, with exception that FLAG also occurrence first detected edge selected polarity. this mode DASM functions standard input capture function similar M68HC11 family timers. this case value latched channel ignored. Figure provides example DASM used input capture.
Mode selection; EDPOL
FLAG reset software
FLAG reset software
FLAG reset software
Input signal Time base FLAG DASMA captured value value value $0500 $1000 $1100 $1250 $1525 $16A0
$xxxx $xxxx $xxxx
$1000 $1000 $xxxx
$1250 $1250 $1000
$16A0 $16A0 $1250
Notes: These values accessible software. These values internal accessible.
Figure DASM input capture example
8.3.5
Output compare (OCB OCAB) modes
mode selected making MODE[3:0] 010x. MODE0 controls setting criteria FLAG bit, i.e. when compare occurs only channel when compare occurs either channel (see Section 8.6.1). This mode allows DASM perform four different output functions: Single-shot output pulse (two edges), with FLAG second edge. Single-shot output pulse (two edges), with FLAG both edges. Single-shot output transition (one edge). Output port pin, with output compare function disabled.
this mode leading trailing edges variable width output pulses generated calculated output compare events occurring channels respectively. mode also
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA
used perform single output compare function, similar M68HC11 timer, used output port bit. this mode, channel accessed register Register used accessible user. Both channels work together generate `single shot' output pulse signal. Channel defines leading edge output pulse, while channel defines trailing edge pulse. FLAG setting done when compare occurs channel only when compare occurs either channel defined MODE0 DASMSIC register). When this mode first selected, both comparators disabled. Each comparator enabled writing data register; remains enabled until next successful comparison made that channel, whereupon disabled. values stored registers compared with count value selected time base when their corresponding comparators enabled. output flip-flop when match occurs channel output flip-flop reset when match occurs channel polarity output signal selected EDPOL bit. output flip-flop level obtained time reading bit. subsequent enabled output compares occur channels output pulses continue output, regardless state FLAG bit. time, FORCA FORCB bits allow software force output flip-flop level corresponding comparison channel respectively. Note that FLAG affected these `force' operations. Totem pole open-drain output circuit configurations selected using DASMSIC register. Warning: There hardware protection disable comparator while comparator enabled. user's responsibility load data registers with values needed produce desired output pulse.
Note:
both channels loaded with same value they will force different levels output flip-flop. Hardware protection circuitry ensures that contention occurs output flip-flop provides logic zero level output.
8.3.5.1
Single shot output pulse operation
single shot output pulse operation selected writing leading edge value desired pulse data register trailing edge value data register single pulse will output desired time, thereby disabling comparators until values written data registers.
Note:
this mode, registers accessible user software consecutive addresses).
MOTOROLA
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
Figure provides example DASM used generate single output pulse.
Mode selection; MODE0 Write Output signal Time base FLAG DASMA value value
FLAG reset software
$0500
$1000
$1100
$0000
$1000
$1100
$xxxx $xxxx
$1000 $1100
$1000 $1100
Note: These values accessible software.
Figure Single-shot output pulse example
8.3.5.2
Single output compare operation
single output compare operation selected writing only data registers thus enabling only comparators. Following first successful match enabled channel, output level fixed remains same level indefinitely with further software intervention being required.
Note:
this mode, registers accessible user software consecutive addresses).
Figure provides example DASM used perform single output compare.
8.3.5.3
Output port operation
output port operation selected leaving both channels disabled, i.e. writing neither register EDPOL alone controls output value.The same result achieved keeping EDPOL zero using FORCA FORCB bits obtain desired output level.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA
Mode selection; MODE0 Write
FLAG reset software Write
FLAG reset software
Input signal Time base FLAG DASMA value value $0500 $1000 $1100 $1000 $1100 $1000
$xxxx $xxxx
$1000 $xxxx
$1000 $1100
$1000 $1100
Note: These values accessible software.
Figure Single shot output transition example
8.3.6
Output pulse width modulation (OPWM) mode
OPWM mode selected making MODE[3:0] 1xxx. MODE[2:0] bits allow some comparator bits masked. This mode allows pulse width modulated output waveforms generated, with eight selectable frequencies (for given time base). Both channels used generate output signal DASM pin. Channel accessed register Register accessible user. Channels define leading trailing edges, respectively, output pulse. value register continuously transferred register time between each trailing edge following leading edge. value loaded register continuously compared with value time base bus. When match occurs, FLAG output flip-flop set. value loaded register continually compared with value time base bus. When match occurs output flip-flop reset. polarity output signal selected EDPOL bit. output flip-flop level obtained time reading bit. subsequent compares occur channels pulses continue output, regardless state FLAG bit. time, FORCA FORCB bits allow software force output flip-flop level corresponding comparison respectively. Note that FLAG affected FORCA FORCB operations.
MOTOROLA 8-10
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
Warning: There hardware protection disable comparator while comparator enabled. user's responsibility load data registers with values needed produce desired output pulse.
Note:
both channels loaded with same value they will force different levels output flip-flop. Hardware protection circuitry ensures that contention occurs output flip-flop provides logic zero level output.
Figure provides example DASM used pulse width modulation.
EDPOL
Write $1500 comparison matches
FLAG reset Write software $1700
FLAG reset software comparison matches comparison matches
comparison matches
output Time base FLAG DASMA value value
$1000
$1100
$0000
$1000
$1500
$1700
$1000 $xxxx $xxxx
$1000 $1500 $xxxx
$1000 $1500 $1500
$1000 $1700 $1700
$1000 $1700 $1700
$1000 $1700 $1700
value
Notes: These values accessible software. These values internal accessible.
Figure DASM output pulse width modulation example
generate output pulses different frequencies, 16-bit comparator have some bits masked. This controlled bits MODE2, MODE1 MODE0. frequency output (fPWM) given following equation (assuming DASM connected free running counter): CPSM DASM
where NCPSM overall CPSM clock divide ratio ÷512 ÷768) NDASM DASM divide ratio. examples frequencies resolutions that obtained shown Table 8-2.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA 8-11
Table DASM example output frequencies/resolutions fSYS
output frequency (Hz) 0.48 122.07 0.95 244.14 1.91 488.28 3.81 976.56 7.63 1953.13 15.26 3906.25 31.04 15625.00 244.14 62500.00 Resolution (bits)
CPSM
DASM 65536 65536 32768 32768 16384 16384 8192 8192 4096 4096 2048 2048
This table valid only DASM connected free-running counter.
When using bits resolution comparator (MODE[2:0] 000), output vary from duty cycle duty cycle 65535/65536. this case possible have 100% duty cycle. cases where 16-bit resolution needed, possible have duty cycle ranging from 100%. Setting value stored register results output being `always set'. Clearing zero) allows normal comparisons occur normal output waveform obtained. Changes from 100% duty cycle done synchronously, other width changes. OPWM mode, selects whether output totem pole driven open-drain.
DASM interrupts
When FLAG set, interrupt request generated eight levels defined interrupt level bits (IL[2:0]) DASMSIC register. interrupt level zero, interrupts disabled.
MOTOROLA 8-12
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
Freeze action DASM
When FREEZE signal recognized, DASM captures compares functions halted. soon FREEZE signal negated, DASM actions resume nothing happened. During freeze, DASMSIC register readable returns level present input input mode selected, output value output mode operation. When output modes operation, force output function remains available, allowing software output desired level simplifying debugging. DASM registers accessible during freeze.
DASM registers
DASM register comprises four 16-bit register locations. shown Table 8-3, register block contains three DASM registers reserved register. unused bits reserved address locations return zero when read software. Writing unused bits reserved address locations meaning effect. register addresses this section specified offsets from base address DASM. Cimplementations featuring multiple DASMs, each DASM registers.
Table DASM register
Address DASM status/interrupt/control register (DASMSIC) DASM register (DASMA) DASM register (DASMB)
Offset from base address DASM submodule.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA 8-13
8.6.1
Bit: DASMSIC Reset:
DASMSIC DASM status/interrupt/control register
FLAG IARB3
FORCA FORCB EDPOL MODE3 MODE2 MODE1 MODE0
Offset from base address DASM submodule.
FLAG Flag status This status indicates whether input capture output compare event occurred. field non-zero, interrupt request generated when FLAG set. (set) input capture output compare event occurred. input capture output compare event occurred.
(clear)
mode, FLAG cleared. IPWM mode, FLAG each time there capture channel mode, FLAG each time there capture channel except first time. mode, FLAG each time there capture channel mode (i.e. when MODE0 FLAG only each time there successful comparison channel OCAB mode (i.e. when MODE0 FLAG each time there successful comparison either channel OPWM mode, FLAG whenever there successful comparison channel
This flag only hardware cleared only software system reset. software clear FLAG either writing zero having first read one, selecting mode. clear flag, software must first read `one') then write `zero' bit.
Note:
flag clearing mechanism will work only flag setting event occurs between read write operations; FLAG setting event occurs between read write operations, FLAG will cleared.
MOTOROLA 8-14
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
IL[2:0] Interrupt level bits three interrupt level bits read/write control bits that select priority level interrupt requests made DASM. These bits read written time cleared reset.
Selected level Interrupt disabled Interrupt level (lowest) Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level Interrupt level (highest)
IARB3 Interrupt arbitration read/write IARB3 works conjunction with IARB[2:0] field BIUSM module configuration register. Each module that generates interrupt requests must have unique value arbitration field (IARB). This interrupt arbitration identification number used arbitrate when modules generate simultaneous interrupts same priority (see Section IARB3 cleared reset. Wired-OR DIS, IPWM, modes, used; reading this returns value that previously written. OCB, OCAB OPWM modes, selects whether output buffer configured open-drain totem pole operation. (set) Output buffer open-drain. Output buffer totem pole.
(clear)
cleared reset. select This control selects time base connected DASM. (set) DASM connected time base DASM connected time base
(clear)
Note:
time base configurations specific each Cimplementation (eg. CTM2). Please refer appropriate appendix details.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA 8-15
Input status DIS, IPWM, modes, this read-only status reflects logic level input pin. OCB, OCAB OPWM modes, reading this returns value latched output flip-flop, after EDPOL polarity selection. Writing this effect. FORCA Force OCB, OCAB OPWM modes, FORCA allows software force output flip-flop behave successful comparison occurred channel (except that FLAG set). Writing FORCA sets output flip-flop; writing zero effect. DIS, IPWM, modes, FORCA used writing effect. FORCA cleared reset always reads zero.
Note:
Writing both FORCA FORCB simultaneously resets output flip-flop.
FORCB Force OCB, OCAB OPWM modes, FORCB allows software force output flip-flop behave successful comparison occurred channel (except that FLAG set). Writing FORCB resets output flip-flop; writing zero effect. DIS, IPWM, modes, FORCB used writing effect. FORCB cleared reset always reads zero.
Note:
Writing both FORCA FORCB simultaneously resets output flip-flop.
EDPOL Edge polarity mode, this used; reading returns last value written. IPWM mode, this used select capture edge sensitivity channels (set) Channel captures falling edge. Channel captures rising edge. Channel captures rising edge. Channel captures falling edge.
(clear)
modes, EDPOL used select input capture edge sensitivity channel
MOTOROLA 8-16
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
(set) Channel captures falling edge. Channel captures rising edge.
(clear)
OCB, OCAB OPWM modes, EDPOL used select voltage level output pin. (set) complement output flip-flop logic level appears output pin: compare channel resets output pin; compare channel sets output pin. output flip-flop logic level appears output pin: compare channel sets output pin, compare channel resets output pin.
(clear)
EDPOL cleared reset. MODE[3:0] Mode select bits four mode select bits select mode operation DASM. avoid spurious interrupts, recommended that DASM interrupts disabled before changing operating mode. mode select bits cleared reset.
DASM control register bits MOD3 MOD2 MOD1 MOD0
Bits Time base resolution bits ignored 15-13 15-12 15-11 15-9 15-7
DASM mode operation Disabled IPWM Input pulse width measurement Input period measurement Input capture Output compare, flag compare OCAB Output compare, flag compare
OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA 8-17
8.6.2
Bit: DASMA Reset:
DASMA DASM data register
Offset from base address DASM submodule.
DASMA data register associated with channel varies with different modes operation: mode, DASMA accessed prepare value subsequent mode selection. IPWM mode, DASMA contains captured value corresponding trailing edge measured pulse. modes, DASMA contains captured value corresponding most recently detected dedicated edge (rising falling edge). OCAB modes, DASMA loaded with value corresponding leading edge pulse generated. Writing DASMA OCAB modes also enables corresponding channel comparator until next successful comparison. OPWM mode, DASMA loaded with value corresponding leading edge pulse generated.
8.6.3
Bit: DASMB Reset:
DASMB DASM data register
Offset from base address DASM submodule.
DASMB data register associated with channel varies with different modes operation. Depending mode selected, software access register register mode, DASMB accessed prepare value subsequent mode selection. this mode, register accessed order prepare value OPWM mode. Unused register hidden cannot read, written with same value when register written. IPWM mode, DASMB contains captured value corresponding leading edge measured pulse. this mode, register accessed; buffer register hidden cannot accessed.
MOTOROLA 8-18
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
modes, DASMB contains captured value corresponding most recently detected period edge (rising falling edge). this mode, register accessed; buffer register hidden cannot accessed. OCAB modes, DASMB loaded with value corresponding trailing edge pulse generated. Writing DASMB OCAB modes also enables corresponding channel comparator until next successful comparison. this mode, register accessed; buffer register hidden cannot accessed. OPWM mode, DASMB loaded with value corresponding trailing edge pulse generated. this mode, register accessed; buffer register hidden cannot accessed.
CREFERENCE
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
MOTOROLA 8-19
8.7.1 DASM examples mode example
DASM_IC (for CPU16 based devices) Demonstration DASM Csub-module operating mode. DASM configured capture first falling input edge, then generate interrupt. Timings assume 16.777MHz system clock interface unit sub-module, BIUSM #$0C01 Cnot stopped, ignore FREEZE, BIUMCR vector base =$4x, IARB2-0=4, displayed counter prescaler module, CPSM #$0008 PRUN start prescaler CPCR PCLK dividers free running counter module, FCSM #$0905 interrupts, arb3=1, timebase driven fcsm25sic Clock using PCLK6 (/64 clock, 3.8147µs) #$0900 dasm10sic MODE %0000 Disable DASM module before re-configuring
Ensure that will respond level interrupt andp #$FF1F with $FF1F clear interrupt mask DASM mode initialization #$1913
MODE %0011 EDPOL IARB3 %001
Select mode Capture edge time base Lowest priority interrupt
loop
dasm10sic loop
Hang here (until interrupt)
interrupt routine. interrupt vector DASM module should contain entry address <ic1> bclr dasm10sic,#$80 dasm10a Clear DASM FLAG edge time into Return from interrupt
MOTOROLA 8-20
More Information This Product, www.freescale.com
DOUBLE ACTION SUBMODULE (DASM)
CREFERENCE
8.7.2 mode example
DASM_IPM (for CPU16 based devices) Demonstration DASM Csub-module operating mode. DASM configured measure periods between input falling edges. interrupt generated after each measured period. interrupt routine <ipm1> calculates period resu
Other recent searches
ZBFS5105-PT - ZBFS5105-PT ZBFS5105-PT Datasheet
UC1875 - UC1875 UC1875 Datasheet
UC2875 - UC2875 UC2875 Datasheet
UC3875 - UC3875 UC3875 Datasheet
TC74AC - TC74AC TC74AC Datasheet
SN74AC - SN74AC SN74AC Datasheet
RN2114FRN2118F - RN2114FRN2118F RN2114FRN2118F Datasheet
RN2115F - RN2115F RN2115F Datasheet
RN2116F - RN2116F RN2116F Datasheet
RN2117F - RN2117F RN2117F Datasheet
MAX1544 - MAX1544 MAX1544 Datasheet
IPD30N10S3L-34 - IPD30N10S3L-34 IPD30N10S3L-34 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
