Media Access Controller Ethernet (MACETM) DISTINCTIVE CHARACTERIS
|
|
|
Top Searches for this datasheet
Am79C940
Media Access Controller Ethernet (MACETM)
DISTINCTIVE CHARACTERISTICS
Integrated Controller with Manchester encoder/decoder 10BASE-T transceiver port Supports IEEE 802.3/ANSI 8802-3 Ethernet standards 84-pin PLCC 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available space critical applications such PCMCIA Modular architecture allows easy tuning specific applications High speed, 16-bit synchronous host system interface with cycles/transfer Individual transmit (136 byte) receive (128 byte) FlFOs provide increase system latency support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion collision frames Automatic retransmission with FIFO reload Direct slave access board configuration/status registers transmit/ receive FlFOs Direct FIFO read/write access simple interface controllers processors Arbitrary byte alignment little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADITM) external hardware address filtering bridge/ router applications JTAG Boundary Scan (IEEE 1149.1) test access port interface board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAITM) allows by-passing differential Attachment Unit Interface (AUI) Supports following types network interface: external 10BASE2, 10BASE5 10BASE-F port external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F General Purpose Serial Interface (GPSI) external encoding/decoding scheme Internal 10BASE-T transceiver with automatic selection 10BASE-T port Sleep mode allows reduced power consumption critical battery powered applications MHz-25 system clock speed Support operation industrial temperature range (-40°C +85°C) available three packages
GENERAL DESCRIPTION
Media Access Controller Ethernet (MACE) chip CMOS VLSI device designed provide flexibility customized design. MACE device specifically designed address applications where multiple peripherals present, centralized system specific required. high speed, 16-bit synchronous system interface optimized external processor system, similar many existing peripheral devices, such SCSI serial link controllers. MACE device slave register based peripheral. transfers from system performed using simple memory read write commands. conjunction with user defined engine, MACE chip provides IEEE 802.3 interface tailored specific application. superior modular architecture versatile system interface allow MACE device configured stand-alone device connectivity cell incorporated into larger, integrated system.
Publication# 16235 Rev: Amendment/0 Issue Date: October 1997
MACE device provides complete Ethernet node solution with integrated 10BASE-T transceiver, supports 25-MHz system clocks. MACE device embodies Media Access Control (MAC) Physical Signaling (PLS) sub-layers IEEE 802.3 standard, provides IEEE defined Attachment Unit Interface (AUI) coupling external Medium Attachment Unit (MAU). MACE device compliant with 10BASE2, 10BASE5, 10BASE-T, 10BASE-F transceivers. Additional features also enhance over-all system design. individual transmit receive FIFOs optimize system overhead, providing substantial latency during packet transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder eliminates need external Serial Interface Adapter (SIA) node system. support external encoding/decoding scheme desired, General Purpose Serial Interface (GPSI) allows direct access to/from MAC. addition, Digital Attachment Interface (DAI), which simplified electrical attachment specification, allows implementation MAUs that require isolation between DTE. port also used indicate transmit, receive, collision status connecting LEDs port. MACE device also provides External Address Detection Interface (EADI) allow external hardware address filtering internet working applications.
Am79C940 MACE chip offered Plastic Leadless Chip Carrier (84-pin PLCC), Plastic Quad Flat Package (100-pin PQFP), Thin Quad Flat Package (TQFP 80-pin). There several small functional physical differences between 80-pin TQFP 84-pin PLCC 100-pin PQFP configurations. Because smaller number pins TQFP configuration versus PLCC configuration, four pins bonded out. Though identical three package configurations, removal these four pins does cause some functionality differences between TQFP PLCC PQFP configurations. Depending application, removal these pins will will have effect. (See section: "Pins Removed TQFP Package Their Effects.) With rise embedded networking applications operating harsh environments where temperatures exceed normal commercial temperature (0°C +70°C) window, industrial temperature (-40°C +85°C) version available three packages; 84pin PLCC, 100-pin PQFP 80-pin TQFP. industrial temperature version MACE Ethernet controller characterized across industrial temperature range (-40°C +85°C) within published power supply specification (4.75 5.25 i.e., VCC). Thus, conformance MACE performance over this temperature range guarantee design characterization monitor.
Am79C940
BLOCK DIAGRAM
XTAL1 XTAL2
DXCVR CLSN EADI Port Control FIFO FIFO FIFO Control 802.3 Core Port SRDCLK SF/BD EAM/R TXD± TXP± LNKST RXPOL TXDAT± TXEN RXDAT RXCRS STDCLK TXDAT+ TXEN SRDCLK RXDAT RXCRS CLSN EADI Port
DBUS 15-0 RDTREQ TDTREQ INTR SCLK EDSEL SLEEP RESET
Interface Unit
10BASE-T
10BASE-T
Command Status Registers
Port
Port
GPSI Port JTAG PORT CNTRL
GPSI
C16235D-1
Notes: Only network ports AUI, 10BASE-T, port GPSI active time. Some shared signals active regardless which network port active, some reconfigured. EADI port active times.
Am79C940
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM CONNECTION DIAGRAMS 080. ORDERING INFORMATION PIN/PACKAGE SUMMARY SUMMARY DESCRIPTION NETWORK INTERFACES ATTACHMENT UNIT INTERFACE (AUI). DIGITAL ATTACHMENT INTERFACE (DAI) 10BASE-T INTERFACE GENERAL PURPOSE SERIAL INTERFACE (GPSI). EXTERNAL ADDRESS DETECTION INTERFACE (EADI) HOST SYSTEM INTERFACE IEEE 1149.1 TEST ACCESS PORT (TAP) INTERFACE. GENERAL INTERFACE POWER SUPPLY. FUNCTIONS AVAILABLE WITHTHE 80-PIN TQFP PACKAGE PINS REMOVED THEIR EFFECTS FUNCTIONAL DESCRIPTION NETWORK INTERFACES SYSTEM INTERFACE DETAILED FUNCTIONS BLOCK LEVEL DESCRIPTION INTERFACE UNIT (BIU) FIFO DATA PATH. CONTROL STATUS REGISTER DATA PATH FIFO SUB-SYSTEM. MEDIA ACCESS CONTROL (MAC) MANCHESTER ENCODER/DECODER (MENDEC) ATTACHMENT UNIT INTERFACE (AUI) DIGITAL ATTACHMENT INTERFACE (DAI) 10BASE-T INTERFACE. TWISTED PAIR TRANSMIT FUNCTION. TWISTED PAIR RECEIVE FUNCTION LINK TEST FUNCTION POLARITY DETECTION REVERSAL. TWISTED PAIR INTERFACE STATUS COLLISION DETECT FUNCTION SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION JABBER FUNCTION EXTERNAL ADDRESS DETECTION INTERFACE (EADI). INTERNAL/EXTERNAL ADDRESS RECOGNITION CAPABILITIES GENERAL PURPOSE SERIAL INTERFACE (GPSI) IEEE 1149.1 TEST ACCESS PORT INTERFACE. SLAVE ACCESS OPERATION READ ACCESS WRITE ACCESS INITIALIZATION REINITIALIZATION TRANSMIT OPERATION TRANSMIT FIFO WRITE.
Am79C940
TRANSMIT FUNCTION PROGRAMMING AUTOMATIC GENERATION TRANSMIT GENERATION TRANSMIT STATUS INFORMATION TRANSMIT EXCEPTION CONDITIONS RECEIVE OPERATION RECEIVE FIFO READ RECEIVE FUNCTION PROGRAMMING. AUTOMATIC STRIPPING RECEIVE CHECKING RECEIVE STATUS INFORMATION RECEIVE EXCEPTION CONDITIONS LOOPBACK OPERATION USER ACCESSIBLE REGISTERS RECEIVE FIFO (RCVFIFO). TRANSMIT FIFO (XMTFIFO) TRANSMIT FRAME CONTROL (XMTFC) TRANSMIT FRAME STATUS (XMTFS) TRANSMIT RETRY COUNT (XMTRC) RECEIVE FRAME CONTROL (RCVFC) RECEIVE FRAME STATUS (RCVFS). RFSO-RECEIVE MESSAGE BYTE COUNT (RCVCNT) RFS1-RECEIVE STATUS (RCVSTS) RFS2-RUNT PACKET COUNT (RNTPC) RFS3-RECEIVE COLLISION COUNT (RCVCC) FIFO FRAME COUNT (FIFOFC) INTERRUPT REGISTER (IR) INTERRUPT MASK REGISTER (IMR) POLL REGISTER (PR) CONFIGURATION CONTROL (BIUCC). FIFO CONFIGURATION CONTROL (FIFOCC) CONFIGURATION CONTROL (MACCC). CONFIGURATION CONTROL (PLSCC) CONFIGURATION CONTROL (PHYCC) CHIP IDENTIFICATION REGISTER (CHIPD [15-00]). INTERNAL ADDRESS CONFIGURATION (IAC) LOGICAL ADDRESS FILTER (LADRF [63-00]) PHYSICAL ADDRESS (PADR [47-00]) MISSED PACKET COUNT (MPC). RUNT PACLET COUNT (RNTPC) RECEIVE COLLISION COUNT (RCVCC) USER TEST REGISTER (UTR). ENABLING FULL DUPLEX OPERATION RESERVED TEST REGISTER (RTR1) RESERVED TEST REGISTER (RTR2) REGISTER TABLE SUMMARY REGISTER SUMMARY. 16-BIT REGISTERS 8-BIT REGISTERS PROGRAMMER'S REGISTER MODEL SYSTEM APPLICATIONS HOST SYSTEM EXAMPLES MOTHERBOARD CONTROLLER SYSTEM INTERFACE MOTHERBOARD EXAMPLE PC/AT ETHERNET ADAPTER CARD NETWORK INTERFACES EXTERNAL ADDRESS DETECTION INTERFACE (EADI). ATTACHMENT UNIT INTERFACE (AUI)
Am79C940
10BASE-T/TWISTED-PAIR ETHERNET 10BASE-T 10BASE2 CONFIGURATION AM79C940. 10BASE-T IMPLEMENTATION AM79C940 MACE COMPATIBLE 10BASE-T FILTERS TRANSFORMSERS MACE COMPATIBLE ISOLATION TRANSFORMERS MACE COMPATIBLE DC/DC CONVERTERS MANUFACTURER CONTACT INFORMATION ABSOLUTE MAXIMUM RATINGS OPERATING RANGES CHARACTERISTICS CHARACTERISTICS Output Valid Delay Load Chart SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS SWITCHING TEST CIRCUITS: NORMAL THREE-STATE OUTPUTS SWITCHING TEST CIRCUITS: SWITCHING TEST CIRCUITS: SWITCHING TEST CIRCUITS: WAVEFORMS WAVEFORMS: CLOCK RSET TIMING WAVEFORMS: HOST SYSTEM INTEFACE-2-CYCLE RECEIVE FIFO/REGISTER READ TIMING .100 WAVEFORMS: HOST SYSTEM INTERFACE-3-CYCLE RECEIVE FIFO/REGISTER READ TIMING .101 WAVEFORMS: HOST: SYSTEM INTERFACE-2-CYCLE TRANSMIT FIFO/REGISTER WRITE TIMING .102 WAVEFORMS: HOST SYSTEM INTERFACE-3-CYCLE TRANSMIT FIFO/REGISTER WRITE TIMING .103 WAVEFORMS: HOST SYSTEM INTERFACE-RDTREG READ TIMING .103 WAVEFORMS: HOST SYSTEM-TDTREG WRITE TIMING .104 TRANSMIT TIMING-START PACKET. .104 PORT TRANSMIT TIMING. .109 EADI FEATURE TIMING-START ADDRESS .110 GPSI TRANSMIT TIMING .112 IEEE 1149.1 TIMING .114 10BASE-T TRANSMIT TIMING .114 PHYSICAL DIMENSIONS .117 084-PIN PLASTIC LEADED CHIP CARRIER .117 100-PIN PLASTIC QUAD FLAT PACK; TRIMMED FORMED .118 100-PIN PLASTIC QUAD FLAT PACK WITH MOLDED CARRIER RING .119 080-PIN THIN QUAD FLAT PACKAGE. .120 APPENDIX LOGICAL ADDRESS FILTERING ETHERNET .121 MAPPING LOGICAL ADDRESS FILTER MASK .122 APPENDIX BSDL DESCRIPTION AM79C940 MACE JTAG STRUCTURE .123
Am79C940
CONNECTION DIAGRAMS PLCC PACKAGE
SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9
RXCRS RXDAT CLSN TXEN/TXEN STDCLK DVSS TXDATTXDAT+ DVSS EDSEL DXCVR DVDD AVDD CIDI+ DIAVDD DOAVSS
Am79C940JC MACE
XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ TXDTXPAVDD RXD+ RXDDVDD DVSS LNKST RXPOL
DBUS10 DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4
16235D-2
Am79C940
CONNECTION DIAGRAMS PQR100 PQFP PACKAGE
SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 DBUS10
RXCRS RXDAT CLSN TXEN/TXEN STDCLK DVSS TXDATTXDAT+ DVSS EDSEL DXCVR DVDD AVDD CIDI+ DIAVDD
MACE Am79C940KC
AVSS XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ AVDD RXD+ DVDD DVSS LNKST RXPOL
DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4
16235D-3
Am79C940
CONNECTION DIAGRAMS PQT080 TQFP PACKAGE
SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ TXDTXPAVDD RXD+ RXDDVDD DVSS LNKST
DBUS10 DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4
RXCRS RXDAT CLSN TXEN/TXEN STDCLK DVSS TXDAT+ DVSS EDSEL DXCVR DVDD AVDD CIDI+ DIAVDD DOAVSS MACE Am79C940VC
16235D-4
Notes: Four functions available PLCC PQFP packages available with TQFP package. (See full data sheet description pins included with 80-pin TQFP package. particular, section "Pin Functions available with 80-pin TQFP package.")
Am79C940
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination
AM79C940
ALTERNATE PACKAGING OPTION Trimmed Formed Tray OPTIONAL PROCESSING Blank Standard Processing TEMPERATURE RANGE Commercial +70°C) Industrial (-40°C +85°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) 84-Pin Plastic Leaded Chip Carrier 084) 100-Pin Plastic Quad Flat Pack (PQR100) 80-Pin Thin Quad Flat Package (PQT080) SPEED Applicable
DEVICE NUMBER/DESCRIPTION (include revision letter) Am79C940 Media Access Controller Ethernet
Valid Combinations KC\W, VC\W KI\W, VI\W
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confir availability specifi valid combinations check newly released combinations.
AM79C940
AM79C940
Note: Currently silicon revision level MACE Ethernet controller revision This designated marking package Am79C940Bxx, where "xx" indicate package type temperature range.
Am79C940
PIN/PACKAGE SUMMARY (PLCC)
PLCC Name DXCVR EDSEL DVSS TXDAT+ TXDAT- DVSS STDCLK TXEN/TXEN CLSN RXDAT RXCRS SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 DBUS10 DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS Disable Transceiver Edge Select Digital Ground Transmit Data Transmit Data Digital Ground Serial Transmit Data Clock Transmit Enable Collision Receive Data Receive Carrier Sense Serial Receive Data Clock External Address Match/Reject Serial Receive Data Start Frame/Byte Delimiter Reset Sleep Mode Digital Power Interrupt Timing Control Data Bus0 Digital Ground Data Bus1 Data Bus2 Data Bus3 Data Bus4 Digital Ground Data Bus5 Data Bus6 Data Bus7 Data Bus8 Data Bus9 Data Bus10 Data Bus11 Data Bus12 Data Bus13 Digital Power Data Bus14 Data Bus15 Digital Ground Frame Data Transfer Valid FIFO Data Strobe Byte Enable0 Function
Am79C940
PIN/PACKAGE SUMMARY (continued)
PLCC Name SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 RXPOL LNKST DVSS DVDD RXD- RXD+ AVDD TXP- TXD- TXP+ TXD+ AVDD XTAL1 AVSS XTAL2 AVSS AVDD AVDD DVDD Byte Enable System Clock Transmit Data Transfer Request Receive Data Transfer Request Address0 Address1 Address2 Address3 Address4 Read/Write Chip Select Receive Polarity Link Status Test Data Test Mode Select Test Clock Digital Ground Test Data Input Digital Power Receive Data- Receive Data+ Analog Power Transmit Pre-distortion Transmit Data- Transmit Pre-distortion+ Transmit Data+ Analog Power Crystal Output Analog Ground Crystal Output Analog Ground Data Out- Data Out+ Analog Power Data Data Control Control Analog Power Digital Power Function
Am79C940
PIN/PACKAGE SUMMARY (PQFP) (continued)
PQFP Name SHDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 DBUS10 DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS Connect Connect Connect Connect Serial Receive Data Clock External Address Match/Reject Serial Receive Data Start Frame/Byte Delimiter Reset Sleep Mode Digital Power Interrupt Timing Control Data Bus0 Digital Ground Data Bus1 Data Bus2 Data Bus3 Data Bus4 Digital Ground Data Bus5 Data Bus6 Data Bus7 Data Bus8 Data Bus9 Connect Connect Connect Data Bus10 Connect Data Bus11 Data Bus12 Data Bus13 Digital Power Data Bus14 Data Bus15 Digital Ground Frame Data Transfer Valid FIFO Data Strobe Byte Enable0 Byte Enable1 Function
Am79C940
PIN/PACKAGE SUMMARY (continued)
PQFP Name SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 RXPOL LNKST DVSS DVDD RXD- RXD+ AVDD TXP- TXD- TXP+ TXD+ AVDD XTAL1 AVSS XTAL2 AVSS AVDD System Clock Transmit Data Transfer Request Receive Data Transfer Request Address0 Address1 Address2 Address3 Address4 Connect Connect Connect Connect Read/Write Chip Select Receive Polarity Link Status Test Data Test Mode Select Test Clock Digital Ground Test Data Input Digital Power Receive Data- Receive Data+ Analog Power Transmit Pre-distortion- Transmit Data- Transmit Pre-distortion+ Transmit Data+ Analog Power Crystal Input Analog Ground Crystal Output Connect Connect Connect Analog Ground Connect Data Out- Data Out+ Analog Power Data Data Function
Am79C940
PIN/PACKAGE SUMMARY (continued)
PQFP Name AVDD DVDD DXCVR EDSEL DVSS TXDAT+ TXDAT- DVSS STDCLK TXEN/TXEN CLSN RXDAT RXCRS Control Control Analog Power Digital Power Disable Transceiver Edge Select Digital Ground Transmit Data Transmit Data- Digital Ground Serial Transmit Data Clock Transmit Enable Collision Receive Data Receive Carrier Sense Function
Am79C940
PIN/PACKAGE SUMMARY (TQFP) (continued)
TQFP Name SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 DBUS10 DBUS11 DBUS12 DBUS13 DVDD DBUS14 DBUS15 DVSS SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 Function Serial Receive Data Clock External Address Match/Reject Start Frame/Byte Delimiter Reset Sleep Mode Digital Power Interrupt Timing Control Data Bus0 Digital Ground Data Bus1 Data Bus2 Data Bus3 Data Bus4 Digital Ground Data Bus5 Data Bus6 Data Bus7 Data Bus8 Data Bus9 Data Bus10 Data Bus11 Data Bus12 Data Bus13 Digital Power Data Bus14 Data Bus15 Digital Ground Frame FIFO Data Strobe Byte Enable0 Byte Enable1 System Clock Transmit Data Transfer Request Receive Data Transfer Request Address0 Address1 Address2 Address3 Address4 TQFP Number Name LNKST DVSS DVDD RXD- RXD+ AVDD TXP- TXD- TXP+ TXD+ AVDD XTAL1 AVSS XTAL2 AVSS AVDD AVDD DVDD DXCVR EDSEL DVSS TXDAT+ DVSS STDCLK TXEN/TXEN CLSN RXDAT RXCRS Function Read/Write Chip/Select Link Status Test Data Test Mode Select Text Clock Digital Ground Test Data Input Digital Power Receive Data- Receive Data+ Analog Power Transmit Pre-distortion- Transmit Data- Transmit Pre-distortion+ Transmit Data+ Analog Power Crystal Output Analog Ground Crystal Output Analog Ground Data Out- Data Out+ Analog Power Data Data Out+ Control Control Analog Power Digital Power Disable Transceiver Edge Select Digital Ground Transmit Data+ Digital Ground Serial Transmit Data Clock Transmit Enable Collision Receive Data Receive Carrier Sense
Am79C940
SUMMARY
Name DO+/DO- DI+/DI- CI+/CI- RXCRS TXEN CLSN DXCVR STDCLK SRDCLK TXDAT+ TXDAT- TXEN RXDAT RXCRS CLSN DXCVR STDCLK SRDCLK TXD+/TXD- TXP+/TXP- RXD+/RXD- LNKST RXPOL TXEN RXCRS CLSN DXCVR STDCLK SRDCLK STDCLK TXDAT+ TXEN SRDCLK RXDAT RXCRS CLSN DXCVR Function Data Data Control Receive Carrier Sense Transmit Enable Collision Disable Transceiver Serial Transmit Data Clock Serial Receive Data Clock Transmit Data Transmit Data- Transmit Enable Receive Data Receive Carrier Sense Collision Disable Transceiver Serial Transmit Data Clock Serial Receive Data Clock Transmit Data Transmit Pre-distortion Receive Data Link Status Receive Polarity Transmit Enable Receive Carrier Sense Collision Disable Transceiver Serial Transmit Data Clock Serial Receive Data Clock Serial Transmit Data Clock Transmit Data Transmit Enable Serial Receive Data Clock Receive Data Receive Carrier Sense Collision Disable Transceiver Type High High High High High High High High Open Drain Open Drain TTL. TXEN port output. Input DAI, GPSI port output. Input GPSI high Output. Input GPSI Output. Input GPSI Input TTL. also port TTL. TXEN port Input. also EADI port TTL. also port input. Output input High High High High High High High Active Pseudo-ECL Pseudo-ECL Pseudo-ECL output. Input DAI, GPSI port TTL. TXEN port output. Input GPSI Output. Input GPSI Output. Input GPSI TTL. also GPSI TTL. TXEN GPSI TTL. also GPSI input. Output output. Input GPSI high Output. Input GPSI Output. Input GPSI Comment Attachment Unit Interface (AUI)
Digital Attachment Interface (DAI)
10BASE-T Interface
General Purpose Serial Interface (GPSI)
Am79C940
SUMMARY (continued)
Name Function Type Active Comment External Address Detection Interface (EADI) SF/BD EAM/R SRDCLK Start Frame/Byte Delimiter Serial Receive Data External Address Match/Reject Serial Receive Data Clock High High Output except GPSI
Host System Interface DBUS 15-0 ADD4-0 RDTREQ TDTREQ INTR EDSEL SCLK RESET Data Address Read/Write Receive Data Transfer Request Transmit Data Transfer Request Data Transfer Valid Frame Byte Enable Byte Enable Chip Select FIFO Data Strobe Interrupt Edge Select Timing Control System Clock Reset High High High/Low High High Internal pull-up Open Drain Tristate
IEEE 1149.1 Test Access Port (TAP) Interface Test Clock Test Mode Select Test Data Input Test Data Internal pull-up Internal pull-up Internal pull-up
General Interface XTAL1 XTAL2 SLEEP DVDD DVSS AVDD AVSS Crystal Input Crystal Output Sleep Mode Digital Power pins) Digital Power pins) Analog Power pins) Analog Power pins) CMOS CMOS
Am79C940
DESCRIPTION Network Interfaces
MACE device five potential network interfaces. Only interfaces that provides physical network attachment used (active) time. Selection between AUI, 10BASE-T, GPSI ports provided programming Configuration Control register. EADI port effectively active times. Some signals, primarily used status reporting, active more than single interface (the CLSN instance). Under each descriptions network interfaces, primary signals which unique that interface described. Where signals active multiple interfaces, they described once under interface most appropriate.
DO+/DO
Data (Output) differential output pair from MACE device transmitting Manchester encoded data network. Operates pseudo-ECL levels.
Digital Attachment Interface (DAI) TXDAT+/TXDAT-
Transmit Data (Output) When port selected, TXDAT± configured complementary pair Manchester encoded data output from MACE device, used transmit data local external network transceiver. During valid transmission (indicated TXEN low), logical indicated TXDAT+ being high state TXDAT- state; logical indicated TXDAT+ being state TXDAT- high state. During idle (TXEN high), TXDAT+ will high state, TXDAT- state. When GPSI port selected, TXDAT+ will provide data output from core, TXDAT- will held state. Operates levels. operations TXDAT+ TXDAT- defined following tables:
Attachment Unit Interface (AUI) CI+/CI
Control (Input) differential input pair, signalling MACE device that collision been detected network media, indicated inputs being exercised with pattern sufficient amplitude duration. Operates pseudo-ECL levels.
DI+/DI
Data (Input) differential input pair MACE device receiving Manchester encoded data from network. Operates pseudo-ECL levels.
TXDAT+ Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance High Impedance (Note High Impedance (Note TXDAT+ Output TXDAT+ Output High Impedance (Note
TXDAT- Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance High Impedance High Impedance TXDAT- Output High Impedance
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
Am79C940
TXEN/TXEN Transmit Enable (Output)
When port selected (PORTSEL [1-0] 00), output indicating that differential output valid Manchester encoded data presented. When 10BASE-T port selected (PORTSEL [1-0] 01), indicates that Manchester data being output TXD±/TXP± complementary outputs. When port selected (PORTSEL [1-0] 10), indicates that Manchester data being output port TXDAT± complementary outputs. When GPSI port selected (PORTSEL [1-0] =11), indicates that data being output from core MACE device, external Manchester encoder/decoder, TXDAT+ output. Active when port selected, active high when AUI, BASE-T GPSI selected. Operates levels.
decoded data input core MACE device, from external Manchester encoder/decoder. Operates levels.
RXCRS
Receive Carrier Sense (Input/Output) When port selected (PORTSEL [1-0] 00), output indicating that input pair receiving valid Manchester encoded data from external transceiver which meets signal amplitude pulse width requirements. When 10BASE-T port selected (PORTSEL [1-0] 01), output indicating that RXD± input pair receiving valid Manchester encoded data from twisted pair cable which meets signal amplitude pulse width requirements. RXCRS will asserted high entire duration receive message. When port selected (PORTSEL [1-0] 10), input signaling MACE device that receive carrier condition been detected network, valid Manchester encoded data being presented MACE device RXDAT line. When GPSI port selected (PORTSEL [1-0] 11), input signalling internal core that valid data being presented RXDAT input. Operates levels.
RXDAT
Receive Data (Input) When port selected (PORTSEL [1-0] 10), Manchester encoded data input integrated clock recovery Manchester decoder MACE device, from external network transceiver. When GPSI port selected (PORTSEL [1-0] =11),
TXEN/TXEN Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance TXEN Output TXEN Output TXEN Output TXEN Output High Impedance (Note
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). When GPSI port selected, TXEN should have external pull-down attached (e.g. 3.3k ensure output held inactive before ENPLSIO set. This should externally terminated, unused, reduce power consumption.
Am79C940
RXDAT Configuration
SLEEP PORTSEL [1-0] ENPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled High Impedance High Impedance (Note High Impedance (Note RXDAT Input RXDAT Input High Impedance (Note Function
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
RXCRS Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance RXCRS Output RXCRS Output RXCRS Output RXCRS Output High Impedance (Note
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
DXCVR
Disable Transceiver (Output) output from MACE device indicate network port use, programmed ASEL PORTSEL [1-0] bits. output provided allow power down external DC-to-DC converter, typically used provide voltage requirements external 10BASE2 transceiver. When Auto Select (ASEL) feature enabled, state PORTSEL [1-0] bits overridden, network interface will selected MACE device,
dependent only status 10BASE-T link. link active (LNKST driven LOW) 10BASE-T port will used active network interface. link inactive (LNKST pulled HIGH) port will used active network interface. Auto Select will continue operate even when SLEEP asserted RWAKE been set. AWAKE does allow Auto Select function, only receive section 10BASE-T port will active (DXCVR HIGH). Active (HIGH) when either 10BASE-T port selected. Inactive (LOW) when GPSI port selected.
Am79C940
DXCVR Configuration-SLEEP Operation
Sleep RWAKE AWAKE ASEL LNKST High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance HIGH PORTSEL [1-0] Bits Interface Description Sleep Mode with EADI port Function High Impedance
10BASE-T with EADI port
HIGH
Invalid
HIGH
Invalid
with EADI port
10BASE-T with EADI port with EADI port 10BASE-T with EADI port 10BASE-T
HIGH HIGH HIGH
Note: RWAKE ASEL located Configuration Control register (REG ADDR 15). PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). bits must programmed prior assertion SLEEP pin.
DXCVR Configuration-Normal Operation
SLEEP ASEL LNKST HIGH PORTSEL [1-0] Bits ENPLSIO Interface Description Test Mode 10BASE-T port GPSI 10BASE-T Function High Impedance HIGH HIGH HIGH
Note: RWAKE ASEL located Configuration Control register (REG ADDR 15). PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14).
Am79C940
10BASE-T INTERFACE TXD+, TXD-
Transmit Data (Output) 10BASE-T port differential drivers.
RXPOL
Receive Polarity (Output, Open Drain) twisted pair receiver capable detecting receive signal with reversed polarity (wiring error). RXPOL normally state, indicating correct polarity received signal. receiver detects received packet with reversed polarity, then this driven (requires external pull-up) polarity subsequent packets inverted. output state, this capable sinking maximum 12mA used drive LED. polarity correction feature disabled setting Disable Auto Polarity Correction (DAPC) Configuration Control register. this case, Receive Polarity correction circuit disabled internal receive signal remains non-inverted, irrespective received signal. Note that RXPOL will continue reflect polarity detected receiver.
TXP+, TXP-
Transmit Pre-Distortion (Output) Transmit wave form differential driver pre-distortion.
RXD+, RXD-
Receive Data (Input) 10BASE-T port differential receiver. These pins should externally terminated reduce power consumption 10BASE-T interface used.
LNKST
Link Status (OutputOpen Drain) This driven link identified functional. link determined nonfunctional, missing idle link pulses data packets, then this driven (requires external pull-up). output state, capable sinking maximum used drive LED. This feature disabled setting Disable Link Test (DLNKTST) Configuration Control register. this case internal Link Test Receive function disabled, LNKST will driven LOW, Transmit Receive functions will remain active regardless arriving idle link pulses data. internal 10BASE-T will continue generate idle link pulses irrespective status DLNKTST bit.
General Purpose Serial Interface (GPSI) STDCLK
Serial Transmit Data Clock (Input/Output) When either AUI, 10BASE-T port selected, STDCLK output operating half crystal XTAL1 frequency. STDCLK encoding clock Manchester data transferred output either pair, 10BASE-T TXD±/TXP± pairs, port TXDAT± pair. When using GPSI port, STDCLK input network data rate, provided external Manchester encode/decoder, strobe data presented TXDAT+ output. This also required internal loopbacks while GPSI mode.
STDCLK Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance STDCLK Output STDCLK Output STDCLK Output STDCLK Output High Impedance (Note
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
Am79C940
CLSN
Collision (Input/Output) external indication that collision condition been detected (internal external) Medium Attachment Unit (MAU), that signals from more nodes present network. When port selected (PORTSEL [1-0] 00), CLSN will activated when input pair receiving collision indication from external transceiver. CLSN will asserted high entire duration collision detection, will asserted during Test message following transmit message AUI. When 10BASE-T port selected (PORTSEL [1-0] 01), CLSN will asserted high when simultaneous transmit receive activity detected (logically detected when TXD±/TXP± RXD± both active). When port selected (PORTSEL [1-0] 10), CLSN will asserted high when simultaneous transmit receive activity detected (logically detected when RXCRS TXEN both active). When GPSI port selected (PORTSEL [1-0] 11), input from external Manchester encoder/decoder signaling MACE device that collision condition been detected network, receive frame progress should aborted.
External Address Detection Interface (EADI) SF/BD
Start Frame/Byte Delimiter (Output) external indication that start frame delimiter been received. serial stream will follow Serial Receive Data (SRD), commencing with destination address field. SF/BD will high times (400 after detecting second received frame. SF/BD will subsequently toggle every (1.25 frequency) with rising edge indicating start (first bit) each subsequent byte received serial stream. SF/BD will inactive during frame transmission.
Serial Receive Data (Output) decoded data from network. available external address detection. Note that when 10BASE-T port selected, transition will only occur during receive activity. When port selected, transition will occur both transmit receive activity.
CLSN Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance CLSN Output CLSN Output CLSN Output CLSN Output High Impedance (Note
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
EAM/R
External Address Match/Reject(Input) incoming frame will received dependent receive operational mode MACE device, polarity EAM/R pin. EAM/R function programmed Receive Frame Control register. set, configured EAM. reset, configured EAR. EAM/R asserted during packet reception accept reject packets based external address comparison.
SRDCLK
Serial Receive Data Clock (Input/Output) Serial Receive Data (SRD) output synchronous SRDCLK running 10MHz receive data clock frequency. configured input, only when GPSI port selected. Note that when 10BASE-T port selected, transition SRDCLK will only occur during receive activity. When port selected, transition SRDCLK will occur during both transmit receive activity.
Am79C940
Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance Output Output Output Output High Impedance
Note: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14).
SRDCLK Configuration
SLEEP PORTSEL [1-0] ENDPLSIO Interface Description Sleep Mode 10BASE-T Port GPSI Status Disabled Function High Impedance SRDCLK Output SRDCLK Output SRDCLK Output SRDCLK Output High Impedance (Note
Notes: PORTSEL [1-0] ENPLSIO located Configuration Control register (REG ADDR 14). This should externally terminated, unused, reduce power consumption.
Am79C940
HOST SYSTEM INTERFACE DBUS15-0
Data (Input/Output/3-state) DBUS contains read write data from internal registers Transmit Receive FIFOs.
available Transmit FIFO, programming Transmit FIFO Watermark (XMTFW bits) FIFO Configuration Control register. TDTREQ will asserted only when Enable Transmit (ENXMT) Configuration Control register.
FIFO Data Select (Input) FIFO Data Select allows direct access transmit Receive FIFO without address bus. must activated conjunction with R/W. When MACE device samples high low, read cycle from Receive FIFO will initiated. When MACE chip samples low, write cycle Transmit FIFO will initiated. line should inactive (high) when FIFO access requested using pin. MACE device samples both active simultaneously, cycle will executed, will remain inactive.
ADD4-0
Address (Input) used access internal registers FIFOs read written.
Read/Write (Input) Indicates direction data flow during MACE device register, Transmit FIFO, Receive FIFO accesses.
RDTREQ
Receive Data Transfer Request(Output) Receive Data Transfer Request indicates that there data Receive FIFO read. When RDTREQ asserted there will minimum bytes read except completion frame, which case will asserted. RDTREQ programmed request receive data transfer when bytes available Receive FIFO, programming Receive FIFO Watermark (RCVFW bits) FIFO Configuration Control register. first assertion RDTREQ will occur until least bytes have been received, frame been verified runt. Runt packets will normally deleted from Receive FIFO with external activity RDTREQ. When Runt Packet Accept enabled (RPA bit) User Test Register, RDTREQ will asserted when runt packet completes, entire frame resides Receive FIFO. RDTREQ will asserted only when Enable Receive (ENRCV) Configuration Control register. RCVFW overridden enabling Latency Receive function (setting LLRCV bit) Receive Frame Control register, which allows RDTREQ asserted after only bytes have been received. Note that this function exposes system interface premature termination receive frame, network events such collisions runt packets. responsibility system designer provide adequate recovery mechanisms these conditions.
Data Transfer Valid (Output/3-state) When asserted, indicates that read write operation completed successfully. absence termination host access cycle MACE device indicates that data transfer unsuccessful. need used system interface guarantee that latency TDTREQ RDTREQ assertion de-assertion will cause Transmit FIFO over-written Receive FIFO over-read. this case, latching strobing read write data synchronized SCLK input rather than output.
Frame (Input/Output/3-state) Frame will asserted MACE device when last byte/word frame data read from Receive FIFO, indicating completion frame data field receive message. Frame must asserted MACE device when last byte/word frame written into Transmit FIFO.
BE1-0
Byte Enable (Input) Used indicate active portion data transfer from internal FIFOs. word (16-bit) transfers, both should activated external host/controller. Single byte transfers performed identifying active data byte activating only signals. function BE1-0 pins programmed using BSWP (BIU Configuration Control register, BE1-0 required accesses MACE device registers.
TDTREQ
Transmit Data Transfer Request (Output) Transmit Data Transfer Request indicates there room Transmit FIFO more data. TDTREQ asserted when there minimum empty bytes Transmit FIFO. TDTREQ programmed request transmit data transfer when bytes
Am79C940
Chip Select (Input) Used access MACE device FIFOs internal registers locations using address bus. FIFOs alternatively directly accessed without supplying FIFO address, using pins.
IEEE 1149.1 TEST ACCESS PORT (TAP) INTERFACE
Test Clock (Input) clock input boundary scan test mode operation. operate MHz. internal (not SLEEP disabled) pull
INTR
Interrupt (Output, Open Drain) attention signal indicating that more following status flags set: XMTINT, RCVINT, MPCO, RPCO, RCVCCO, CERR, BABL JAB. Each interrupt source individually masked. interrupt condition take place MACE device immediately after hardware software reset.
Test Mode Select (Input) serial input stream used define specific boundary scan test executed. internal (not SLEEP disabled) pull
Test Data Input (Input) test data input path MACE device. internal (not SLEEP disabled) pull
RESET
Reset (Input) Reset clears internal logic. Reset asynchronous SCLK, must asserted minimum duration SCLK cycles.
Test Data (Output) test data output path from MACE device.
SCLK
System Clock (Input) system clock input controls operational frequency slave interface MACE device internal processing frames. SCLK unrelated clock frequency required 802.3/ Ethernet interface. SCLK frequency range MHz-25 MHz.
GENERAL INTERFACE XTAL1
Crystal Connection (Input) internal clock generator uses crystal that attached pins XTAL1 XTAL2. Internally, crystal frequency divided which determines network data rate. Alternatively, external CMOS-compatible clock signal used drive this pin. MACE device supports crystals generate frequency which compatible with IEEE 802.3 network quency tolerance jitter specifications.
EDSEL
System Clock Edge Select (Input) EDSEL static input that allows System Clock (SCLK) edge selection. EDSEL tied high, interface unit will assume falling edge timing. EDSEL tied low, interface unit will assume rising edge timing, which will effectively invert SCLK enters MACE device, i.e., address, control lines (CS, R/W, FDS, etc) data latched rising edge SCLK, data driven rising edge SCLK.
XTAL2
Crystal Connection (Output) internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock generator used XTAL1, then XTAL2 should left unconnected.
Timing Control (Input) Timing Control input conditions minimum number System Clocks (SCLK) cycles taken read write internal registers FIFOs. used wait state generator, allow additional time data presented host during write cycle, allow additional time data latched during read cycle. internal (SLEEP disabled) pull Timing Control
Number Clocks
SLEEP
Sleep Mode (Input) optimal power savings made extracted asserting SLEEP with both Auto Wake (AWAKE bit) Remote Wake (RWAKE bit) functions disabled. this "deep sleep" mode, outputs will forced into their inactive high impedance state, inputs will ignored except SLEEP, RESET, SCLK, TCK, TMS, pins. SCLK must cycles after assertion SLEEP. During "Deep Sleep", SCLK input optionally suspended maximum power savings. Upon exiting "Deep Sleep", hardware RESET must asserted SCLK restored. system must delay setting
Am79C940
bits configuration Control Register internal analog circuits allow stabilization. AWAKE prior activation SLEEP, 10BASE-T receiver LNKST output remain operational. RWAKE prior SLEEP being asserted, Manchester encoder/decoder, 10BASE-T cells remain operational, SRD, SRDCLK SF/BD outputs. input XTAL1 must remain active AWAKE RWAKE features operate. After exit from Auto Wake Remote Wake modes, activation hardware RESET required when SLEEP reasserted. deassertion SLEEP, MACE device will through internally generated hardware reset sequence, requiring re-initialization MACE registers.
power ground pins deleted. MACE device does have several sets media interfaces which typically unused most designs, however. Pins from some these interfaces deleted instead. Removed following: TXDAT- (previously used interface) (previously used EADI interface) (previously used host interface) RXPOL (previously used receive frame polarity driver) Note that pins from four separate interfaces removed rather than removing pins from single interface. Each these pins comes from four sides device. This done maintain symmetry, thus avoiding bond problems. general, most critical four removed pins TXDAT- SRD. Depending application, either EADI interface important. most designs, however, this will case.
Power Supply DVDD
Digital Power There four Digital pins.
PINS REMOVED TQFP PACKAGE THEIR EFFECTS
TXDAT- removal TXDAT- means that interface longer usable. interface designed used with media types that require isolation between DTE. Media which require isolation implemented more simply using interface, rather than interface. most designs this problem because most media requires isolation (10BASE-T, 10BASE2, 10BASE5) will port. About only media which does require isolation 10BASE-F. output used MACE device transfer receive data stream external address detection logic. part EADI interface. This used help interface MACE device external device. external typically required when application will operate promiscuous mode will need perfect filtering (i.e., internal hash filter will suffice). Example applications this sort operation bridges routers. Lack perfect filtering these applications forces more involved filtering thus either slows forwarding rates achieved forces more powerful CPU. part host interface MACE device. used indicate that read write cycle MACE device successful. asserted cycle, data transfer successful. Basically, this will happen write full transmit FIFO read from empty receive
DVSS
Digital Ground There Digital pins.
AVDD
Analog Power There four analog pins. Special attention should paid printed circuit board layout avoid excessive noise supply Manchester encoder/decoder (pins PLCC, pins PQFP). These supply lines should kept separate from DVDD lines back power supply practically possible.
AVSS
Analog Ground There analog pins. Special attention should paid printed circuit board layout avoid excessive noise supply Manchester encoder/decoder (pin PLCC, PQFP). These supply lines should kept separate from lines back power supply practically possible.
FUNCTIONS AVAILABLE WITH 80-PIN TQFP PACKAGE
84-pin PLCC configuration, pins used while 100-pin PQFP version, pins specified Connects. Moving 80-pin TQFP configuration requires removal pins. Since Ethernet controllers with integrated 10BASE-T have analog portions which very sensitive noise,
Am79C940
FIFO. general, there ways ensure that transfer always valid this required many designs. instance, TDTREQ RDTREQ pins used monitor state FIFOs ensure that data transfer only occurs correct times.
RXPOL RXPOL typically used drive indicating polarity receive frames. This function necessary correct operation Ethernet serves strictly status indication user. status receive polarity still available through PHYCC register.
Am79C940
FUNCTIONAL DESCRIPTION
Media Access Controller Ethernet (MACE) chip embodies Media Access Control (MAC) Physical Signaling (PLS) sub-layers 802.3 Standard. MACE device provides IEEE defined Attachment Unit Interface (AUI) coupling remote Media Attachment Units (MAUs) on-board transceivers. MACE device also provides Digital Attachment interface. system interface provides fundamental data conduit from 802.3 network. MACE device conjunction with user defined engine, provides 802.3 interface tailored specific application. addition, MACE device combined with similarly architected peripheral devices multi-channel controller, thereby providing system with access multiple peripheral devices with single master interface memory.
R/W. alternative FIFO access mechanism allows lines, ignoring address lines (ADD4-0). state line conjunction with input determines whether Receive FIFO read (R/W high) Transmit FIFO written (R/W low). MACE device system interface permits interleaved transmit receive transfers, allowing Transmit FIFO filled (primed) while frame being received from network and/or read from Receive FIFO. receive operation, MACE device asserts Receive Data Transfer Request (RDTREQ) when FIFO contains adequate data. first indication receive frame, bytes must received, assuming normal operation. Once initial byte threshold been reached, RDTREQ assertion de-assertion dependent programming Receive FIFO Watermark (RCVFW bits Configuration Control register). RDTREQ programmed activate when there bytes data available Receive FIFO. Enable Receive (ENRCV Configuration Control register) must assert RDTREQ. Runt Packet Accept feature invoked (RPA User Test Register), RDTREQ will asserted receive frames less than bytes basis internal and/or external address match only. When set, RDTREQ will asserted when entire frame been received when initial byte threshold been exceeded. FIFO Sub-Systems section further details. Note that Receive FIFO contain data bytes time RDTREQ asserted, automatic stripping feature been enabled (ASTRP Receive Frame Control register) minimum length packet with received. MACE device will check minimum received length from network, strip characters, pass only data frame through Receive FIFO. Latency Receive feature enabled (LLRCV Receive Frame Control Register), RDTREQ will asserted once watermark threshold been reached bytes plus some additional synchronization time). Note that system interface will therefore exposed potential disruption receive frame network condition (see FIFO Sub-System description additional details). transmit operation, MACE device asserts Transmit Data Transfer Request (TDTREQ) dependent programming Transmit FIFO Watermark (XMTFW bits Configuration Control register). TDTREQ will permanently asserted when Transmit FIFO empty. TDTREQ programmed activate when there bytes space available Transmit FIFO. Enable Transmit (ENXMT Configuration Control register) must assert TDTREQ. Write cycles
Network Interfaces
MACE device connected 802.3 network using AUI, BASE-T, GPSI network interfaces. Attachment Unit Interface (AUI) provides IEEE compliant differential interface remote on-board transceiver. integrated 10BASE-T provides direct interface twisted pair Ethernet networks. port connect local transceiver devices 10BASE2, 10BASE-T 10BASE-F connections. General Purpose Serial Interface (GPSI) supported, which effectively bypasses integrated Manchester encoder/ decoder, allows direct access to/from integral 802.3 Media Access Controller (MAC) provide support external encoding/decoding schemes. interface determined PORTSEL [1-0] bits Configuration Control register. EADI port does provide network connectivity, allows optional external circuit assist receive packet accept/reject.
System Interface
MACE device slave register based peripheral. transfers from device, including data, performed using simple memory read write commands. Access registers, including Transmit Receive FIFOs, performed with identical read write timing. information system interface synchronous system clock (SCLK), which allows simple exter logic designed interrogate device status control network data flow. Receive Transmit FIFOs read written driving appropriate address lines asserting
Am79C940
Transmit FIFO will return ENXMT disabled, data will written. MACE device will commence preamble sequence once Transmit Start Point (XMTSP bits Configuration Control register) threshold reached Transmit FIFO. Transmit FIFO data will overwritten until least data bits have been transmitted onto network. collision occurs within slot time (512 time) window, MACE device will generate sequence 32-bit zeroes pattern) before ceasing transmission. Transmit FIFO will reset point start transmit data field, message will retried after random back-off interval expired.
byte operation required, read/write transfers performed either upper lower data asserting appropriate byte enable. instance with BSWP reading from writing DBUS15-8 accomplished asserting BE1, allows data stream read from written appropriate FIFO byte order (byte byte 1,.byte equally valid read write data stream using DBUS7-0 asserting BE0. BSWP reading from writing DBUS15-8 accomplished asserting BE0, allows byte stream transferred byte order. When word operations required, BSWP ensures that byte ordering target memory compatible with 802.3 requirement send/receive data stream byte ascending order. With BSWP data transferred to/from FIFO assumes that byte will DBUS7-0 (activated BE0) byte will DBUS15-8 (activated BE1). With BSWP data transferred to/from FIFO assumes that byte will presented DBUS15-8 (activated BE0), byte will DBUS7-0 (activated BE1). There some additional special cases above generalized rules, which follows: When performing byte read operations, both halves data driven with identical data, effectively allowing user arbitrarily read from either upper lower data bus, when only byte enables activated. When byte write operations performed, Transmit FIFO latency affected. FIFO Sub-System section additional details. word read performed last data byte receive frame (EOF asserted), message contained number bytes host requested word operation asserting both BE1, then MACE device will present valid non-valid byte data bus. placement valid data data byte dependent target memory architecture. Regardless BSWP, single valid byte will read from memory bank. BSWP corresponds DBUS7-0; BSWP corresponds DBUS15-8. byte read performed when last data byte read receive frame (when MACE device activates signal), then same byte will presented both upper lower byte data bus, regardless which byte enable activated case byte read operations). When writing last byte transmit message Transmit FIFO, portion data
DETAILED FUNCTIONS Block Level Description
following sections describe major sub-blocks external interfaces MACE device.
Interface Unit (BIU)
performs interface between host system Transmit Receive FIFOs, well chip control status registers. configured accept data presented either little-endian indian format, minimizing external logic required access MACE device internal FIFOs registers. addition, directly supports 8-bit transfers incorporates features external latches. Externally, FIFOs appear independent registers located individual addresses. remainder internal registers occupy additional consecutive addresses, appear 8-bits wide.
FIFO Data Path
operates assuming that 16-bit data path to/from internal FIFOs configured independent byte paths, activated Byte Enable nals BE1. only used during accesses 16-bit wide Transmit Receive FIFOs. After hardware software reset, BSWP will cleared. FIFO accesses MACE device will operate assuming Intel 80x86 type memory convention (most significant byte word stored higher addressed byte). Word data transfers to/from FIFOs over DBUS15-0 lines will have least significant byte located DBUS7-0 (activated BE0) most significant byte located DBUS15-8 (activated BE1). FIFO data read written using either byte and/ word operations.
Am79C940
that last byte transferred over irrelevant, providing appropriate byte enable used. BSWP data presented DBUS7-0 using DBUS15-8 using BE1. BSWP data presented DBUS7-0 using DBUS15-8 using BE0. When neither asserted, data transfer will take place. will asserted. Byte Alignment FIFO Read Operations
BSWP DBUS7-0 DBUS15-8
Byte Alignment Register Write Operations
BSWP DBUS7-0 Write Data DBUS15-8 Write Data
FIFO Sub-System
MACE device independent FIFOs, with 128-bytes receive 136-bytes transmit operations. FIFO sub-system contains both FIFOs, control logic handle normal exception related conditions. Transmit Receive FIFOs interface network side with serializer/de-serializer engine. provides access between FIFOs host system enable movement data from network. Internally, FIFOs appear independent 16-bit wide registers. Bytes words written Transmit FIFO (XMTFIFO), read from Receive FIFO (RCVFIFO). Byte word transfers mixed order. will ensure correct byte ordering dependent target host system, determined programming BSWP Configuration Control register. XMTFIFO RCVFIFO have three different modes operation. These Normal (Default), Burst Latency Receive. Default operation will used after hardware RESET software SWRST have been activated. remainder this general description applies modes except where specific differences noted. Transmit FIFO-General Operation When writing bytes XMTFIFO, certain restrictions apply. These restrictions have direct influence latency provided FIFO host system. When byte written FIFO location, entire word location used. unused byte marked hole XMTFIFO. These holes skipped during serialization process performed engine, when bytes unloaded from XMTFIFO. instance, assume Transmit FIFO Watermark (XMTFW) write cycles. host writes byte wide data XMTFIFO, after write cycles there will space left XMTFIFO only more write cycles. Therefore TDTREQ will de-assert even though only 36-bytes data have been loaded into XMTFIFO. Transmission will commence until 64-bytes End-of-Frame available XMFIFO, transmission would star TDTREQ would remain de-asserted. Hence byte
Byte Alignment FIFO Write Operations
BSWP DBUS7-0 DBUS15-8
Control Status Register Data Path
registers address range 2-31 8-bits wide. When read cycle executed these registers, MACE device will drive data both bytes data bus, regardless programming BSWP. When write cycle executed, MACE device strobes data based programming BSWP shown tables below. accesses addresses 2-31 independent pins. Byte Alignment Register Read Operations
BSWP DBUS7-0 Read Data Read Data DBUS15-8 Read Data Read Data
Am79C940
wide data transfers, XMTFW should programmed write cycle limit, host should ensure that sufficient data will written XMTFIFO after TDTREQ been de-asserted (which permitted), guarantee that transmission will commence. third alternative program Transmit Start Point (XMTSP) Configuration Control register below 64-byte default; thereby imposing lower latency host system requiring additional data ensure XMTFIFO does underflow during transmit process, versus using default XMTSP value. Note that single byte writes executed XMTFIFO, XMTSP 64-bytes, transmission will commence, XMTFIFO. number write cycles that host uses write packet into Transmit FIFO will also directly influence amount space utilized transmit message. number write cycles required transfer packet Transmit FIFO even, number bytes used Transmit FIFO will 2*n. number write cycles required transfer packet Transmit FIFO odd, number bytes used Transmit FIFO will because Frame indication XMTFIFO always placed 4-byte boundary. example, 32-byte message written bytes cycles) will 64-bytes space Transmit FIFO (2*n 64), whereas 65-byte message written words byte cycles) would 68-bytes (2*n Transmit FIFO been sized appropriately minimize system interface overhead. However, consideration must given overall system design byte writes supported. order guarantee that sufficient space present XMTFIFO accept number write cycles programmed XMTFW (including Frame delimiter), TDTREQ inactive before XMTSP threshold reached when using burst mode (XMTBRST instance, assume that XMTFW programmed allow write cycles (default), XMTSP programmed require bytes (default) before starting transmission. Assuming that host bursts transmit data cycle block, writing single byte anywhere within this block will mean that XMTSP will have been reached. This would typical scenario transmit data buffer aligned word boundary. MACE device will continue assert TDTREQ since additional write cycles still executed. host starts second burst, XMTSP will reached, TDTREQ will deassert when less that write cycle performed although data written host will continue accepted.
host must aware that additional space exists XMTFIFO although TDTREQ becomes inactive, must continue write data ensure XMTSP threshold achieved. transmit activity will commence until XMTSP threshold reached. Once write cycles have been executed. Note that write cycles performed XMTFIFO even TDTREQ inactive. When TDTREQ asserted, guarantees that minimum amount space exists, when TDTREQ deasserted, does necessarily indicate that there space XMTFIFO. will indicate successful acceptance data Transmit FIFO. another example, assume again that XMTFW programmed write cycles. host writes word wide data continuously XMTFIFO, TDTREQ will deassert when writes have executed XMTFIFO, which point 72-bytes will have been written XMTFIFO, 64-byte XMTSP will have been exceeded transmission preamble will have commenced. TDTREQ will re-assert until transmission packet data commenced possibility losing data collision within slot time removed (512 bits have been transmitted without collision indication). Assuming that host actually stopped writing data after initial 72-bytes, there will only 16-bytes data remaining XMTFIFO (8-bytes preamble/SFD plus 56-bytes data have been transmitted), corresponding 12.8 latency before XMTFIFO underrun occurs. This latency considerably less than maximum possible 57.6 system have assumed. host continued with block transfer until write cycles been performed, 128-bytes would have been written XMTFIFO, 72-bytes latency re-asserted. Transmit FIFO-Burst Operation XMTFIFO burst mode, programmed XMTBRST FIFO Configuration Control register, modifies TDTREQ behavior. assertion TDTREQ controlled programming XMTFW bits, such that when specified number write cycles guaranteed 32), TDTREQ will asserted. TDTREQ will de-asser when FIFO only accept single write cycle (one word write including Frame delimiter) allowing external device burst data into XMTFIFO when TDTREQ asserted, stop when TDTREQ deasserted. Receive FIFO-General Operation Receive FIFO contains additional logic ensure that sufficient data present RCVFIFO allow specified number bytes read, regardless ordering byte/word read accesses. This
Am79C940
impact perceived latency that Receive FIFO provides host system. description table below outline point which RDTREQ will asserted when first duration packet been received when subsequent transfer packet host system required. preamble/SFD bytes loaded into Receive FIFO. references bytes pass through receive FIFO. These references received after preamble/SFD sequence. first assertion RDTREQ packet will occur after longer following conditions met: 64-bytes have been received assure runt packets packets experiencing collision within slot time will rejected).
Bytes Required First Assertion RDTREQ
RCVFW threshold reached plus additional bytes. additional bytes necessary ensure that permutation byte/word read access guaranteed. They required threshold values, case 32-byte thresholds, requirement that slot time criteria dominates. subsequent assertion RDTREQ necessary complete transfer packet will occur after RCVFW threshold reached plus additional bytes. table below also outlines latency provided MACE device when RDTREQ asserted.
Receive FIFO Watermarks, RDTREQ Assertion Latency
RCVFW [1-0] Bytes Latency After First Assertion RDTREQ Bytes Required Subsequent Assertion RDTREQ Bytes Latency After Subsequent Assertion RDTREQ
Receive FIFO-Burst Operation RCVFIFO also provides burst mode capability, programmed RCVBRST FIFO Configuration Control register, modify operation RDTREQ.The assertion RDTREQ will occur according programming RCVFW bits. RDTREQ will de-asserted when RCVFIFO only provide single read cycle (one word read). This allows external device burst data from RCVFIFO once RDTREQ asserted, stop when RDTREQ deasserted. Receive FIFO-Low Latency Receive Operation Latency Receive mode programmed using Latency Receive (LLRCV Receive Frame Control register). This effectively causes assertion RDTREQ directly coupled watermark bytes RCVFIFO. Once 12-byte threshold reached (plus some internal synchronization delay less than byte), RDTREQ will asserted, will remain active until RCVFIFO support only read cycle (one word data), burst operation described earlier. exception case where bytes padding required FIFO design, unless packet. intended Latency Receive mode allow fast forwarding received packet bridge application. this case, receiving process made aware receive packet after only instead waiting 60.8 (76-bytes) necessary initial assertion RDTREQ. Ethernet-to-Ethernet bridge
employing MACE device Ethernet connections) with XMTSP MACE controller FIFOs minimum (4-bytes), forwarding receive packet achieved within delay including processing overhead. Note however that this mode places significant burden host processor. receiving MACE device will longer delete runt packets. runt packet will have Receive Frame Status appended receive data which host must read normal. MACE device will attempt delete runt packets from RCVFIFO Latency Receive mode. Collision fragments will also passed host they detected after 12-byte threshold been reached. collision occurs, Receive Frame Status (RCVFS) will appended data successfully received RCVFIFO point collision detected. additional receive data will written RCVFIFO. Note that RCVFS will become available until after receive activity ceases. collision indication (CLSN) Receive Status (RCVSTS) will set, Receive Message Byte Count (RCVCNT) will correct count total duration activity, including period that collision detected. detection normal (slot time) collisions versus late collisions only made counting number bytes that were successfully received prior termination packet data. cases where reception ends prematurely (runt collision), data that successfully received prior termination reception must read from RCVFIFO before RCVFS bytes available.
Am79C940
Media Access Control (MAC)
Media Access Control engine heart MACE device, incorporating essential protocol requirements operation compliant Ethernet/ 802.3 node, providing interface between FIFO sub-system Manchester Encoder/ Decoder (MENDEC). engine fully compliant Section ISO/ 8802-3 (ANSI/IEEE Standard 1990 Second edition) ANSI/IEEE 802.3 (1985). engine provides enhanced features, programmed through Transmit Frame Control Receive Frame Control registers, designed minimize host supervision post message processing. These features include ability disable retries after packet-by-packet basis, automatic field insertion deletion enforce minimum frame size attributes. primary attributes engine are: Transmit receive message data encapsulation Framing (frame boundary delimitation, frame synchronization) Addressing (source destination address handling) Error detection (physical medium transmission errors) Media access management Medium allocation (collision avoidance) Contention resolution (collision handling) Transmit Receive Message Data Encapsulation Data passed MACE device Transmit FIFO will assumed correctly formatted transmission over network valid packet. user required pass data stream transmission MACE chip correct order, according byte ordering convention programmed BIU. MACE device provides minimum frame size enforcement transmit receive packets. When APAD (default), transmit messages will padded with sufficient bytes (containing 00h) ensure that receiving station will observe information field (destination address, source address, length/type, data FCS) 64-bytes. When ASTRP (default), receiver will automatically strip bytes from received message value length field below minimum data size (46-bytes). Both features independently over-ridden allow illegally short (less than 64-bytes and/or received.
Framing (Frame Boundary Delimitation, Frame Synchronization)
MACE device will autonomously handle construction transmit frame. When Transmit FIFO been filled predetermined threshold (set XMTSP), providing access channel currently permitted, MACE device will commence the7 byte preamble sequence (10101010b, where first transmitted MACE device will subsequently append Start Frame Delimiter (SFD) byte (10101011) followed serialized data from Transmit FIFO. Once data been completed, MACE device will append (most significant first) computed entire data tion message. Note that user responsible correct ordering content each fields frame, including destination address, source address, length/type packet data. receive section MACE device will detect incoming preamble sequence lock encoded clock. internal MENDEC will decode serial stream present this engine. will discard first 8-bits information before searching sequence. Once detected, subsequent bits treated part frame. MACE device will inspect length field ensure minimum frame size, strip unnecessary characters enabled), pass remaining bytes through Receive FIFO host. stripping performed, MACE device will also strip received bytes, although normal computation checking will occur. Note that apart from stripping, frame will passed unmodified host. length field value greater, MACE device will attempt validate length against number bytes contained message. frame terminates suffers collision before 64-bytes information (after SFD) have been received, MACE device will automatically delete frame from Receive FIFO, without host intervention. Note however, that Latency Receive option been enabled (LLRCV Receive Frame Control register), MACE device will delete receive frames which experience collision once 12-byte watermark been reached (see FIFO Sub-System section additional details).
Addressing (Source Destination Address Handling)
first 6-bytes information after will interpreted destination address field. MACE device provides facilities physical, logical broadcast address reception. addition, multiple physical addresses constructed (perfect
Am79C940
address filtering) using external logic conjunction with EADI interface.
Error Detection (Physical Medium Transmission Errors)
MACE device provides several facilities which report recover from errors medium. addition, network protected from gross errors inability host keep pace with MACE device activity. completion transmission, MACE device will report Transmit Frame Status frame. exact number transmission retry attempts reported (ONE, MORE used with XMTRC, RTRY), whether MACE device Defer (DEFER) channel activity. addition, Loss Carrier reported, indicating that there interruption ability MACE device monitor transmission. Repeated LCAR errors indicate potentially faulty transceiver network connection. Excessive Defer (EXDEF) will reported Transmit Retry Count register transmit frame wait abnormally long period before transmission. Additional transmit error conditions reported through Interrupt Register. Late Collision (LCOL) error indicates that transmission suffered collision after slot time. This indicative badly configured network. Late collisions should occur normal operating network. Collision Error (CERR) indicates that transceiver respond with Test message within predetermined time after transmission completed. This failed transceiver, disconnected faulty transceiver drop cable, fact transceiver does support this feature disabled). addition reporting network errors, MACE device will also attempt prevent creation network error caused inability host service MACE device. During transmission, host fails keep Transmit FIFO filled sufficiently, causing underflow, MACE device will guarantee message either sent runt packet (which will deleted receiving station) invalid (which will also allow receiving station reject message). status each receive message passed Receive Frame Status bytes. Framing errors (FRAM) reported, although received frame still passed host. FRAM error will only reported error detected there integral number bytes message. MACE device will ignore seven additional bits message (dribbling bits), which occur under normal network operating conditions. reception
eight additional bits will cause MACE device de-serialize entire byte, will result received message being modified. Received messages which suffer collision after 64-byte times (after SFD) will marked indicate they have suffered late collision (CLSN). Additional counters provided report Receive Collision Count Runt Packet Count used network statistics utilization calculations. Note that MACE device detects received packet which pattern preamble (after first 8-bits which ignored), entire packet will ignored. MACE device will wait network inactive before attempting receive additional frames. Media Access Management basic requirement stations network provide fairness channel allocation. 802.3/ Ethernet protocols define media access mechanism which permits stations access channel with equality. node attempt contend channel waiting predetermined time (Inter Packet interval) after last activity, before transmitting media. channel multidrop communications medium (with various topological configurations permitted) which allows single station transmit other stations receive. nodes simultaneously contend channel, their signals will interact causing loss data, defined collision. responsibility attempt avoid recover from collision, guarantee data integrity end-to-end transmission receiving station.
Medium Allocation (Collision Avoidance)
IEEE 802.3 Standard (ISO/IEC 8802-3 1990) requires that CSMA/CD monitors medium traffic watching carrier activity. When carrier detected, media considered busy, should defer existing message. IEEE 802.3 Standard also allows optional part deferral after receive message. ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.1:
Note: possible carrier sense indication fail asserted during collision media. deference process simply times interFrame based this indication possible short interFrame generated, leading potential reception failure subsequent frame. enhance system robustness following optional measures, specified 4.2.8, recommended when interFrameSpacing Part1 other than zero:"
Upon completing transmission, start timing interpacket gap, soon transmitting carrier Sense both false.
Am79C940
When timing interFrame following reception, reset interFrame timing carrierSense becomes true during first interFrame timing interval. During final interval timer shall reset ensure fair access medium. initial period shorter than interval permissible including zero." engine implements optional receive inter-frame-spacing time second part inter-frame-spacing interval therefore MACE device will perform part deferral algorithm specified Section 4.2.8 (Process Deference). Inter Packet (IPG) timer will start timing InterFrameSpacing after receive carrier (InterFrameSpacingPart1-IFS1) MACE device will defer pending transmit frame respond receive message. counter will reset zero continuously until carrier deasserts, which point counter will resume count once again. Once IFS1 period 6.0µs elapsed, MACE device will begin timing second part deferral (InterFrameSpacingPart2-IFS2) Once IFS1 completed, IFS2 commenced, MACE chip will defer receive packet transmit packet pending. This means that MACE device will attempt receive incoming packet, will start transmit regardless network activity, forcing collision existing transmission progress. MACE device will guarantee complete preamble (64-bit) (32-bit) sequence before ceasing transmission invoking random backoff algorithm. addition deferral after receive process, MACE device also allows transmit part deferral implemented option. option disabled using DXMT2PD Configurat transmission useful ensuring that severe shrinkage cannot occur specific circumstances, causing transmit message follow receive message closely, make them indistinguishable. During time period immediately after transmission been completed, external transceiver case standard connected device), should generate Test message nominal burst 5-15 duration) pair (within 0.61.6 after transmission ceases). During time period which Test message expected MACE device will respond receive carrier sense.
t42I/IEEE 802.3-1990 Edition, 7.2.4.6 (1)): conclusion output function, opens time window during which expects signal_quality_error signal asserted Control circuit. time window begins when CARRIER_STATUS becomes CARRIER_OFF. execution output function does cause CARRIER_ON occur, test occurs DTE. duration window shall least more than During time window Carrier Sense Function inhibited." MACE device implements carrier sense blinding period within µs-4.0 from deassertion carrier sense after transmission. This effectively means that when transmit part deferral enabled (DXMT2PD Configuration Control register cleared) IFS1 time from after transmission. However, since shrinkage below will encountered correctly configured networks, since fragment size will larger than blinding window, then counter will reset worst case shrinkage/fragment scenario MACE device will defer transmission. MACE chip will restart carrier sense blinding period carrier detected within 4.0-6.0 portion IFS1, will restart timing entire IFS1 period.
Contention Resolution (Collision Handling)
Collision detection performed reported engine either integrated Manchester Encoder/Decoder (MENDEC), external function (e.g. Serial Interface Adaptor, Am7992B) utilizing GPSI. collision detected before complete preamble/ sequence been transmitted, MACE device will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed, prior bits being transmitted, MACE device will abort transmission, append sequence immediately. sequence 32-bit zeroes pattern. MACE device will attempt transmit frame total times (initial attempt plus retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled, dependent backoff time that MACE device computes. Each collision which occurs during transmission process will cause value XMTRC Transmit Retry Count register updated. single retry required, will Transmit Frame Status. more than retry required, MORE will set, exact number attempts deter mined (XMTRC+1). attempts experienced collisions,
Am79C940
RTRY will (ONE MORE will clear), transmit message will flushed from XMTFIFO, either resetting XMTFIFO End-of-Frame exists) moving XMTFIFO End-of-Frame present). retries have been disabled setting DRTRY bit, MACE device will abandon transmission frame detection first collision. this case, only RTRY will transmit message will flushed from XMTFIFO. RTRY condition will cause de-assertion TDTREQ, assertion INTR pin, providing XMTINbit cleared. collision detected after times have been transmitted, collision termed late collision. MACE device will abort transmission, append sequence LCOL Transmit Frame Status. retry attempt will scheduled detection late collision, XMTFIFO will flushed. late collision condition will cause de-assertion TDTREQ, assertion INTR pin, providing XMTINbit cleared. IEEE 802.3 Standard requires truncated binary exponential backoff algorithm which provides controlled pseudo random mechanism enforce collision backoff interval, before re-transmission attempted.
nodes await reduction channel activity. Once channel activity reduced, nodes resolving collision time-out their slot time counters normal. receive message suffers collision, will either runt, which case will deleted Receive FIFO, will marked receive late collision, using CLSN Receive Frame Status register. frames which suffer collision within slot time will deleted Receive FIFO without requesting host intervention, providing that LLRCV (Receive Frame Control) set. Runt packets which suffer collision will aborted regardless state (User Test Register). collision commences after slot time, MACE device receiver will stop sending collided packet data Receive FIFO packet data read system will contain amount data received point collision; CLSN Receive Frame Status register will indicate receive late collision. Note that Receive Message Byte Count will report total number bytes during receive activity, including collision. normal receive collision cases, MACE device eliminates transfer packet data across host bus. receive late collision condition, MACE chip minimizes amount transferred. These functions preserve bandwidth utilization.
ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.5:
enforcing collision (jamming), CSMA/CD sublayer delays before attempting re-transmit frame. delay integer multiple slotTime. number slot times delay before re-transmission attempt chosen uniformly distributed random integer range: where (n,10)." MACE device implements random number experiencing collision, will have their retry intervals track identically, causing retry errors. MACE device provides alternative algorithm, which suspends counting slot time/IPG during time that receive carrier sense detected. This aids networks where large numbers nodes present, numerous nodes collision. effectively accelerates increase backoff time busy networks, allows nodes involved collision access channel whilst colliding
Manchester Encoder/Decoder (MENDEC)
integrated Manchester Encoder/Decoder provides (Physical Signaling) functions required fully compliant IEEE 802.3 station. MENDEC block contains AUI, interfaces, supports 10BASE-T interface; which transfer data appropriate transceiver devices Manchester encoded format. MENDEC provides encoding function data transmitted network using high accuracy on-board oscillator, driven either crystal oscillator external CMOS level compatible clock generator. MENDEC also provides decoding function from data received from network. MENDEC contains Power Reset (POR) circuit, which ensures that analog portions MACE device forced into their correct state during power prevents erroneous data transmission and/or reception during this time. External Crystal Characteristics When using crystal drive oscillator, following crystal specification should used ensure less than ±0.5 jitter
Am79C940
Parameter Parallel Resonant Frequency Resonant Frequency Error Change Resonant Frequency With Respect Temperature pF)* Crystal Capacitance Motional Crystal Capacitance (C1) Series Resistance Shunt Capacitance
Units
0.022
Requires trimming crystal spec; trim total
External Clock Drive Characteristics When driving oscillator from external clock source, XTAL2 must left floating (unconnected). external clock having following characteristics must used ensure less than ±0.5 jitter DO±.
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time (tHIGH/tLOW): XTAL1 Falling Edge Falling Edge Jitter: ±0.01% from VDD-0.5 duty cycle ±0.2 input (VDD/2)
also used stable rate clock receive section controller. oscillator requires external 0.005% crystal, external 0.01% CMOS-level input reference. accuracy requirements external crystal used tighter because allowance on-chip oscillator must made deliver final accuracy 0.01%. Transmission enabled controller. long ITENA request remains active, serial output controller will Manchester encoded appear DO±. When internal request dropped controller, differential transmit outputs idle states, dependent TSEL Mode Register (CSR15,
TSEL LOW: idle state yields "zero" differential operate transformercoupled loads. TSEL HIGH: this idle state, positive with respect (logical\HIGH).
MENDEC Transmit Path transmit section encodes separate clock data input signals into standard Manchester encoded serial stream. transmit outputs (DO±) designed operate into terminated transmission lines. When operating into terminated transmission line, signaling meets required output levels skew Cheapernet, Ethernet IEEE-802.3. Transmitter Timing Operation fundamental mode crystal oscillator provides basic timing reference portion MACE device. divided two, create internal transmit clock reference. Both clocks into SIA's Manchester Encoder generate transitions encoded data stream. internal transmit clock used internally synchronize Internal Transmit Data (ITXD) from controller Internal Transmit Enable (ITENA). internal transmit clock
Receive Path principal functions Receiver signal MACE device that there information receive pair, separate incoming Manchester encoded data stream into clock data. Receiver section (see Receiver Block Diagram) consists parallel paths. receive data path zero threshold, wide bandwidth line receiver. carrier path offset threshold bandpass detecting line receiver. Both receivers share common bias networks allow operation over wide input common mode range.
Am79C940
Data Receiver
Manchester Decoder
SRDCLK
Noise Reject Filter
Carrier Detect Circuit
RXCRS
Receiver Block Diagram
16235D-5
Input Signal Conditioning Transient noise pulses input data stream rejected Noise Rejection Filter. Pulse width rejection proportional transmit data rate. inputs more negative than minus also suppressed. Carrier Detection circuitry detects presence incoming data packet discerning rejecting noise from expected Manchester data, controls stop start phase-lock loop during clock acquisition. Clock acquisition requires valid Manchester pattern 1010 lock onto incoming message. When input amplitude pulse width conditions DI±, internal enable signal from controller (RXCRS) asserted clock acquisition cycle initiated. Clock Acquisition When there activity (receiver idle), receive oscillator phase locked TCK. first negative clock transition (bit cell center first valid Manchester "0") after RXCRS asserted interrupts receive oscillator. oscillator then restarted second Manchester (bit time phase locked result, acquires clock from incoming Manchester pattern times with "1010" Manchester pattern. SRDCLK enabled time after clock acquisition cell ENPLSIO configuration control register. HIGH state when receiver idle SRDCLK). however, undefined when clock acquired remain HIGH change state whenever SRDCLK enabled. time through cell
controller portion MACE device sees first SRDCLK transition. This also strobes incoming fifth Manchester "1". make transition after SRDCLK rising edge cell state still undefined. Manchester clocked output time cell Tracking After clock acquisition, phase-locked clock compared incoming transition cell center (BCC) resulting phase error applied correction circuit. This circuit ensures that phase-locked clock remains locked received signal. Individual cell phase corrections Voltage Controlled Oscillator (VCO) limited phase differencebetween BCCand phaselocked clock. Carrier Tracking Message carrier detection circuit monitors inputs after RXCRS asserted message. RXCRS de-asserts times after last positive transition incoming message. This initiates reception cycle. time delay from last rising edge message RXCRS deassert allows last strobed SRDCLK transferred controller section, prevents extra bit(s) message. When IRENA de-asserts (see Receive Timing-End Reception (Last Receive Timing-End Reception (Last waveform diagrams) RXCRS hold timer inhibits RXCRS assertion least times. Data Decoding data receiver comparator with clocked output minimize noise sensitivity inputs. Input error less than minimize sensitivity
Am79C940
input rise fall time. SRDCLK strobes data receiver output time determine value Manchester bit, clocks data following SRDCLK. data receiver also generates signal used phase detector comparison internal voltage controlled oscillator (VCO). Differential Input Terminations differential input Manchester data (DI±) externally terminated 40.2 resistors
optional common-mode bypass capacitor, shown Differential Input Termination diagram below. differential input impedance, ZIDF, common-mode input impedance, ZICM, specified that Ethernet specification cable termination impedance using standard resistor terminators. devices used, ohms also suitable value. differential inputs terminated exactly same pair.
Isolation Transformer CURIO
40.2
40.2
0.01µF
16235D-6
Differential Input Termination
Collision Detection transceiver detects collision condition network generates differential signal inputs. This collision signal passes through input stage which detects signal levels pulse duration. When signal detected MENDEC sets CLSN line HIGH. condition continues approximately times after last LOW-to-HIGH transition CI±. Jitter Tolerance Definition Receive Timing-Start Reception Clock Acquisition waveform diagram shows internal timing relationships implemented decoding Manchester data module. utilizes clock capture circuit align internal data strobe with incoming stream. clock acquisition circuitry requires four valid bits with values 1010. Clock phase locked negative transition cell center second pattern. Since data strobed time, Manchester transitions which shift from their nominal placement through time will result improperly decoded
data. With this criteria error, definition "Jitter Handling" peak deviation approaching crossing cell position from nominal input transition, which section will properly decode data.
Attachment Unit Interface (AUI)
(Physical Signaling) (Physical Medium Attachment) interface which effectively connects MAU. differential interface provided MACE device fully compliant Section 8802-3 (ANSI/IEEE 802.3). After MACE device initiates transmission will expect data looped-back pair (AUI port selected). This will internally generate carrier sense, indicating that integrity data path from intact, that operating correctly. This carrier sense signal must asserted during transmission when using port (DO± transmitting). carrier sense does become active response data transmission, becomes inactive before transmission, loss carrier (LCAR) error will Transmit
Am79C940
Frame Status (bit after packet been transmitted.
Digital Attachment Interface (DAI)
Digital Attachment Interface simplified electrical attachment specification which allows MAUs which require isolation between (e.g. devices compatible with 10BASE-T Standard 10BASE-FL Draft document) implemented. data transferred across port Manchester Encoded. Decoding encoding performed MENDEC. port will accept receive data basis that RXCRS input active, will take data presented RXDAT input valid Manchester data. Transmit data sent external transceiver MACE device asserting TXEN presenting complimentary data TXDAT± pair. During idle, MACE device will assert TXDAT+ line high, TXDAT line low, while TXEN maintained inactive (high). MACE device implements logical collision detection will simultaneous assertion TXEN RXCRS internally detect collision condition, take appropriate internal action (such abort current transmit receive activity), provide external indication using CLSN pin. external transceiver utilized interface must loop back transmit data (presented MACE device) TXDAT± pins RXDAT pin. Neither should transceiver assert RXCRS when transmitting data network. Duplication these functions external transceiver (unless MACE device external loop back test configuration) will cause false collision indications detected. order provide integrity test connectivity between MACE device external transceiver similar Test Message provided part functionality, MACE device programmed operate port external loopback test. this case, external transceiver assumed loopback TXDAT± data stream RXDAT pin, assert RXCRS response TXEN request. When external loopback mode operation (programmed LOOP [1-0] 01), MACE device will internally detect collision condition. external transceiver assumed take action ensure that this test will disrupt network. This type test intended operated very limited period (e.g. after power up), since transceiver assumed located physically close MACE device with minimal risk disconnection (e.g. connected printed circuit board traces). Note that when port selected, LCAR errors will occur, since MACE device will internally loop back transmit data path receiver. This loop back function must duplicated transceiver
which externally connected port, since this will result condition where collision generated during transmit activity. transmit function port protected jabber mechanism which will invoked TXDAT± TXEN circuit active excessive period ms). This prevents single node from disrupting network stuck-on faulty transmitter. this maximum transmit time exceeded, port transmitter circuitry disabled, CLSN asserted, Jabber (JAB Interrupt Register) INTR will asserted providing JABM (Interrupt Mask Register) cleared. Once internal transmit data stream from MENDEC stops (TXEN deasserts), unjab time ms-750 will elapse before MACE device deasserts CLSN indication re-enables transmit circuitry. When jabber detected, MACE device will assert CLSN pin, de-assert TXEN (regardless internal MENDEC activity) TXDAT+ TXDAT pins their inactive state.
10BASE-T Interface Twisted Pair Transmit Function
Data transmission over 10BASE-T medium requires integrated 10BASE-T MAU, uses differential driver circuitry TXD± TXP± pins. driver circuitry provides necessary electrical driving capability pre-distortion control transmitting signals over maximum length Twisted Pair cable, specified 10BASE-T supplement IEEE 802.3 Standard. transmit function data output meets propagation delays jitter specified standard. During normal transmission, providing that 10BASE-T Link Fail jabber state, TXEN will driven HIGH used indirectly drive status LED.
Twisted Pair Receive Function
receiver complies with receiver specifications IEEE 802.3 10BASE-T Standard, including noise immunity received signal rejection criteria (Smart Squelch). Signals meeting this criteria appearing RXD± differential input pair routed internal MENDEC. receiver function meets propagation delays jitter requirements specified 10BASE-T Standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals mitigate carrier fade event worst case signal attenuation crosstalk noise conditions. During receive, RXCRS driven HIGH used indirectly drive status LED. Note that 10BASE-T Standard defines receive input amplitude external Media Dependent Interface
Am79C940
(MDI). Filter transformer loss specified. 10BASE-T receiver squelch levels defined account insertion loss MHz, which typical type receive filters/transformers recommended (see Appendix additional details). Normal 10BASE-T compatible receive thresholds employed when inactive (PHY Configuration Control register). When set, Receive Threshold option invoked, sensitivity 10BASE-T receiver increased. This allows longer line lengths employed, exceeding 100m target distance normal 10BASE-T (assuming typical cable). additional cable distance attributes directly increased signal attenuation reduced signal amplitude 10BASE-T receiver. However, from system perspective, making receiver more sensitive means that also more susceptible extraneous noise, primarily caused coupling from co-resident services (crosstalk). this reason, recommended that when using Receive Threshold option that service should installed 4-pair cable only. Multi-pair cables within same outer sheath have lower crosstalk attenuation, allow noise emitted from adjacent pairs couple into receive pair, sufficient amplitude falsely unsquelch 10BASE-T receiver.
MACE devices integrated 10BASE-T transceiver will mimic performance externally connected device (such 10BASE-T connected using AUI). When 10BASE-T transceiver link fail, receive data path transceiver must disabled. MACE device will report Loss Carrier error (LCAR Transmit Frame Status register) absence normal loopback path, every packet transmitted during link fail condition. addition, Collision Error (CERR Transmit Frame Status register) will also reported (see section Signal Quality Error Test Function additional details). AWAKE Configuration Control register prior assertion hardware SLEEP pin, 10BASE-T receiver remains operable, able detect indicate (using LNKST output) presence legitimate Link Test pulses receive activity. transmission Link Test pulses suspended reduce power consumption. RWAKE Configuration Control register prior assertion hardware SLEEP pin, 10BASE-T receiver transmitter functions remain active, LNKST output disabled, EADI output pins enabled. addition port (transmit receive) remains active. Note that since core will sleep mode, transmit activity possible, transmission Link Test pulses also suspended reduce power consumption.
Link Test Function
link test function implemented specified 10BASE-T standard. During periods transmit pair inactivity, Link Test pulses will periodically sentover twisted pair medium constantly monitor medium integrity. When link test function enabled, absence Link Test pulses receive data RXD± pair will cause 10BASE-T into Link Fail state. Link Fail state, data transmission, data reception, data loopback collision detection functions disabled, remain disabled until valid data consecutive link pulses appear RXD± pair. During Link Fail, LNKST inactive (externally pulled HIGH), Link Fail (LNKFL Configuration Control register) will set. When link identified functional, LNKST driven (capable directly driving Link using integrated driver) LNKFL will cleared. order inter-operate with systems which implement link test, this function disabled setting Disable Link Test (DLNKTST Configuration Control register). With link test disabled, data driver, receiver loopback functions well collision detection remain enabled irrespective presence absence data link pulses RXD± pair.
Polarity Detection Reversal
Twisted Pair receive function includes ability invert polarity signals appearing RXD± pair polarity received signal reversed (such case wiring error). This feature allows data packets received from reverse wired RXD± input pair corrected 10BASE-T prior transfer MENDEC. polarity detection function activated following reset Link Fail, will reverse receive polarity based both polarity previous Link Test pulses polarity subsequent packets with valid Transmit Delimiter (ETD). When Link Fail state, internal 10BASE-T receiver will recognize Link Test pulses either positive negative polarity. Exit from Link Fail state made reception five consecutive Link Test pulses identical polarity. entry Link Pass state, polarity last five Link Test pulses used determine initial receive polarity configuration receiver reconfigured subsequently recognize only Link Test pulses previously recognized polarity. This link pulse algorithm employed only until polarity determination made described later inthis section.
Am79C940
Positive Link Test pulses defined received signal with positive amplitude greater than (LRT LOW) with pulse width ns-200 This positive excursion followed negative excursion. This definition consistent with expected received signal correctly wired receiver, when Link Test pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. Negative Link Test pulses defined received signals with negative amplitude greater than (LRT LOW) with pulse width ns-200 This negative excursion followed positive excursion. This definition consistent with expected received signal reverse wired receiver, when Link Test pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. polarity detection/correction algorithm will remain armed until consecutive packets with valid identical polarity detected. When armed, receiver capable changing initial previous polarity configuration based most recent polarity. receipt first packet with valid following reset Link Fail, MACE device will utilize inferred polarity information configure RXD± input, regardless previous state. receipt second packet with valid with correct polarity, detection/correction algorithm will lock-in received polarity. second subsequent) packet detected confirming previous polarity decision, most recently detected polarity will used default. Note that packets with invalid have effect updating previous polarity decision. Once consecutive packets with valid have been received, MACE device will disable detection/correction algorithm until either Link Fail condition occurs hardware software reset occurs. During polarity reversal, RXPOL should externally pulled HIGH Reversed Polarity (REVPOL Configuration Control register) will set. During normal polarity conditions, RXPOL driven (capable directly driving Polarity using integrated driver) REVPOL will cleared. desired, polarity correction function disabled setting Disable Auto Polarity Correction (DAPC Configuration Control register). However, polarity detection portion algorithm continues operate independently, RXPOL REVPOL bits will reflect polarity state receiver.
Twisted Pair Interface Status
Three outputs (TXEN, RXCRS CLSN) indicate whether MACE device transmitting (MENDECto Twisted Pair), receiving (Twisted Pair MENDEC), collision state with both functions active simultaneously. MACE device will power Link Fail state. normal algorithm will apply allow enter Link Pass state. power TXEN, RXCRS CLSN) pins will high impedance state until they enabled setting Enable (ENPLSIO Configuration Control register) 10BASE-T port enters Link Pass state. Link Pass state, transmit receive activity which passes pulse width/amplitude requirements RXD± inputs, will indicated TXEN RXCRS respectively going active. TXEN, RXCRS CLSN asserted during collision. Link Fail state, TXEN, RXCRS CLSN inactive. jabber detect mode, MACE device will activate CLSN pin, disable TXEN (regardless Manchester data output from MENDEC), allow RXCRS indicate current state RXD± pair. there receive activity RXD±, only CLSN will active during jabber detect. there RXD± activity, both CLSN RXCRS will active. SLEEP asserted (regardless programming AWAKE RWAKE bits Configuration Control register), TXEN, RXCRS CLSN outputs will placed high impedance state.
Collision Detect Function
Simultaneous activity (presence valid data signals) from both internal MENDEC transmit function (indicated externally TXEN active) twisted pair RXD± pins constitutes collision, thereby causing external indication CLSN pin, internal indication which returned core. TXEN, RXCRS CLSN pins driven high during collision.
Signal Quality Error (SQE) Test (Heartbeat) Function
Test message burst normally returned pair every transmission) intended self-test indication that collision circuitry functional cable/connection intact. This minimal relevance when 10BASE-T embedded controller. Collision Error (CERR Interrupt Register) will reported only when 10BASE-T port link fail state, since collision circuit will disabled, causing absence Test message. GPSI mode
Am79C940
external encoder/decoder responsible asserting CLSN after each transmission. mode Test relevance.
Addressable Memor (CAM) other address detection device. allow simple serial parallel conversion, SF/BD provided strobe and/or marker indicate delineation bytes, subsequent SFD. This feature provides mechanism allow only capture and/or decoding physical logical (group) address, also facilitates capture header inter-networking information. EAM/R driven external address comparison logic, either reject accept packet. alternative modes permitted, allowing external logic either accept packet based address match, reject packet there match. alternate methods programmed using Match/Reject (M/R) Receive Frame Control register. set, configured (External Address Match). MACE device configured with Physical, Logical Broadcast Address comparison operational. internal address match detected, packet will accepted regardless condition EAM. Additional addresses located external address detection logic. match detected, must active within last destination address field (end byte being presented output, guarantee frame reception. addition, must inactive after match been detected previous packet, before next match take place subsequent packet. must asserted minimum pulse width clear (default state after either RESET SWRST have been activated), configured (External Address Reject). MACE device configured with Physical, Logical Broadcast Address comparison operational. internal address match detected, packet will accepted regardless condition EAR. Incoming packets which pass internal address comparison will continue received MACE device. must externally presented MACE chip prior first assertion RDTREQ, guarantee rejection unwanted packets. This allows approximately byte times after last destination address available generate signal, assuming MACE device configured accept runt packets. will ignored MACE device from byte times after SFD, packet will accepted been asserted before this time. MACE device configured accept runt packets, signal must generated prior receive message completion, which could short byte times (assuming bytes source address, bytes length, data, four bytes FCS) after last destination address
Jabber Function
Jabber function inhibits twisted pair transmit function MACE device TXD±/TXP± circuits active excessive period (20-150 ms). This prevents node from disrupting network stuck-on faulty transmitter. this maximum transmit time exceeded, data path through 10BASE-T transmitter circuitry disabled (although Link Test pulses will continue sent), CLSN asserted, Jabber (JAB Interrupt Register) INTR will asserted providing JABM (Interrupt Mask Register) eared. Once internal transmit data stream from MENDEC stops (TXEN deasserts), unjab time 250-750 will elapse before MACE device deasserts CLSN indication re-enables transmit circuitry. When jabber detected, MACE device will assert CLSN pin, de-assert TXEN (regardless internal MENDEC activity), allow RXCRS indicate current state RXD± pair. there receive activity RXD±, only CLSN will active during jabber detect. there RXD± activity, both CLSN RXCRS will active.
External Address Detection Interface (EADI)
This interface provided allow external perfect address filtering. This feature typically utilized terminal server, bridge and/or router type products. external logic required, capture serial stream from MACE device, compare this with table stored addresses identifiers. EADI port diagram Systems Applications section, Network Interfaces sub-section, details. EADI interface operates directly from decoded data clock recovered Manchester decoder. This allows external address detection performed parallel with frame reception address comparison Station Address Detection (SAD) block. SRDCLK provided allow clocking receive stream from MACE device, into external address detection logic. Once received packet commences data clock available from decoder, EADI interface logic will monitor alternating (1,0) preamble pattern until ones Start Frame Delimiter (1,0,1,0,1,0,1,1) detected, which point SF/BD output will driven high. After SF/BD asserted serial data from should de-serialized sent Content
Am79C940
available. must have pulse width least Note that setting PROM (MAC Configuration Control) will cause receive packets received,
regardless programming state EAM/R input. following table summarizes operation EADI features.
Internal/External Address Recognition Capabilities
PROM EAM/R Required Timing timing requirements timing requirements within 512-bits after timing requirements within 8-bits after field Received Messages Received Frames Received Frames Physical/Logical/Broadcast Matches Physical/Logical/Broadcast Matches Received Frames
General Purpose Serial Interface (GPSI)
GPSI port provides signals necessary present interface consistent with encoded data functions observed to/from controller such Am7990 Local Area Network Controller Ethernet (LANCE). actual GPSI pins functionally identical some pins from EADI ports, GPSI replicates this type interface. GPSI allows external Manchester encoder/decoder, such Am7992B Serial Interface Adapter (SIA). addition, allows MACE device used sublayer engine repeater based Am79C980 Integrated Multiport Repeater (IMR). Simple connection Expansion allows view packet data passing through number interconnected IMRs, allowing statistics network management information collected. GPSI functional pins duplicated follows: Configuration GPSI Function
Function Receive Data Receive Clock Receive Carrier Sense Collision Transmit Data Transmit Clock Transmit Enable Type LANCE RCLK RENA CLSN TENA MACE RXDAT SRDCLK RXCRS CLSN TXDAT+ STDCLK TXEN
DI±, CI±), crystal input (XTAL1/XTAL2) pins, tested. following brief summary IEEE 1149.1 compatible test functions implemented MACE device. additional details, consult IEEE Standard Test Access Port Boundary-Scan Architecture document (IEEE 1149.1-1990). boundary scan test circuit requires four pins (TCK, TMS, defined Test Access Port (TAP). includes finite state machine (FSM), instruction register, data register array power reset circuit. Internal pull-up resistors provided TCK, pins. engine state FSM, driven Test Clock (TCK) Test Mode Select (TMS) pins. independent power reset circuit provided ensure TEST_LOGIC_RESET state power addition minimum IEEE 1149.1 instruction requirements (EXTEST, SAMPLE BYPASS), three additional instructions (IDCODE, TRI_ST SET_I/ provided further ease board level testing. unused instruction codes reserved.
IEEE 1149.1 Supported Instruction Summary
Inst Description Selected Data Bypass Bypass Bypass Mode Test Inst Code 0000
EXTEST External Test IDCode Code Inspection Sample Boundary Force Tristate Control BoundaryTo Bypass Scan
Normal 0001 Normal 0010 Normal 0011 Test 0100
IEEE 1149.1 Test Access Port Interface
IEEE 1149.1 compatible boundary scan Test Access Port provided board level continuity test diagnostics. digital input, output input/output input/output pins tested. Analog pins, including differential driver (DO±) receivers
Sample TRI_ST SET_I/0 Bypass
Normal 1111
Am79C940
After hardware software reset, IDCODE instruction always invoked. decoding logic provides signals control data flow DATA registers according current instruction. Each Boundary Scan Register (BSR) cell also stages. flip-flop latch used SERIAL SHIFT STAGE PARALLEL OUTPUT STAGE respectively. There four possible operational modes cell: CAPTURE SHIFT UPDATE SYSTEM FUNCTION Other Data Registers BYPASS bit) Device Identification Register bits) Bits 31-28:Version bits) Bits 27-12:Part number bits) 9400H Bits 11-1:Manufacturer bits). manufacturer code 00000000001 accordance with JEDEC Publication 106-A. 0:Always logic
dynamically changed cycle cycle basis program slave cycle execution HIGH) three LOW) SCLK cycles. must stable falling edge SCLK (EDSEL High) start cycle, should only changed multiple cycle burst. read cycle initiated when either sampled falling edge SCLK must asserted exclusively. they active simultaneously when sampled, MACE device will execute read write cycle. low, Register Address read will take place. state ADD4-0 will used commence decoding appropriate internal register/FIFO. low, FIFO Direct read will take place from RCVFIFO. state ADD4-0 irrelevant FIFO Direct mode. With either input active, state ADD0-4 (for Register Address reads), (high indicate read cycle), will also latched falling (EDSEL HIGH) edge SCLK From falling edge SCLK (EDSEL HIGH), MACE device will drive data DBUS15-0 activate output (providing read cycle completed successfully). cycle read last byte/wor
Other recent searches
W9825G6EH - W9825G6EH W9825G6EH Datasheet
uPD481850 - uPD481850 uPD481850 Datasheet
SY100EL38 - SY100EL38 SY100EL38 Datasheet
LI3930-PF - LI3930-PF LI3930-PF Datasheet
ICX209AK - ICX209AK ICX209AK Datasheet
ICX069AK - ICX069AK ICX069AK Datasheet
CYW2332 - CYW2332 CYW2332 Datasheet
ADF4153 - ADF4153 ADF4153 Datasheet
ADF4110 - ADF4110 ADF4110 Datasheet
ADF4111 - ADF4111 ADF4111 Datasheet
ADF4112 - ADF4112 ADF4112 Datasheet
ADF4113 - ADF4113 ADF4113 Datasheet
ADF4106 - ADF4106 ADF4106 Datasheet
1851054 - 1851054 1851054 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
