This errata describes corrections updates MCF5407 ColdFire Integrated

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MCF5407UMAD/D Rev. 2/2003 Errata MCF5407 Integrated Microprocessor User's Manual,
This errata describes corrections updates MCF5407 ColdFire Integrated Microprocessor User's Manual, Motorola document order number MCF5407UM/D. General MCF5407 Changes section contains information that needs changed throughout book. Please check world wide latest updates.
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General MCF5407 Changes
MCF5407 offered with temperature frequency specifications shown Table
Table MCF5407 Temperature Frequency Specifications
Package plastic plastic Operating Temperature Frequency CLIN/ PCLK CLKIN/ PCLK MIPS Rating Dhrystone MIPS Dhrystone MIPS
NOTE These specifications further amend electrical characteristics described Section "General MCF5407 Changes." following section "Chapter Electrical Specifications" replaces Chapter MCF5407 ColdFire Integrated Microprocessor User's Manual.
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General Parameters
Chapter Electrical Specifications
This chapter describes electrical specifications thermal characteristics MCF5407. Note that this information correct time this book published. process technologies improve, there likelihood that this information change. confirm that this latest information, Motorola's ColdFire webpage,
20.1 General Parameters
Table 20-1 lists maximum minimum ratings supply operating voltages storage temperature. Operating outside these ranges cause erratic behavior damage processor.
Table 20-1. Absolute Maximum Ratings
Rating External (I/O pads) supply voltage (3.3-V power pins) Internal logic supply voltage supply voltage Internal logic supply voltage, input voltage level Storage temperature range IVcc must exceed EVcc IVcc PVcc must differ more than must exceed must exceed EVcc
Symbol EVcc IVcc PVcc Tstg
Value -0.3 +4.0 -0.5 +2.0
Units
-0.5 +2.0 -0.5 +3.6 +150
Table 20-2 lists junction ambient operating temperatures.
Table 20-2. Operating Temperatures
Characteristic Maximum operating junction temperature Maximum operating junction temperature (Extended Temperature Device) Maximum operating ambient temperature Maximum operating ambient temperature (Extended Temperature Device) Minimum operating ambient temperature Minimum operating ambient temperature (Extended Temperature Device)
Symbol TAmax TAmax TAmin TAmin
Value
Units
This published maximum operating ambient temperature should used only system design guideline. device operating parameters guaranteed only when junction temperature lies within specified range.
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General Parameters
Table 20-3 lists thermal resistances.
Table 20-3. Thermal Resistance
Characteristic Junction ambient Junction reference Symbol Value 26.1 Units
oC/W
Table 20-4 lists electrical specifications. This table based operating voltage EVcc IVcc 0.10 Vdc.
Table 20-4. Electrical Specifications
Characteristic External (I/O pads) operation voltage range Internal logic operation voltage range operation voltage range Input high voltage
Symbol EVcc IVcc PVcc ITSI
1.65 -0.5
1.95
Units
Input voltage2 Input signal undershoot Input signal overshoot Input leakage current 0.5/2.4 during normal operation High impedance (three-state) leakage current 0.5/2.4 during normal operation Signal input current, Signal high input current, Output high voltage Output voltage
Load capacitance (all outputs) Capacitance
IVcc PVcc should same voltage. pins except MTMOD. MTMOD 2.6V, 0.4V. BKPT/TMS, DSI/TDI, DSCLK/TRST D[31:0], A[23:0], PP[15:0],TS, SIZ[1:0], R/W, RSTO, CS[7:0], BE[3:0], PSTCLK, PSTDDATA[7:0], DSO, TOUT[1:0], SCL, SDA, RTS[1:0], TXD[1:0] BCLKO, RAS[1:0], CAS[3:0], DRAMW, SCKE, SRAS, SCAS Capacitance periodically sampled rather than 100% tested.
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General Parameters
20.1.1 Supply Voltage Sequencing Separation Cautions
Figure 20-1 shows situations avoid sequencing IVcc EVcc supplies.
Power Supply Voltage
3.3V
EVcc
Supplies Stable
1.8V
IVcc, PVcc
Time Notes: IVcc, PVcc rising before EVcc EVcc rising much faster than IVcc, PVcc
Figure 20-1. Supply Voltage Sequencing Separation Cautions
IVcc should allowed rise early (1). This usually avoided running regulator IVcc supply (1.8 from voltage generated 3.3-V EVcc supply (Figure 20-2). This keeps IVcc from rising faster than EVcc. IVcc should rise late that large voltage difference allowed between supplies (2). Typically this situation avoided using external discrete diodes series between supplies shown Figure 20-2. series diodes forward bias when difference between EVcc IVcc reaches approximately 2.1V, causing IVcc rise EVcc ramps When IVcc regulator begins proper operation, difference between supplies should exceed conduction through diode chain reduces essentially leakage current. During supply sequencing, following general relationship should adhered EVcc IVcc (EVcc (PVcc) supply should comply with these constraints just IVcc does. practice, PVcc typically connected directly IVcc with some filtering.
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Clock Timing Specifications
Supply
Regulator
EVcc
Regulator
IVcc, PVcc
Figure 20-2. Example Circuit Control Supply Sequencing
20.2 Clock Timing Specifications
Table 20-5 shows MCF5407 encodings. Note that they differ from MCF5307 DIVIDE[1:0] encodings.
Table 20-5. Divide Ratio Encodings
Input Clock (MHz) D[2:0]/DIVIDE[2:0] 00x-010 40.0-54.0 25.0-40.5 25.0-32.4 25.0-27.0 40.0-55.0 25.0-55.0 25.0-44.0 25.0-36.6 Multiplier Reserved 120.0-162 100.0-162 125.0-162 150.0-162 Reserved 120.0-165 100.0-220 125.0-220 150.0-220 60.0-81.0 50.0-81.0 67.5-81.0 75.0-81.0 60.0-82.5 50.0-110 67.5-110 75.0-110 Core Clock (MHz) PSTCLK (MHz)
Figure 20-3 correlates CLKIN core clock frequencies 3x-6x multipliers.
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Clock Timing Specifications
CLKIN
Core Clock
40.5
32.4
36.6
CLKIN (MHz) Device Device
Core Clock (MHz)
Figure 20-3. CLKIN-to-Core Clock Frequency Ranges
Table 20-6 lists specifications clock timing parameters shown Figure 20-4 Figure 20-5. Motorola recommends that CLKIN used system clock. BCLKO provided only compatibility with slower MCF5307 designs. Regardless CLKIN frequency driven power-up, CLKIN (and BCLKO) have same ratio value PCLK. Although either signal used clock reference, CLKIN leaves more room meet specifications than BCLKO, which generated phase-aligned signal CLKIN.
Table 20-6. Clock Timing Specification
Characteristic CLKIN cycle time CLKIN rise time (0.5V CLKIN fall time (2.4V CLKIN duty cycle PSTCLK cycle time 18.5 12.3 Note Note
Units 18.18 Note Note
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Input/Output Timing Specifications
Table 20-6. Clock Timing Specification
Units Note 18.18 -1.5 Note 18.5 -1.5
Characteristic PSTCLK duty cycle BCLKO cycle time BCLKO duty cycle CLKIN BCLKO
low-frequency limit depends clock divide ratio chosen. Table 20-5.
Figure 20-4 shows timings parameters listed Table 20-6.
CLKIN
BCLKO
Note: Input output timing specifications measured CLKIN with 50-pF load capacitance (not including capacitance).
Figure 20-4. Clock Timing
Figure 20-5 shows PSTCLK timings parameters listed Table 20-6.
PSTCLK
Figure 20-5. PSTCLK Timing
20.3 Input/Output Timing Specifications
Table 20-7 lists specifications parameters shown Figure 20-6 Figure 20-7. Note that inputs IRQ[7,5,3,1], BKPT, synchronized internally; that logic level
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Input/Output Timing Specifications
validated value does change consecutive rising CLKIN edges. Setup hold times must only recognition particular clock edge required.
Table 20-7. Input Timing Specification
Units 7.51, 8.52 0.5(C1) clock
Characteristic Valid CLKIN rising (setup) CLKIN rising invalid (hold) Valid CLKIN rising (setup) CLKIN rising invalid (hold) CLKIN input high impedance CLKIN EDGESEL delay 0.5(C1)
Inputs: A[23:0], PP[15:0], SIZ[1:0], R/W, EDGESEL, D[31:0], BKPT Inputs IRQ[7,5,3,1] Inputs: Inputs: D[31:0]
Table 20-8 lists specifications timings Figure 20-6, Figure 20-7, Figure 20-13. Although output signals that share specification number have approximately same timing, loading differences, they necessarily change same time. However, they have similar timings; that minimum maximum times mixed.
Table 20-8. Output Timing Specification
Characteristic CLKIN rising valid
3,4,5
Units 10.5
0.5(C1)
10.54 12.5 0.5(C1) +10.59 0.5(C1) +12.510
0.5(C1)
12.5
CLKIN rising invalid (hold) CLKIN high impedance (three-state) CLKIN rising valid CLKIN rising invalid (hold) EDGESEL valid EDGESEL invalid (hold) high impedance Impedance
8,2,3 8,2,3
0.5(C1) +10.5 0.5(C1) +12.5
Outputs that change only rising edge CLKIN: RSTO, R/W, SIZ[1:0], PP[7:0] (and PP[15:8] when configured parallel port outputs). Outputs that change either CLKIN edge depending only EDGESEL: D[31:0], A[23:0], SCKE, SRAS, SCAS, DRAMW PP[15:8] when individually configured A[31:24] outputs.
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Input/Output Timing Specifications
Outputs that change either CLKIN edge depending upon EDGESEL interface operating mode (DRAM/SDRAM): RAS[1:0], CAS[3:0] SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0] D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, PP[15:8] when individually configured A[31:24] outputs. High impedance (three-state): D[31:0] Outputs that transition high impedance arbitration: A[23:0], R/W, SIZ[1:0], PP[15:8] when individually configured A[31:24] outputs. Outputs that change only falling edge CLKIN: CS[7:0], BE[3:0], SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0], CS[7:0], BE[3:0], D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, PP[15:8] when individually configured A[31:24] outputs.
Note that these figures show representative operations attempt show cases. explanations states, S0-S5, Section 18.4, "Data Transfer Operation." Note that Figure 20-7 does show signals that apply each timing specification. previous tables complete listing. Figure 20-6 shows timings normal read write cycles.
CLKIN A[31:0] TM[2:0] TT[1:0] SIZ[1:0]
BE/BWE[3:0]
D[31:0]
Figure 20-6. Timings-Normal Read Write Cycles
Figure 20-7 shows timings read cycle with EDGESEL tied buffered CLKIN.
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Input/Output Timing Specifications
CLKIN
EDGESEL
A[31:0]
Column
SRAS
SCAS
DRAMW
D[31:0]
ACTV DACR[CASL] READ PALL
Figure 20-7. SDRAM Read Cycle with EDGESEL Tied Buffered CLKIN
Figure 20-8 shows SDRAM write cycle with EDGESEL tied buffered CLKIN.
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Input/Output Timing Specifications
CLKIN
EDGESEL
A[31:0]
Column
SRAS
SCAS
DRAMW
D[31:0]
ACTV DACR[CASL] WRITE PALL
Figure 20-8. SDRAM Write Cycle with EDGESEL Tied Buffered CLKIN
Figure 20-9 shows SDRAM read cycle with EDGESEL tied high.
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Input/Output Timing Specifications
CLKIN
A[31:0]
Column
SRAS
SCAS
DRAMW
D[31:0]
ACTV DACR[CASL] READ PALL
Figure 20-9. SDRAM Read Cycle with EDGESEL Tied High
Figure 20-10 shows SDRAM write cycle with EDGESEL tied high.
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Input/Output Timing Specifications
CLKIN
A[31:0]
Column
SRAS
SCAS1
DRAMW
D[31:0]
ACTV WRITE PALL
DACR[CASL]
Figure 20-10. SDRAM Write Cycle with EDGESEL Tied High
Figure 20-11 shows SDRAM read cycle with EDGESEL tied low.
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Input/Output Timing Specifications
CLKIN
A[31:0]
Column
SRAS
SCAS1
DRAMW
D[31:0]
ACTV DACR[CASL] READ PALL
Figure 20-11. SDRAM Read Cycle with EDGESEL Tied
Figure 20-12 shows SDRAM write cycle with EDGESEL tied low.
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Input/Output Timing Specifications
CLKIN
A[31:0]
Column
SRAS
SCAS1
DRAMW
D[31:0]
ACTV DACR[CASL] WRITE PALL
Figure 20-12. SDRAM Write Cycle with EDGESEL Tied
Figure 20-13 shows timing showing high impedance.
OUTPUTS
Figure 20-13. Output Timing-High Impedance
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Reset Timing Specifications
20.4 Reset Timing Specifications
Table 20-9 lists specifications reset timing parameters shown Figure 20-14.
Table 20-9. Reset Timing Specification
Units
Characteristic Valid CLKIN (setup) CLKIN invalid (hold) RSTI invalid (hold)
RSTI D[7:0] synchronized internally. Setup hold times must only recognition particular clock required.
Figure 20-14 shows reset timing values Table 20-9.
CLKIN
RSTI
D[7:0]
Note: Mode selects registered rising CLKIN edge before cycle which RSTI recognized being negated.
Figure 20-14. Reset Timing
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Debug Timing Specifications
20.5 Debug Timing Specifications
Table 20-10 lists specifications debug timing parameters shown Figure 20-16.
Table 20-10. Debug Timing Specification
Characteristic PSTDDATA PSTCLK setup PSTCLK PSTDDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time PSTCLKs PSTCLKs PSTCLKs Units
DSCLK synchronized internally. measured from synchronized DSCLK input relative rising edge PSTCLK.
Figure 20-15 shows real-time trace timing values Table 20-10.
PSTCLK
PSTDDATA[7:0]
Figure 20-15. Real-Time Trace Timing
Figure 20-16 shows serial port timing values Table 20-10.
PSTCLK
DSCLK
Current
Next
Past
Current
Figure 20-16. Serial Port Timing
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Timer Module Timing Specifications
20.6 Timer Module Timing Specifications
Table 20-11 lists specifications timer module timing parameters shown Figure 20-17.
Table 20-11. Timer Module Timing Specification
Characteristic cycle time valid CLKIN (input setup) CLKIN invalid (input hold) CLKIN TOUT valid (output valid) CLKIN TOUT invalid (output hold) pulse width TOUT pulse width clocks clocks clocks Units
Figure 20-17 shows timings Table 20-11.
CLKIN
TOUT
Figure 20-17. Timer Module Timing
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Input/Output Timing Specifications
20.7 Input/Output Timing Specifications
Table 20-12 lists specifications input timing parameters shown Figure 20-18.
Table 20-12. Input Timing Specifications between
Characteristic Start condition hold time Clock period SCL/SDA rise time (VIL Data hold time SCL/SDA fall time (VIH Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time clocks clocks clocks clocks clocks Units
Table 20-13 lists specifications output timing parameters shown Figure 20-18.
Table 20-13. Output Timing Specifications between
Units Note Note clocks clocks clocks clocks clocks clocks clocks
Characteristic Start condition hold time Clock period SCL/SDA rise time (VIL Data hold time SCL/SDA fall time (VIH Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Note Note
Programming IFDR with maximum frequency (IFDR 0x20) results minimum output timings listed here. interface designed scale data transition time, moving middle period. actual position affected prescale division values programmed IFDR. Because open-collector-type outputs, which processor only actively drive low, time takes reach high level depends external signal capacitance pull-up resistor values. Specified nominal 50-pF load.
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UART Module Timing Specifications
Figure 20-18 shows timing values Table 20-12 Table 20-13.
Figure 20-18. Input/Output Timings
20.8 UART Module Timing Specifications
Table 20-14 lists specifications UART module timing parameters Figure 20-19.
Table 20-14. UART Module Timing Specifications
Characteristic valid CLKIN (input setup) CLKIN invalid (input hold) valid CLKIN (input setup) CLKIN invalid (input hold) CLKIN valid (output valid) CLKIN invalid (output hold) CLKIN valid (output valid) CLKIN invalid (output hold) high time time rising valid setup falling hold from falling (remote loop back) TIN1 setup falling TIN1 hold from falling rising asserted Units
Figure 20-19 shows UART0 UART1 timing values Table 20-14.
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UART Module Timing Specifications
CLKIN
Figure 20-19. UART0 UART1 Module Timing-UART Mode
Figure 20-19 shows timing UART1 16-bit CODEC mode.
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UART Module Timing Specifications
CTS/ Serial clock
TIN1/ Frame sync
Figure 20-20. UART1 16-bit CODEC Mode
Figure 20-21 shows timing UART1 mode.
CTS/ clock RTS/ Frame sync
Figure 20-21. UART1 Mode
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Parallel Port (General-Purpose I/O) Timing Specifications
20.9 Parallel Port (General-Purpose I/O) Timing Specifications
Table 20-15 lists specifications general-purpose timing parameters Figure 20-22.
Table 20-15. General-Purpose Port Timing Specifications
Characteristic valid CLKIN (input setup) CLKIN invalid (input hold) CLKIN valid (output valid) CLKIN invalid (output hold) 12.5 12.5 Units
Figure 20-22 shows general-purpose timing.
CLKIN
Figure 20-22. General-Purpose Timing
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Timing Specifications
20.10 Timing Specifications
Table 20-15 lists specifications timing parameters shown Figure 20-22.
Table 20-16. Timing Specifications
Characteristic DREQ valid CLKIN (input setup) CLKIN DREQ invalid (input hold) CLKIN DACK valid (output valid) CLKIN DACK invalid (output hold) Units
Figure 20-23 shows timing.
CLKIN
DREQ DACK
Figure 20-23. Timing
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IEEE 1149.1 (JTAG) Timing Specifications
20.11 IEEE 1149.1 (JTAG) Timing Specifications
Table 20-17 lists specifications JTAG timing parameters shown Figure 20-24.
Table 20-17. IEEE 1149.1 (JTAG) Timing Specifications
Characteristic Frequencies frequency operation cycle time clock pulse high width (measured clock pulse width (measured fall time (VIH 0.5V) rise time (VIL 0.5v 2.4V) TDI, rising (input setup) rising TDI, invalid (hold) Boundary scan data valid (setup) boundary-scan data invalid (hold) TRST pulse width (asynchronous clock edges) falling valid (signal from driven three-state) falling high impedance falling boundary scan data valid (signal from driven three-state) falling boundary scan data high impedance Units
Figure 20-24 shows JTAG timing.
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IEEE 1149.1 (JTAG) Timing Specifications
TDI, BOUNDARY SCAN DATA INPUT
TRST BOUNDARY SCAN DATA OUTPUT
Figure 20-24. IEEE 1149.1 (JTAG) Timing
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MCF5407UMAD/D
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This errata describes corrections updates MCF5407 ColdFire Integrated

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