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8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA VFBGA Packages

MicroStar Jr. is a trademark of Texas Instruments.

Application Report
SZZA028A - November 2001
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
Frank Mortan and Mark Frimann ABSTRACT Texas Instruments 20-ball MicroStar Jr. package is a standardized JEDEC VFBGA package designed to satisfy requirements for minimizing board area. This ball grid array package provides improved thermal performance, reduced inductance and capacitance, cost savings for OEMs in the system manufacturing process, and greater package reliability. Advantages of the MicroStar Jr. package over SSOP, TSSOP, and TVSOP packages are quantified. Package marking and packing specifications are provided. Standard Linear & Logic
MicroStar Jr. is a trademark of Texas Instruments.
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8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Introduction
FAMILY ABT CBT LVC LVT LV DESCRIPTION Advanced BiCMOS technology Crossbar technology Low-voltage CMOS technology Low-voltage BiCMOS technology RELEASED FUNCTION 245B, 573A, 574A 3244, 3245A 138A, 244A, 245A, 373A, 573A, 574A, 2245A 240, 244A, 244B, 245A, 245B, 573, 574 245A, 373A, 374A, 573A, 574A
Low-voltage CMOS With bus-hold option
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Application Examples
Industry Requirements
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Customer Requirements
Each customer has unique requirements. However, there are common issues across the industry to be addressed, and our goal is to provide a targeted solution to these needs. Within the personal computer (PC) industry, the trend is to integrate as much logic as possible into smaller packages to save space on motherboards and peripheral cards. Due to space constraints, PC cards require dense integration and small footprints with improved electrical and thermal performance. Commonality of package types for clocks, registers, and memory chips on dual-inline memory modules (DIMMs) can be achieved by the use of the MicroStar Jr. package, thus creating cost-effective and common manufacturing processes for OEMs. In the telecommunications industry, base stations are becoming small and ubiquitous, requiring the repackaging of many circuits into denser boards. Also, within the telecommunications industry, new, complex, and smaller equipment must interface with legacy systems to provide cost-effective upgrade solutions to existing capabilities. The reduced footprint of a MicroStar Jr. package will enable these requirements to be met without sacrificing performance.
Comparison of Alternative Solutions
Table 3. Area / Bit Ratio Comparison
PIN COUNT 20 20 20 20 20 PACKAGE TYPE MicroStar Jr. TVSOP TSSOP PLCC SSOP FOOTPRINT (mm2) 12.0 32.0 41.6 98.11 56.16 AREA / BIT (mm2) 1.5 4.0 5.2 12.26 7.02 WEIGHT (g) 0.022 0.055 0.075 0.62 0.151
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Physical Description
Package Characteristics
Figure 1 shows a cross-section view of the MicroStar Jr. package.
Epoxy Molding
Silicon Die
Gold Bond Wire
Tape Substrate
Copper Trace
Figure 1. MicroStar Jr. Package Cross Section Table 4 summarizes the package attributes for the 20-ball MicroStar Jr. package. Table 4. 20-Ball MicroStar Jr. Package Attributes
Package qualified at JEDEC level 2 moisture condition, 220°C reflow
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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MicroStar Jr. Package Dimensions
Figures 2 and 3 show the physical dimensions of the 20-ball MicroStar Jr. package. Pin A1 quadrant is identified by the via.
All dimensions are in millimeters.
Figure 2. 20-Ball MicroStar Jr. Package, Profile and Bottom Views
All dimensions are in millimeters.
Figure 3. 20-Ball MicroStar Jr. Package, Top View
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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MicroStar Jr. Package Pinout Configurations
The pinout configuration in Figure 4 has the same naming convention that is applied in the industry to logic devices in 20-pin packages (i.e., TSSOP, TVSOP, SSOP).
Figure 4. 20-Pin Function Pin Assignment, Top View
Package Reliability
Thermal shock (-85°C to 150°C, 1000 cycles) Salt atmosphere Moisture-sensitivity Level 2 High-temperature storage (150°C for 1000 hours) X-ray Physical dimensions Manufacturability
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Power Dissipation
2 1.8 1.6 Power Dissipation - W 1.4 1.2 1 0.8 0.6 0.4 0.2 0 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 TA - Ambient Temperature - °C
20-ball MicroStar Jr. package
20-pin SSOP 20-pin TSSOP 20-pin TVSOP 20-pin PLCC
Figure 5. MicroStar Jr. Package Thermal Comparison on Multilayer JEDEC 1S2P Test Board, Zero Airflow, No Thermal Vias
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Table 6. Thermal-Impedance Guidelines
AIR VELOCITY (LFM) 0 ja (°C / W) jc (°C / W) jb (°C / W) 76.9 53.5 36.3 150 74.9 250 73.9 500 72.5
Figure 6. MicroStar Jr. Package Thermal Performance on Multilayer JEDEC 1S2P Test Board, at Various Airflow Velocities, No Thermal Vias
Figure 7. Effect of Thermal Vias on MicroStar Jr. Package Thermal Performance on JEDEC 1S2P Test Board at Various Airflow Velocities
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Table 7. Effect of Vias on Thermal Impedance
MicroStar Jr. Package
Electrical Characteristics Package Parasitics
Inductance is directly related to the length of a wire and its proximity to the ground plane. Any wire naturally creates an inductor. The longer the wire, the greater is its inductance. Inductance occurs when current is induced into a wire, creating an electromagnetic field. The closer this induced electromagnetic field is to ground, the less effective it becomes. As the wire gets shorter and / or closer to the ground plane, its inductance decreases.
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Capacitance is created when two plates (wires, lines, or layers) overlap and are separated by a given distance. This distance can be insulated by air, plastic, glass, or other material. Capacitance can be calculated by the following formula: C
L (nH) Minimum Mean Maximum 0.896 1.317 2.088 C (pF) 0.064 0.113 0.190
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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JEDEC Definition
The 20-ball VFBGA received final registration from JEDEC JC-11 under semiconductor package standard MO-225. The device pinout was submitted to the JC-40 Council, and passed a final council vote in March 2001.
VFBGA Benefits
In summary, key features and corresponding advantages for logic products assembled in the MicroStar Jr. VFBGA package are:
Minimum footprint available in the industry allows use of the smallest board area among all industry-standard packages. Required trace width and spacing is well defined for major PCB manufacturers. Vastly improved parasitic capacitance and inductance provides better high-speed performance. JEDEC standard package under MO-225 meets worldwide mechanical and pinout specifications. No external components required, other than decoupling capacitors, which translates to lower cost, lower maintenance, and higher reliability Improved thermal performance over TSSOP and TVSOP packages. Improved device reliability over alternative packages. Lower ground bounce provides more noise margin. Minimized skew pattern provides additional design margin for high-speed buses. High assembly yields, with documented defect levels of 4 ppm and less
Evaluation Units
For evaluation units, contact authorized distributors or, for more information, refer to: http://www.ti.com / sc / msjunior
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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MicroStar Jr. Package Marking and Packing
Marking
TI uses a laser to mark the product number, year and month manufactured, lot trace code, manufacturing site, and pin 1 location. A device marking example for the LVTH2245 is shown in Figure 9.
LK245 TI YMS O Part Number: LVTH2245 Year, Month, Site o: Pin 1 Location
Figure 9. Device Marking Example The namerule for the MicroStar Jr. VFGBA package is rule C1, with seven characters maximum. Table 10 shows the namerule logic and how each marking is derived. The key to the naming convention is to first note the alphanumeric code under namerule A. This code under namerule A is condensed into the codes under namerules B and C, and the remaining function numbers are added on in place of the asterisks. For example, to mark an SN74ALVCH374 VFBGA device, note that the code under namerule A is SN74ALVCH. Namerule C applies to VFBGA, therefore, SN74ALVCH is replaced by the code VB found under namerule C. The remaining function numbers (374) are added onto VB to get VB374. Table 10. Samples of Name Markings for Various 20-Ball MicroStar Jr. Package Offerings
DEVICE NAME SN74ALVCH374 SN74ABT245B SN74ALVC244 SN74CBT3245A SN74LV573A NAMERULE A SN74ALVCH SN74ABT2 SN74ALVC SN74CBT32 SN74LV NAMERULE B ALVCH ABT2 ALVC CBT32 LV NAMERULE C VB AA VA BV LV TOP-SIDE MARKING VB374 AA245B VA244 BV3245A LV573A
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Tape and Reel
Embossed tape and reel feed is the preferred method for automatic pick and place machines. TI offers tape and reel packaging for the 20-ball MicroStar Jr. package. The standard quantity is 1000 units per reel. Packaging materials include the carrier tape, cover tape, and reel. All materials used meet industry guidelines for ESD protection and comply fully with EIA Standard 481-A, Taping of Surface Mount Components for Automatic Placement. The dimensions of interest to the end user are tape width (W), pocket pitch (P), and quantity per reel. Figure 10 and Table 11 show the carrier tape dimensions. Figure 11 gives dimensions of the reel assembly.
NOTE A: All dimensions are in millimeters.
Figure 10. Tape Dimensions Table 11. Carrier Tape Dimensions
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Reel Diameter
Reel Width Cover Tape Width
REEL WIDTH (mm) 12.00 +2.0 / -0
REEL DIAMETER (mm) 330 maximum
NOTE A: Standard quantity is 1000 devices per reel, however, this is subject to change per market demand.
Figure 11. Reel Assembly Dimensions
Sockets and Socket Ordering Information
Loranger part number: 040030020U6617 Loranger International Corporation 817 Fourth Avenue Warren, PA 16365 Telephone: (814) 723-2250
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
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Conclusion
This application report shows that the 20-ball MicroStar Jr. package is the optimal solution for addressing performance and economic issues such as:
The spacing between balls for this 0.65-mm VFBGA package is equal to that of other 0.8-mm-pitch BGA packages, therefore, defect rates due to solder bridging are similar to those of larger BGA packages. AC performance of the MicroStar Jr. package has a definite advantage over other standard packages. The simultaneous-switching data and graphs see 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch BGA (VFBGA) Packages application report (SZZA029) clearly show this smaller package, with its lower capacitance and inductance, has speed and noise advantages over the SSOP, TSSOP, and TVSOP packages. Designers using the MicroStar Jr. package can take advantage of the win-win combination of electrical and physical properties offered. With the introduction of the MicroStar Jr. VFBGA packages by TI, OEMs are assured of a standardized JEDEC package, pinout, and availability of the previously stated product families and functions. More device families and functions will be included in the MicroStar Jr. package as market interest dictates.
8-Bit Linear and Logic Families in 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch BGA (VFBGA) Packages
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated