Frank Mortan Mark Frimann ABSTRACT Texas Instruments 20-ball MicroStar
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8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
Frank Mortan Mark Frimann ABSTRACT Texas Instruments 20-ball MicroStar package standardized JEDEC VFBGA package designed satisfy requirements minimizing board area. This ball grid array package provides improved thermal performance, reduced inductance capacitance, cost savings OEMs system manufacturing process, greater package reliability. Advantages MicroStar package over SSOP, TSSOP, TVSOP packages quantified. Package marking packing specifications provided. Standard Linear Logic
Contents Introduction Application Examples Industry Requirements Customer Requirements Comparison Alternative Solutions
Physical Description Package Characteristics 3.1.1 MicroStar Package Dimensions 3.1.2 MicroStar Package Pinout Configurations 3.1.3 Package Reliability 3.1.4 Power Dissipation Electrical Characteristics 3.2.1 Package Parasitics JEDEC Definition VFBGA Benefits Evaluation Units MicroStar Package Marking Packing Marking Tape Reel Sockets Socket Ordering Information Conclusion
MicroStar trademark Texas Instruments.
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List Figures MicroStar Package Cross Section 20-Ball MicroStar Package, Profile Bottom Views 20-Ball MicroStar Package, View 20-Pin Function Assignment, View MicroStar Package Thermal Comparison Multilayer JEDEC 1S2P Test Board, Zero Airflow, Thermal Vias MicroStar Package Thermal Performance Multilayer JEDEC 1S2P Test Board, Various Airflow Velocities, Thermal Vias Effect Thermal Vias MicroStar Package Thermal Performance JEDEC 1S2P Test Board Various Airflow Velocities Area Normalized Power Dissipation 25°C Using JEDEC 1S2P Test Board Device Marking Example Tape Dimensions Reel Assembly Dimensions List Tables 20-Ball MicroStar Package Releases Date 20-Ball MicroStar Package Area Savings Area/Bit Ratio Comparison 20-Ball MicroStar Package Attributes Package Reliability Qualification Results Thermal-Impedance Guidelines Effect Vias Thermal Impedance Electrical Characteristics 20-Ball MicroStar Package Comparison 20-Ball MicroStar Package Parasitics Alternative Packages Samples Name Markings Various 20-Ball MicroStar Package Offerings Carrier Tape Dimensions
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Introduction
system circuit complexity increases, competitive pressures force reduction system prices, requirement cost-effective bus-interface technology creates necessity solutions system needs. major challenge today's digital processing industry reduction overall system costs complexity increases. These marketplace forces have resulted circuit integration board miniaturization becoming necessary trend. address these rapidly evolving customer requirements, Texas Instruments defined very-thin-profile fine-pitch ball grid array (VFBGA) package solution, known MicroStar package, best serve customer needs. Modeling experimentation have shown that MicroStar package optimal solution reducing inductance capacitance improving thermal performance, while minimizing board area support integrated functions. objective provide significant improvements over existing packages, well cost savings manufacturing process. purpose this application report introduce newest VFBGA solution, 20-ball MicroStar package. definition this package terms standardization, both physical mechanical, developed provide customers with industry-compatible solutions. Additional products released based market interest customer demand. Current products listed Table include bus-hold options. Table 20-Ball MicroStar Package Releases Date
FAMILY DESCRIPTION Advanced BiCMOS technology Crossbar technology Low-voltage CMOS technology Low-voltage BiCMOS technology RELEASED FUNCTION 245B, 573A, 574A 3244, 3245A 138A, 244A, 245A, 373A, 573A, 574A, 2245A 240, 244A, 244B, 245A, 245B, 573, 245A, 373A, 374A, 573A, 574A
Low-voltage CMOS With bus-hold option
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Application Examples
Industry Requirements
requirement reduce board area necessitates packaging solution that integrates logic, addresses improved electrical thermal packaging characteristics. selection 20-ball MicroStar package addresses these issues with improved performance standardized pinouts. 1999, initial study OEMs worldwide subcontractors revealed that customers desired solutions with identification bottom sides, pinout that allows routing traces minimal board space. MicroStar package provides this capability with single-layer routing pins. found that 0.65-mm pitch 0.117-mm (4.6 mil) trace width/spacing both desired OEMs feasible manufacture. technology progressed point that 10-mil drill economical technology 1.5748-mm mil) boards, micro-via technology that employs lasers reduced costs vias with 0.2032-mm mil) diameter less. More recently, technology progressed even further, with respect trace width spacing. Many offshore printed circuit board (PCB) manufacturers currently produce 0.0508-mm (2.2 mil) boards with via-in-pad interconnects. This capability however, more expensive must balanced with production volumes pay-back considerations. Because these reduced-pitch efforts, 0.117-mm (4.6 mil) capabilities have experienced increased yields through similar process material innovations, becoming common technology. Informal discussions with United States manufacturers reveal that majority domestic industry process capabilities down 0.107-mm (4.4 mil) level. This percentage manufacturers even higher Asian market. pushing envelope vendors, determined that 0.65-mm pitch optimal choice this time, given current technology raw-board yields. MicroStar package offered supports customer requirements enables easier, economical, design/layout, along with improved solder-joint reliability based life-cycle studies, while reducing consumption valuable board space. Experiments modeling also have shown improvement board-level reliability over land grid array (LGA) packages increased seating height. VFBGA package also provides significant improvements parasitic capacitance inductance over 20-pin thin shrink small-outline package (TSSOP) thin very small-outline package (TVSOP). Improved thermal performance overall height less than makes MicroStar package ideal height-constrained applications, such PCMCIA. more detailed package comparison provided other subsections this application report.
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Customer Requirements
Each customer unique requirements. However, there common issues across industry addressed, goal provide targeted solution these needs. Within personal computer (PC) industry, trend integrate much logic possible into smaller packages save space motherboards peripheral cards. space constraints, cards require dense integration small footprints with improved electrical thermal performance. Commonality package types clocks, registers, memory chips dual-inline memory modules (DIMMs) achieved MicroStar package, thus creating cost-effective common manufacturing processes OEMs. telecommunications industry, base stations becoming small ubiquitous, requiring repackaging many circuits into denser boards. Also, within telecommunications industry, new, complex, smaller equipment must interface with legacy systems provide cost-effective upgrade solutions existing capabilities. reduced footprint MicroStar package will enable these requirements without sacrificing performance.
Comparison Alternative Solutions
Comparisons footprint areas 20-Ball MicroStar package shows space savings 62.5% when compared 20-pin TVSOP, space savings compared 20-pin TSSOP. Table compares physical dimensions area savings 20-ball MicroStar package alternative packages. Table compares area-to-bit ratios weight savings. Table 20-Ball MicroStar Package Area Savings
COUNT PACKAGE TYPE MicroStar TVSOP TSSOP PLCC SSOP PITCH (mm) 0.65 0.65 0.65 PACKAGE DIMENSION (mm) 9.905 9.905 FOOTPRINT (mm2) 12.0 32.0 41.6 98.11 56.16 MAXIMUM HEIGHT (mm) 4.57 62.5 71.15 87.77 78.63 AREA SAVINGS
Table Area/Bit Ratio Comparison
COUNT PACKAGE TYPE MicroStar TVSOP TSSOP PLCC SSOP FOOTPRINT (mm2) 12.0 32.0 41.6 98.11 56.16 AREA/BIT (mm2) 12.26 7.02 WEIGHT 0.022 0.055 0.075 0.62 0.151
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Physical Description
Package Characteristics
Figure shows cross-section view MicroStar package.
Epoxy Molding
Silicon
Gold Bond Wire
Tape Substrate
Copper Trace
Figure MicroStar Package Cross Section Table summarizes package attributes 20-ball MicroStar package. Table 20-Ball MicroStar Package Attributes
ATTRIBUTE Ball count Ball configuration (rows, columns) Ball-to-ball pitch (mm) Square/rectangular Ball diameter (mm) Package body width (mm) Package body length (mm) Package thickness (total height, Package weight Shipping media, tape reel (units) Desiccant pack MicroStar PACKAGE 0.65 Rectangular 0.35 minimum maximum 0.022 1000 Level
Package qualified JEDEC level moisture condition, 220°C reflow
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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3.1.1
MicroStar Package Dimensions
Figures show physical dimensions 20-ball MicroStar package. quadrant identified via.
0.65 0.65 ±0.03 0.65 Indicates Quadrant 0.08 -f0.40 ±0.05
0.05
0.20 ±0.05 1.00
dimensions millimeters.
Figure 20-Ball MicroStar Package, Profile Bottom Views
3.00 ±0.20
dimensions millimeters.
Figure 20-Ball MicroStar Package, View
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
4.00 ±0.20
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3.1.2
MicroStar Package Pinout Configurations
pinout configuration Figure same naming convention that applied industry logic devices 20-pin packages (i.e., TSSOP, TVSOP, SSOP).
=VCC signal Control Ground
Figure 20-Pin Function Assignment, View
3.1.3
Package Reliability
20-ball MicroStar package qualified Joint Electronics Device Engineering Council (JEDEC) Moisture Level released Level optimum reliability, reflow(s) should completed soon practical after removing components from pack, however, JEDEC Level allows four weeks before baking required (assuming ambient conditions 30°C relative humidity). Table summarizes package reliability data obtained during qualification testing. test chip LVTH2245, size 1.22 2.28 mil), with preconditioning JEDEC Level (85°C relative humidity with three infrared (IR) reflows 220°C). Table Package Reliability Qualification Results
RELIABILITY QUALIFICATION TEST SAMPLE SIZE/FAILS QUALIFICATION 39/0 26/0 77/0 77/0 22/0 12/0 45/0 15/0 Pass QUALIFICATION 39/0 26/0 77/0 77/0 22/0 12/0 45/0 15/0 Pass QUALIFICATION 39/0 26/0 77/0 77/0 22/0 12/0 45/0 15/0 Pass
Steady-state life test (150°C, hours) Highly Accelerated Stress Test (HAST) (130°C relative humidity) Autoclave (121°C hours) Solderability hours steam age) Flammability
Thermal shock (-85°C 150°C, 1000 cycles) Salt atmosphere Moisture-sensitivity Level High-temperature storage (150°C 1000 hours) X-ray Physical dimensions Manufacturability
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Board-level reliability (BLR) testing conducted using packaged daisy-chain measuring package soldered nonsolder-mask defined (NSMD) single-sided, 0.8-mm mil)-thick board, with organic solder preservative (OSP)-finished copper pads 0.40-mm diameter. Eutectic solder used. Temperature-cycling parameters were -40°C 125°C, with 15-minute dwell extremes. units passed 2460 thermal cycles with zero failures, test terminated. Further evaluations planned will incorporate temperature cycling thicker boards plus four-point bending, torque, vibration, shock tests. results will published when available.
3.1.4
Power Dissipation
Because small size, convective cooling unit area more efficient with 20-ball MicroStar package compared larger packages. However, conduction dominant mode transfer, with minor contribution from radiation. conduction mode, balls serve sink path PCB. number weight metal layers, plus component layout proximity other power sources, have significant effect dissipation. Thermal performance also significantly influenced size because conduction efficiency depends number balls overlapped chip. However, design largest effect, models show that introduction thermal 0.30-mm mil) diameter ground ball improves performance additional multimetal-layered PCBs. performance data Figure modeled using JEDEC 1S2P test board, with thermal conductivity approximately W/mK. must emphasized that system-level performance extremely dependent numerous factors, such design, component layout proximity other power sources PCB, airflow, orientation, board-to-board spacing system upper-level assembly. values thermal impedance Table should used only guidelines further system-level modeling, indication total system thermal performance. Figures through compare MicroStar package thermal performance alternative packages, illustrate effect forced cooling power dissipation, both with without thermal vias.
Power Dissipation Ambient Temperature
20-ball MicroStar package
20-pin SSOP 20-pin TSSOP 20-pin TVSOP 20-pin PLCC
NOTE Power dissipation calculated using 125°C. 1.23 1.88
Figure MicroStar Package Thermal Comparison Multilayer JEDEC 1S2P Test Board, Zero Airflow, Thermal Vias
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Table Thermal-Impedance Guidelines
VELOCITY (LFM) (°C/W) (°C/W) (°C/W) 76.9 53.5 36.3 74.9 73.9 72.5
Power Dissipation Ambient Temperature NOTE Power dissipation calculated using 125°C, with thermal 1.23 1.88
Figure MicroStar Package Thermal Performance Multilayer JEDEC 1S2P Test Board, Various Airflow Velocities, Thermal Vias
Power Dissipation Ambient Temperature NOTE Power dissipation calculated using 125°C, with thermal 1.23 1.88
Figure Effect Thermal Vias MicroStar Package Thermal Performance JEDEC 1S2P Test Board Various Airflow Velocities
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Table Effect Vias Thermal Impedance
VELOCITY (LFM) with vias (°C/W) effect power dissipation 67.8 65.9 14.85% 13.7% 63.8
comparison area normalized thermal dissipation TSSOP, TVSOP, 20-ball MicroStar package shows that 20-ball MicroStar package 25°C (zero airflow thermal vias) exceeds TVSOP TSSOP (see Figure
108.4 Normalized Power Dissipation 25°C mW/mm2 25.6 20-Ball 20-Pin SSOP 20-Pin TSSOP 20-Pin TVSOP 20-Pin PLCC 29.0 34.0 18.5
MicroStar Package
Figure Area Normalized Power Dissipation 25°C Using JEDEC 1S2P Test Board
3.2.1
Electrical Characteristics Package Parasitics
Inductance directly related length wire proximity ground plane. wire naturally creates inductor. longer wire, greater inductance. Inductance occurs when current induced into wire, creating electromagnetic field. closer this induced electromagnetic field ground, less effective becomes. wire gets shorter and/or closer ground plane, inductance decreases.
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Capacitance created when plates (wires, lines, layers) overlap separated given distance. This distance insulated air, plastic, glass, other material. Capacitance calculated following formula:
Where: capacitance dielectric value insulator area plates overlap distance between plates Area part equation that changes most from package package. distance between plates (wires balls) varies somewhat, while package material dielectric value insulator remain constant. plate area greatly reduced package because solder balls used instead standard wire solder leads seen other packages. adjacent balls create much smaller overlap area than adjacent wire leads. spacing between plates increases, capacitance decreases. 20-ball MicroStar package smallest package offered 20-pin devices. reduced size positive effect inherent inductance capacitance packaged device. Table summarizes parasitic inductance capacitance characteristics 20-ball MicroStar package. Minimum, mean, maximum values given balls package. Table Electrical Characteristics 20-Ball MicroStar Package
(nH) Minimum Mean Maximum 0.896 1.317 2.088 (pF) 0.064 0.113 0.190
Table summarizes differences between 20-ball MicroStar package other 20-pin package alternatives. 20-ball MicroStar package offers less inductance less capacitance than 20-pin SSOP package. Resistance values were virtually unchanged omitted. Table Comparison 20-Ball MicroStar Package Parasitics Alternative Packages
PACKAGE 20-ball MicroStar 20-pin TSSOP 20-pin TVSOP 20-pin SSOP 20-pin PLCC (nH) 1.317 2.694 2.561 3.495 2.610 (pF) 0.113 0.156 0.342 0.420 0.389 51.1 48.6 62.3 49.5 27.6
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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JEDEC Definition
20-ball VFBGA received final registration from JEDEC JC-11 under semiconductor package standard MO-225. device pinout submitted JC-40 Council, passed final council vote March 2001.
VFBGA Benefits
summary, features corresponding advantages logic products assembled MicroStar VFBGA package are:
Minimum footprint available industry allows smallest board area among industry-standard packages. Required trace width spacing well defined major manufacturers. Vastly improved parasitic capacitance inductance provides better high-speed performance. JEDEC standard package under MO-225 meets worldwide mechanical pinout specifications. external components required, other than decoupling capacitors, which translates lower cost, lower maintenance, higher reliability Improved thermal performance over TSSOP TVSOP packages. Improved device reliability over alternative packages. Lower ground bounce provides more noise margin. Minimized skew pattern provides additional design margin high-speed buses. High assembly yields, with documented defect levels less
Evaluation Units
evaluation units, contact authorized distributors more information, refer http://www.ti.com/sc/msjunior
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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MicroStar Package Marking Packing
Marking
uses laser mark product number, year month manufactured, trace code, manufacturing site, location. device marking example LVTH2245 shown Figure
LK245 Part Number: LVTH2245 Year, Month, Site Location
Figure Device Marking Example namerule MicroStar VFGBA package rule with seven characters maximum. Table shows namerule logic each marking derived. naming convention first note alphanumeric code under namerule This code under namerule condensed into codes under namerules remaining function numbers added place asterisks. example, mark SN74ALVCH374 VFBGA device, note that code under namerule SN74ALVCH***. Namerule applies VFBGA, therefore, SN74ALVCH replaced code found under namerule remaining function numbers (374) added onto VB374. Table Samples Name Markings Various 20-Ball MicroStar Package Offerings
DEVICE NAME SN74ALVCH374 SN74ABT245B SN74ALVC244 SN74CBT3245A SN74LV573A NAMERULE SN74ALVCH*** SN74ABT2*** SN74ALVC*** SN74CBT32*** SN74LV*** NAMERULE ALVCH*** ABT2*** ALVC*** CBT32*** LV*** NAMERULE VB*** AA*** VA*** BV*** LV*** TOP-SIDE MARKING VB374 AA245B VA244 BV3245A LV573A
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Tape Reel
Embossed tape reel feed preferred method automatic pick place machines. offers tape reel packaging 20-ball MicroStar package. standard quantity 1000 units reel. Packaging materials include carrier tape, cover tape, reel. materials used meet industry guidelines protection comply fully with Standard 481-A, Taping Surface Mount Components Automatic Placement. dimensions interest user tape width (W), pocket pitch (P), quantity reel. Figure Table show carrier tape dimensions. Figure gives dimensions reel assembly.
NOTE dimensions millimeters.
Figure Tape Dimensions Table Carrier Tape Dimensions
CARRIER TAPE WIDTH POCKET PITCH (P1) POCKET WIDTH (A0) POCKET LENGTH (B0) 4.30 POCKET DEPTH (K0) 1.60 HOLE-TOPOCKET CENTERLINE (P2) HOLE-TOPOCKET CENTERLINE 5.50 SPROCKET HOLE PITCH (P0) DEVICE QUANTITY REEL 1000
12.00 8.00 3.30 dimensions millimeters.
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Reel Diameter
Reel Width Cover Tape Width
REEL WIDTH (mm) 12.00 +2.0/-0
REEL DIAMETER (mm) maximum
NOTE Standard quantity 1000 devices reel, however, this subject change market demand.
Figure Reel Assembly Dimensions
Sockets Socket Ordering Information
Loranger part number: 040030020U6617 Loranger International Corporation Fourth Avenue Warren, 16365 Telephone: (814) 723-2250
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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Conclusion
This application report shows that 20-ball MicroStar package optimal solution addressing performance economic issues such
area savings over TSSOP Minimized skew reducing pin-to-pin inductance, thereby enabling support high-speed applications with greater bandwidth Improved thermal dissipation Improved board-mount assembly yields inherent processes
spacing between balls this 0.65-mm VFBGA package equal that other 0.8-mm-pitch packages, therefore, defect rates solder bridging similar those larger packages. performance MicroStar package definite advantage over other standard packages. simultaneous-switching data graphs [see 16-Bit Widebus Logic Families 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch (VFBGA) Packages application report (SZZA029)] clearly show this smaller package, with lower capacitance inductance, speed noise advantages over SSOP, TSSOP, TVSOP packages. Designers using MicroStar package take advantage win-win combination electrical physical properties offered. With introduction MicroStar VFBGA packages OEMs assured standardized JEDEC package, pinout, availability previously stated product families functions. More device families functions will included MicroStar package market interest dictates.
8-Bit Linear Logic Families 20-Ball, 0.65-mm Pitch, Very-Thin, Fine-Pitch (VFBGA) Packages
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