Microelectronic Package Standard 1999 Printed U.S.A. 0199

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Microelectronic Package Standard 1999 Printed U.S.A. 0199

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JEDEC Publication
Microelectronic Package Standard
1999
Printed U.S.A. 0199
SZZA006
JEDEC Publication Microelectronic Package Standard
SZZA006 January 1999
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
Title Page Abstract What EIA/JEDEC? What Publication Purpose Registered Outlines Standard Outlines Documents Controlled? Changes Made? Does Package Outline Conform JEDEC? What Contained Publication Contents Requirements Document Registration Definitions Symbology Various Registered-Outline Types Various Standard-Outline Types Access Publication
Find Registration Standard Number Option Option Option Option Option Search Procedure Guides Designers Summary Glossary Acknowledgment Bibliography Appendix
List Illustrations
Figure Title Page Page JEDEC Page Access Publication Publication Page Publication Web-Page Extension Master Index Other Sections (Design Guides) Standard Practices Procedures (SPP) Microelectronic Outlines (MO) Index Family Listing Ball Grid Array Registrations
Example Registered-Outline Drawing Sheet Example Standard-Outline Drawing Sheet Example Carrier Registered-Outline Drawing Sheet Example Diode Registered-Outline (DO) Drawing Sheet
Abstract
Many electronics companies have joined Joint Electron Device Engineering Council (JEDEC) JC-11 Mechanical (Package Outline) Standardization committee gain further understanding industry package standards register their product lines. member JC-11, company receives hardcopy Publication that generally custody committee member. publication updated maintained member alternate. JC-11 member, alternate, often contacted information, drawing copy, instructions registering package with JEDEC. JEDEC provides free access Publication JEDEC page. This document intended familiarize reader with JC-11 procedures, requirements registration, locate Publication available information useful packaging engineers, component engineers, product engineers, users, designers, marketing personnel.
What EIA/JEDEC?
Electronic Industries Alliance (formerly Electronic Industries Association), which provides many services benefits electronics industry. umbrella organization many standardization activities committees, which JEDEC. web-page address www.eia.org (see Figure JEDEC accessed from this page selecting JEDEC Solid-State Products Electronics Technology Division.
Figure Page JEDEC became full division January 1998 controls budget operation. JEDEC been serving industry many decades standardization efforts areas test methods, nomenclature, packaging, product characterization. JEDEC governed board directors composed representatives various member companies. JEDEC, with many committees, engineering standardization body solid-state products United States, with membership more then companies. JEDEC web-page address www.jedec.org (see Figure
Figure JEDEC Page JEDEC Committee Roster found JEDEC page (Figure accessing Committee Roster, under JEDEC seal. This roster provides information JEDEC office staff various JEDEC committees chairs, with their company affiliations. committees within JEDEC are: JC10 JC-11 JC-13 JC-14 JC-15 JC-16 JC-17 JC-22 JC-25 JC-40 JC-41 JC-42 JC-44 Terms, Definitions, Symbols Mechanical (Package Outline) Standardization Government Liaison Quality Reliability Solid-State Products Electrical Thermal Characterization Techniques Electronic Packages Interconnects Electrical Interface Power-Supply Standards Electronic Components Microelectromechanical Systems (MEMS) Diodes Thyristors Transistors Standardization Digital Logic Linear Integrated Circuits Solid-State Memories Semicustom Integrated Circuits
This document provides insight into JC-11 Package Outline committee Publication JC-11 committee meets four times year. size committee, attendance restricted company members alternates, invitation approval committee chair.
What Publication
Purpose Publication (Pub-95, JEP95), JEDEC Registered Standard Outlines Solid State Related Products, many documents published EIA/JEDEC. Pub-95 documents several-hundred Registered Outlines, Standard Outlines, various Design Guides endorsed JC-11, Mechanical (Package Outline) Standardization. publication grown three loose-leaf binders, which divided into sections easier use. first sections provide general information latter sections contain various Registration Standard documents. Pub-95 accessed from JEDEC page (see Figure selecting Free Standards, located just left JEDEC seal. screen shown Figure displayed. From this screen, scroll down select Publication
Figure Access Publication resulting screen (Figures page Publication Registered Outlines Standard Outlines Registered- Standard-Outline drawings look identical, except outline number statement above page title block. Registered Outline following statement bottom page drawing: This Registered Outline been prepared JEDEC JC-11 committee reflects product with anticipated usage electronics industry; changes likely occur. Appendix Figure example. Note number near lower right corner. Standard Outline following statement page drawing: This Standard Outline been prepared JEDEC JC-11 committee approved JEDEC Council reflects product with wide acceptance electronics industry; changes likely occur. Appendix Figure example. Note number near lower right corner.
Documents Controlled? JC-11 committee approves additions changes Pub-95. Changes Standards, Standards, also must have JEDEC Board Directors approval. Once approved, change forwarded JEDEC office Arlington, Virginia, update made Pub-95. 1997, Pub-95 placed JEDEC page (see Figures
Figure Publication Page
Figure Publication Web-Page Extension
Changes Made? JC-11 member company propose Registration Registration change. proposals approved ballot must have two-thirds affirmative vote before being published. Organizations within company should contact their JC-11 member needed changes registrations. company listing committee members available, contact company JEDEC board member. Standard Registration that being elevated Standard) process includes same JC-11 committee ballot approval and, addition, must have unanimous JEDEC board approval published. Does Package Outline Conform JEDEC? first questions asked ``Does package conform JEDEC?" Checking JEDEC conformance manual process finding potential similar Registrations Standards performing dimensional comparison analysis.
What Contained Publication
Contents Information Pub-95 useful package designers, component engineers, product engineers, designers, marketing personnel. question that frequently asked ``Does package meet conform JEDEC?" Package designers concerned that design concepts conform JEDEC Design Guides. Pub-95 divided into sections easier reference; each section table contents. Master Index provides overview entire document. sections are:
Guide Outline Preparation Symbol List, Terminal Positions (drawings conform ASME Y14.5M1994) Outline Classifications JEDEC 95-1: Standard Practices Procedures. Standard Outlines: (Microelectronic Standard), (Carrier Standard) Carrier Outlines (CO-nnn) -nnn denotes sequential number assigned committee Diode Outlines (DO-nnn) Transistor Outlines (TO-nnn) Uncased Outlines (UO-nnn) Gauges (GS-nnn) Microelectronic Outlines (MO-nnn)
Requirements Document Registration member company propose register outline (package) introducing proposal business item regularly scheduled meeting JC-11. sponsor must present outline drawing conforming committee requirements drafting standard ASME Y14.5 M1994. sponsor required provide either sample outlines company literature demonstrating company commitment. member company also sponsor elevation Registration Standard. outline raised Standard should well accepted industry must have been registered years before being elevated Standard. voting process first must pass JC-11 committee then JEDEC board. Normally, Registration number rescinded Standard number assigned. document published appropriate standard section. Definitions Symbology Documents included Publication must conform procedures defined Publication 95-1 (Pub-95, Section This section defines requirements, such guide drawing preparation, symbols used, approved classification system, various design guidelines. Appendix Figures A-2, examples. JC-11 Committee packaging adopted Dimensioning Tolerancing Standard ASME Y14.5M-1994 reference document documents registered. Standard Practice Procedure (SPP-13) defines border format titles. Individual company drawings acceptable registration.
Symbology standardized when comparing registrations JEDEC EIAJ IEC47D. Each organization uses different symbols formats. This problem very cumbersome when organization wishes move registration another organization. Joint meetings held routinely address these issues. Various Registered-Outline Types member company approach committee register package. result, there many types registered outlines (see Figures Carrier Outline denoted CO-nnn, where -nnn sequential number assigned committee. Carrier registration types include PDIP shipping tubes, PLCC shipping tubes, trays various types (see Figure A-3). Diode Outline denoted DO-nnn. Diode outlines include two- three-lead devices, well axial-lead devices. Activity this category very (see Figure A-4). Transistor Outline denoted TO-nnn. Recent outline registrations this category include two-, three- four-lead surface-mount packages similar Small-Outline Packages (SOPs) packages similar TO-220 surface-mount package. Uncased Outline denoted UO-nnn. There only registered outlines this category, Beam Lead TAB. largest category Microelectronic Outlines, denoted MO-nnn. This category includes outlines PDIP, SOJ, SOP, SSOP, QFP, BGA, DIMM, ceramic packages, bottom-contact (no-lead) packages. This category more than registrations. Various Standard-Outline Types Standard Outlines packages that have become widely accepted industry considered true standard. Very Registrations become Standard.
REGISTERED OUTLINE CO-nnn DO-nnn TO-nnn UO-nnn MO-nnn (Carrier Outline) (Diode Outline) (Transistor Outline) (Uncased Outline) (Microelectronic Outline) CS-nnn DS-nnn TS-nnn US-nnn MS-nnn STANDARD OUTLINE (Carrier Standard) (Diode Standard) (Transistor Standard) (Uncased Standard) (Microelectronic Standard)
more than Registrations, there only Standards. Access Publication Pub-95 free access password required) viewers with access. Anyone with computer access access registration print document. AdobeAcrobatReader required view documents. Access Pub-95 through page going directly JEDEC home page. home page: Enter www.eia.org. Select JEDEC Solid-State Products Technology Division (see Figure Select Free Standards (see Figure Scroll down select Publication (see Figure Figure shows introduction JEDEC Publication
Find JEDEC home page entering page www.jedec.org from Step above, follow Steps From JEDEC Publication screen (see Figures reader access Master Index, Registrations Standards, Standard Policies Procedures, Design Guides.
Adobe Acrobat trademarks Adobe Systems Incorporated.
Find Registration Standard Number
Find package outline drawings Pub-95 address following five steps Access Publication Web. Either method provides same screen shown Figure There several options available from this screen. Option Selecting Master Index provides numerical listing Registration Standard types Pub-95 (see Figure
Figure Master Index
Option Selecting Other Sections displays listing various Design Guides adopted JC-11 (See Figure
Figure Other Sections (Design Guides) Option Selecting Standard Policies Procedures provides listing JC-11 committee operating procedures (see Figure
Figure Standard Policies Procedures (SPP)
Option Selecting Other Links allows access Package Land-Pattern Calculator (see Figure Option screen shown Figure displays comparison Outlines/Registrations Standards (Mechanical Standards); example, Search Procedure common question ``Does package meet JEDEC?" determine this, manual search through Pub-95 required find similar drawings compare them package question, dimension dimension. example, assume package comparison needed. reader accesses selection Figure screen shown Figure displayed.
Figure Microelectronic Outlines (MO) From this screen, three basic choices available. Master Index same Pub-95 overall index described earlier shown Figure Scroll down list look registrations. This undesirable choice because Adobe Acrobat must activated just display index then, after viewing list, reader must through registrations find list MOs. drawings cannot read directly. Scrolling down screen (see Figure reveals sequential numerical listing registration outlines. reader click name choice view drawing using Adobe Acrobat. This better choice, still most efficient method. Selecting MO-Index (see Figure displays By-Family Index Registered Microelectronic Outlines (MO) JEP-95 (see Figure 10).
Figure Index Family Selecting package family name, this case Ball Grid Array (BGA) Family, produces screen outlines having this family description, both Registration Standard MSs. This, far, most direct method find similar package registrations review (see Figure 11). view registration, select click blue title.
Figure Listing Ball Grid Array Registrations
future, search acronyms such SSOP, QFP, PDIP will added page. knowing type package, reader search quickly particular package type screen many name description. Guides Designers Various Design Guides located Pub-95 page (see Figure There also link Package Land-Pattern Calculator. Current Design Guides included 95-1 are: Section Section Section Section Section Section Quad Flatpack Generic Matrix Tray Handling Shipping Dual Inline Plastic Family Metric Package Ball Grid Array Package Fine-Pitch (pending)
Summary
Pub-95 been provided member companies JC-11 many years. Access been limited committee members, alternates, member companies willing added additional copies. past, member-company employees contact committee member obtain information concerning package registration registration details. Today, anyone with access view Registration Standard print copy. single most misunderstood factor with JC-11 difference Registrations Standards. This difference been explained, readers understand difference know find them efficiently using JEDEC page.
Glossary
ASME ASME Y14.5M-1994 EIAJ GD&T American Society Mechanical Engineers Dimensioning Tolerancing Standard endorsed JC-11 Ball grid array package Electronic Industries Alliance (formerly known Electronic Industries Association) Electronic Industries Association Japan Geometric Dimensioning Tolerancing drafting methodology endorsed ASME Y14.5M-1994 JC-11 International Electrotechnical Commission Committee Number JEDEC, with responsibility establishing package-outline Registrations Standards JEDEC Bulletin number Joint Electron Device Engineering Council JEDEC Board Directors (formerly known JEDEC Council) Section Pub-95, Design Guidelines JEDEC Publication Publication JEDEC JC-11 committee Package-outline drawing approved JC-11 committee Small-outline J-lead package Standard Policies Procedures JC-11 committee JC-11 Registration that attained wide industry recognized industry standard Thin Shrink Small-Outline Package
JC-11
JEB-xx JEDEC JEDEC JEDEC Standard 95-1 JEP-95 Pub-95 Registered Standard
TSSOP
Acknowledgment
John Yantis, P.E., acknowledged author this report. Sadly, John died accident prior publication. John contributor TI's Logic Products packaging group over years representative JEDEC JC-11 committee packaging standardization. contributor JEDEC Publication that this application report describes also chaired JC-11.10 subcommittee Microelectronic Ceramic Packages JC-11.7 subcommittee Interface. behalf John's family, friends, colleagues, acknowledge extensive contributions practice engineering pride association with him.
Bibliography
Publication Registered Outlines Solid State Related Products, EIA, Arlington, 1996. ASME Y14.5M-1994, Dimensioning Tolerancing, American Society Mechanical Engineers, York, N.Y., 1995. http://www.jedec.org, EIA-JEDEC, Arlington, 1997
Appendix
Figure A-1. Example Registered-Outline Drawing Sheet
Figure A-2. Example Standard-Outline Drawing Sheet
Figure A-3. Example Carrier Registered-Outline Drawing Sheet
Figure A-4. Example Diode Registered-Outline (DO) Drawing Sheet

Microelectronic Package Standard 1999 Printed U.S.A. 0199

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