1999 Printed U.S.A 0399 SZZA003 Package Thermal Charact

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1999 Printed U.S.A 0399 SZZA003 Package Thermal Charact

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Package Thermal Characterization Methodologies
1999
Printed U.S.A 0399
SZZA003
Package Thermal Characterization Methodologies
SZZA003 March 1999
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
Title Page Abstract Introduction Background Junction-to-Case Thermal Resistance Military Standard Description Simulated Infinite Heat Sink Description Other JC-Like Determinations Prior JEDEC Method Description Military Ceramic Plastic
Characterizing Using JEDEC Method Summary Acknowledgment References
List Illustrations
Figure Title Page Representation Distributed Resistance Thermal Dissipation Device Representation Distributed Thermal Resistance With External Factors Added Schematic Thermal Characterization Military Test Configuration Illustrated MIL-STD-883 Method 1012.1 Small-Die Large-Die Dissipation Areas Simulated Infinite Heat Sink Military-Standard Method JEDEC Method Test Setup Still-Air Portion Test
Abstract
Improving performance semiconductor devices increased per-device power consumption, allowable junction temperatures. Historically, thermal-resistance measurements have been made variety ways that have been explained thoroughly. advantages JEDEC method (JESD explained compared with other methods used determine thermal resistance semiconductor devices.
Introduction
Even with lower voltage levels, steady increase logic clock speed gate count resulted device parasitic heat loss that would have been almost unbelievable just years ago. Some leading-edge processors must dissipate much small incandescent room light. This offers significant challenges system-level designers, particularly because allowable junction temperatures increasing. Conversely, some technologies, junction temperatures must maintained lower than could previously allowed reliability concerns with newer metal systems smaller geometries. Historically, tool that system designers have used compare devices determine operating junction temperatures properties published semiconductor manufacturers that specify ability device packages dissipate junction-generated heat away from surface silicon die. Although relatively simple concept, these thermal-resistance values sometimes misunderstood misused, partly because manufacturers rarely publish they measured what they represent physically. Without this knowledge, advantages JEDEC method (JESD measuring thermal impedance cannot appreciated. This application report begins with explanation thermal-impedance values have been obtained historically, then describes advantages newer JESD method.
Background
Thermal resistance solid much like electrical resistance that steady-state defining equation across solid heat (watts) conducted through solid
(usually expressed °C/W)
Where thermal resistance material. That measured temperature, across solid would mean T/RT watts power passes through Figure shows simplified two-dimensional diagram resistance heat flow from junctions surface surface package.
Figure Representation Distributed Resistance Thermal Dissipation Device
etc., equivalent thermal resistances from surface section package. Because thermal resistance solid depends material properties, length path, cross-sectional area path, each section package contributes unique thermal resistance. Thermal power dissipation from surface surface package calculated Overall power dissipated Where: l.TS package surface temperatures exterior locations shown average junction temperature surface Rl.Rn distributed thermal resistances each section package smaller overall package thermal resistance becomes, better able package conduct heat away from surface. ability package conduct heat from outside surface were that required predict junction temperatures, semiconductor manufacturers could provide accurate thermal resistance using finite-element analysis (FEA) equivalent discrete models. Unfortunately, external factors, such airflow spacing from printed circuit board (PCB), affect package thermal resistance much more than package construction itself. Figure shows effects external factors thermal resistance assembled device.
TS1) TS7) )AAA TSN) (RN)
Ral.Ran
thermal resistance around device thermal resistance whatever under package (e.g., thermal grease gap) lead thermal resistance thermal resistance, etc.
Figure Representation Distributed Thermal Resistance With External Factors Added Table shows effects environment junction temperature. Table Selected Thermal-Resistance Values
MATERIAL Copper (lead frame) Silicon (die) Ceramic Mold compound (plastic case) Thermal grease (PWB) THERMAL RESISTIVITY 0.003 0.007 0.055 1.59 .7468 38.2
These values most often published inversely conductivity), listed here resistive consistent with overall package thermal resistance expressed. These values thermal conduction only. Actual thermal analysis involves conduction, convection, radiation, which calculated differently estimated accurately only dedicated using empirical data. purpose explaining package thermal resistance, simplified resistor model used here. Because external resistances surrounding air, PCB, thermal grease, etc. series with package resistance, factors external package affect junction temperature significantly. package overall thermal resistance equivalent Equation Figure about 14°C/W after adding external resistive factors, such surrounding (equivalent Figure thermal resistance 40°C/W, higher, could expected. This presents problem device manufacturers want provide thermal information about their packages because external factors known package thermal characterization. solution, semiconductor manufacturers historically have provided types resistance values: (resistance from junction case) attempt account end-use environments.
Junction-to-Case Thermal Resistance
approximately, ability device dissipate heat ideal environment, that mounted with infinite temperature-controlled heat sink. However, test methods used determine have varied past proper this value depends which method used determine specified value. Military Standard
Description
Instructions determining military products specified MIL-STD-883 Method 1012.1. determined using this method defines ability device dissipate heat mounted temperature-controlled heat sink. establish temperature reference surface die, temperature-dependent forward bias voltage bipolar junction calibrated constant bias current several different temperatures oven. This unused junction device, usually special thermal characterization assembled package being tested (see Figure
Temperature Calibration Forward Bias Voltage Over Temperature 0.68 0.66 0.64 0.62 0.58 0.56 0.54 0.52 24.6 Controlled-Temperature Environment Temperature
Figure Schematic Thermal Characterization
device then placed copper heat sink that maintained constant temperature, using thermal grease ensure best possible conductivity. thermocouple inserted through heat sink pressed against underside package nearest device record package surface temperature. MIL-STD-883 Method 1012.1 specifies that thermocouple placed hottest part case (see Figure
Pressure Adjustment Wing Nuts With Threads Inch
Contact Pressure Spring Package 21.2 lbs/in Clamping
Adapter Heatsink
Primary Heatsink
Plastic Sleeve Over Probe Leads Electrical Leads
Figure Military Test Configuration Illustrated MIL-STD-883 Method 1012.1 With some amount power applied power-dissipating elements die, forward bias voltage measured after temperature stabilized surface temperature determined. then calculated using formula:
surface temperature Package surface temperature Power applied
Package surface temperature temperature recorded thermocouple pressed against underside package. surface temperature temperature derived from previously calibrated forward bias voltage. Power applied product voltage current applied resistive network (bias current small enough ignored).
Thermocouple Leads SIDE VIEW
Pressure Plate
Chip Microelectronic Package 24-pin DIP, Typical
Sockets Electrical Contacts
Probe Tip, 0.62 Diameter Typical
Thermal Probe (HYPO) Assembly
Contact Pressure Spring Probe 1.10 lbs/in
Pressure Adjustment Cap, Threads Inch
configuration Figure represents, nearly possible, ideal heat sink placed directly under die. does comprehend other heat sink position, does include additional cooling, such flow. With heat sink maintained constant temperature during testing, MIL-STD-883 Method 1012.1 provides more nearly ideal than device were mounted passive heat slug. Assembly designers often measured this approximate junction temperatures circuit conception. unit mounted surface with known thermal properties, such thermal rail, heat assumed taken along this path, estimation junction temperature straightforward. Because many military applications enclosed, with heat extraction through heat sink bottom device case thermal rail same configuration test), thermocouple attached measured package surface used estimate realistic junction temperatures assembled system. thermocouple applied this manner gives erroneous results heat sink used in-use configuration differs from test configuration. far, largest variation potential values measured this manner size used test. With standard thermal sizes available, unidirectional heat flow from finite source fans approximately 45-degree angle isotropic material (see Figure
0.120 0.030 Package 0.180 0.0324 dimensions inches. 0.030 0.240 Package 0.300 0.09
Figure Small-Die Large-Die Dissipation Areas larger dissipates power over area three times that smaller die, thus heat dissipated large-die device about one-third that smaller die. This much problem seem first because test-die sizes chosen match size device die. does explain though, smaller packages, and, therefore, smaller die, have significantly higher values when measured using MIL-STD-883 Method 1012.1. addition, several devices slightly varying size same package, causing slight deviations from published thermal-resistance values. Default values that significantly higher than package were measured have been published miltary standards. Therefore, particular package type been characterized manufacturer, default values used cause some military thermal-resistance values seem extraordinarily high. Although ceramic much better thermal conductor than most organics, military semiconductor users occasionally confused fact that plastic packages sometimes have lower published (and discussed later this application report) values than equivalent ceramic-package devices. root this paradox package materials, different methods characterizing Simulated Infinite Heat Sink
Description
historical method characterizing similar that used military devices, device immersed agitated, electrically insulating fluorinert fluid rather than sitting heat sink. This test method attempt measure directly overall thermal resistance package. Even though thermal resistance fluorinert poor, this method emulates, some extent, infinite heat sink parts package. Figure shows practical difference between simulated infinite heat sink military-standard method.
Immersed
Military Standard
Where:
)AAA)
fluid thermal resistance exterior package Figure Simulated Infinite Heat Sink Military-Standard Method parallel resistance net, composed entire package opposed only bottom section, explains package made thermally inferior material, such plastic instead ceramic, sometimes have lower published thermal resistance values.
Thermal resistance determined this best used comparison purposes only (with other similarly measured devices). Thermal resistance cannot used approximate junction temperatures prior component assembly power because package surface used extract heat during this test impossible know package will affected system environment.
Other -Like Determinations
There universal standard been determined various ways. instance, some package vendors models determine thermal performance their packages. this category, been calculated from surface most remote part package, well calculated from resistance meshes similar equation newer method, differentiated designator defined EIA/JESD 51-2. This method entails measuring case temperature using fine-gage thermocouple glued package during operation PCB. This allows more accurate calculation system-level situ junction temperatures because more closely replicates typical end-use conditions1. Semiconductor data sheets typically published using consistent thermal-resistance-measuring techniques described here, but, thermal information obtained from third party, such package vendor, important understand their definition
Prior JEDEC Method
Description measure ability device dissipate heat while operating open without heat sink. Recently, JEDEC refined terminology open-air testing that, test performed still air, properly termed performed wind tunnel with calibrated velocity, called JMA. Before this refinement, types open-air testing usually were labeled lack standardized methodology, this general description also differing methods results. Military Ceramic There specific requirement military specifications provide JMA, typical military testing, when published, usually determined most conservative interpretation. example, Military Semiconductor Group tests with unit suspended open under cover with flow. Because very good insulator, thermal resistance values produced worst case. times, this troublesome because device that would usable provided added heat-dissipative capabilities mount, might eliminated during preliminary consideration deceptively high junction temperatures derived from highly conservative value Devices suspended have values more times that mounted units, depending device configuration.
Plastic values plastic-package devices have been characterized environmental conditions considered manufacturer adequate in-use junction-temperature estimation. This vary from suspended air, mounted boards, sitting countertops, inserted sockets. Generally, used comparison tool between package types. preliminary estimates on-board junction-temperature, derating curves derived from using formula Equation Maximum device power
Maximum junction temperature allowed Estimated ambient temperature
considered worst case measured open air, socket, possibly, nominal measured mounted PCB. trace dimensions, device orientation, turbulence method measuring velocity, proximity ambient temperature thermocouple, enclosure size, any, additional factors that change value. Junction maximum allowable ambient temperatures often calculated from device product engineers, this very conservative approach measured open with conduction PCB. Experiments have shown that heat produced typical package dissipated from test board2. Conversely, this calculation result only nominal optimistic values measured mounted PCB, particularly thermal vias power planes. Unfortunately, semiconductor manufacturers often publish their thermal-resistance values were determined.
Characterizing Using JEDEC Method
JEDEC Method provides semiconductor industry method eliminating most troublesome aspect characterization: inconsistency. addition, this test method emulates slightly conservative, realistic, system-level environment junction-temperature estimations. Method enforces rigid environmental requirements, controlling parameters that contributed previously resistance variability. Figure shows test fixture still-air portion test.
Unit under test Insulating suport specific dimensions Insulating cover specific dimensions without planes thermal vias; trace size length, connector type board material construction defined. (see Note Thermocouple used record ambient temperature; location defined JEDEC Test leads
NOTE: Although EIA/JEDEC Standard 51-3 (August 1998) lists only board described here planes thermal vias) there another board design pending publication that four layers power planes. Because currently published board called effective thermal-conductivity test board, power-plane design could considered high- higher-conductivity test board. This board used many companies.
Figure JEDEC Method Test Setup Still-Air Portion Test JEDEC explicitly defined parameters because studies indicated surprising thermal effects environment, addition parameters mentioned previously. example, study shows that trace length affect measured plastic package almost much presence absence lf/m airflow1. Also, modeling evaluations have shown that this methodology sufficiently controlled that only package configuration need measured. Other packages same material configuration, different size, then characterized using parameters determined from measured unit. Because large portion heat generated surface conducted PCB, this arrangement provides much more consistent realistic value between characterization laboratories than previous methods. addition, junction-temperature calculations based this method characterization provide good conservative nominal first-pass value. JEDEC method measuring does provide junction temperatures from case temperature newer provide, these values, equivalent, continue required data-sheet entries. Presumably, ambiguous characterization methods, such immersion, will replaced defined methods similar military
Summary
primary purpose this application report inform users thermal-resistance values derating curves hidden variabilities historical values emphasize importance inquiring into test methodology before using results. addition, explanation inconsistencies measurements between manufacturers package types been provided. JEDEC methods have potential greatly improving accuracy reliability semiconductor-package thermal characterization. This application report also explains rationale behind TI's conversion JEDEC standard. provides MIL-STD-883 method 1012.1 military parts, adds more realistic JEDEC method. commercial plastic devices have been characterized using JEDEC method since 1995.
Acknowledgment
author this application report Pauley.
References
JEDEC Standard K-Factor Test-Board Design Impact Thermal Impedance Measurements, literature number SCAA022A

1999 Printed U.S.A 0399 SZZA003 Package Thermal Charact

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