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TMS320C4x User's Guide
SPRU063C 1999
Copyright 1999, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This user's guide serves reference book TMS320C40 TMS320C44 digital signal processors. Throughout book, references TMS320C4x apply both devices, except when otherwise noted.
This Manual
following table summarizes information contained this user's guide:
looking information about: Addressing modes ARAUs Bootloader Structure Turn these chapters: Chapter Addressing Modes Chapter Architectural Overview Chapter Bootloader Chapter Architectural Overview
Chapter External Operation
Cache Communication Ports Architecture Chapter Memory Instruction Cache Chapter Communication Ports Chapter Architectural Overview Chapter Registers Data Formats Delayed Branches Instruction Chapter Coprocessor Chapter Data Formats Floating-Point Operation Chapter Program Flow Control Chapter Assembly Language Instructions
Style Symbol Conventions
looking information about: Interrupts Memory
Turn these chapters: Chapter Program Flow Control Chapter Architectural Overview Chapter Memory Instruction Cache
Peripherals
Chapter Communication Ports Chapter Coprocessor Chapter Timers
Overview 'C4x Program control Pipeline Registers
Chapter Introduction Chapter Program Flow Control Chapter Pipeline Operation Chapter Registers Chapter Communication Ports Chapter Coprocessor Chapter Timers
Repeat Mode Reset Timers Traps
Chapter Program Flow Control Chapter Program Flow Control Chapter Timers Chapter Program Flow Control
Style Symbol Conventions
This document uses following conventions:
Program listings, program examples, file names, symbol names
shown special font. Examples bold version special font emphasis. Here sample program listing segment:
LOOP1 RPTB CMPF LDFLT LOOP2 RPTB CMPF LDFLT NEXT
*AR0,R0 *AR0,R0 NEXT *AR0++(1),R0 *-AR0(1),R0
;Compare number maximum greater, this
;Compare number minimum smaller, this minimum
Style Symbol Conventions
syntax descriptions, instruction bold face parameters
italic face. Portions syntax that bold face should entered shown; portions syntax that italic face describe type information that should entered. Here example instruction: CMPF3 src2,src1 Notice that although instruction mnemonic (CMPF3 this example) capital letters, 'C4x assembler case sensitive assemble mnemonics entered either upper lower case. CMPF3 instruction mnemonic. This instruction parameters, indicated src2 src1.
Square brackets identify optional parameter.
optional parameter, must specify information within brackets; however, don't enter brackets themselves. Here's example instruction that optional parameter: [label] [,DP] instruction shown with parameters; optional. first parameter, src, required. second parameter, label, optional. this syntax shows, optional second parameter, must precede with comma.
Throughout this book indicates most significant
indicates least significant bit. indicates most significant byte indicates least significant byte.
Read This First
Information About Cautions Warnings
Information About Cautions Warnings
This book contain cautions warnings.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
This example warning statement. warning statement describes situation that could potentially cause harm you.
information caution warning provided your protection. Please read each caution warning carefully.
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
following books describe TMS320 floating-point devices related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number.
TMS320C4x General-Purpose Applications User's Guide (literature number SPRU159) describes software hardware applications 'C4x processor. Also includes development support information, parts lists, XDS510 emulator design considerations. TMS320C4x Parallel Processing Development System Technical Reference (literature number SPRU075) describes TMS320C4x parallel processing system, system with four C4xs with shared distributed memory. Parallel Processing with TMS320C4x (literature number SPRA031) describes parallel processing 'C4x used parallel processing. Also provides sample parallel processing applications. TMS320 Floating-Point Assembly Language Tools User's Guide (literature number SPRU035) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C3x 'C4x generations devices. TMS320 Floating-Point Optimizing Compiler User's Guide (literature number SPRU034) describes TMS320 floating-point compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C3x 'C4x generations devices. TMS320C4x Source Debugger User's Guide (literature number SPRU054) tells invoke 'C4x emulator simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C4x Technical Brief (literature number SPRU076) gives condensed overview 'C4x development tools. also lists TMS320C4x third parties.
Read This First
Related Articles Books
TMS320 Family Development Support Reference Guide (literature number SPRU011) describes '320 family digital signal processors various products that support This includes code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). This book also lists related documentation, outlines seminars university program, gives factory repair exchange information. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that supply various products that serve family '320 digital signal processors-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. TMS320 Designer's Notebook: Volume (SPRT125). Presents solutions common design problems using 'C2x, 'C3x, 'C4x, 'C5x, other DSPs.
Related Articles Books
wide variety related documentation available digital signal processing. These references fall into following application categories:
General-Purpose Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references. Texas Instruments strongly suggests that refer these publications.
General-Purpose DSP:
Antoniou, Digital Filters: Analysis Design, York, McGraw-Hill Company, Inc., 1979.
viii
Related Articles Books
Brigham, E.O., Fast Fourier Transform, Englewood Cliffs, Prentice-Hall, Inc., 1974. Burrus, C.S., T.W. Parks, DFT/FFT Convolution Algorithms, York, John Wiley Sons, Inc., 1984. Chassaing, Horning, D.W., Digital Signal Processing with Fixed Floating-Point Processors." CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988. Erskine, Magar, "Architecture Applications Second-Generation Digital Signal Processor." Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor." IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986. Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing." Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987. Gold, Bernard, C.M. Rader, Digital Processing Signals, York, McGraw-Hill Company, Inc., 1969. Hamming, R.W., Digital Filters, Englewood Cliffs, Prentice-Hall, Inc., 1977. IEEE ASSP Committee (Editor), Programs Digital Signal Processing, York, IEEE Press, 1979. Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988.
Read This First
Related Articles Books
Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors." Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987. Lovrich, Reimer, Advanced Audio Signal Processor." Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability." Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Morris, Robert Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. Oppenheim, Alan (Editor), Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1978. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Oppenheim, A.V., A.N. Willsky, I.T. Young, Signals Systems, Englewood Cliffs, Prentice-Hall, Inc., 1983. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed Bit-Reversed Order Algorithms." Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13-29, December 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor." Computers Education Journal, USA, Volume Number pages 12-16, July-September 1993. Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor." Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume page 1678, April 1988.
Related Articles Books
Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip." Proceedings ICASSP USA, Catalog Number 87CH2396 Volume pages 535-538, April 1987. Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor." 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Andrews, H.C., B.R. Hunt, Digital Image Restoration, Englewood Cliffs, Prentice-Hall, Inc., 1977. Gonzales, Rafael Paul Wintz, Digital Image Processing, Reading, Addison-Wesley Publishing Company, Inc., 1977. Papamichalis, P.E., "FFT Implementation TMS320C30." Proceedings ICASSP USA, Volume page 1399, April 1988. Pratt, William Digital Image Processing, York, John Wiley Sons, 1978. Reimer, Lovrich, "Graphics with TMS32020." WESCON/85 Conference Record, USA, 1985.
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25." Proceedings SPEECH TECH pages 218-221, 1989. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17." Proceedings SPEECH TECH '87, pages 25-29, April 1987. Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Jayant, N.S., Peter Noll, Digital Coding Waveforms, Englewood Cliffs, Prentice-Hall, Inc., 1984. Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25." Proceedings SPEECH TECH '87, pages 201-204, April 1987.
Read This First
Related Articles Books
Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer." Proceedings ICASSP USA, pages 801- 804, 1989. Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications." Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP." Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application." PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors." MOTORCON '88, pages 248-262, September 1988. Ahmed, Lindquist, "Digital Signal Processors: Simplifying High-Performance Control." Machine Design, September 1987. Ahmed, Meshkat, "Using DSPs Control." Control Engineering, February 1988. Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives." Electronics Letters, Volume Number pages 2188-2190, November 1992. Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion." Proceedings IECON '87, Volume pages 454-463, November 1987. Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988. Jacquot, Modern Digital Control Systems, York, Marcel Dekker, Inc., 1981. Katz, Digital Control Using Microprocessors, Englewood Cliffs, Prentice-Hall, Inc., 1981. Kuo, B.C., Digital Control Systems, York, Holt, Reinholt, Winston, Inc., 1980.
Related Articles Books
Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control." Proceedings ICASSP USA, Volume page 1734, April 1988. Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors." IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Meshkat, Ahmed, "Using DSPs Induction Motor Drives." Control Engineering, February 1988. Panahi, Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. Phillips, Nagle, Digital Control System Analysis Design, Englewood Cliffs, Prentice-Hall, Inc., 1984.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance." Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen." Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010." Digital Signal Processing Applications, 1986.
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25." Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder." Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020." Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020." Proceedings IEEE
Read This First
xiii
Related Articles Books
International Conference Acoustics, Speech Signal Processing, USA, 1986.
Lovrich, Reimer, Multi-Rate Transcoder." Transactions Consumer Electronics, USA, November 1989. Lovrich, Reimer, Multi-Rate Transcoder." Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989. Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25." Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987. Mock, "Add DTMF Generation Decoding DSP- Designs." Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip." Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor." Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Automotive:
Lin, "Trends Digital Signal Processing Automotive." International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product." Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product." Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC." Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis." Proceedings ICASSP USA, Volume page 2493, April 1988.
Related Articles Books
Morris, L.R., P.B. Barszczewski, "Design Evolution Pocket-Sized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications." Proceedings ICASSP USA, Volume page 2516, April 1988.
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320." MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Read This First
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Contents
Contents
Introduction Introduces TMS320 family TMS320C4x TMS320C4x Devices 1.1.1 TMS320C40 1.1.2 TMS320C44 Features TMS320C4x TMS320C40 TMS320C44 Device Comparison
Architectural Overview Briefly describes architecture CPU, buses, interrupts, peripherals 'C4x Central Processing Unit (CPU) 2.1.1 Floating-Point/Integer Multiplier 2.1.2 Arithmetic Logic Unit (ALU) Internal Buses 2.1.3 Auxiliary Register Arithmetic Units (ARAUs) 2.1.4 Primary Register File 2.1.5 Expansion Register File 2-10 Memory Organization 2-11 2.2.1 RAM, ROM, Cache 2-11 2.2.2 Memory Maps 2-13 2.2.3 Memory Aliasing ('C44 only) 2-17 2.2.4 Memory Addressing Modes 2-18 Internal Operation 2-19 External Operation 2-20 Interrupts 2-21 Peripherals 2-22 2.6.1 Communication Ports 2-23 2.6.2 Direct Memory Access (DMA) Coprocessor 2-23 2.6.3 Timers 2-24
xvii
Contents
Registers Lists describes contents primary register file expansion register file Primary Register File 3.1.1 Extended-Precision Registers (R0-R11) 3.1.2 Auxiliary Registers (AR0-AR7) 3.1.3 Data-Page Pointer (DP) 3.1.4 Index Registers (IR0, IR1) 3.1.5 Block-Size Register (BK) 3.1.6 System Stack Pointer (SP) 3.1.7 Status Register (ST) 3.1.8 Coprocessor Interrupt Enable Register (DIE) 3.1.9 Internal Interrupt Enable Register (IIE) 3-11 3.1.10 IIOF Flag Register (IIF) 3-13 3.1.11 Block-Repeat (RS, Repeat-Count (RC) Registers 3-16 3.1.12 Program Counter (PC) 3-16 3.1.13 Reserved Bits Compatibility 3-16 Expansion Register File 3-17
Memory Instruction Cache Describes structure memory architecture instruction cache Memory Peripheral Memory 4.2.1 Local Global Memory Interface Control Registers 4.2.2 Analysis Module Registers 4.2.3 Timer Registers 4.2.4 Communication Port Memory 4.2.5 Coprocessor Registers Instruction Cache 4-10 4.3.1 Instruction Cache Architecture 4-10 4.3.2 Cache Control Bits 4-12 4.3.3 Using Cache 4-13 4.3.4 Cache Algorithm 4-14
Data Formats Floating-Point Operation Describes integer floating-point data formats discusses some mathematical operations performed floating-point numbers Signed-Integer Formats 5.1.1 Short Integer Format 5.1.2 Single-Precision Integer Format Unsigned-Integer Formats 5.2.1 Short Unsigned-Integer Format 5.2.2 Single-Precision Unsigned-Integer Format
xviii
Contents
Floating-Point Formats 5.3.1 Short Floating-Point Format 5.3.2 Single-Precision Floating-Point Format 5.3.3 Extended-Precision Floating-Point Format 5.3.4 Determining Decimal Equivalent Floating-Point Number 5.3.5 Conversion Between Floating-Point Formats 5-11 Floating-Point Conversion (IEEE Std. 754) 5-13 5.4.1 Converting IEEE Format Twos-Complement 'C4x Floating-Point Format 5-14 5.4.2 Converting Twos-Complement 'C4x Floating-Point Format IEEE Format 5-17 Floating-Point Multiplication 5-19 Floating-Point Addition Subtraction 5-23 Normalization (NORM Instruction) 5-27 Rounding (RND Instruction) 5-29 Floating-Point-to-Integer Conversion (FIX Instruction) 5-31 5.10 Integer-to-Floating-Point Conversion (FLOAT Instruction) 5-33 5.11 Reciprocal (RCPF Instruction) 5-34 5.11.1 Reciprocal Algorithm 5-35 5.12 Reciprocal Square Root (RSQRF Instruction) 5-36 Newton-Raphson Algorithm 5-37 Addressing Modes Describes addressing modes, using address registers, stack managements 'C4x Addressing Types Register Addressing Direct Addressing Indirect Addressing Immediate Addressing 6-18 PC-Relative Addressing 6-19 Encoding Addressing Modes 6-21 6.7.1 General Addressing Modes 6-21 6.7.2 Three-Operand Addressing Modes 6-22 6.7.3 Parallel Addressing Modes 6-24 6.7.4 Conditional-Branch Addressing Modes 6-25 Circular Addressing 6-27 Bit-Reversed Addressing 6-32 Program Flow Control Describes software hardware features that control program flows Repeat Mode 7.1.1 Control Bits 7.1.2 Repeat-Mode Operation 7.1.3 RPTB RPTBD Instructions 7.1.4 RPTS Instruction 7.1.5 Repeat Mode Restriction Rules 7.1.6 Register Value After Repeat Mode Completes 7.1.7 Nesting Block Repeats
Contents
Contents
Delayed Branches 7.2.1 Delayed Branches Without Annulling 7-10 7.2.2 Delayed Branches With Annulling 7-11 Calls, Traps, Branches, Jumps, Returns 7-12 Interrupts 7-15 7.4.1 Interrupt Vector Table Prioritization 7-15 7.4.2 Interrupt Control Bits 7-17 7.4.3 Interrupt Processing 7-18 7.4.4 Interrupt Latency 7-20 7.4.5 External Interrupts 7-21 Traps 7-24 7.5.1 Initialization Traps Interrupts 7-24 7.5.2 Operation Traps 7-24 7.5.3 Overlapping Trap Interrupt Vector Tables 7-25 Interrupts 7-26 7.6.1 Interrupt Control Bits 7-26 7.6.2 Interrupt Processing 7-27 7.6.3 CPU/DMA Interrupt Interaction 7-28 Reset 7-29 7.7.1 Reset's Effects States 7-29 7.7.2 Reset Vector Location 7-35 7.7.3 Additional Reset Operations 7-35
Pipeline Operation Describes explains operation four pipeline stages 'C4x Pipeline Structure Pipeline Conflicts 8.2.1 Branch Conflicts 8.2.2 Register Conflicts 8.2.3 Memory Conflicts 8-10 Memory Accesses Maximum Performance 8-17 Clocking Memory Accesses 8-19 8.4.1 Program Fetches 8-19 8.4.2 Data Loads Stores 8-20
External Operation Describes features functions 'C4x external buses Overview Memory Interface Signals Memory-Interface Control Registers 9.3.1 Mapping Addresses Strobes 9-12 9.3.2 Page Size Operation 9-13 Programmable Wait States 9-14 Memory Interface Timing 9-16
Contents
Using Enable Signals Control Signal Groups Interlocked Operations 9.7.1 LDFI LDII 9.7.2 STFI STII 9.7.3 SIGI 9.7.4 Interlocked Examples 9.7.5 Bus-Lock Pins Timing IACK Timing
9-38 9-39 9-40 9-40 9-41 9-41 9-44 9-49
Bootloader 10-1 Describes 'C4x bootloader operation also lists bootloader code 10.1 10.2 10.3 10.4 10.5 10.6 10.7 Bootloader Description 10-2 Mode Selection 10-3 Bootloading Sequence 10-5 Bootloading from External Memory (Examples) 10-10 Bootloading from Communication Port (Examples) 10-16 Modifying IIOFx Pins After Bootloading 10-19 Bootloader Program 10-20
Coprocessor 11-1 Describes discusses operation 'C4x coprocessor 11.1 11.2 11.3 Introduction 11-2 Functional Description 11-3 11.2.1 Basic Operation 11-5 Registers 11-7 11.3.1 Control Register 11-7 11.3.2 Address Index Registers 11-15 11.3.3 Transfer Counter Auxiliary Transfer Counter Registers 11-16 11.3.4 Link Pointer Auxiliary Link-Pointer Registers 11-17 Unified Mode 11-19 Split Mode 11-20 Internal Priority Schemes 11-22 11.6.1 Fixed Priority Scheme 11-22 11.6.2 Rotating Priority Scheme 11-22 11.6.3 Split Mode Channel Arbitration 11-24 Coprocessor Arbitration 11-27 Data Transfer Modes 11-28 11.8.1 Running TRANSFER MODE 11-28 11.8.2 Running TRANSFER MODE 11-29 11.8.3 Running TRANSFER MODE (Autoinitialization 11-29 11.8.4 Running TRANSFER MODE (Autoinitialization 11-31
11.4 11.5 11.6
11.7 11.8
Contents
Contents
Autoinitialization 11.9.1 Unified Mode 11.9.2 Split Mode 11.9.3 Incrementing Link Pointer 11.9.4 Synchronization 11.9.5 Effect Control Register Bits 11.9.6 Consecutive Autoinitializations 11.10 Interrupts 11.10.1 Interrupts Synchronization Channels 11.10.2 Synchronization Mode Bits 11.11 Memory Transfer Timing 11.11.1 Single Memory Transfer Timing 11.11.2 Transfer Rate Synchronization Mode
11.9
11-34 11-35 11-35 11-36 11-37 11-38 11-40 11-42 11-43 11-46 11-51 11-51 11-55
Communication Ports 12-1 Describes provides tips using communication ports 12.1 12.2 Features 12-2 Operational Overview 12-3 12.2.1 Token Transfer Operation 12-5 12.2.2 Data Transfer Operation 12-6 12.3 Memory Registers 12-7 12.3.1 Communication-Port Control Register (CPCR) 12-8 12.3.2 Input-Port Register 12-9 12.3.3 Output-Port Register 12-9 12.3.4 Communication-Port Software Reset Register 12-10 12.4 Port Arbitration Units (PAUs) 12-11 12.5 Halting Input Output FIFOs 12-14 12.5.1 Input FIFO Halt Operation 12-15 12.5.2 Output FIFO Halt Operation 12-15 12.6 Coordinating Communication Ports With Coprocessor 12-17 12.7 Token Transfer Operation 12-19 12.8 Word Transfer Operation 12-22 CSTRB Width Restrictions 12-25 12.9 Synchronizers 12-26 12.10 Module Reset 12-29 12.11 Tips Using Communication Ports 12-32
Timers 13-1 Describes discusses operation 'C4x on-chip timers 13.1 13.2 Overview Timers 13-2 Timer Pins 13-4
xxii
Contents
13.3
13.4 13.5
13.6
13.7 13.8
Timer Control Registers 13-5 13.3.1 Timer Control Register 13-6 13.3.2 Timer Period Register 13-7 13.3.3 Timer Counter Register 13-8 13.3.4 Boundary Conditions Control Registers 13-8 Timer Pulse Generation 13-9 Timer Interrupts 13-11 13.5.1 Timer Interrupts Their Vectors 13-11 13.5.2 Timer Interrupt Operation 13-11 13.5.3 Considerations When Using Timer Interrupt 13-12 Selecting CLKSRC FUNC Values 13-13 13.6.1 CLKSRC FUNC 13-13 13.6.2 CLKSRC=1 FUNC=1 13-13 13.6.3 CLKSRC FUNC 13-14 13.6.4 CLKSRC FUNC 13-14 Using TCLKx General-Purpose Pins 13-15 Configuring Timer 13-16
Assembly Language Instructions 14-1 Lists entire instruction 'C4x 14.1 Instruction 14-2 14.1.1 Load-and-Store Instructions 14-2 14.1.2 Two-Operand Instructions 14-4 14.1.3 Three-Operand Instructions 14-6 14.1.4 Program Control Instructions 14-7 14.1.5 Interlocked Operations Instructions 14-8 14.1.6 Parallel Operations Instructions 14-9 14.1.7 Illegal Instructions 14-11 Condition Codes Flags 14-12 Individual Instruction Descriptions 14-16 14.3.1 Symbols Abbreviations 14-16 14.3.2 Optional Assembler Syntaxes 14-18 14.3.3 Individual Instruction Descriptions 14-20
14.2 14.3
Glossary
Contents
xxiii
Figures
Figures
5-10 5-11 TMS320C4x Block Diagram Central Processing Unit (CPU) Memory Organization 2-12 'C40 Memory 2-14 'C44 Memory 2-15 Peripheral Memory 2-16 Memory Aliasing ('C44 only) 2-17 Peripheral Modules 2-22 Extended-Precision Register Floating-Point Format Extended-Precision Register Integer Format Status Register (ST) Interrupt Enable Register Functions Unified Mode Interrupt Enable Register Functions Split Mode 3-10 Internal Interrupt Enable Register (IIE) 3-12 Interrupt Flag Register (IIF) 3-14 'C40 Memory 'C44 Memory Peripheral Memory Memory Interface Control Registers Timer Registers Communication Port Memory Coprocessor Memory Address Partitioning Cache Control Algorithm 4-10 Instruction Cache Architecture 4-11 Short-Integer Format Sign Extension Short Integer Single-Precision Integer Format Short Unsigned-Integer Format Zero Fill Single-Precision Unsigned-Integer Format General Floating-Point Format Short Floating-Point Format Single-Precision Floating-Point Format Extended-Precision Floating-Point Format Short Floating-Point Format Conversion Single-Precision Floating-Point Format 5-11 Short Floating-Point Format Conversion Extended-Precision Floating-Point Format 5-11 Single-Precision Floating-Point Format Conversion Extended-Precision Floating-Point Format 5-12
xxiv
Figures
5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 6-10 6-11 6-12
Extended-Precision Floating-Point Format Conversion Single-Precision Floating-Point Format 5-12 IEEE Single-Precision Std. Floating-Point Format 5-13 'C4x Single-Precision Twos-Complement Floating-Point Format 5-13 Flowchart Floating-Point Multiplication 5-20 Flowchart Floating-Point Addition 5-24 Flowchart NORM Instruction Operation 5-27 Flowchart Floating-Point Rounding Instruction 5-30 Flowchart Floating-Point-to-Integer Conversion Instruction 5-32 Flowchart Integer-to-Floating-Point Conversion FLOAT Instructions 5-33 RCPF Instruction Algorithm 5-34 RSQRF Instruction Algorithm 5-37 Direct Addressing Indirect Addressing Operand Encoding Encoding 24-Bit PC-Relative Addressing Mode 6-20 Encoding General Addressing Modes 6-22 Encoding Type Three-Operand Addressing Modes ('C3x 'C4x) 6-24 Encoding Type Three-Operand Addressing Modes ('C4x Only) 6-24 Encoding Parallel Multiply With ADD/SUB 6-24 Encoding Conditional-Branch Addressing Modes 6-26 Register Relationships Circular Addressing 6-28 Circular Buffer Implementation 6-29 Circular Addressing Example 6-30 Data Structure Filters 6-31 CALL Response Timing 7-14 Interrupt-Vector Table (IVT) 7-16 Register Modification 7-18 Interrupt Processing 7-19 Flow Traps 7-24 Trap Vector Table (TVT) 7-25 Interrupt Processing 7-27 Parallel Interrupt Processing 7-28 Pipeline Structure Two-Operand Instruction Word 8-20 Three-Operand Instruction Word 8-20 Multiply Operation With Parallel Store 8-21 Parallel Stores 8-22 Parallel Multiplies Adds 8-23 Global Local Memory Interface Control Signals Location Memory-Interface Control Registers Fields Memory-Interface Control Registers Effects STRB ACTIVE Global Memory Memory 9-12 STRBx PAGESIZE Fields Example 9-13 STRB Timing 9-16
Contents
Figures
9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9
xxvi
Read Same Page, Read Same Page, Write Same Page Sequence 9-18 Write Same Page, Write Same Page, Read Same Page Sequence 9-19 Read Same Page, Read Different Page, Read Same Page Sequence 9-20 Write Same Page, Write Different Page, Write Same Page Sequence 9-21 Write Same Page, Read Different Page, Write Different Page Sequence 9-22 Read Different Page, Read Different Page, Write Same Page Sequence 9-23 Write Different Page, Write Different Page, Read Same Page Sequence 9-24 Read Same Page, Write Different Page, Read Different Page Sequence 9-25 Read Same Page, Idle Cycle, Read Same Page Sequence 9-26 Write Same Page, Idle Cycle, Write Different Page Sequence 9-27 Idle, Read Different Page, Idle Sequence 9-28 Idle, Write Same Page, Idle Sequence 9-29 Write Different Same Page, Idle, Idle Sequence 9-30 Read Same Page STRB1, STRB0, STRB1 Sequence When STRB SWITCH 9-31 Read Same Page STRB1, STRB0, Read Different Page STRB1 Sequence When STRB SWITCH 9-32 Read Same Page STRB1, STRB0, STRB1 Sequence When STRB SWITCH 9-33 Read Same Page STRB1, STRB0, Read Different Page STRB1 Sequence When STRB SWITCH 9-34 Write Same Page STRB1, STRB0, Read Same Page STRB1 Sequence 9-35 Read With Wait State 9-36 Write With Wait State 9-37 Using Enable Signals Signal Groups High-Impedance State 9-38 Multiple 'C4x Devices Sharing Global Memory 9-42 LDII LDFI External Access 9-45 LDII LDFI STII STFI External Access 9-46 SIGI External Access Timing 9-47 SIGI When LOCK Already 9-48 IACK Timing 9-50 Mode Selection Flow 10-4 Memory Load Flow 10-6 Communication-Port Load Mode Flow 10-7 Circuit Generation IIOF Signal Bootloader Selection 10-19 Coprocessor Memory 11-4 Channel Control Register 11-8 Coprocessor Address Generation 11-16 Transfer Counter Registers 11-17 Link Pointer Registers 11-18 Typical Unified-Mode Channel Configuration 11-19 Typical Split-Mode Configuration 11-21 Rotating Priority Mode Example Coprocessor 11-23 Rotating Priority Read Write Sequence Example (Unified Mode) 11-23
Figures
11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14
Example Priority Wheel 11-24 Example Channel Priority Scheme Split Mode 11-25 Service Sequence Split Mode Priority Example 11-26 Channel Running Transfer Mode (Autoinitialization Method 11-29 Channel Running Transfer Mode (Autoinitialization Method 11-30 Channel Running Transfer Mode (Autoinitialization Method 11-31 Channel Running Transfer Mode (Autoinitialization Method 11-33 Store Values Channel Registers Memory (SPLIT MODE 11-35 Store Values Channel Registers Memory (SPLIT MODE Transfer Counter 11-36 Store Values Channel Registers Memory (SPLIT MODE Auxiliary Transfer Counter 11-36 Channel Control Register Bits Modifiable Autoinitialization Unified Mode 11-39 Channel Control Register Modifiable Autoinitialization Primary Channel Split Mode 11-40 Channel Control Register Bits That Modified Autoinitialization Auxiliary Channel Split Mode 11-40 Self-Referential Link Pointer 11-41 Referring Link Pointer 11-41 Register Functions Unified Mode 11-44 Register Functions Split Mode 11-45 Synchronization 11-47 Source Synchronization 11-48 Destination Synchronization 11-49 Unified Mode Source Destination Synchronization 11-50 Timing Number Cycles Transfers On-Chip Destination 11-52 Timing Number Cycles Transfers Local-Bus Destination 11-53 Timing Number Cycles Transfers Global-Bus Destination 11-54 Unified-Mode Timing Different Synchronizations 11-55 Split-Mode Timing Different Synchronizations 11-56 Communication Port Block Diagram 12-4 'C4x Communication-Port Interface-Connection Example 12-5 Communication-Port Memory 12-7 Communication-Port Control Register (CPCR) 12-8 Communication-Port Arbitration-Unit State Diagram 12-12 Token Transfer Operation 12-20 Word Transfer Operation 12-23 Type-One Synchronizer Minimum Delay 12-26 Type-One Synchronizer Maximum Delay 12-26 Type-Two Synchronizer Minimum Delay 12-27 Type-Two Synchronizer Maximum Delay 12-27 Type-Three Synchronizer Minimum Delay 12-27 Type-Three Synchronizer Maximum Delay 12-28 Post-Reset State Output Port 12-30
Contents
xxvii
Figures
12-15 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 14-1
Post-Reset State Input Port 12-31 Timer Block Diagram 13-3 Memory-Mapped Timer Locations 13-5 Timer Control Register 13-6 Timer Pulse Mode Clock Mode Timing 13-9 Timer Output Generation Examples 13-10 Timer Configuration With CLKSRC=1 FUNC=0 13-13 Timer Configuration With CLKSRC FUNC 13-13 Timer Configuration With CLKSRC FUNC 13-14 Timer Configuration With CLKSRC FUNC 13-14 TCLK Input (I/O 13-15 TCLK Output (I/O 13-15 Status Register 14-13
xxviii
Tables
Tables
10-1 10-2 10-3 10-4 10-5 11-1 11-2 Comparison 'C40 'C44 Features Primary Registers Primary Register File Summary Bits Channels (DMA0 DMA1) Unified Mode Synchronization Interrupts Channels (DMA2 DMA5) Unified Mode Synchronization Interrupts Channels (DMA0 DMA1) Split-Mode Synchronization Interrupts 3-10 Channels (DMA2 DMA5) Split-Mode Synchronization Interrupts 3-11 Expansion Registers 3-17 Combined Effect Bits 4-13 Converting IEEE Format Twos-Complement Floating-Point Format 5-14 Converting Twos-Complement Floating-Point Format IEEE Format 5-17 Register/Assembler Syntax Function Indirect Addressing Three-Operand Instruction Addressing Modes 6-22 Index Steps Bit-Reversed Addressing 6-33 Repeat-Mode Registers Interrupt Latency 7-21 States System Reset 7-29 RESET Vector Locations 7-35 Program Fetch Data Access Maximum Performance 8-17 Program Fetch Data Accesses Maximum Performance 8-18 Global Memory Interface Signals Global Memory Port Status STRB0 STRB1 Accesses Page Size Defined STRB0/1 PAGESIZE Bits Address Ranges Specified STRB ACTIVE Bits 9-10 Address Ranges Specified LSTRB ACTIVE Bits 9-11 Wait-State Generation Each Value 9-15 Interlocked Operations 9-39 Bootloader Mode Selection Using Pins IIOF(3-0) 10-3 Structure Source Program Data Stream 10-8 Byte-Wide Configured Memory 10-11 16-Bit Wide Configured Memory 10-14 32-Bit Wide Configured Memory 10-15 Bits CPU/DMA Arbitration Rules 11-12 TRANSFER MODE (AUX TRANSFER MODE) Field Descriptions 11-12
Contents
xxix
Tables
11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 12-1 12-2 12-3 12-4 12-5 12-6 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10
SYNC MODE Field Descriptions Unified Mode 11-13 SYNC MODE Field Descriptions Split Mode 11-13 START (AUX START) Field Descriptions 11-14 STATUS (AUX STATUS) Field Descriptions 11-14 Bits CPU/DMA Arbitration Rules 11-27 TRANSFER MODE (AUX TRANSFER MODE) Field Descriptions 11-28 Effect SYNC MODE AUTOINIT MODE Bits Autoinitialization 11-38 Channels (DMA0 DMA1) Unified-Mode Synchronization Interrupts 11-44 Channels (DMA2 DMA5) Unified-Mode Synchronization Interrupts 11-45 Channels (DMA0 DMA1) Split-Mode Synchronization Interrupts 11-46 Channels (DMA2 DMA5) Split-Mode Synchronization Interrupts 11-46 Communication-Port Software Reset Address ('C44 'C40 5.0) 12-10 State Definitions 12-11 Summary Input Output FIFO Halting 12-14 Token Transfer Sequence 12-21 Word Transfer Sequence 12-24 Communication-Port Signals Synchronizer Delays 12-28 Load-and-Store Instructions 14-3 Two-Operand Instructions 14-4 Three-Operand Instructions 14-6 Program Control Instructions 14-7 Interlocked Operations Instructions 14-8 Parallel Instructions 14-9 Output Value Formats 14-12 Condition Codes Flags 14-14 Instruction Symbols 14-17 Register Symbols 14-21
Examples
Examples
5-10 5-11 5-12 5-13 5-14 5-15 5-16 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 Enabling Cache 4-13 Positive Number Negative Number 5-10 Fractional Number 5-10 IEEE 'C4x Conversion Within Block Memory Transfer 5-16 'C4x IEEE Conversion Within Block Memory Transfer 5-18 Floating-Point Multiply (Both Mantissas -2.0) 5-21 Floating-Point Multiply (Both Mantissas 1.5) 5-21 Floating-Point Multiply (Both Mantissas 1.0) 5-22 Floating-Point Multiply Between Positive Negative Numbers 5-22 Floating-Point Addition 5-25 Floating-Point Subtraction 5-25 Floating-Point Addition With 32-Bit Shift 5-26 Floating-Point Addition/Subtraction Zero 5-26 NORM Instruction 5-28 Newton-Raphson Algorithm Computing Reciprocal 5-35 Newton-Raphson Algorithm Computing Reciprocal Square Root 5-38 Direct Addressing Auxiliary Register Indirect Indirect With Predisplacement Indirect With Predisplacement Subtract 6-10 Indirect With Predisplacement Modify 6-10 Indirect With Predisplacement Subtract Modify 6-11 Indirect With Postdisplacement Modify 6-11 Indirect With Postdisplacement Subtract Modify 6-12 Indirect With Postdisplacement Circular Modify 6-12 Indirect With Postdisplacement Subtract Circular Modify 6-13 Indirect With Preindex 6-13 Indirect With Preindex Subtract 6-14 Indirect With Preindex Modify 6-14 Indirect With Preindex Subtract Modify 6-15 Indirect With Postindex Modify 6-15 Indirect With Postindex Subtract Modify 6-16 Indirect With Postindex Circular Modify 6-16 Indirect With Postindex Subtract Circular Modify 6-17 Indirect With Postindex Bit-Reversed Modify 6-17
Contents
xxxi
Examples
6-20 6-21 6-22 6-23 8-10 8-11 8-12 8-13 10-1 12-2 13-1
Immediate Addressing 6-18 PC-Relative Addressing 6-19 Filter Code Using Circular Addressing 6-31 Bit-Reversed Addressing Example 6-32 Repeat-Mode Control Algorithm RPTB Operation Incorrectly Placed Standard Branch Incorrectly Placed Delayed Branch Pipeline Conflict RPTB Instruction Incorrectly Placed Delayed Branches 7-10 Delayed Branch Execution 7-10 Standard Branch Delayed Branch Without Annul Option Using BcondAF BcondAT Instructions Write Followed Address Generation Read Followed Address Generation Program Wait Until Data Access Completes 8-11 Program Wait Multicycle Access 8-12 Multicycle Program Memory Fetches 8-12 Single Store Followed Reads 8-13 Parallel Store Followed Single Read 8-14 Busy External Port 8-15 Multicycle Data Reads 8-16 Conditional Calls Traps 8-16 Busy-Waiting Loop 9-42 Task Counter Manipulation 9-42 Implementation V(S) 9-43 Implementation P(S) 9-43 Booting 'C4x Multiprocessor System 10-17 Communication Port Reset 12-10 Maximum Frequency Timer Clock Setup 13-16
xxxii
Chapter
Introduction
TMS320C4x devices 32-bit floating-point digital signal processors optimized parallel processing. 'C4x family combines high performance controller with communication ports meet needs multiprocessor I/O-intensive applications. 'C4x devices compatible with TI's multi-chip development environment. Each device contains on-chip analysis module, which supports hardware breakpoints parallelprocessing development debugging. 'C4x family source-code compatible with TMS320C3x family floating-point DSPs.
Topic
Page
TMS320C4x Devices Features TMS320C4x TMS320C40 TMS320C44 Device Comparison
Chapter Title-Attribute Reference
TMS320C4x Devices
TMS320C4x Devices
TMS320C4x family made three different members: TMS320C40 TMS320C44.
1.1.1
TMS320C40
TMS320C40 original member 'C4x family. features that deliver MIPS/60 MFLOPS with maximum bandwidth 384M bytes/s. 'C40 words on-chip RAM, words program cache bootloader. external buses provide address reach gigawords unified memory space. 'C40 available 325-pin CPGA package.
1.1.2
TMS320C44
TMS320C44 lower cost version 'C40, parallel processing applications that more price sensitive. 'C44 features four communication ports external address reach words over external buses. further reduce cost, 'C44 comes 304-pin PQFP package. TMS320C44 deliver MIPS/60 MFLOPS performance with maximum bandwidth 384M bytes/s. 'C44 source-code compatible with 'C40.
Features TMS320C4x
Features TMS320C4x
TMS320C4x several features:
MIPS/80 MFLOPS performance with 488-Mbytes/s capability
IEEE floating-point conversion ease Register-based Single-cycle byte half-word manipulation capabilities Divide square root support improved performance
On-chip memory includes words SRAM, words program
cache, bootloader
external buses providing address reach gigawords memory-mapped 32-bit timers channel communication ports multiprocessor communication Idle mode reduced power consumption
Introduction
TMS320C40 TMS320C44 Device Comparison
TMS320C40 TMS320C44 Device Comparison
Table shows major differences features 'C40 'C44.
Table 1-1. Comparison 'C40 'C44 Features
Feature External local address External global address Address reach Number comm ports Commport direction with grant feature Individual comm port reset Package 'C40 pins pins (for revisions 5.0) (for revisions 5.0) 325-pin CPGA 'C44 pins pins 304-pin PQFP
Running Title-Attribute Reference
Chapter
Architectural Overview
'C4x's high performance achieved through precision wide dynamic range floating-point units, on-chip memory, high degree parallelism, communication ports, coprocessor. This chapter gives architectural overview 'C4x processor. Figure block diagram 'C4x.
Topic
Page
Central Processing Unit (CPU) Memory Organization 2-11 Internal Operation 2-19 External Operation 2-20 Interrupts 2-21 Peripherals 2-22
Chapter Title-Attribute Reference
Block Diagram
Figure 2-1. TMS320C4x Block Diagram
Cache (512 bytes) PDATA D(31-0) 'C40: A(30-0) 'C44: A(23-0) STAT(3-0) LOCK STRB0,1 R/W0,1 PAGE0,1 RDY0,1 CE0,1 PADDR DDATA DADDR DADDR DMADATA DMAADDR X2/CLKIN CPU1 CPU2 REG1 REG2 block bytes) block bytes) block (reserved)
ROMEN RESET RESETLOC0-1 IIOF(3-0) IACK CVSS DVDD DVSS IVSS LADVDD LDDVDD VDDL VSSL SUBS
Multiplier
32-bit barrel shifter
Extended precision register (R0-R11) DISP, IR0, ARAU0 ARAU1
Auxiliary registers (AR0-AR7)
Other registers (14)
Continued next page
Block Diagram
Figure 2-1.TMS320C4x Block Diagram (Continued)
Continued from previous page
PDATA PADDR DDATA DADDR DADDR DMADATA DMAADDR LD(31-0) 'C40: LA(30-0) 'C44: LA(23-0) LSTAT(3-0) LLOCK LSTRB0,1 LR/W0,1 LPAGE0,1 LRDY0,1 LCE0,1
coprocessor channel channel channel channel channel channel Port Input FIFO Output FIFO Port control registers
CREQ0 CACK0 CSTRB0 CRDY0 CD0(7-0)
Timer Global control register Time period register Timer counter register Timer Global control register Time period register Timer counter register Port control Global Local Port Input FIFO Output FIFO Port control registers
'C40: communication ports (0,1,2,3,4,5) 'C44: communication ports (1,2,4,5)
Channels
CREQ5 CACK5 CSTRB5 CRDY5 CD5(7-0)
TCLK0
TCLK1
Architectural Overview
Central Processing Unit (CPU)
Central Processing Unit (CPU)
'C4x's register-based architecture. consists several components:
Floating-point/integer multiplier Arithmetic Logic Unit (ALU) 32-bit barrel shifter Internal buses (CPU1/CPU2 REG1/REG2) Auxiliary register arithmetic units (ARAUs) register file
Figure shows CPU's components.
2.1.1
Floating-Point/Integer Multiplier
multiplier performs single-cycle multiplications 32-bit integer 40-bit floating-point values. 'C4x implementation floating-point arithmetic allows floating-point operations fixed-point speeds 25-ns instruction cycle high degree parallelism. gain even higher throughput, parallel instructions perform multiply operation single cycle. When multiplier performs floating-point multiplication, inputs 40-bit floating-point numbers, result 40-bit floating-point number. When multiplier performs integer multiplication, input data bits yields either most-significant bits least-significant bits resulting 64-bit product. Chapter Data Formats Floating-Point Operation, detailed information data formats floating-point operation.
2.1.2
Arithmetic Logic Unit (ALU) Internal Buses
performs single-cycle operations 32-bit integer, 32-bit logical, 40-bit floating-point data, including single-cycle integer floating-point conversions. Results always maintained 32-bit integer 40-bit floating-point formats. barrel shifter used shift bits left right single cycle. Four internal buses, CPU1, CPU2, REG1, REG2, carry operands from memory operands from register file, thus allowing parallel multiplies adds/subtracts four integer floating-point operands single cycle.
Central Processing Unit (CPU)
Figure 2-2. Central Processing Unit (CPU)
DADDR1 DADDR2 DDATA CPU1 CPU2 REG1 Multiplier Extended precision register (R0-R11) DISP, IR0, ARAU0 Auxiliary Registers (AR0-AR7) ARAU1 REG2
32-bit barrel shifter
Other Registers (14)
Architectural Overview
Central Processing Unit (CPU)
2.1.3
Auxiliary Register Arithmetic Units (ARAUs)
auxiliary register arithmetic units (ARAU0 ARAU1) generate addresses single cycle. ARAUs operate parallel with multiplier ALU. They support addressing with displacements, index registers (IR0 IR1), circular bit-reversed addressing. Chapter Addressing Modes, description addressing modes.
2.1.4
Primary Register File
'C4x primary register file provides registers multiport register file that tightly coupled CPU. Table lists register names functions, followed section number page each description. primary register file registers operated upon multiplier used general-purpose registers. However, registers also have some special functions. example, extended-precision registers especially suited maintaining floating-point results. eight auxiliary registers support variety indirect addressing modes used general-purpose 32-bit integer logical registers. remaining registers provide system functions such addressing, stack management, processor status, interrupts, block repeat. Chapter Registers, detailed information about registers. Chapter Addressing Modes, information about register usage addressing. extended-precision registers (R0-R11) capable storing supporting operations 32-bit integer 40-bit floating-point numbers. instruction that assumes that operands floating-point numbers uses bits 39-0. operands either signed unsigned integers, only bits 31-0 used, bits 39-32 remain unchanged. This true shift operations. Chapter Data Formats Floating-Point Operation, extended-precision register formats floating-point integer numbers. 32-bit auxiliary registers (AR0-AR7) accessed modified auxiliary register arithmetic units (ARAUs). primary function auxiliary registers generation 32-bit addresses. They also used loop counters 32-bit general-purpose registers that modified multiplier ALU. Chapter Addressing Modes, detailed information examples auxiliary registers addressing.
Central Processing Unit (CPU)
Table 2-1. Primary Registers
Assembler Syntax Assigned Function Name Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Data-page pointer Index register Index register Block-size register System stack pointer Subsection 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.3 3.1.4 3.1.4 3.1.5 3.1.6 Page
Architectural Overview
Central Processing Unit (CPU)
Table 2-1. Primary Registers (Continued)
Assembler Syntax Assigned Function Name Status register Coprocessor interrupt enable Internal-interrupt enable register IIOF flag register Repeat start address Repeat address Repeat counter Subsection 3.1.7 3.1.8 3.1.9 3.1.10 3.1.11 3.1.11 3.1.11 Page 3-11 3-13 3-16 3-16 3-16
data page pointer (DP) 32-bit register. LSBs data page pointer used direct addressing mode pointer page data being addressed. 'C4x address pages, each page containing words. data page pointer described subsection 6.3, Direct Addressing, page 6-5. 32-bit index registers contain value used auxiliary register arithmetic unit (ARAU) compute indexed address. Section 6.4, Indirect Addressing, page 6-6, Section 6.9, Bit-Reversed Addressing, page 6-32, more information about ARAU. ARAU uses 32-bit block size register (BK) circular addressing specify data block size. Circular addressing described Section 6.8, Circular Addressing, page 6-27. system stack pointer (SP) 32-bit register that contains address system stack. always points last element pushed onto stack. push performs preincrement, performs postdecrement system stack pointer. manipulated interrupts, traps, calls, returns, PUSH/PUSHF POP/POPF instructions. Section 1.4, System User Stack Management, TMS320C4x General-Purpose Applications User's Guide information about managing stacks.
Central Processing Unit (CPU)
status register (ST) contains global information related state CPU. Typically, operations condition flags status register according whether result zero, negative, etc. This includes register load store operations well arithmetic logical functions. When status register loaded, however, bit-for-bit replacement performed with contents source operand, regardless state bits source operand. Therefore, following load, contents status register identically equal contents source operand. This allows status register easily saved restored. subsection 3.1.7, Status Register (ST), page 3-5, definitions status register bits. coprocessor interrupt enable register (DIE) 32-bit register containing 3-bit fields designate interrupt synchronization scheme each channels. allows each channel service corresponding input communication port output communication port. Also, each channel synchronized with external interrupts on-chip timers. This register described subsection 3.1.8, Coprocessor Interrupt Enable Register (DIE), page 3-8. internal interrupt enable register (IIE) 32-bit register that enables/disables interrupts communication ports, both timers, coprocessor channels. described subsection 3.1.9, Interrupt Enable Register (IIE), page 3-11. IIOF flag register (IIF) controls function (general-purpose interrupt) four external pins (IIOF0 IIOF3). also contains timer/DMA interrupt flags. Subsection 3.1.10, IIOF Flag Register (IIF), page 3-13, provides further description this register. 32-bit repeat counter (RC) register specifies number times block code repeated when block repeat performed. When processor operating repeat mode, 32-bit repeat start address register (RS) contains starting address block program memory repeated, 32-bit repeat address register (RE) contains ending address block repeated. Further information about these registers subsection 3.1.11, Block Repear (RS,RE) Repeat Count (RC) Registers, page 3-16. program counter (PC) 32-bit register containing address next instruction fetched. Although part register file, register that modified instructions that modify program flow.
Architectural Overview
Central Processing Unit (CPU)
2.1.5
Expansion Register File
Besides primary register file, expansion register file contains special registers that pointers:
IVTP register points interrupt-vector table (IVT), which defines
vectors interrupts.
TVTP register points trap vector table (TVT), which defines vec-
tors traps. These registers fully described Section 3.2, Expansion Register File page 3-17.
2-10
Memory Organization
Memory Organization
total memory reach 'C4x 32-bit words. Program memory (onchip external memory) well registers affecting timers, communication ports, channels contained within this space. This allows tables, coefficients, program code, data stored either ROM. Thus, memory usage maximized, memory space allocated desired. manipulating external (ROMEN), configure first onemegaword area memory (0000 0000h 000F FFFFh) address local address address on-chip when bootloader (with remaining space reserved). This capability further discussed Section 4.1, Memory Map, page 4-2.
2.2.1
RAM, ROM, Cache
Figure shows memory organized 'C4x. blocks bytes bits) each. block reserved contains bootloader. Each block capable supporting accesses single cycle. separate program buses, data buses, buses allow parallel program fetches, data reads writes, operations. example: access data values block perform external program fetch parallel with coprocessor loading another block, within single cycle. reserved block (upper right Figure 2-3) contains bootloader. This loader supports loading program data reset time. Loading from 16-, 32-bit wide memories communication ports. Chapter Bootloader, explains bootloader detail. 32-bit instruction cache provided store often-repeated sections code, thus greatly reducing number needed off-chip accesses. This allows code stored off-chip slower, lower-cost memories. using cache execute your program, external buses freed controller CPU. further information about memory instruction cache, Section 4.1, Memory Organization, Section 4.3, Cache Memory.
Architectural Overview
2-11
Memory Organization
Figure 2-3. Memory Organization
Cache (128 (512 bytes) block bytes) block bytes) block (bootloader) (reserved)
PDATA D(31-0) 'C40: A(30-0) 'C44: A(23-0) STAT(3-0) LOCK STRBx R/Wx PAGEx RDYx PADDR DDATA DADDR1 DADDR2 DMADATA DMAADDR LD(31-0) 'C40: LA(30-0) 'C44: LA(23-0) LSTAT(3-0) LLOCK LSTRBx LR/Wx LPAGEx LRDYx LCEx
Program counter/ instruction register coprocessor
2-12
Memory Organization
2.2.2
Memory Maps
memory each processor shown Figure ('C40) Figure ('C44); each processor, level external ROMEN determines whether first megaword memory addresses internal external memory. maps illustrate entire address space 'C40 'C44. value ROMEN affects only first megaword memory:
external ROMEN causes internal enabled 0000h
with one-megaword space reserved (0000 0000h 000F FFFFh). This shown right side figure.
ROMEN causes addresses 0000 0000h 000F FFFFh acces-
sible local bus. This shown left side figure. rest memory same either level ROMEN:
second megaword memory devoted peripherals shown
Figure 2-6).
third megaword memory contains 1K-word (4K-byte) blocks
(BLK0 BLK1 shown 002F F800h 002F FFFFh).
rest first gigawords (0030 0000h 7FFF FFFFh)
(external).
second gigawords (8000 0000h FFFF FFFFh) global
(external). Section 4.1, Memory Map, page describes memory maps greater detail. Section 9.2, Memory Interface Signals page 9-3, Section 9.3, Memory Interface Control Registers page 9-6, discuss local global interfaces memory. peripheral vector locations reset, interrupts, traps also explained those sections.
Caution access reserved area address space produces unpredictable results. attempt access reserved areas.
Architectural Overview
2-13
Memory Organization
Figure 2-4. 'C40 Memory
Structure depends upon ROMEN 00000 0000h Accessible local (external) 00000 0FFFh 00000 1000h Bootloader (Internal) Reserved Peripherals (internal) (see Figure 2-6) Reserved 0001F FFFFh 00020 0000h Reserved (internal) (internal) 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h Reserved (internal) (internal) 0000F FFFFh 00010 0000h 00010 00FFh 00010 0100h Peripherals (internal) (see Figure 2-6) Reserved
Structure identical
2G-3M
Local (external)
Local (external)
07FFF FFFFh 08000 0000h
Global (external)
Global (external)
0FFFF FFFFh Internal disabled (ROMEN Microprocessor mode Internal enabled (ROMEN Microcomputer mode
2-14
Memory Organization
Figure 2-5. 'C44 Memory
Structure depends upon ROMEN 00000 0000h Accessible local (external) 00000 0FFFh 00000 1000h Bootloader (internal) Reserved 0000F FFFFh 00010 0000h 00010 00FFh 00010 0100h 0001F FFFFh 00020 0000h Reserved (internal) (internal) Local (external) 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h Reserved (internal) (internal) Local (external) Peripherals (internal) (see Figure 2-6) Reserved
Peripherals (internal) (see Figure 2-6) Reserved
Structure identical
2G-16M
Local (alias region) (see section 2.2.3) 07FFF FFFFh 08000 0000h
Local (alias region)
Global (external)
Global (external)
Global (alias region) (see section 2.2.3)
Global (alias region)
0FFFF FFFFh Internal disabled (ROMEN Microprocessor mode Internal enabled (ROMEN Microcomputer mode
Architectural Overview
2-15
Memory Organization
Figure 2-6. Peripheral Memory
Address 0010 0000h 0010 000Fh
Peripheral Local global port control words)
Described Subsection 4.2.1, Figure 4-4, page Subsection 4.2.2.
0010 0010h 0010 001Fh 0010 0020h 0010 002Fh 0010 0030h 0010 003Fh 0010 0040h 0010 004Fh 0010 0050h 0010 005Fh 0010 0060h 0010 006Fh 0010 0070h 0010 007Fh 0010 0080h 0010 008Fh 0010 0090h 0010 009Fh 0010 00A0h 0010 00AFh 0010 00B0h 0010 00BFh 0010 00C0h 0010 00CFh 0010 00D0h 0010 00DFh 0010 00E0h 0010 00EFh 0010 00F0h 0010 00FFh
Analysis block registers words)
Timer registers words) Timer registers words)
Subsection 4.2.3, Figure 4-5, page
Communication port words) ('C40 only) Communication port words) Communication port words) Communication port words) ('C40 only) Communication port words) Communication port words)
Subsection 4.2.4, Figure 4-6, page
coprocessor channel words) coprocessor channel words) coprocessor channel words) coprocessor channel words) coprocessor channel words) coprocessor channel words)
Subsection 4.2.5, Figure 4-7, page
2-16
Memory Organization
2.2.3
Memory Aliasing ('C44 only)
Memory aliasing occurs 'C44, since both global local ports that device have pins, instead pins each port 'C40. Memory aliasing causes first each address space repeated memory map. Memory local occupies, aliased, first address space, memory global occupies, aliased, second address space. Figure shows alias regions local global buses.
Figure 2-7. Memory Aliasing ('C44 only)
Local 0x0000 0000 Base address region 0x00FF FFFF 0x0100 0000 Alias 0x01FF FFFF 0x0200 0000 Alias 0x02FF FFFF 0x82FF FFFF 0x81FF FFFF 0x8200 0000 Alias 0x80FF FFFF 0x8100 0000 Alias 0x8000 0000 Base address region Global
0x7F00 0000 Alias 0x7FFFFFFF
0xFF00 0000 Alias 0xFFFFFFFF
Architectural Overview
2-17
Memory Organization
2.2.4
Memory Addressing Modes
'C4x supports base general-purpose instructions well arithmetic-intensive instructions that particularly suited digital signal processing other numeric-intensive applications. Refer Chapter Addressing Modes, detailed information addressing. Four groups addressing modes provided 'C4x. Each group uses more several different addressing types. following list shows addressing modes with their addressing types.
General addressing modes:
Register. operand register. Immediate. operand 16-bit immediate value. Direct. operand contents 32-bit address (concatenation bits data page pointer 16-bit operand). Indirect. 32-bit auxiliary register indicates address operand.
Three-operand addressing modes:
Register. (same general addressing mode). Indirect. (same general addressing mode). Immediate. operand 8-bit immediate value.
Parallel addressing modes:
Register. operand extended-precision register. Indirect. (same general addressing mode).
Branch addressing modes:
Register. (same general addressing mode). PC-relative. signed 16-bit displacement 24-bit displacement added
2-18
Internal Operation
Internal Operation
large portion 'C4x's high performance internal busing parallelism. Separate buses allow parallel program fetches, data accesses, accesses:
Program buses PADDR PDATA Data buses DADDR1, DADDR2, DDATA buses DMAADDR DMADATA
These buses connect physical spaces (on-chip memory, off-chip memory, on-chip peripherals) supported 'C4x. Figure shows these internal buses their connections on-chip off-chip memory blocks. program counter (PC) connected 32-bit program address (PADDR). instruction register (IR) connected 32-bit program data (PDATA). this configuration, buses fetch single instruction word every machine cycle. 32-bit data address buses (DADDR1 DADDR2) 32-bit data data (DDATA) support data memory accesses every machine cycle. DDATA carries data over CPU1 CPU2 buses. CPU1 CPU2 buses carry data memory operands multiplier, ALU, register file every machine cycle. Also internal register buses REG1 REG2, which carry data values from register file multiplier every machine cycle. Figure shows buses that internal section processor. controller supported with 32-bit address (DMAADDR) 32-bit data (DMADATA). These buses allow perform memory accesses parallel with memory accesses occurring from data program buses.
Architectural Overview
2-19
External Operation
External Operation
'C4x provides identical external interfaces: global memory interface local memory interface. Each consists 32-bit data bus, 31-bit ('C40) 24-bit ('C44) address bus, sets control signals. Both buses used address external program/data memory space. buses also have external signals wait-state generation with wait states inserted under software control. Chapter External Operation, covers external operation. multiple processors access global memory share data coherent manner, arbitration necessary. This arbitration (handshaking) purpose 'C4x's interlocked operations, handled through interlocked instructions. more information about interlocked instructions, Section page 9-39, Interlocked Operations.
2-20
Interrupts
Interrupts
'C4x supports four external interrupts (IIOF3-0), number internal interrupts, nonmaskable external interrupt, nonmaskable external RESET signal, which sets processor known state. communication ports have their internal interrupts. When responds interrupt, IACK used signal external interrupt acknowledge. Section 7.4, page 7-15, Interrupts, covers RESET interrupt processing.
Architectural Overview
2-21
Peripherals
Peripherals
'C4x on-chip peripherals controlled through memory-mapped registers dedicated peripheral bus. This peripheral composed 32-bit data 32-bit address bus. This peripheral permits straightforward communication peripherals. 'C4x peripherals include timers ('C40) four ('C44) communication ports. Figure shows peripherals with associated buses signals.
Figure 2-8. Peripheral Modules
PDATA PADDR DDATA DADDR DADDR DMADATA DMAADDR
Port Controller channel channel channel channel channel channel Port control registers Input FIFO Output FIFO CREQ0 CACK0 CSTRB0 CRDY0 CD0(7-0) 'C40: communication ports (0,1,2,3,4,5) 'C44: communication ports (1,2,4,5)
Port Input FIFO Output FIFO CREQ5 CACK5 CSTRB5 CRDY5 CD5(7-0)
Channels
Port control registers Timer Global control register Time period register Timer counter register TCLK0
Timer Global control register Time period register Timer counter register TCLK1
2-22
Peripherals
2.6.1
Communication Ports
('C40) four ('C44) high-speed communication ports provide rapid processor-to-processor communication through each port's dedicated communication interfaces. Coupled with 'C4x's memory interfaces (global local), this allows construct parallel processor system that attains optimum system performance distributing tasks among several processors. Each 'C4x pass results work another 'C4x through communication port, enabling each 'C4x continue working. Chapter Communication Ports, explains communication port operation detail. communication ports offer several features:
160-megabits/s (20-Mbytes 5-Mwords second) bidirectional data
transfer operations 40-ns cycle time)
Simple processor-to-processor communication eight data lines
four control lines
Buffering data transfers, both input output Automatic arbitration ensure communication synchronization Synchronization between direct-memory access (DMA)
coprocessor communication ports internal interrupts internal ready signals.
Port direction (CDIR) ease interfacing ('C44 only)
2.6.2
Direct Memory Access (DMA) Coprocessor
channels on-chip coprocessor read from write location memory without interfering with operation CPU. This allows interfacing slow external memories peripherals without reducing throughput CPU. coprocessor contains address generators, source destination registers, transfer counter. Dedicated address data buses allow minimization conflicts between coprocessor. operation consists block single-word transfer from memory. feature coprocessor ability automatically reinitialize each channel following data transfer. Chapter Coprocessor, detailed information coprocessor.
Architectural Overview
2-23
Peripherals
2.6.3
Timers
timer modules general-purpose 32-bit timer/event counters with signaling modes internal external clocking. They signal internally 'C4x externally outside world specified intervals, they count external events. Each timer that used input clock timer, output signal driven timer, generalpurpose pin. timers described detail Chapter Timers.
2-24
Running Title-Attribute Reference
Chapter
Registers
primary register file contains registers that used operands multiplier (arithmetic logic unit). register file includes auxiliary registers, extended-precision registers, index registers. These registers support addressing, floating-point/integer operations, stack management, processor status, block repeats, branching, interrupts. expansion register file contains registers interrupt vector table pointer (IVTP) trap vector table pointer (TVTP). This chapter describes each registers.
Topic
Page
Primary Register File Expansion Register File 3-17
Chapter Title-Attribute Reference
Primary Register File
Primary Register File
'C4x provides registers multiport register file that tightly coupled CPU. (program counter) included register file. contents register file listed Table 3-1.
Table 3-1. Primary Register File
Register Machine Value (hex)
Register Symbol
Assigned Function Name Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Extended-precision register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Data-page pointer Index register Index register Block-size register System stack pointer
Subsection 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.1 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.2 3.1.3 3.1.4 3.1.4 3.1.5 3.1.6
Page
Primary Register File
Table 3-1. Primary Register File (Continued)
Register Symbol Register Machine Value (hex) Subsection 3.1.7 3.1.8 3.1.9 3.1.10 3.1.11 3.1.11 3.1.11 Page 3-11 3-13 3-16 3-16 3-16
Assigned Function Name Status register coprocessor interrupt enable Internal-interrupt enable register IIOF flag register (IIOF3-0 pins, timers, DMA) Repeat start address Repeat address Repeat counter
these registers used both operands multiplier ALU, general-purpose 32-bit registers. However, registers also perform some special functions. example, extended-precision registers maintain extended-precision floating-point results. eight auxiliary registers support variety indirect addressing modes used general-purpose 32-bit integer logical registers. remaining registers provide system functions such addressing, stack management, processor status, interrupts, block repeat. Refer Chapter Addressing Modes, detailed information examples registers used addressing.
3.1.1
Extended-Precision Registers (R0-R11)
extended-precision registers (R0-R11) store support operations 32-bit integer 40-bit floating-point numbers. floating-point numbers, these registers consist separate distinct fields:
Bits 39-32: store exponent floating-point number. Bits 31-0: store mantissa floating-point number:
sign (s), Bits 30-0: fraction (f).
instruction that assumes that operands floating-point numbers uses bits 39-0. Figure illustrates storage 40-bit floating-point numbers extended-precision registers.
Registers
Primary Register File
Figure 3-1. Extended-Precision Register Floating-Point Format
fraction mantissa
integer operations, bits 31-0 extended-precision registers contain integer (signed unsigned). instruction that assumes that operands either signed unsigned integers uses only bits 31-0. Bits 39-32 remain unchanged. This true shift operations. storage 32-bit integers extended-precision registers shown Figure 3-2.
Figure 3-2. Extended-Precision Register Integer Format
unchanged signed unsigned integer
3.1.2
Auxiliary Registers (AR0-AR7)
eight 32-bit auxiliary registers (AR0-AR7) accessed modified auxiliary register arithmetic units (ARAUs). primary function auxiliary registers generation 32-bit addresses. However, they also operate loop counters indirect addressing 32-bit general-purpose registers that modified multiplier ALU. Chapter Addressing Modes, detailed information examples auxiliary registers addressing.
3.1.3
Data-Page Pointer (DP)
data-page pointer (DP) 32-bit register whose LSBs used direct addressing mode pointer page data being addressed. Data pages words long with total (65,536) pages. Bits 31-16 reserved; they always read zeros should modified writing register. loaded using pseudoinstruction instruction. Figure 6-1, page 6-5, describes this register's functions.
3.1.4
Index Registers (IR0, IR1)
32-bit index registers (IR0 IR1) used auxiliary register arithmetic unit (ARAU) indexing address. also used bit-reversed addressing. Chapter Addressing Modes, detailed information examples index registers addressing. Section 6.4, Indirect Addressing, page 6-6, discusses provides examples using indirect addressing. Section 6.9, Bit-Reversed Addressing, page 6-32, describes using with bit-reversed addressing.
Primary Register File
3.1.5
Block-Size Register (BK)
32-bit block-size register (BK) used ARAU circular addressing specify data block size (see Section 6.8, Circular Addressing, page 6-27, more information about register).
3.1.6
System Stack Pointer (SP)
system stack pointer (SP) 32-bit register that contains address system stack. always points last element pushed onto stack. manipulated interrupts, traps, calls, returns, PUSH, PUSHF, POP, POPF instructions. Pushes pops stack perform preincrement postdecrement, respectively, bits
3.1.7
Status Register (ST)
status register (ST) contains global information about CPU's state. Typically, load, store, arithmetic, logical operations affect ST's condition flags. When loaded, contents load instruction's source operand replace ST's current contents, regardless state bit(s) source operand. Therefore, following load, contents identical contents source operand. This allows status register saved easily restored. system reset, written after reset, format shown Figure 3-3. text following figure describes each field
Figure 3-3. Status Register (ST)
ANALYSIS
grant
PGIE
NOTE: reserved bit. read, write.
Carry-condition flag. Overflow condition flag. Zero condition flag. Negative condition flag. Floating-point underflow condition flag. Latched overflow condition flag. Latched floating-point underflow condition flag.
Registers
Primary Register File
Overflow mode (OVM) flag. This flag affects only integer operations. overflow mode turned off. integer results overflowing positive direction most positive 32-bit twos-complement number (7FFF FFFFh), integer results overflowing negative direction most negative 32-bit twos-complement number (8000 0000h). Note that functions bits independent setting OVM.
Repeat mode (RM) flag. modified either repeatblock repeat-single mode. Previous state When trap executes interrupt taken, bit's previous value. RETI RETID instructions, explained chapter Assembly Language Instructions, copy bit.
Cache freeze (CF). Enables disables updating cache. freeze cache. fetches from cache cache clearing allowed, modification cache contents allowed. reset, this cleared zero; after reset. When cache automatically updated instruction fetches from external memory cache clearing allowed. Traps interrupts RETI RETID instructions copy bit. Table summarizes bits.
Cache enable (CE). enables disables instruction cache. enable cache, allowing cache used according (least recently used) cache algorithm. disable cache, preventing cache modifications fetches. Cache clearing allowed when reset, written
Cache clear. invalidates entries cache (contents guaranteed). This always cleared after written thus always read reset, written this bit. cache flags when cache cleared.
Primary Register File
Table 3-2. Summary Bits
Effect Cache enabled Cache enabled Cache enabled frozen Cache enabled frozen (cache read only)
Global interrupt enable. Enables disables maskable interrupts. responds enabled interrupts. does respond enabled interrupts. This does affect NMIs. IDLE, LAT, RETI, RETID, TRAP instructions affect this bit's value. cleared when trap executed interrupt taken.
PGIE
Previous state GIE. When trap executes interrupt taken, cleared When this occurs, PGIE bit's value before trap interrupt. Note that RETIcond RETIcondD instructions copy PGIE bit. reset, this cleared
COND This determines condition flags bits set. (SC) COND condition flags operation's target extended-precision register R11). This setting makes 'C4x similar 'C3x, regarding condition flag settings. This cleared reset. COND condition flags target operation register primary register files except status register. Condition flags always when CMPF, CMPI, CMPF3, CMPI3, TSTB, TSTB3 instruction executed, regardless value COND. ANALYSIS grant This read-only used analysis mode provide state information emulation. ('C44 'C40 revision only) bus-grant feature useful correcting communication-port errors when used with communication-port software reset feature. internal peripheral bus-grant signal forced falling edge NMI. asserted when peripheral stall condition, breaks pending cycle then jumps service routine. stall condition occur when writing full output FIFO, when reading from empty input FIFO. Reserved. Value undefined. These bits read-only.
Registers
Primary Register File
3.1.8
Coprocessor Interrupt Enable Register (DIE)
32-bit interrupt enable register (DIE) broken into subfields that determine which interrupts used control synchronization each coprocessor channels. Synchronization controls when channel reads writes. reset, zeros written register bits. Each channel looks only synchronous interrupts selected also synchronization mode that channel currently using (see Table 11-3). synchronization mode specified SYNC MODE field channel control registers located coprocessor. using interrupt synchronization, each channel (for example) service corresponding communication port. Note that DMAi synchronized only signals coming from communication port (where Also, each channel synchronized external interrupts on-chip timers.
3.1.8.1
Unified Mode
Figure shows interrupt enable register unified mode. Table summarizes interrupt activity each four possible combinations DMA0 DMA1 unified mode. Table summarizes interrupts enabled three-bit values DMA2 through DMA5 unified mode.
Figure 3-4. Interrupt Enable Register Functions Unified Mode
DMA5 Write DMA3 Write DMA1 Write DMA1 Read DMA5 Read DMA3 Read DMA0 Write DMA4 Write DMA2 Write DMA0 Read DMA4 Read DMA2 Read
Read Write
Primary Register File
Table 3-3. Channels (DMA0 DMA1) Unified Mode Synchronization Interrupts
Interrupt Enabled DMA0 DMA1 Value DMA0 DMA1) DMA0 Read None ICRDY0 IIOF0 TIM0 DMA0 Write None OCRDY0 IIOF1 TIM0 DMA1 Read None ICRDY1 IIOF2 TIM0 DMA1 Write None OCRDY1 IIOF3 TIM0 Interrupt Source Synchronization From communication port From external pins IIOF0-IIOF3 From timer TIM0
channel halts read write operation proceeds) synchronous transfer used. This option available DMA0 DMA3 'C44.
Table 3-4. Channels (DMA2 DMA5) Unified Mode Synchronization Interrupts
Value DMA2 DMA5) Interrupt Enabled DMA2-DMA5 DMAx Read None ICRDYx IIOF0 IIOF1 IIOF2 IIOF3 TIM0 TIM1 DMAx Write None OCRDYx IIOF0 IIOF1 IIOF2 IIOF3 TIM0 TIM1 From timers TIM0 TIM1 Interrupt Interr Source Synchronization From communication port From external pins IIOF0-IIOF3
DMAx channel number, which also number corresponding ICRDYx OCRDYx interrupts. example, 0012 both DMA2 READ DMA5 WRITE would enable interrupts ICRDY2 OCRDY5, respectively. other viable values (0102 1112) same shown table) DMA2 through DMA5. channel halts read write operation proceeds) synchronous transfer used. This option available DMA0 DMA3 'C44.
Note:
Coprocessor Uses Signals Synchronize
interrupts Table Table (ICRDYx, OCRDYx, TIM0, etc.) vectored. coprocessor uses these signals synchronize coprocessor transfers. This process explained Section 11.10.
Registers
Primary Register File
3.1.8.2
Split Mode
Figure shows interrupt enable register split mode. Table summarizes interrupt activity each four possible combinations DMA0 DMA1 split mode. Table summarizes interrupts enabled three-bit values DMA2 through DMA5 split mode.
Figure 3-5. Interrupt Enable Register Functions Split Mode
DMA5 Primary Write DMA5 Auxiliary Read DMA4 Primary Write DMA4 Auxiliary Read
DMA3 Primary Write
DMA3 Auxiliary Read
DMA2 Primary Write
DMA2 Auxiliary Read
DMA1 Primary Write
DMA1 Auxiliary Read
DMA0 Primary Write
DMA0 Auxiliary Read
Read Write
Table 3-5. Channels (DMA0 DMA1) Split-Mode Synchronization Interrupts
Value DMA0 DMA1) Interrupt Enabled DMA0 DMA1 DMA0 Auxiliary Read None ICRDY0 IIOF0 TIM0 DMA0 Primary Write None OCRDY0 IIOF1 TIM0 DMA1 Auxiliary Read None ICRDY1 IIOF2 TIM0 DMA1 Primary Write None OCRDY1 IIOF3 TIM0 Interrupt Source Synchronization From communication port From external pins IIOF0-IIOF3 From timer TIM0
channel halts read write operation proceeds) synchronous transfer used. This option available DMA0 DMA3 'C44.
3-10
Primary Register File
Table 3-6. Channels (DMA2 DMA5) Split-Mode Synchronization Interrupts
Interrupt Enabled DMA2-DMA5 Value DMA2 DMA5) DMAx Auxiliary Read None ICRDYx IIOF0 IIOF1 IIOF2 IIOF3 TIM0 TIM1 DMAx Primary Write None OCRDYx IIOF0 IIOF1 IIOF2 IIOF3 TIM0 TIM1 From timers TIM0 TIM1 Interrupt Source Synchronization From communication port From external pins IIOF0-IIOF3
DMAx channel number, which also number corresponding ICRDYx OCRDYx interrupts. example, 0012 both DMA2 READ DMA5 WRITE would enable interrupts ICRDY2 OCRDY5, respectively. other viable values (0102 1112) same shown table) DMA2 through DMA5. channel halts read write operation proceeds) synchronous transfer used. This option available DMA0 DMA3 'C44.
3.1.9
Internal Interrupt Enable Register (IIE)
32-bit internal interrupt enable register, shown Figure 3-6, enables/disables following interrupts CPU:
Timers communication ports 0-5:
Input-buffer full Input-buffer ready Output-buffer ready Output-buffer empty
coprocessor channels
Figure shows register bits. means corresponding interrupt enabled; indicates disabled. reset, zeros written register bits.
Registers
3-11
Primary Register File
Figure 3-6. Internal Interrupt Enable Register (IIE)
ETINT1 EMPTY4 EMPTY1 EDMA INT5 RDY4 RDY1 EDMA INT4 RDY4 EDMA INT3 EDMA INT2 EDMA INT1 EDMA INT0 EOC- EMPTY5 EOC- RDY5 EIC- RDY5 EIC- FULL5 FULL2 ETINT0
FULL4 RDY1
Read, Write, Read/Write
Notes: figure, shaded boxes reserved bits 'C44. Zero should written each these bits. fields corresponding each unit separated double lines. following definitions each bits IIE. EICFULLx EICRDYx EOCRDYx EOCEMPTYx EDMAINTx ETINT0 ETINT1 Comm. port input-buffer full interrupt Comm. port input-buffer ready interrupt Comm. port output-buffer ready interrupt Comm. port output-buffer empty interrupt coprocessor channel interrupt Timer interrupt Timer interrupt each field label, represents communication port number coprocessor channel number (0-5). example, causes interrupts generated when communication port number input buffer becomes full. enables channel coprocessor respond interrupts. enables each interrupt; disables
3-12
EMPTY3 RDY3 RDY3 FULL3 EMPTY2 RDY2 FULL1 EMPTY0 RDY0 RDY0 FULL0
RDY2
Primary Register File
3.1.10
IIOF Flag Register (IIF)
register controls external interrupt pins IIOF(3 specify:
Which IIOF pins used general-purpose which used
interrupts
Whether general-purpose input (read only) output (read/write) Whether interrupt edge-triggered level-triggered interrupts, Whether external interrupt enabled disabled
register also contains timer, interrupt flags. Figure shows register's bits. text following figure explains these bits detail. register bits read from written under software control. This provides access IIOFx pins, which treated general-purpose interrupt pins. example, register, FUNCx (I/O pin) TYPEx (output pin), then writing into FLAGx bit, also write external IIOFx. FUNCx (interrupt pin), writing register FLAGx same effect incoming interrupt received corresponding pin. Consequently, interrupts triggered and/or cleared through software. Since interrupt bits also read from, interrupt pins polled software when interrupt-driven interface required. Internal interrupts operate similar manner. register, corresponding internal interrupt (e.g., TINT0, TINT1) read from written through software. Writing sets interrupt latch, writing clears internal interrupts H1/H3 cycle length. Modify using logic operations (AND, etc.) shown:
correct @MASK,R0 incorrect IIF, @MASK,
Traps interrupts described briefly Section 3.2, Expansion Register File, page 3-17, detail Section 7.4, Interrupts, page 7-15, Section 7.5, Traps, page 7-24.
Registers
3-13
Primary Register File
Figure 3-7. Interrupt Flag Register (IIF)
TINT1 EIIOF3
DMAINT5
DMAINT4
DMAINT3
DMAINT2
DMAINT1
DMAINT0
TINT0 FUNC2
FLAG3
TYPE3
FUNC3
EIIOF2
FLAG2
TYPE2
Read, Write, Read/Write
FUNCx TYPEx
FLAGx
EIIFOx
3-14
EIIOF1 FLAG1 TYPE1 FUNC1 EIIOF0 FLAG0 TYPE0 FUNC0
Mode IIOFx. FUNCx IIOFx general-purpose (R/W) pin. FUNCx IIOFx interrupt pin. Type function IIOFx. IIOFx general-purpose (FUNCx TYPEx makes IIOFx input pin. TYPEx makes IIOFx output IIOFx interrupt (FUNCx TYPEx makes IIOFx edge-triggered latched interrupt, TYPEx makes IIOFx level-triggered unlatched interrupt. Flag IIOFx. IIOFx general-purpose input (FUNCx TYPEx FLAGx value IIOFx read only. IIOFx general-purpose output (FUNCx TYPEx FLAGx value IIOFx R/W. IIOFx interrupt (FUNCx FLAGx interrupt asserted. FLAGx interrupt asserted. (zero) written FLAGx, corresponding interrupt cleared unless interrupt same pin; that case, interrupt will remain set. Disable/enable external interrupt. EIIOFx disables external interrupts IIOFx. EIIOFx enables external interrupts IIOFx.
Primary Register File
Nonmaskable Interrupt flag (NMI). interrupt external pin) behaves like other interrupts, except that cannot masked (disabled) writing bit. temporarily masked during delayed branches multicycle operations. reset, this cleared. asserted interrupt cleared only servicing interrupt. negative-going, edge-triggered, latched interrupt. read-only. Reading indicates that interrupt asserted. Reading indicates that interrupt asserted.
Reserved TINT0 TINT1
Reserved; read zeros. Timer interrupt flags Reading TINTx indicates that timer interrupt asserted. Reading TINTx indicates that timer interrupt asserted. zero written this clears interrupt unless interrupt asserted same time; that case, interrupt will shown asserted. Interrupt flag coprocessor channels Reading DMAINTx indicates that channel interrupt asserted. Reading DMAINTx indicates that channel interrupt asserted. zero written this clears interrupt unless interrupt asserted same time; that case, interrupt shown asserted. Notes: Shaded bits apply IIOF0; shaded bits apply IIOF1, etc. represents corresponding IIOF interrupt (IIOF0-3)
DMAINTx
Registers
3-15
Primary Register File
3.1.11 Block-Repeat (RS, Repeat-Count (RC) Registers
32-bit repeat start address register (RS) contains starting address block program memory repeated when operating repeat mode. 32-bit repeat address register (RE) contains ending address block program memory repeated when operating repeat mode. Note: block program memory repeated, code does loop backwards. However, ST(RM) remains repeat-count register (RC) 32-bit register that specifies number times block code repeated when block repeat performed. contains number loop executed times.
3.1.12 Program Counter (PC)
program counter (PC) 32-bit register containing address next instruction fetch. While program counter part register file, modified same instructions that modify program flow.
3.1.13 Reserved Bits Compatibility
retain compatibility with future members 'C4x family microprocessors, reserved bits that read zero must written zero. Reserved bits that have undefined value must have their current value modified. other cases, maintain reserved bits specified.
3-16
Expansion Register File
Expansion Register File
This expansion register file contains special control registers:
Interrupt-vector table pointer (IVTP) Trap-vector table pointer (TVTP)
Table 3-7. Expansion Registers
Assembler Syntax IVTP TVTP Register Machine Value (Hex)
Function Name Interrupt-vector table pointer. Points start interrupt-vector table. Trap-vector table pointer. Points start trap-vector table.
LDEP instruction load (copy) expansion register primary register (e.g., auxiliary registers AR7; Table page 3-2). example: LDEP IVTP,AR5 IVTP contents
Likewise, LDPE instruction load (copy) primary register expansion register. Neither these instructions affects status register condition flags. LDPE AR5,IVTP contents IVTP
Note that both interrupt-vector table trap-vector table required 512-word boundary; thus, nine least significant bits these pointers zeros (i.e., 0000 00002 200h). Write only zeros these bits (though register forces these zeros). 32-bit IVTP register points essentially base address for) interrupt-vector table (IVT) memory. 32-bit TVTP register essentially base address trap-vector table (TVT) memory. This table contains vectors TRAP instruction's 512-trap addresses (TRAP0-TRAP511). interrupt trap vector tables share same 512-byte space memory. this configuration, place trap vectors where there interrupt vectors. example, since interrupt vector 02Ch unused, could place trap vector IVTP 02Ch (which also TVTP 02Ch tables overlap) then call that trap specifying 02Ch TRAP instruction. reset, IVTP TVTP both zero.
Registers
3-17
Chapter
Memory Instruction Cache
'C40 accesses total memory space 32-bit words (16G bytes) program, data, space; 'C44 accesses total memory space 32-bit words (128M bytes). internal blocks bits each bytes) internal block containing bootloader permit accesses block single cycle. 32-bit instruction cache allows code stored off-chip slower, lower-cost memories without degrading performance. cache also speeds data fetches same physical space program because does burden with program instruction fetches. This chapter describes memory maps instruction cache.
Topic
Page
Memory Peripheral Memory Instruction Cache 4-10
Memory Instruction Cache
Memory
Memory
'C4x memory space gigawords bits where 230) shown memory maps Figure Figure 4-2. contents first segment address space, 0000 0000h 000F FFFFh, selected value enable (ROMEN) pin:
ROMEN Addresses 0000 0000h 0000 0FFFh on-chip
block (reserved bootloader operations), 0000 1000h -000F FFFFh reserved.
addresses
ROMEN on-chip (reserved) disabled, addresses
0000 0000h 000F FFFFh mapped local bus. Memory starting 0010 0000h affected ROMEN. following general summary address ranges:
0000 0000h 000F FFFFh: local on-chip (reserved) ROM,
depending value ROMEN. ROMEN=0, these addresses mapped local bus. ROMEN=1, these addresses mapped on-chip ROM.
0010 0000h 0010 00FFh: Internal peripherals (DMA
coprocessor, communications ports, timers, etc.).
0010 0100h 002F F7FFh Reserved. 002F F800h 002F FBFFh: Block 002F FC00h 002F FFFFh: Block
Instructions cannot loaded from these areas.
0030 0000h 7FFF FFFFh: Local bus. These addresses mapped
local bus.
8000 0000h 0FFFF FFFFh: Global bus. These addresses mapped
global bus. data accesses accesses made from unreserved part 'C4x memory map. Instruction fetches take place from unreserved area 'C4x memory map, except from peripheral space (addresses 0010 0000h 0010 00FFh). Note: 'C4x internal generally reserved internal only. However, high-volume applications, request that install your code internal ROM.
Memory
Figure 4-1. 'C40 Memory
Structure depends upon ROMEN 00000 0000h Accessible local (external) 00000 0FFFh 00000 1000h Bootloader (internal) Reserved 0000F FFFFh 00010 0000h 00010 00FFh 00010 0100h Peripherals (internal) (see Figure 2-6) Reserved 0001F FFFFh 00020 0000h Reserved (Internal) (Internal) 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h Reserved (Internal) (Internal)
Peripherals (internal) (see Figure 2-6) Reserved
Structure identical
2G-3M
Local (external)
Local (external)
07FFF FFFFh 08000 0000h
Global (external)
Global (external)
0FFFF FFFFh Internal disabled (ROMEN Microprocessor Mode Internal enabled (ROMEN Microcomputer Mode
Memory Instruction Cache
Memory
Figure 4-2. 'C44 Memory
Structure depends upon ROMEN 00000 0000h Accessible local (external) 00000 0FFFh 00000 1000h Bootloader (internal) Reserved 0000F FFFFh 00010 0000h 00010 00FFh 00010 0100h 0001F FFFFh 00020 0000h Reserved (internal) (internal) Local (external) 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h Reserved (internal) (internal) Local (external) Peripherals (internal) (see Figure 2-6) Reserved
Peripherals (internal) (see Figure 2-6) Reserved
Structure identical
2G-16M
Local (alias region) 07FFF FFFFh 08000 0000h
Local (alias region)
Global (external)
Global (external)
Global (alias region)
Global (alias region)
0FFFF FFFFh Internal disabled (ROMEN Microprocessor Mode Internal enabled (ROMEN Microcomputer Mode
Peripheral Memory
Peripheral Memory
peripheral memory resides addresses 0010 0000h 0010 00FFh. Each peripheral requires 16-word area. Figure shows locations registers each peripheral memory map.
Figure 4-3. Peripheral Memory
0010 0000h 0010 000Fh 0010 0010h 0010 001Fh 0010 0020h 0010 002Fh 0010 003Fh 0010 0040h 0010 004Fh 0010 0050h 0010 005Fh 0010 0060h 0010 006Fh 0010 0070h 0010 007Fh 0010 0080h 0010 008Fh 0010 0090h 0010 009Fh 0010 00A0h 0010 00AFh 0010 00B0h 0010 00BFh 0010 00C0h 0010 00CFh 0010 00D0h 0010 00DFh 0010 00E0h 0010 00EFh 0010 00F0h 0010 00FFh
Local Global Port Control words) (See subsection 4.2.1 Figure 4-4) Analysis Module Block Registers words)
(See subsection 4.2.2)
Timer Registers words)
(See subsection 4.2.3 Figure 4-5) (See subsection 4.2.3 Figure 4-5)
0010 0030h Timer Registers words)
Communication Port words) ('C40 only)
(See subsection 4.2.4 Figure 4-5)
Communication Port words)
(See subsection 4.2.4 Figure 4-5)
Communication Port words)
(See subsection 4.2.4 Figure 4-5)
Communication Port words) ('C40 only)
(See subsection 4.2.4 Figure 4-5)
Communication Port words)
(See subsection 4.2.4 Figure 4-5)
Communication Port words)
(See subsection 4.2.4 Figure 4-5)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Coprocessor Channel words)
(See subsection 4.2.5 Figure 4-6)
Memory Instruction Cache
Peripheral Memory
4.2.1
Local Global Memory Interface Control Registers
These registers control local global memory interfaces. They occupy first 16-word block peripheral memory map, shown Figure 4-3. registers themselves shown Figure 4-4. Chapter External Operation, covers operation these registers. These registers define several settings:
page sizes used strobes each port Address ranges over which strobes active Wait states Other similar operations that compose memory interfaces
Figure 4-4. Memory Interface Control Registers
0010 0000h 0010 0001h 0010 0003h 0010 0004h 0010 0005h Global Memory Interface Control Register Reserved Local Memory Interface Control Register Reserved 0010 000Fh
4.2.2
Analysis Module Registers
second lowest 16-word block peripheral memory map, shown Figure 4-3, contains part analysis module registers. These registers reserved emulation functions. TMS320C4x Source Debugger User's Guide (literature number SPRU054) describes analysis module user interface provided 'C4x debugger.
Peripheral Memory
4.2.3
Timer Registers
This group registers occupies 0010 0020h 0010 003Fh range peripheral memory shown Figure 4-3, page 4-5. Timers their registers covered detail Chapter Timers.
Figure 4-5. Timer Registers
0010 0020h 0010 0021h 0010 0023h Timer 0010 0024h 0010 0025h Reserved 0010 0027h 0010 0028h Timer period register Timer counter register Timer control register Reserved
Reserved
0010 0030h 0010 0031h
Timer control register Reserved
0010 0033h Timer 0010 0034h 0010 0035h Reserved 0010 0037h 0010 0038h Timer period register Timer counter register
Reserved
0010 003Fh
Memory Instruction Cache
Peripheral Memory
4.2.4
Communication Port Memory
Figure illustrates communication-port control registers (CPCR) input output FIFO buffers. This central group registers peripheral memory shown Figure 4-4, page 4-6. These registers described more detail Chapter Communication Ports.
Figure 4-6. Communication Port Memory
0010 0040h 0010 0041h 0010 0042h 0010 0043h 0010 0050h 0010 0051h 0010 0052h 0010 0053h 0010 0060h 0010 0061h 0010 0062h 0010 0063h 0010 0070h 0010 0071h 0010 0072h 0010 0073h 0010 0080h 0010 0081h 0010 0082h 0010 0083h 0010 0090h 0010 0091h 0010 0092h 0010 0093h
CPCR ('C40 only) input port FIFO position output port FIFO position Port software reset CPCR input port FIFO position output port FIFO position Port software reset CPCR input port FIFO position output port FIFO position Port software reset CPCR ('C40 only) input port FIFO position output port FIFO position Port software reset
CPCR input port FIFO position output port FIFO position Port software reset CPCR input port FIFO position output port FIFO position Port software reset
0010 009Fh
Peripheral Memory
4.2.5
Coprocessor Registers
registers (shown Figure 4-7) bottom block registers peripheral memory (Figure page 4-5). These registers described Chapter Coprocessor.
Figure 4-7. Coprocessor Memory
0010 00A0h
0010 00A8h 0010 00A9h 0010 00AFh 0010 00B0h
Channel registers (see exploded view)
Reserved
0010 00B8h 0010 00B9h
Channel registers (see exploded view)
Reserved
Exploded View Each Channel Register 00z0h 00z1h 00z2h 00z3h 00z4h 00z5h 00z6h 00z7h 00z8h Control register Source address Source address index Transfer counter Destination address Destination address index Link pointer Auxiliary transfer counter Auxiliary link pointer
0010 00BFh 0010 00C0h
0010 00C8h 0010 00C9h 0010 00CFh 0010 00D0h
Channel registers (see exploded view)
Reserved
0010 00D8h 0010 00D9h
Channel registers (see exploded view)
Reserved
channel number (e.g., channel channel etc.) corresponding hexadecimal digit channel address (e.g., substitute channel channel etc.)
0010 00DFh 0010 00E0h
0010 00E8h 0010 00E9h 0010 00EFh 0010 00F0h
Channel registers (see exploded view)
Reserved
0010 00F8h 0010 00F9h 0010 00FFh
Channel registers (see exploded view)
Reserved
Memory Instruction Cache
Instruction Cache
Instruction Cache
32-bit instruction cache speeds instruction fetches lowers system cost. instruction cache allows slow external memories while still achieving single-cycle access performance. cache also frees external buses from program fetches, thus, allowing these buses other system needs. cache operate completely automatic fashion without need external intervention. uses form (least recently used) cache update algorithm.
4.3.1
Instruction Cache Architecture
instruction cache (see Figure page 4-11 contains 32-bit words RAM, enough hold words program memory. divided into four 32-word segments. Associated with each segment 27-bit segment start address (SSA) register. each word cache, there corresponding single-bit present flag. When requests instruction word, check made determine whether word already instruction cache. partitioning instruction address used cache control algorithm shown Figure 4-8. most significant bits (MSBs) instruction address select segment, five least significant bits (LSBs) define address instruction word within pertinent segment. MSBs instruction address compared with four registers. match found, relevant flag checked. flag indicates whether word within particular segment already present cache memory:
word already present cache memory. location cache invalid (e.g., contains garbage).
Figure 4-8. Address Partitioning Cache Control Algorithm
Segment start address (SSA) Instruction word address within segment
there match, segments must replaced data. segment replaced this circumstance determined (least recently used) algorithm. stack (see upper-right portion Figure 4-9) maintained this purpose.
4-10
Instruction Cache
Figure 4-9. Instruction Cache Architecture
Segment start address registers Register bits Flags Segment Words Segment word Segment word Segment word Segment word bits Register Segment word Segment word Segment Segment word Segment word Segment bits Least recently used segment number Stack Most recently used segment number
Register Register
Segment word Segment word Segment
Segment word Segment word
Register Register
Segment word Segment word Segment
Segment word Segment word
Memory Instruction Cache
4-11
Instruction Cache
stack keeps track which segment qualifies least recently used after each access cache. Each time segment accessed, segment number removed from stack pushed onto stack. Therefore, number stack most recently used segment number, number bottom stack least recently used segment number. reset, following occur instruction cache:
Cache disabled (ST(CE) After reset cache frozen (ST(CF)
section 3.1.7, Status Register (ST), page 3-5, details.
flags zero. stack initialized with segment top, followed seg-
ments bottom. registers equal (due reset conditions) cache occurs, instruction word fetched from most recently used segment. When replacement necessary, least recently used segment selected replacement. Also, flags segment replaced segment's register replaced with MSBs instruction's address.
4.3.2
Cache Control Bits
Four cache control bits located status register (ST): cache clear (CC), cache enable (CE), cache freeze (CF), previous cache freeze (PCF). status register shown Figure 3-3. Cache Clear (CC). invalidate entries cache. This always cleared after written thus, always read reset, written this bit. cache flag when cache cleared. Cache Enable (CE). enable cache, allowing cache used according (least recently used) cache algorithm. disable cache; this prevents cache updates modifications (thus, cache fetches made). reset, written this bit. Cache clearing allowed when Cache Freeze (CF). freeze cache including freezing (least recently used) stack manipulation. cache enabled cache frozen fetches from cache allowed, modification cache contents allowed. Cache clearing allowed when reset, this cleared after reset When cache clearing (CC=1) allowed. when trap interrupt taken. Also, RETI RETID instructions copy bit.
4-12
Instruction Cache
Table summarizes effects bits.
Table 4-1. Combined Effect Bits
Effect Cache enabled Cache enabled Cache enabled frozen Cache enabled frozen
Previous Cache Freeze (PCF). When interrupt trap vector taken, value copied bit, This protects cache during interrupt processing particularly useful when code loops interrupted. interrupt service routine optionally cache under software control. Interrupts also nested, providing that status register saved before interrupts enabled. When instructions RETIcond RETIcondD executed complete interrupt processing, contents copied bit.
4.3.3
Using Cache
Only instructions fetched from program cache. reads writes data from memory, bypass cache. Program fetches from internal memory modify cache generate cache hits misses. program cache single-access memory block. Dummy program fetches (i.e., following branch) generate cache misses cache updates. Example shows typical clear enable cache.
Example 4-1.Enabling Cache
1800h,ST
cache more efficiently, take precautions: Avoid using self-modifying code. instruction resides cache corresponding location primary memory modified, copy instruction cache modified. Align program code. .align directive when coding assembly language align code 32-word address boundaries.
Memory Instruction Cache
4-13
Instruction Cache
4.3.4
Cache Algorithm
When 'C4x requests instruction word from external memory, possible actions cache cache miss:
Cache Hit. cache contains requested instruction, follow-
actions occur:
instruction word read from cache. number segment containing word removed from stack pushed stack already top), thus moving other segment numbers toward bottom stack.
Cache Miss. cache does contain instruction. There
types cache misses:
Subsegment miss. segment address register matches instruction address, relevant flag set. following actions occur: instruction word read from memory copied into cache. number segment containing word removed from stack pushed stack already top), thus moving other segment numbers toward bottom stack. relevant flag set.
Segment miss. None segment addresses matches instruction address. following actions occur: least recently used segment selected replacement flags words cleared. register selected segment loaded with MSBs address requested instruction word. instruction word fetched copied into cache. goes into appropriate word least recently used segment. flag that word number segment containing instruction word removed from stack pushed stack, thus moving other segment numbers toward bottom stack.
4-14
Running Title-Attribute Reference
Chapter
Data Formats Floating-Point Operation
'C4x architecture, data organized into three fundamental types: integer, unsigned-integer, floating-point. Note that terms, integer signed-integer, considered equivalent. 'C4x supports short single-precision formats signed unsigned integers. also supports short, single-precision extended-precision formats floating-point data. Floating-point operations make fast, trouble-free, accurate, precise computations. Specifically, 'C4x implementation floating- point arithmetic facilitates floating-point operations integer speeds while preventing problems with overflow, operand alignment, other burdensome tasks common integer operations. This chapter discusses detail data formats floating-point operations supported 'C4x.
Topic
Page
Signed-Intege
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