Literature Number: SPRU056D June 1998 Copyright 1998, Texas Instr
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TMS320C5x User's Guide
Literature Number: SPRU056D June 1998
Copyright 1998, Texas Instruments Incorporated
Preface
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About This Manual
This user's guide describes architecture, hardware, assembly language instructions, general operation TMS320C5x digital signal processors (DSPs). This manual also used reference guide developing hardware and/or software applications.
This Manual
following table summarizes 'C5x information contained this user's guide:
looking information about: Addressing modes Assembly language instructions Boot loader Clock generator Control bits Custom from Development support information Features Host port interface Input/output ports Interrupts Memory configuration Memory interface On-chip peripherals Opcodes Part order information Turn Chapter Addressing Modes Chapter Assembly Language Instructions Chapter Memory Chapter On-Chip Peripherals Chapter Program Control Chapter Central Processing Unit (CPU) Appendix Submitting Codes Appendix Development Support Part Order Information Chapter Introduction Chapter Architectural Overview Chapter On-Chip Peripherals Chapter Memory Chapter Program Control Chapter Memory Chapter Memory Chapter On-Chip Peripherals Chapter Assembly Language Instructions Appendix Development Support Part Order Information
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Notational Conventions Notational Conventions This Manual
looking information about: Pinouts Pipeline operation Program control Serial ports Status registers Timer Upgrading from 'C25 Wait-state generators XDS510 Emulator
Turn Appendix Pinouts Signal Descriptions Chapter Pipeline Chapter Program Control Chapter On-Chip Peripherals Chapter Program Control Chapter On-Chip Peripherals Appendix System Migration Chapter On-Chip Peripherals Appendix Design Considerations Using XDS510 Emulator
Notational Conventions
This document uses following conventions.
Program listings, program examples, interactive displays shown
special typeface similar typewriter's. Examples bold version special typeface emphasis; interactive displays bold version special typeface distinguish commands that enter from items that system displays (such prompts, command output, error messages, etc.). Here sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even
Here example system prompt command that might enter:
/user/ti/simuboard/utilities
syntax descriptions, instruction, command, directive bold
typeface font parameters italic typeface. Portions syntax that bold should entered shown; portions syntax that italics describe type information that should entered. Here example directive syntax: .asect "section name", address .asect directive. This directive parameters, indicated section name address. When .asect, first parameter must
Notational Conventions
actual section name, enclosed double quotes; second parameter must address.
Square brackets identify optional parameter.
optional parameter, specify information within brackets; don't enter brackets themselves. Here's example instruction that optional parameter: LALK 16-bit constant shift] LALK instruction parameters. first parameter, 16-bit constant, required. second parameter, shift, optional. this syntax shows, optional second parameter, must precede with comma. Square brackets also used part pathname specification pathnames; this case, brackets actually part pathname (they optional).
Braces indicate list. symbol (read separates items
within list. Here's example list: This provides three choices: Unless list enclosed square brackets, must choose item from list.
Some directives have varying number parameters. example,
.byte directive have parameters. syntax this directive .byte value1 valuen This syntax shows that .byte must have least value parameter, have option supplying additional value parameters, separated commas.
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Information About Cautions Warnings Related Documentaiton From Texas Instruments Information About Cautions Warnings
Information About Cautions Warnings
This book contain cautions warnings.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
information caution provided your protection. Please read each caution warning carefully.
Related Documentation From Texas Instruments
following books describe 'C5x related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number.
TMS320C5x General-Purpose Applications User's Guide (literature number SPRU164) serves reference book developing hardware and/ software applications 'C5x generation devices. TMS320C5x, TMS320LC5x Digital Signal Processors (literature number SPRS030) data sheet contains electrical timing specifications these devices, well signal descriptions pinouts available packages. TMS320C1x/C2x/C2xx/C5x Code Generation Tools Getting Started Guide (literature number SPRU121) describes install TMS320C1x, TMS320C2x, TMS320C2xx, TMS320C5x assembly language tools compiler 'C1x, 'C2x, 'C2xx, 'C5x devices. installation MS-DOSTM, OS/2TM, SunOSTM, Solarissystems covered. TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User's Guide (literature number SPRU018) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C1x, 'C2x, 'C2xx, 'C5x generations devices.
Related Documentation From Texas Instruments
TMS320C2x/C2xx/C5x Optimizing Compiler User's Guide (literature number SPRU024) describes 'C2x/C2xx/C5x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C2x, 'C2xx, 'C5x generations devices. TMS320C5x Source Debugger User's Guide (literature number SPRU055) tells invoke 'C5x emulator, evaluation module, simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C5x Evaluation Module Technical Reference (literature number SPRU087) describes 'C5x evaluation module, features, design details external interfaces. TMS320C5x Evaluation Module Getting Started Guide (literature number SPRU126) tells install MS-DOSTM, PC-DOSTM, Windowsversions 'C5x evaluation module. TMS320C54x Simulator Getting Started Guide (literature number SPRU137) describes install TMS320C54x simulator source debugger 'C54x. installation Windows 3.1, SunOSTM, HP-UXsystems covered. XDS51x Emulator Installation Guide (literature number SPNU070) describes installation XDS510TM, XDS510PPTM, XDS510WSemulator controllers. installation XDS511emulator also described. JTAG/MPSD Emulation Technical Reference (literature number SPDU079) provides design requirements XDS510emulator controller, discusses JTAG designs (based IEEE 1149.1 standard), modular port scan device (MPSD) designs. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that provide various products that serve family TMS320 digital signal processors. myriad products applications offered-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
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Technical Articles Related Documentation From Texas Instruments Technical Articles
TMS320 Development Support Reference Guide (literature number SPRU011) describes TMS320 family digital signal processors tools that support these devices. Included code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). Also covered available documentation, seminars, university program, factory repair exchange.
assembly language programmer would like more information about expressions, find this book useful:
Programming Language (second edition, 1988), Brian Kernighan Dennis Ritchie, published Prentice-Hall, Englewood Cliffs, Jersey.
Technical Articles
wide variety related documentation available digital signal processing. These references fall into following application categories:
General-Purpose Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references. Texas Instruments strongly suggests that refer these publications.
General-Purpose DSP:
Antoniou, Digital Filters: Analysis Design, York, McGrawHill Company, Inc., 1979. Brigham, E.O., Fast Fourier Transform, Englewood Cliffs, Prentice-Hall, Inc., 1974.
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Technical Articles
Burrus, C.S., T.W. Parks, DFT/FFT Convolution Algorithms, York, John Wiley Sons, Inc., 1984. Chassaing, Horning, D.W., "Digital Signal Processing with Fixed Floating-Point Processors." CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988. Erskine, Magar, "Architecture Applications SecondGeneration Digital Signal Processor." Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor." IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986. Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing." Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987. Gold, Bernard, C.M. Rader, Digital Processing Signals, York, McGraw-Hill Company, Inc., 1969. Hamming, R.W., Digital Filters, Englewood Cliffs, Prentice-Hall, Inc., 1977. IEEE ASSP Committee (Editor), Programs Digital Signal Processing, York, IEEE Press, 1979. Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988. Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors." Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987.
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Technical Articles
Lovrich, Reimer, Advanced Audio Signal Processor." Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability." Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Morris, Robert Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. Oppenheim, Alan (Editor), Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1978. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Oppenheim, A.V., A.N. Willsky, I.T. Young, Signals Systems, Englewood Cliffs, Prentice-Hall, Inc., 1983. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed BitReversed Order Algorithms." Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13-29, December 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor." Computers Education Journal, USA, Volume Number pages 12-16, July- September 1993. Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor." Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume page 1678, April 1988. Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip." Proceedings ICASSP USA, Catalog Number 87CH2396 Volume pages 535-538, April 1987.
Technical Articles
Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor." 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Andrews, H.C., B.R. Hunt, Digital Image Restoration, Englewood Cliffs, Prentice-Hall, Inc., 1977. Gonzales, Rafael Paul Wintz, Digital Image Processing, Reading, Addison-Wesley Publishing Company, Inc., 1977. Papamichalis, P.E., "FFT Implementation TMS320C30." Proceedings ICASSP USA, Volume page 1399, April 1988. Pratt, William Digital Image Processing, York, John Wiley Sons, 1978. Reimer, Lovrich, "Graphics with TMS32020." WESCON/85 Conference Record, USA, 1985.
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25." Proceedings SPEECH TECH pages 218-221, 1989. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17." Proceedings SPEECH TECH '87, pages 25-29, April 1987. Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Jayant, N.S., Peter Noll, Digital Coding Waveforms, Englewood Cliffs, Prentice-Hall, Inc., 1984. Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25." Proceedings SPEECH TECH '87, pages 201-204, April 1987. Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer." Proceedings ICASSP USA, pages 801- 804, 1989.
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Technical Articles
Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications." Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP." Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application." PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors." MOTORCON '88, pages 248-262, September 1988. Ahmed, Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control." Machine Design, September 1987. Ahmed, Meshkat, "Using DSPs Control." Control Engineering, February 1988. Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives." Electronics Letters, Volume Number pages 2188-2190, November 1992. Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion." Proceedings IECON '87, Volume pages 454-463, November 1987. Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988. Jacquot, Modern Digital Control Systems, York, Marcel Dekker, Inc., 1981. Katz, Digital Control Using Microprocessors, Englewood Cliffs, Prentice-Hall, Inc., 1981. Kuo, B.C., Digital Control Systems, York, Holt, Reinholt, Winston, Inc., 1980. Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control." Proceedings ICASSP USA, Volume page 1734, April 1988.
Technical Articles
Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors." IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Meshkat, Ahmed, "Using DSPs Induction Motor Drives." Control Engineering, February 1988. Panahi, Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. Phillips, Nagle, Digital Control System Analysis Design, Englewood Cliffs, Prentice-Hall, Inc., 1984.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance." Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen." Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010." Digital Signal Processing Applications, 1986.
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25." Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder." Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020." Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020." Proceedings IEEE International Conference Acoustics, Speech Signal Processing, USA, 1986. Lovrich, Reimer, Multi-Rate Transcoder." Transactions Consumer Electronics, USA, November 1989.
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Technical Articles
Lovrich, Reimer, Multi-Rate Transcoder." Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989. Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25." Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987. Mock, "Add DTMF Generation Decoding DSP- Designs." Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip." Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor." Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Automotive:
Lin, "Trends Digital Signal Processing Automotive." International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product." Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product." Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC." Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis." Proceedings ICASSP USA, Volume page 2493, April 1988. Morris, L.R., P.B. Barszczewski, "Design Evolution PocketSized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications." Proceedings ICASSP USA, Volume page 2516, April 1988.
Technical Articles Technical Articles Trademarks
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320." MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Trademarks
DuPont Electronics registered trademark E.I. DuPont Corporation. HP-UX trademark Hewlett-Packard Company. IBM, OS/2, PC-DOS trademarks International Business Machines Corporation. Windows registered trademarks Microsoft Corporation. Solaris SunOS trademarks Microsystems, Inc. SPARC trademark SPARC International, Inc., licensed exclusively Microsystems, Inc. Hotline On-line, XDS510, XDS510WS trademarks Texas Instruments Incorporated. trademarks Digital Equipment Corp.
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Contents
Contents
Introduction Summarizes features TMS320 family products presents typical applications. Describes TMS320C5x lists features. TMS320 Family Overview 1.1.1 History, Development, Advantages TMS320 DSPs 1.1.2 TMS320 Typical Applications TMS320C5x Overview TMS320C5x Features
Architectural Overview Summarizes TMS320C5x architecture. Provides general information about structure, CPU, internal memory organization, on-chip peripherals, scanning logic. Structure Central Processing Unit (CPU) 2.2.1 Central Arithmetic Logic Unit (CALU) 2.2.2 Parallel Logic Unit (PLU) 2.2.3 Auxiliary Register Arithmetic Unit (ARAU) 2.2.4 Memory-Mapped Registers 2.2.5 Program Controller On-Chip Memory 2.3.1 Program 2.3.2 Data/Program Dual-Access 2.3.3 Data/Program Single-Access 2.3.4 On-Chip Memory Protection On-Chip Peripherals 2.4.1 Clock Generator 2.4.2 Hardware Timer 2.4.3 Software-Programmable Wait-State Generators 2.4.4 Parallel Ports 2.4.5 Host Port Interface (HPI) 2.4.6 Serial Port 2.4.7 Buffered Serial Port (BSP) 2.4.8 Serial Port 2.4.9 User-Maskable Interrupts Test/Emulation
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Central Processing Unit (CPU) Describes TMS320C5x operations. Includes information about central arithmetic logic unit, parallel logic unit, auxiliary register arithmetic unit. Also provides summary registers. Functional Overview Central Arithmetic Logic Unit (CALU) 3.2.1 Multiplier, Product Register (PREG), Temporary Register (TREG0) 3.2.2 Arithmetic Logic Unit (ALU) Accumulators 3.2.3 Scaling Shifters Temporary Register (TREG1) Parallel Logic Unit (PLU) Auxiliary Register Arithmetic Unit (ARAU) Summary Registers 3.5.1 Auxiliary Registers (AR0-AR7) 3.5.2 Auxiliary Register Compare Register (ARCR) 3.5.3 Block Move Address Register (BMAR) 3.5.4 Block Repeat Registers (RPTC, BRCR, PASR, PAER) 3.5.5 Buffered Serial Port Registers (ARR, AXR, BKR, BKX, SPCE) 3.5.6 Circular Buffer Registers (CBSR1, CBER1, CBSR2, CBER2, CBCR) 3.5.7 Dynamic Manipulation Register (DBMR) 3.5.8 Global Memory Allocation Register (GREG) 3.5.9 Host Port Interface Registers (HPIC, HPIA) 3.5.10 Index Register (INDX) 3.5.11 Space (PA0-PA15) 3.5.12 Instruction Register (IREG) 3.5.13 Interrupt Registers (IMR, IFR) 3.5.14 Processor Mode Status Register (PMST) 3.5.15 Product Register (PREG) 3.5.16 Serial Port Interface Registers (SPC, DRR, DXR, XSR, RSR) 3.5.17 Software-Programmable Wait-State Registers (PDWSR, IOWSR, CWSR) 3.5.18 Status Registers (ST0, ST1) 3.5.19 Temporary Registers (TREG0, TREG1, TREG2) 3.5.20 Timer Registers (TIM, PRD, TCR) 3.5.21 Serial Port Registers (TRCV, TDXR, TSPC, TCSR, TRTA, TRAD, TRSR)
Program Control Describes TMS320C5x program control mechanisms. Includes information about program counter, hardware stack, address generation, status control registers, interrupts, reset, power-down modes. Program Counter (PC) Hardware Stack Program-Memory Address Generation Status Control Registers 4.4.1 Circular Buffer Control Register (CBCR)
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4.10
4.4.2 Processor Mode Status Register (PMST) 4.4.3 Status Registers (ST0 ST1) Conditional Operations 4.5.1 Conditional Branch 4.5.2 Conditional Call 4.5.3 Conditional Return 4.5.4 Multiconditional Instructions 4.5.5 Delayed Conditional Branches, Calls, Returns 4.5.6 Conditional Execution Single Instruction Repeat Function Block Repeat Function 4.7.1 Context Save Restore Used With Block Repeat 4.7.2 Interrupt Operation Block Repeat Interrupts 4.8.1 Interrupt Vector Locations 4.8.2 Interrupt Operation 4.8.3 Interrupt Flag Register (IFR) 4.8.4 Interrupt Mask Register (IMR) 4.8.5 Interrupt Mode (INTM) 4.8.6 Nonmaskable Interrupts 4.8.7 Software-Initiated Interrupts 4.8.8 Interrupt Context Save 4.8.9 Interrupt Latency Reset Power-Down Mode 4.10.1 IDLE Instruction 4.10.2 IDLE2 Instruction 4.10.3 Power Down Using HOLD
Addressing Modes Describes basic addressing modes TMS320C5x Direct Addressing Indirect Addressing 5.2.1 Indirect Addressing Options 5.2.2 Indirect Addressing Opcode Format 5.2.3 Bit-Reversed Addressing Immediate Addressing 5.3.1 Short Immediate Addressing 5.3.2 Long Immediate Addressing Dedicated-Register Addressing 5.4.1 Using Contents BMAR 5.4.2 Using Contents DBMR Memory-Mapped Register Addressing Circular Addressing
Contents
Contents
Assembly Language Instructions Lists defines symbols abbreviations used instruction summary individual instruction descriptions. Provides summary instruction divided into seven basic types operation. Also provides example description instruction describes TMS320C5x assembly language instructions individually. Instruction Symbols Notations 6.1.1 Symbols Abbreviations Used Instruction Opcodes 6.1.2 Symbols Abbreviations Used Instruction Descriptions 6.1.3 Notations Used Instruction Descriptions Instruction Summary Instruction Descriptions
Pipeline Describes TMS320C5x pipeline operation lists pipeline latency cycles these types latencies Pipeline Structure Pipeline Operation 7.2.1 Normal Pipeline Operation 7.2.2 Pipeline Operation Branch Subroutine Call 7.2.3 Pipeline Operation ARAU Memory-Mapped Registers 7.2.4 Pipeline Operation External Memory Conflict Pipeline Latency
Memory Describes TMS320C5x memory configuration operation. Includes memory maps descriptions program memory, data memory, space. Also includes descriptions direct memory access (DMA), memory management, available bootloader options. Memory Space Overview Program Memory 8.2.1 Program Memory Configurability 8.2.2 Program Memory Address 8.2.3 Program Memory Addressing 8.2.4 Program Memory Protection Feature Local Data Memory 8.3.1 Local Data Memory Configurability 8.3.2 Local Data Memory Address 8.3.3 Local Data Memory Addressing Global Data Memory 8.4.1 Global Data Memory Configurability 8.4.2 Global Data Memory Addressing Input/Output (I/O) Space 8.5.1 Addressing Ports Direct Memory Access (DMA) 8.6.1 Master-Slave Configuration
Contents
8.10
8.6.2 External Memory Management 8.7.1 Memory-to-Memory Moves 8.7.2 Memory Block Moves Boot Loader 8.8.1 Boot Mode ('C57 only) 8.8.2 Serial Boot Mode 8.8.3 Parallel EPROM Boot Mode 8.8.4 Parallel Boot Mode 8.8.5 Warm Boot Mode External Parallel Interface Operation Software Wait-State Generation
On-Chip Peripherals Describes TMS320C5x on-chip peripherals control them. Includes information about clock generator, timer, wait-state generators, general-purpose pins, parallel ports, standard serial port interface, buffered serial port interface, time-division multiplexed serial port interface, host port interface. Peripheral Control 9.1.1 Memory-Mapped Peripheral Registers Ports 9.1.2 External Interrupts 9.1.3 Peripheral Reset Clock Generator 9.2.1 Standard Clock Options ('C50, 'C51, 'C52, 'C53, 'C53S only) 9.2.2 Clock Options ('LC56, 'C57S, 'LC57 only) Timer 9.3.1 Timer Registers 9.3.2 Timer Operation Software-Programmable Wait-State Generators 9.4.1 Program/Data Wait-State Register (PDWSR) 9.4.2 Wait-State Register (IOWSR) 9.4.3 Wait-State Control Register (CWSR) 9.4.4 Logic External Program Space General-Purpose Pins 9.5.1 Branch Control Input (BIO) 9.5.2 External Flag Output (XF) Parallel Ports Serial Port Interface 9.7.1 Serial Port Interface Registers 9.7.2 Serial Port Interface Operation 9.7.3 Setting Serial Port Configuration 9.7.4 Burst Mode Transmit Receive Operations 9.7.5 Continuous Mode Transmit Receive Operations 9.7.6 Serial Port Interface Exception Conditions
Contents
Contents
9.10
9.7.7 Example Serial Port Interface Operation Buffered Serial Port (BSP) Interface 9.8.1 Operation Standard Mode 9.8.2 Autobuffering Unit (ABU) Operation 9.8.3 System Considerations Operation 9.8.4 Operation Power-Down Mode Time-Division Multiplexed (TDM) Serial Port Interface 9.9.1 Basic Time-Division Multiplexed Operation 9.9.2 Serial Port Interface Registers 9.9.3 Serial Port Interface Operation 9.9.4 Mode Transmit Receive Operations 9.9.5 Serial Port Interface Exception Conditions 9.9.6 Examples Serial Port Interface Operation Host Port Interface 9.10.1 Basic Host Port Interface Functional Description 9.10.2 Details Host Port Interface Operation 9.10.3 Host Read/Write Access 9.10.4 DSPINT HINT Function Operation 9.10.5 Considerations Changing Memory Access Mode (SAM/HOM) IDLE2 9.10.6 Access Memory During Reset
Pinouts Signal Descriptions Provides pinouts signal descriptions TMS320C5x devices 100-Pin Pinout ('C52) 100-Pin TQFP Pinout ('C51, 'C52, 'C53S, 'LC56) 128-Pin TQFP Pinout ('LC57) 132-Pin BQFP Pinout ('C50, 'C51, 'C53) 144-Pin TQFP Pinout ('C57S) 100-Pin TQFP Device-Specific Pinouts Signal Descriptions
Instruction Classes Cycles Describes classes lists cycles instruction Cycle Class-to-Instruction Summary Instruction Set-to-Cycle Class Summary
System Migration Provides information that necessary upgrade TMS320C2x system into TMS320C5x system. Consists detailed list programming differences hardware timing differences between generations TMS320 DSPs. Package Layout Timing C.2.1 Device Clock Speed
xxii
Contents
C.2.2 Pipeline C.2.3 External Memory Interfacing C.2.4 Execution Cycle Times On-Chip Peripheral Interfacing 'C2x-to-'C5x Instruction C.4.1 Overview C.4.2 Serial Port Control Instructions C.4.3 'C2x-to-'C5x Instruction Mapping
Design Considerations Using XDS510 Emulator Describes JTAG emulator cable construct 14-pin connector your target system connect target system emulator Cable Header Signals Protocol Emulator Cable Emulator Cable Signal Timings Target System Test Clock Configuring Multiple Processors Connections Between Emulator Target System D.7.1 Emulation Signals Buffered D.7.2 Emulation Signals Buffered Emulation Timing Calculations
Memories, Sockets, Crystals Provides product information regarding memories sockets that manufactured Texas Instruments compatible with TMS320C5x Memories Sockets Crystals
Submitting Codes Provides information submitting codes Texas Instruments Single-Chip Solution TMS320 Development Flow Submitting TMS320 Code
Development Support Part Order Information Provides device part numbers support tool ordering information TMS320C5x development support information available from third-party vendors Development Support G.1.1 Software Hardware Development Tools G.1.2 Third-Party Support G.1.3 Technical Training Organization (TTO) TMS320 Workshops G.1.4 Assistance
Contents
xxiii
Contents
Part Order Information G.2.1 Device Development Support Tool Nomenclature G.2.2 Device Nomenclature G.2.3 Development Support Tools Hewlett-Packard E2442A Preprocessor 'C5x Interface G.3.1 Capabilities G.3.2 Logic Analyzers Supported G.3.3 Pods Required G.3.4 Termination Adapters (TAs) G.3.5 Availability
Glossary Defines terms abbreviations used throughout this book Summary Updates This Document Provides summary updates this version document
xxiv
Figures
Figures
4-10 5-10 5-11 Evolution TMS320 Family Typical Applications TMS320 Family 'C5x Functional Block Diagram Block Diagram 'C5x Central Processing Unit (CPU) Central Arithmetic Logic Unit Examples Carry Operations Parallel Logic Unit Block Diagram Indirect Auxiliary Register Addressing Example Auxiliary Register Arithmetic Unit Program Control Functional Block Diagram Circular Buffer Control Register (CBCR) Diagram Processor Mode Status Register (PMST) Diagram Status Register (ST0) Diagram Status Register (ST1) Diagram Interrupt Vector Address Generation Interrupt Flag Register (IFR) Diagram Interrupt Mask Register (IMR) Diagram Minimum Interrupt Latency HOLD Interaction Direct Addressing Direct Addressing Mode Indirect Addressing Indirect Addressing Opcode Format Diagram Short Immediate Addressing Mode Long Immediate Addressing Mode Data Memory Access Long Immediate Addressing Mode Operands Dedicated-Register Addressing Using BMAR Dedicated-Register Addressing Using DBMR Memory-Mapped Register Addressing Memory-Mapped Addressing Direct Addressing Mode Four Level Pipeline Operation 'C50 Memory 'C51 Memory 'C52 Memory 'C53 'C53S Memory 'LC56 'LC57 Memory
Contents
Figures
8-10 8-11 8-12 8-13 8-14 8-15 8-16 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30
xxvi
'C57S Memory Direct Memory Access Using Master-Slave Configuration Boot Routine Selection Word 16-Bit Word Transfer 8-Bit Word Transfer 16-Bit Source Address Parallel EPROM Boot Mode Handshake Protocol 16-Bit Entry Address Warm Boot Mode External Interface Operation Read-Read-Write (Zero Wait States) External Interface Operation Write-Write-Read (Zero Wait States) External Interface Operation Read-Write (One Wait State) External Interrupt Logic Diagram Timer Block Diagram Timer Control Register (TCR) Diagram Program/Data Wait-State Register (PDWSR) Diagram ('C50, 'C51, 'C52 only) Program/Data Wait-State Register (PDWSR) Diagram ('C53S, 'LC56, 'C57 only) Port Wait-State Register (IOWSR) Diagram Wait-State Control Register (CWSR) Diagram Software-Programmable Wait-State Generator Block Diagram Timing Diagram Timing Diagram Port Interface Circuitry One-Way Serial Port Transfer Serial Port Interface Block Diagram Serial Port Control Register (SPC) Diagram Receiver Signal MUXes Burst Mode Serial Port Transmit Operation Serial Port Transmit With Long Pulse Burst Mode Serial Port Transmit Operation With Delayed Frame Sync External Frame Sync Mode (SP) Burst Mode Serial Port Transmit Operation With Delayed Frame Sync External Frame Sync Mode (BSP) Burst Mode Serial Port Receive Operation Burst Mode Serial Port Receive Overrun Serial Port Receive With Long pulse Burst Mode Serial Port Transmit Maximum Packet Frequency Burst Mode Serial Port Receive Maximum Packet-Frequency Continuous Mode Serial Port Transmit Continuous Mode Serial Port Receive Receiver Functional Operation (Burst Mode) Receiver Functional Operation (Burst Mode) SP/BSP Transmitter Functional Operation (Burst Mode) SP/BSP Receiver Functional Operation (Continuous Mode)
Figures
9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52
SP/BSP Transmitter Functional Operation (Continuous Mode) Block Diagram Control Extension Register (SPCE) Diagram Serial Port Control Bits Transmit Continuous Mode with External Frame (Format bits) Block Diagram Control Extension Register (SPCE) Diagram Control Bits Circular Addressing Registers Transmit Buffer Receive Buffer Mapping Example Standard Mode Initialization Timing Autobuffering Mode Initialization Timing Time-Division Multiplexing 4-Wire Serial Port Registers Diagram Serial Port Timing (TDM Mode) Host Port Interface Block Diagram Generic System Block Diagram Select Input Logic HPIC Diagram Host Reads from HPIC HPIC Diagram Host Writes HPIC HPIC Diagram 'C5x Reads From HPIC HPIC Diagram 'C5x Writes HPIC Timing Diagram Pin/Signal Assignments 'C52 100-Pin Pin/Signal Assignments 'C51, 'C52, 'C53S, 'LC56 100-Pin TQFP Pin/Signal Assignments 'LC57 128-Pin TQFP Pin/Signal Assignments 'C50, 'C51, 'C53 132-Pin BQFP Pin/Signal Assignments 'C57S 144-Pin TQFP TMS320C25 68-Pin CPGA TMS320C25 68-Pin PLCC TMS320C25-to-TMS320C5x Pin/Signal Relationship TMS320C25 TMS320C5x Clocking Schemes TMS320C25 IACK Versus TMS320C5x IACK Header Signals Header Dimensions Emulator Cable Interface Emulator Cable Timings Target-System Generated Test Clock Multiprocessor Connections Emulator Connections Without Signal Buffering Buffered Signals TMS320 Code Submittal Flowchart TMS320 Device Nomenclature TMS320 Development Tool Nomenclature
Contents
xxvii
Tables
Tables
4-10 4-11 4-12 4-13 4-14 4-15 4-16
xxviii
Characteristics 'C5x DSPs Number Serial/Parallel Ports Available Different 'C5x Package Types IEEE Std.1149.1 (JTAG)/Boundary-Scan Interface Configurations 'C5x 'C5x Internal Hardware Summary Auxiliary Register Arithmetic Unit Functions Address Loading Into Program Counter Circular Buffer Control Register (CBCR) Summary Processor Mode Status Register (PMST) Summary On-Chip Configuration Using OVLY Bits Status Register (ST0) Summary Status Register (ST1) Summary Product Shifter Mode Determined Bits Conditions Branch, Call, Return Instructions Groups Multiconditional Instructions Multi-cycle Instructions Transformed Into Single-Cycle Instructions Repeat Function Repeatable Instructions Instructions Meaningful Repeat Nonrepeatable Instructions Interrupt Vector Locations Priorities Registers' Status Reset Peripheral Registers' Status Reset Indirect Addressing Opcode Format Summary Indirect Addressing Arithmetic Operations Instruction Field Values Indirect Addressing Bit-Reversed Addresses Instructions That Support Immediate Addressing Instruction Opcode Symbols Abbreviations Instruction Descriptions Symbols Abbreviations Instruction Descriptions Notations Accumulator Memory Reference Instructions Auxiliary Registers Data Memory Page Pointer Instructions Parallel Logic Unit (PLU) Instructions TREG0, PREG, Multiply Instructions Branch Call Instructions Data Memory Operation Instructions
Tables
6-10 6-11 7-10 8-10 8-11 8-12 8-13 8-14 8-15 8-16 9-10 9-11 9-12 9-13
Control Instructions Address Blocks On-Chip Single-Access Pipeline Operation 1-Word Instruction Pipeline Operation 2-Word Instruction Pipeline Operation with Branch Taken Pipeline Operation with Branch Taken Pipeline Operation with Subroutine Call Return Pipeline Operation with Load Pipeline Operation with Load Instruction Pipeline Operation with Load Instructions Pipeline Operation with External Conflicts Latencies Required 'C50 Program Memory Configuration 'C51 Program Memory Configuration 'C52 Program Memory Configuration 'C53 'C53S Program Memory Configuration 'LC56 'LC57 Program Memory Configuration 'C57S Program Memory Configuration 'C5x Interrupt Vector Addresses 'C50 Local Data Memory Configuration 'C51 Local Data Memory Configuration 'C52 Local Data Memory Configuration 'C53 'C53S Local Data Memory Configuration 'LC56, 'LC57, 'C57S Local Data Memory Configuration Data Page Address Registers Global Data Memory Configurations Address Ranges On-Chip Single-Access During External Number CLKOUT1 Cycles Access Various Numbers Wait States Data Page Address Peripheral Registers Ports Standard Clock Options ('C50, 'C51, 'C52, 'C53, 'C53S only) Clock Options ('LC56, 'C57S, 'LC57 only) Timer Control Register (TCR) Summary Program/Data Wait-State Register (PDWSR) Address Ranges ('C50, 'C51, 'C52 only) Program/Data Wait-State Register (PDWSR) Address Ranges ('C53S, 'LC56, 'C57 only) Number CLKOUT1 Cycles Access Various Numbers Wait States Port Wait-State Register (IOWSR) Address Ranges Wait-State Control Register (CWSR) Summary Wait-State Field Values Number Wait States Function CWSR Bits Serial Port Registers Serial Port Pins Serial Port Control Register (SPC) Summary
Contents
xxix
Tables
9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18
Serial Port Clock Configuration Buffered Serial Port Registers Differences Between Operation Standard Mode Control Extension Register (SPCE) Summary Serial Port Control Bits Buffered Serial Port Word Length Configuration Autobuffering Unit Registers Control Extension Register (SPCE) Summary Control Bits Serial Port Registers Interprocessor Communications Scenario Register Contents Registers Description Signal Names Functions Input Control Signals Function Selection Descriptions Control Register (HPIC) Descriptions HPIC Host/'C5x Read/Write Characteristics Wait-State Generation Conditions Initialization HPIA Read Access with Autoincrement Write Access with Auto-Increment Sequence Entering Exiting IDLE2 Operation During RESET Signal/Pin Assignments 'C52 100-Pin Signal/Pin Assignments 'C51, 'C52, 'C53S, 'LC56 100-Pin TQFP Signal/Pin Assignments 'LC57 128-Pin TQFP Signal/Pin Assignments 'C50, 'C51, 'C53 132-Pin BQFP Signal/Pin Assignments 'C57S 144-Pin TQFP Device-Specific Pin/Signal Assignments 'C51, 'C52, 'C53S, 'LC56 100-Pin TQFP Address Data Signal Descriptions Memory Control Signal Descriptions Multiprocessing Signal Descriptions Initialization, Interrupt, Reset Operations Signal Descriptions Supply Signal Descriptions Oscillator/Timer Signal Descriptions Oscillator/Timer Standard Options ('C50, 'C51, C52, 'C53, 'C53S Only) Oscillator/Timer Expanded Options ('LC56, 'C57S, 'LC57 Only) Serial Port Interface Signal Descriptions Buffered Serial Port Interface Signal Descriptions ('LC56 'C57 Only) Host Port Interface Signal Descriptions ('C57 Only) Emulation/Testing Signal Descriptions Cycle Class-to-Instruction Summary Instruction Set-to-Cycle Class Summary TMS320C2x Versus TMS320C5x Instruction TMS320C2x TMS320C5x Serial Port Instructions
Tables
TMS320C2x-to-TMS320C5x Accumulator Memory Reference Instructions TMS320C2x-to-TMS320C5x Auxiliary Registers Data Memory Page Pointer Instructions TMS320C2x-to-TMS320C5x TREG0, PREG, Multiply Instructions TMS320C2x-to-TMS320C5x Branch Call Instructions TMS320C2x-to-TMS320C5x Data Memory Operation Instructions TMS320C2x-to-TMS320C5x Control Instructions XDS510 Header Signal Description Emulator Cable Timing Parameters Commonly Used Crystal Frequencies TMS320C5x Development Support Tools Part Numbers
Contents
xxxi
Examples
Examples
4-10 4-11 4-12 4-13 5-10 5-11 5-12 5-13
xxxii
Conditional Returns (RETC Instruction) Conditional Branch (BCND Instruction) Delayed Conditional Branch (BCNDD Instruction) Conditional Branch Operation Conditional Execution Instruction) Execution with Unstable Condition Execution with Stable Condition Block Repeat (RPTB Instruction) Context Save Restore Used With Block Repeat Block Repeat with Small Loop Code Interrupt Operation With Single-Word Instruction RPTB Interrupt Operation With Single-Word Instruction Before RPTB Modifying Register Values During Interrupt Context Save Indirect Addressing With Change Indirect Addressing With Autodecrement Indirect Addressing With Autoincrement Indirect Addressing With Autoincrement Change Indirect Addressing With INDX Subtracted from Indirect Addressing With INDX Added Indirect Addressing With INDX Subtracted from With Reverse Carry Indirect Addressing With INDX Added With Reverse Carry Indirect Addressing Routine Sequence Auxiliary Register Modifications Bit-Reversed Addressing Memory-Mapped Register Addressing Indirect Addressing Mode Memory-Mapped Register Addressing Direct Addressing Mode Circular Addressing Pipeline Operation 1-Word Instruction Pipeline Operation 2-Word Instruction Pipeline Operation with Branch Taken Pipeline Operation with Branch Taken Pipeline Operation with Subroutine Call Return Pipeline Operation with Load Pipeline Operation with Load Instruction Pipeline Operation with Load Instructions Pipeline Operation with External Conflicts Moving External Data Internal Data Memory With BLDD Instruction
Examples
Moving External Data Internal Program Memory With BLDP Instruction Moving External Data Internal Program Memory With TBLW Instruction Moving External Program Internal Data Memory With BLPD Instruction Moving External Program Internal Data Memory With TBLR Instruction Moving Data From Internal Data Memory Space With LMMR Instruction Moving Data from Space Internal Data Memory With SMMR Instruction Code Initialization Generating 50-kHz Clock Signal Interrupt Service Routine 50-kHz Sample Rate Device Transmit Code (Serial Port Interface Operation) Device Receive Code (Serial Port Interface Operation) Transmit Initialization Burst Mode with External Frame Sync External Clock (Format bits) Receive Initialization Continuous Mode (Format bits) Device Transmit Code (TDM Operation) Device Receive Code (TDM Operation)
Contents
xxxiii
Chapter
Introduction
This user's guide discusses TMS320C5x generation fixed-point digital signal processors (DSPs) TMS320 family. 'C5x provides improved performance over earlier 'C1x 'C2x generations while maintaining upward compatibility source code between devices. 'C5x central processing unit (CPU) based 'C25 incorporates additional architectural enhancements that allow device twice fast 'C2x devices. Future expansion enhancements expected heighten performance range applications 'C5x DSPs. 'C5x generation static CMOS DSPs consists following devices:
Device TMS320C50/LC50 TMS320C51/LC51 TMS320C52/LC52 TMS320C53/LC53 TMS320C53S/LC53S TMS320LC56 TMS320LC57 TMS320C57S/LC57S On-Chip words words words words words words words words On-Chip words words words words words words words words
Topic
Page
TMS320 Family Overview TMS320C5x Overview TMS320C5x Features
Introduction
TMS320 Family Overview
TMS320 Family Overview
TMS320 family consists types single-chip DSPs: 16-bit fixedpoint 32-bit floating-point. These DSPs possess operational flexibility high-speed controllers numerical capability array processors. Combining these qualities, TMS320 processors inexpensive alternatives custom-fabricated VLSI multichip bit-slice processors. Refer subsection 1.1.2, TMS320 Typical Applications, detailed list applications TMS320 family. following characteristics make this family ideal choice wide range processing applications:
Very flexible instruction Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness
1.1.1
History, Development, Advantages TMS320 DSPs
1982, Texas Instruments introduced TMS32010 first fixed-point TMS320 family. Before year, Electronic Products magazine awarded TMS32010 title "Product Year". TMS32010 became model future TMS320 generations. Today, TMS320 family consists eight generations: 'C1x, 'C2x, 'C2xx, 'C5x, 'C54x fixed-point, 'C3x 'C4x floating-point, 'C8x multiprocessor. Figure illustrates performance gains that TMS320 family made over time with successive generations. Source code upward compatible from fixed-point generation next fixed-point generation (except 'C54x), from floating-point generation next floating-point generation. Upward compatibility preserves software generation your investment, thereby providing convenient cost-efficient means higher-performance, more versatile system. Each generation TMS320 devices variety on-chip memory peripheral configurations developing spin-off devices. These spin-off devices satisfy wide range needs worldwide electronics market. When memory peripherals integrated into processor, overall system cost greatly reduced, circuit board space saved.
TMS320 Family Overview
Figure 1-1. Evolution TMS320 Family
Introduction
TMS320 Family Overview
1.1.2
TMS320 Typical Applications
TMS320 family DSPs offers better, more adaptable approaches traditional signal-processing problems, such vocoding, filtering, error coding. Furthermore, TMS320 family supports complex applications that often require multiple operations performed simultaneously. Figure shows many typical applications TMS320 family.
Figure 1-2. Typical Applications TMS320 Family
Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control
Graphics/Imaging rotation Animation/digital Homomorphic processing Pattern recognition Image enhancement Image compression/transmission Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications
Industrial Numeric control Power-line monitoring Robotics Security access
Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speech enhancement Speech recognition Speech synthesis Speaker verification Speech vocoding Voice mail Text-to-speech
1200- 19200-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) Personal digital assistants (PDA)
DTMF encoding/decoding Echo cancellation Line repeaters Speaker phones Spread spectrum communications Video conferencing X.25 Packet Switching Personal communications systems (PCS)
TMS320C5x Overview
TMS320C5x Overview
'C5x generation consists 'C50, 'C51, 'C52, 'C53, 'C53S, 'C56, 'C57, 'C57S DSPs, which fabricated CMOS integrated-circuit technology. Their architectural design based 'C25. operational flexibility speed 'C5x result combining advanced Harvard architecture (which separate buses program memory data memory), with application-specific hardware logic, on-chip peripherals, on-chip memory, highly specialized instruction set. 'C5x designed execute million instructions second (MIPS). Spin-off devices that combine 'C5x with customized on-chip memory peripheral configurations developed special applications worldwide electronics market. 'C5x devices offer these advantages:
Enhanced TMS320 architectural design increased performance
versatility
Modular architectural design fast development spin-off devices Advanced integrated-circuit processing technology increased per-
formance power consumption
Source code compatibility with 'C1x, 'C2x, 'C2xx DSPs fast
easy performance upgrades
Enhanced instruction faster algorithms optimized high-level
language operation
Reduced power consumption increased radiation hardness because
static design techniques Table lists major characteristics 'C5x DSPs. table shows capacity on-chip ROM, number serial parallel input/output (I/O) ports, power supply requirements, execution time machine cycle, package types available with total count. Table guidance choosing best 'C5x your application.
Introduction
TMS320C5x Overview
Table 1-1. Characteristics 'C5x DSPs
On-Chip Memory (16-bit words) DARAM SARAM 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 Ports Serial Parallel 64Kk 64Kk 64Kk Power Supply pply Cycle Time (ns) 50/35/25 50/40/25
TMS320 Device 'C50 'LC50 'C51 'C51 'LC51 'LC51 'C52 'C52 'LC52 'LC52 'C53 'C53S 'LC53 'LC53S 'LC56 'C57S 'LC57 'LC57S
Package Type BQFPd BQFPd
50/35/25/20 BQFPd 50/35/25/20 TQFPk 50/40/25 50/40/25 BQFPd TQFPk
50/35/25/20 QFPh 50/35/25/20 TQFPk 50/40/25 50/40/25 50/35/25 50/35/25 50/40/25 50/40/25 50/35/25 50/35/25 50/35/25 50/35 QFPh TQFPk BQFPd TQFPk BQFPd TQFPk TQFPk TQFPD pinTQFPk TQFPD
Dual-access (DARAM) Single-access (SARAM) bootloader available Includes time-division multiplexed (TDM) serial port Includes buffered serial port (BSP) Includes host port interface (HPI) bumpered quad flat-pack (BQFP) package thin quad flat-pack (TQFP) package quad flat-pack (QFP) package thin quad flat-pack (TQFP) package Sixteen parallel ports memory mapped.
TMS320C5x Features
TMS320C5x Features
features 'C5x DSPs listed below. Where feature exclusive particular device, device's name enclosed within parentheses noted after that feature.
Compatibility: Speed:
Source-code compatible with 'C1x, 'C2x, 'C2xx devices
20-/25-/35-/50-ns single-cycle fixed-point instruction execution time (50/40/28.6/20 MIPS)
Power
3.3-V static CMOS technology with power-down modes Power consumption control with IDLE1 IDLE2 instructions power-down modes
Memory
224K-word 16-bit maximum addressable external memory space (64K-word program, 64K-word data, 64K-word I/O, 32K-word global memory) 1056-word 16-bit dual-access on-chip data 9K-word 16-bit single-access on-chip program/data ('C50) 2K-word 16-bit single-access on-chip boot ('C50, 'C57S) 1K-word 16-bit single-access on-chip program/data ('C51) 8K-word 16-bit single-access on-chip program ('C51) 4K-word 16-bit single-access on-chip program ('C52) 3K-word 16-bit single-access on-chip program/data ('C53, 'C53S) 16K-word 16-bit single-access on-chip program ('C53, 'C53S) 6K-word 16-bit single-access on-chip program/data ('LC56, 'C57S, 'LC57) 32K-word 16-bit single-access on-chip program ('LC56, 'LC57)
Introduction
TMS320C5x Features
Central processing unit (CPU)
Central arithmetic logic unit (CALU) consisting following: 32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC), 32-bit accumulator buffer (ACCB) 16-bit 16-bit parallel multiplier with 32-bit product capability 16-bit left right data barrel-shifters 64-bit incremental data shifter
16-bit parallel logic unit (PLU) Dedicated auxiliary register arithmetic unit (ARAU) indirect addressing Eight auxiliary registers
Program control
8-level hardware stack 4-deep pipelined operation delayed branch, call, return instructions Eleven shadow registers storing strategic CPU-controlled registers during interrupt service routine (ISR) Extended hold operation concurrent external direct memory access (DMA) external memory on-chip indirectly addressed circular buffers circular addressing
Instruction
Single-cycle multiply/accumulate instructions Single-instruction repeat block repeat operations Block memory move instructions better program data management Memory-mapped register load store instructions Conditional branch call instructions Delayed execution branch call instructions Fast return from interrupt instructions Index-addressing mode Bit-reversed index-addressing mode radix-2 fast-Fourier transforms (FFTs)
TMS320C5x Features
On-chip peripherals
parallel ports ports memory-mapped) Sixteen software-programmable wait-state generators program, data, memory spaces Interval timer with period, control, counter registers software stop, start, reset Phase-locked loop (PLL) clock generator with internal oscillator external clock source Multiple clocking option (x1, depending device) Full-duplex synchronous serial port interface direct communication between 'C5x another serial device Time-division multiplexed (TDM) serial port ('C50, 'C51, 'C53) Buffered serial port (BSP) ('LC56, 'C57S, 'LC57) 8-bit parallel host port interface (HPI) ('C57, 'C57S)
Test/Emulation
On-chip scan-based emulation logic IEEE JTAG Standard 1149.1 boundary scan logic ('C50, 'C51, 'C53, 'C57S)
Packages
100-pin quad flat-pack (QFP) package ('C52) 100-pin thin quad flat-pack (TQFP) package ('C51, 'C52, 'C53S, 'LC56) 128-pin TQFP package ('LC57) 132-pin bumpered quad flat-pack (BQFP) package ('C50, 'C51, 'C53) 144-pin TQFP package ('C57S)
Introduction
Chapter
Architectural Overview
This chapter provides overview architectural structure 'C5x, which consists buses, on-chip memory, central processing unit (CPU), on-chip peripherals. 'C5x uses advanced, modified Harvard-type architecture based 'C25 architecture maximizes processing power with separate buses program memory data memory. instruction supports data transfers between memory spaces. Figure shows functional block diagram 'C5x. 'C5x DSPs have same structure; however, they have different on-chip memory configurations on-chip peripherals.
Topic
Page
Structure Central Processing Unit (CPU) On-Chip Memory On-Chip Peripherals Test/Emulation 2-11
Architectural Overview
'C5x Functional Block Diagram
Figure 2-1. 'C5x Functional Block Diagram
Data
Memory Program 'C50 'C51 'C52 'C53 'LC56 'C57S 'LC57 Data/Program SARAM 'C50 'C51 'C52 'C53 'LC56 'C57S 'LC57 Peripherals Serial port Data DARAM Data/Program DARAM (512 (512 serial port Program Buffered serial port Serial port
Timer Program controller Memory control Multiprocessing Interrupts Initialization Oscillator/timer Program counter Status/control registers Hardware stack Address generation logic Instruction register Auxiliary register arithmetic unit (ARAU) Memorymapped registers Host port interface CALU Multiplier Accumulator Buffer Shifters Arithmetic logic unit (ALU) Parallel logic unit (PLU) Test/emulation
Data
Structure
Structure
Separate program data buses allow simultaneous access program instructions data, providing high degree parallelism. example, while data multiplied, previous product loaded into, added subtracted from accumulator and, same time, address generated. Such parallelism supports powerful arithmetic, logic, bit-manipulation operations that performed single machine cycle. addition, 'C5x includes control mechanisms manage interrupts, repeated operations, function calling. 'C5x architecture built around four major buses:
Program (PB) Program address (PAB) Data read (DB) Data read address (DAB)
provides addresses program memory space both reads writes. also carries instruction code immediate operands from program memory space CPU. interconnects various elements data memory space. program data buses work together transfer data from on-chip data memory internal external program memory multiplier single-cycle multiply/accumulate operations.
Architectural Overview
Central Processing Unit (CPU)
Central Processing Unit (CPU)
'C5x consists these elements:
Central arithmetic logic unit (CALU) Parallel logic unit (PLU) Auxiliary register arithmetic unit (ARAU) Memory-mapped registers Program controller
'C5x maintains source-code compatibility with 'C1x 'C2x generations while achieving high performance greater versatility. Improvements include 32-bit accumulator buffer, additional scaling capabilities, host instructions. instruction exploits additional hardware features flexible wide range applications. Data management been improved through block move instructions memory-mapped register instructions. Chapter Central Processing Unit (CPU).
2.2.1
Central Arithmetic Logic Unit (CALU)
uses CALU perform 2s-complement arithmetic. CALU consists these elements:
16-bit 16-bit multiplier 32-bit arithmetic logic unit (ALU) 32-bit accumulator (ACC) 32-bit accumulator buffer (ACCB) Additional shifters outputs both accumulator product register (PREG)
information CALU, Section 3.2, Central Arithmetic Logic Unit (CALU), page 3-7.
2.2.2
Parallel Logic Unit (PLU)
includes independent PLU, which operates separately from, parallel with, ALU. performs Boolean operations manipulations required high-speed controllers. set, clear, test, toggle bits status register, control register, data memory location. provides direct logic operation path data memory values without affecting contents PREG. Results function written back original data memory location. information PLU, Section 3.3, Parallel Logic Unit (PLU), page 3-15.
Central Processing Unit (CPU)
2.2.3
Auxiliary Register Arithmetic Unit (ARAU)
includes unsigned 16-bit arithmetic logic unit that calculates indirect addresses using inputs from auxiliary registers (ARs), index register (INDX), auxiliary register compare register (ARCR). ARAU autoindex current while data memory location being addressed index either contents INDX. result, accessing data does require CALU address manipulation; therefore, CALU free other operations parallel. information ARAU, Section 3.4, Auxiliary Register Arithmetic Unit (ARAU), page 3-17.
2.2.4
Memory-Mapped Registers
'C5x registers mapped into page data memory space. 'C5x DSPs have registers input/output (I/O) port registers have different numbers peripheral reserved registers (see Chapter Memory). Since memory-mapped registers component data memory space, they written read from same other data memory location. memory-mapped registers used indirect data address pointers, temporary storage, status control, integer arithmetic processing through ARAU. information registers, Section 3.5, Summary Registers, page 3-21.
2.2.5
Program Controller
program controller contains logic circuitry that decodes operational instructions, manages pipeline, stores status operations, decodes conditional operations. Parallelism architecture lets 'C5x perform three concurrent memory operations given machine cycle: fetch instruction, read operand, write operand. Chapter Program Control, Chapter Pipeline. program controller consists these elements:
Program counter Status control registers Hardware stack Address generation logic Instruction register
Architectural Overview
On-Chip Memory
On-Chip Memory
'C5x architecture contains considerable amount on-chip memory system performance integration:
Program read-only memory (ROM) Data/program dual-access (DARAM) Data/program single-access (SARAM)
'C5x total address range 224K words bits. memory space divided into four individually selectable memory segments: 64K-word program memory space, 64K-word local data memory space, 64K-word input/ output ports, 32K-word global data memory space. information memory organization, Chapter Memory.
2.3.1
Program
'C5x DSPs carry 16-bit on-chip maskable programmable (see Table sizes). 'C50 'C57S DSPs have boot loader code resident on-chip ROM, other 'C5x DSPs offer boot loader code option. This memory used booting program code from slower external EPROM fast on-chip external RAM. Once custom program been booted into RAM, boot space removed from program memory space setting MP/MC processor mode status register (PMST). on-chip selected reset driving MP/MC low. on-chip selected, 'C5x devices start execution from off-chip memory. information program ROM, Section 8.2, Program Memory, page 8-7. on-chip configured with without boot loader code. However, on-chip intended your specific program. Once program final form, submit code Texas Instruments implementation into your device. details submit code Texas Instruments program your ROM, Appendix Submitting Codes
2.3.2
Data/Program Dual-Access
'C5x DSPs carry 1056-word 16-bit on-chip dual-access (DARAM). DARAM divided into three individually selectable memory blocks: 512-word data program DARAM block 512-word data DARAM block 32-word data DARAM block DARAM primarily intended store data values but, when needed, used store programs well. DARAM blocks always configured data memory; however, DARAM
On-Chip Memory
block configured software data program memory. DARAM configured ways:
1056 words bits configured data memory words bits configured data memory words bits
configured program memory DARAM improves operational speed 'C5x CPU. operates with 4-deep pipeline. this pipeline, reads data third stage writes data fourth stage. Hence, given instruction sequence, second instruction could reading data same time first instruction writing data. dual data buses DAB) allow read from write DARAM same machine cycle. information DARAM, Section 8.3, Local Data Memory, page 8-15.
2.3.3
Data/Program Single-Access
'C5x DSPs except 'C52 carry 16-bit on-chip single-access (SARAM) various sizes (see Table 1-1). Code booted from offchip then executed full speed, once loaded into on-chip SARAM. SARAM configured software three ways:
SARAM configured data memory SARAM configured program memory SARAM configured both data memory program memory
SARAM divided into and/or 2K-word blocks contiguous address memory space. 'C5x CPUs support parallel accesses these SARAM blocks. However, SARAM block accessed only once machine cycle. other words, read from write SARAM block while accessing another SARAM block. When requests multiple accesses, SARAM schedules accesses providing not-ready condition executing multiple accesses cycle time. SARAM supports more flexible address mapping than DARAM because SARAM mapped both program data memory space simultaneously. However, because simultaneous program data mapping, instruction fetch data fetch that could performed machine cycle with DARAM take machine cycles with SARAM. information SARAM, Section 8.3, Local Data Memory, page 8-15.
2.3.4
On-Chip Memory Protection
'C5x DSPs have maskable option that protects contents on-chip memories. When related set, externally originating instruction access on-chip memory spaces. information protection feature, subsection 8.2.4, Program Memory Protection Feature, page 8-14.
Architectural Overview
On-Chip Peripherals
On-Chip Peripherals
'C5x DSPs have same structure; however, they have different onchip peripherals connected their CPUs. 'C5x on-chip peripherals available are:
Clock generator Hardware timer Software-programmable wait-state generators Parallel ports Host port interface (HPI) Serial port Buffered serial port (BSP) Time-division multiplexed (TDM) serial port User-maskable interrupts
2.4.1
Clock Generator
clock generator consists internal oscillator phase-locked loop (PLL) circuit. clock generator driven internally crystal resonator circuit driven externally clock source. circuit generate internal clock multiplying clock source specific factor, clock source with lower frequency than that CPU. information, Section 9.2, Clock Generator, page 9-7.
2.4.2
Hardware Timer
16-bit hardware timer with 4-bit prescaler available. This programmable timer clocks rate that between 1/32 machine cycle rate (CLKOUT1), depending upon timer's divide-down ratio. timer stopped, restarted, reset, disabled specific status bits. information, Section 9.3, Timer, page 9-9.
2.4.3
Software-Programmable Wait-State Generators
Software-programmable wait-state logic incorporated 'C5x DSPs allowing wait-state generation without external hardware interfacing with slower off-chip memory devices. This feature consists multiple waitstate generating circuits. Each circuit user-programmable operate different wait states off-chip memory accesses. information, Section 9.4, Software-Programmable Wait-State Generators, page 9-13.
On-Chip Peripherals
2.4.4
Parallel Ports
total ports available, sixteen these ports memory-mapped data memory space. Each ports addressed instruction. memory-mapped ports accessed with instruction that reads from writes data memory. signal indicates read write operation through port. 'C5x easily interface with external devices through ports while requiring minimal off-chip address decoding circuits. information, Section 9.6, Parallel Ports, page 9-22. Table lists number type parallel ports available 'C5x DSPs with various package types.
2.4.5
Host Port Interface (HPI)
available 'C57S 'LC57 8-bit parallel port that provides interface host processor. Information exchanged between host processor through on-chip memory that accessible both host processor 'C57. information, Section 9.10, Host Port Interface, page 9-87.
Table 2-1. Number Serial/Parallel Ports Available Different 'C5x Package Types
TMS320 Device Package High-Speed Serial Port Serial Port Buffered Serial Port Host Port (Parallel) 'C50/'LC50 'C51/'LC51 'C52/'LC52 'C53/'LC53 PQ/PZ PJ/PZ 'C53S/'LC53S 'LC56 'C57S/'LC57S 'LC57
thin quad flat-pack (TQFP) package quad flat-pack (QFP) package bumpered quad flat-pack (BQFP) package thin quad flat-pack (TQFP) package
Architectural Overview
On-Chip Peripherals
2.4.6
Serial Port
Three different kinds serial ports available: general-purpose serial port, time-division multiplexed (TDM) serial port, buffered serial port (BSP). Each 'C5x contains least general-purpose, high-speed synchronous, full-duplexed serial port interface that provides direct communication with serial devices such codecs, serial analog-to-digital (A/D) converters, other serial systems. serial port capable operating onefourth machine cycle rate (CLKOUT1). serial port transmitter receiver double-buffered individually controlled maskable external interrupt signals. Data framed either bytes words. Table lists number type serial ports available 'C5x DSPs with various package types. information serial ports, Section 9.7, Serial Port Interface, page 9-23.
2.4.7
Buffered Serial Port (BSP)
available 'C56 'C57 devices full-duplexed, doublebuffered serial port autobuffering unit (ABU). provides flexibility data stream length. supports high-speed data transfer reduces interrupt latencies. Table lists number type serial ports available 'C5x DSPs with various package types. information, Section 9.8, Buffered Serial Port (BSP) Interface, page 9-53.
2.4.8
Serial Port
serial port available 'C50, 'C51, 'C53 devices fullduplexed serial port that configured software either synchronous operations time-division multiplexed operations. serial port commonly used multiprocessor applications. Table lists number type serial ports available 'C5x DSPs with various package types. information, Section 9.9, Time-Division Multiplexed (TDM) Serial Port Interface, page 9-74.
2.4.9
User-Maskable Interrupts
Four external interrupt lines (INT1-INT4) five internal interrupts, timer interrupt four serial port interrupts, user maskable. When interrupt service routine (ISR) executed, contents program counter saved 8-level hardware stack, contents eleven specific registers automatically saved (shadowed) 1-level-deep stack. When return from interrupt instruction executed, registers' contents restored. information, Section 4.8, Interrupts, page 4-36.
2-10
Test/Emulation
Test/Emulation
'C50, 'LC50, 'C51, 'LC51, 'C53, 'LC53, 'C57S 'LC57S, IEEE standard 1149.1 (JTAG) interface with boundary scan capability used emulation test. This logic provides boundary scan from interfacing devices. used test pin-to-pin continuity perform operational tests devices that peripheral 'C5x. 'C52, 'LC52, 'C53S, 'LC53S, 'LC56, 'LC57, IEEE standard 1149.1 (JTAG) interface without boundary scan capability used emulation purposes only interfaced other internal scanning logic circuitry that access on-chip resources. Thus, 'C5x perform on-board emulation means IEEE standard 1149.1 serial scan pins emulation-dedicated pins. on-chip analysis block conjunction with 'C5x debugger software provides capability perform debugging performance evaluation functions target system. full analysis block provides following capabilities:
Flexible breakpoint setup. Breakpoints triggered based fol-
lowing events:
Program fetches/reads/writes EMU0/1 activity Data reads/writes events (calls, returns, interrupts/traps, branches, pipeline clock) Event counter overflow
Counting following events performance analysis:
clocks Pipeline advances Instruction fetches Calls, returns, interrupts/traps, branches Program fetches/reads/writes Data reads/writes
Program counter discontinuity trace buffer monitor program counter
flow. reduced analysis block 'C53S 'LC53S provides capability breakpoint triggering based program fetches/reads/writes EMU0/1 activity. Table lists IEEE standard 1149.1 (JTAG) interface, boundary scan capability, on-chip analysis block functions supported 'C5x. IEEE Std. 1149.1 more details.
Architectural Overview
2-11
Test/Emulation
Table 2-2. IEEE Std.1149.1 (JTAG)/Boundary-Scan Interface Configurations 'C5x
Refer TMS320 Development Support Reference Guide additional information available TMS320 development tools.
'LC57 'C57S/'LC57S 'LC56 'C53S/'LC53S 'C53/'LC53 'C52/'LC52 'C51/'LC51 'C50/'LC50 TMS320 Device IEEE Std.1149.1 Interface Boundary Scan Capability On-Chip Analysis Block Reduced Full Full Full Full Full Full Full
2-12
Chapter
Central Processing Unit (CPU)
TMS320C5x central processing unit (CPU) perform high-speed arithmetic within short instruction cycle means highly parallel architecture, which consists following elements:
Program controller Central arithmetic logic unit (CALU) Parallel logic unit (PLU) Auxiliary register arithmetic unit (ARAU) Memory-mapped registers
This chapter does discuss memory peripheral segments, except relation CPU.
Topic
Page
Functional Overview Central Arithmetic Logic Unit (CALU) Parallel Logic Unit (PLU) 3-15 Auxiliary Register Arithmetic Unit (ARAU) 3-17 Summary Registers 3-21
Central Processing Unit (CPU)
Functional Overview
Functional Overview
block diagram shown Figure outlines principal blocks data paths within 'C5x. succeeding sections provide further details functional blocks CPU. internal hardware 'C5x executes functions that other processors typically implement software microcode. example, 'C5x contains hardware single-cycle 16-bit multiplication, data shifting, address manipulation. This hardware-intensive approach provides computing power previously unavailable single chip. Table presents summary 'C5x's internal hardware. This summary table alphabetized. table includes internal processing elements, registers, buses. symbols used table correspond functional blocks illustrated Figure 3-1, succeeding block diagrams this chapter, text throughout this document.
Functional Overview
Figure 3-1. Block Diagram 'C5x Central Processing Unit (CPU)
CLKMD1 CLKMD2 CLKMD3 STRB READY HOLD HOLDA IACK MP/MC INT(1-4) PROGRAM Software wait-states PDWSR IOWSR Program Controller CWSR(5) CLKOUT1 X2/CLKIN CLKIN2 PAER COMPARE Address A15-A0 Stack (8x16) PASR IREG BMAR PMST RPTC GREG BRCR TREG1(5) TREG2(4) Serial Port
Instruction RBIT PROGRAM D15-D0
Serial Port
DATA from IREG CBCR(8) CBSR1 CBSR2 CBER1 CBER2 INDX PRESCALER SFR(0-16) Emulation PRESCALER SFL(0-16) MULTIPLIER PREG(32) P-SCALER (-6,0,1,4) TREG0 Timer [DP] DBMR Time-Division Multiplexed Serial Port
DATA
Buffered Serial Port
[ARP]
Host Port Interface
Ports
ARCR
ARAU Data/Program SARAM Data/Program DARAM Data DARAM POSTSCALER (0-7) PROGRAM DATA ALU(32)
PA15
ACCH
ACCL
ACCB(32)
Notes: registers data lines 16-bits wide unless otherwise specified. available devices.
Central Processing Unit (CPU)
Functional Overview
Table 3-1. 'C5x Internal Hardware Summary
Symbol A15-A0 ACC(32) ACCB(32) ACCH ACCL ALU(32) AR0-AR7 ARAU ARB(3) ARCR ARP(3) BMAR BRAF(1) BRCR CALU CBCR(8) CBER1, CBER2 CBSR1, CBSR2 COMPARE D15-D0 DATA DBMR dma(7) DP(9) Name Address Accumulator Accumulator buffer Accumulator high byte Accumulator byte Arithmetic logic unit Auxiliary registers Auxiliary register arithmetic unit Auxiliary register buffer bits Auxiliary register compare register Auxiliary register pointer bits Block move address register Block repeat active flag Block repeat counter register Carry Central arithmetic logic unit Circular buffer control register Circular buffer registers Circular buffer start registers Configuration control Compare program address Data Data Dynamic manipulation register Data memory address (immediate register) Data memory page pointer bits
Functional Overview
Table 3-1. 'C5x Internal Hardware Summary (Continued)
Symbol GREG HM(1) INDX INTM(1) IPTR(5) IREG MP/MC MULTIPLIER NDX(1) OV(1) OVLY(1) OVM(1) P-SCALER (-6, PAER PASR PM(2) PMST POSTSCALER(0-7) Name Direct data memory address Global memory allocation register Hold mode Interrupt flag register Interrupt mask register Index register Interrupt mode Interrupt vector pointer bits Instruction register Microcall stack Microprocessor/microcomputer Multiplier Multiplexer Enable extra index register Overflow overlay Overflow mode Product shifter Block repeat program address register Block repeat program address start register Program counter Prefetch counter Parallel logic unit Product shifter mode bits Processor mode status register Accumulator postscaling shifter
Central Processing Unit (CPU)
Functional Overview
Table 3-1. 'C5x Internal Hardware Summary (Continued)
Symbol PREG(32) PRESCALER, SFL(0-16), SFR(0-16) PROGRAM RAM(1) RPTC ST0, STACK SXM(1) TC(1) TREG0 TREG1(5) TREG2(4) TRM(1) XF(1) Name Product register Prescaling shifters Program Program enable Repeat counter register Status registers Stack Sign-extension mode Test/control Temporary register (multiplicand) Temporary register (dynamic shift count) Temporary register (bit pointer dynamic test) Enable multiple temporary registers External flag status
Central Arithmetic Logic Unit (CALU)
Central Arithmetic Logic Unit (CALU)
CALU components, shown Figure 3-2, consists following:
16-bit 16-bit parallel multiplier 32-bit 2s-complement arithmetic logic unit (ALU) 32-bit accumulator (ACC) 32-bit accumulator buffer (ACCB) 4-bit left 6-bit right shifter 16-bit left barrel shifter 16-bit right barrel shifter 7-bit left barrel shifter
3.2.1
Multiplier, Product Register (PREG), Temporary Register (TREG0)
16-bit 16-bit hardware multiplier compute signed unsigned 32-bit product single machine cycle. multiply instructions except multiply unsigned (MPYU) instruction perform signed multiply operation multiplier. That numbers being multiplied treated 2s-complement numbers, result 32-bit 2s-complement number. input multiplier from memory-mapped temporary register (TREG0), other input from data program bus. 32-bit result from multiplier stored PREG available ALU. uses 16-bit words taken from data memory derived from immediate instruction, uses 32-bit result stored PREG perform arithmetic operations. also perform Boolean operations. 32-bit result from stored ACC; also supplies second input ALU. Instructions provided storing highand low-order accumulator words memory. shifters (p-scaler, prescaler, postscaler) make possible CALU perform numerical scaling, extraction, extended-precision arithmetic, overflow prevention. These shifters connected output PREG ACC. four product shift modes (PM) PREG output useful performing multiply/accumulate operations fractional arithmetic justifying fractional products. field status register specifies shift mode p-scaler:
002, PREG 32-bit output shifted when transferred into
stored.
012, PREG output left-shifted when transferred into
stored, zero filled. This shift mode compensates extra sign gained when multiplying 16-bit 2s-complement numbers.
Central Processing Unit (CPU)
Central Arithmetic Logic Unit (CALU)
Figure 3-2. Central Arithmetic Logic Unit
Data
TREG0 Multiplier
PRESCALER SFL(0-16)
TREG1(5)
PREG(32) P-SCALER (-6,0,1,4)
PRESCALER SFR(0-16)
ALU(32) C(1)
ACCH
ACCL
ACCB(32)
POSTSCALER (0-7)
Program
Data
Notes: registers data lines 16-bits wide unless otherwise specified.
102, PREG output left-shifted bits when transferred into
stored, LSBs zero filled. This shift mode used conjunction with instruction with short immediate value bits less) eliminate four extra sign bits gained when multiplying a16-bit number times 13-bit number.
112, PREG output right-shifted bits, sign extended, when
transferred into stored, LSBs lost. This shift mode enables execution consecutive multiply/accumulates without possibility overflow. Note that product always sign extended, regardless value sign extension mode (SXM) ST1.
Central Arithmetic Logic Unit (CALU)
shifts also occur when PREG contents stored data memory. PREG contents remain unchanged during shifts. (load TREG0) instruction loads TREG0, from data bus, with first operand; instruction provides second operand multiplication operations. perfrom multiplication with short long immediate operand, instruction with immediate operand. product obtained every cycles except when long immediate operand used. Four multiply/accumulate instructions (MAC, MACD, MADD, MADS) fully utilize computational bandwidth multiplier, which allows both operands processed simultaneously. data these operations transferred multiplier each cycle program data buses. When four multiply/accumulate instructions used with RPTZ instruction, instruction becomes single-cycle multiply/accumulate function. these repeated instructions, coefficient addresses generated while data addresses generated ARAU. This allows instruction sequentially access values from coefficient table step through data indirect addressing modes. RPTZ instruction also clears PREG initialize multiply/ accumulate operation. example, consider multiplying matrix times column second matrix: there matrices, MTRX1 points beginning first matrix, INDX current points beginning second matrix:
RPTZ MTRX1,*0+ ;For ;PREG=DATA(MTRX1+i) DATA[MTRX2 INDX)] ;ACC PREG. ;ACC PREG.
APAC
MACD instructions obtain their coefficient pointer from long immediate address are, therefore, 2-word instructions. MADS MADD instructions obtain their coefficient pointer from BMAR are, therefore, 1-word instructions. When BMAR source coefficient table, block code support multiple applications, change long immediate address without modifying executable code. MACD MADD instructions include data move (DMOV) operation that, conjunction with fetch data multiplicand, writes data value next higher data address.
Central Processing Unit (CPU)
Central Arithmetic Logic Unit (CALU)
MACD MADD instructions, when repeated, support filter constructs (weighted running averages) that sum-of-products operation executed, sample data shifted memory make room next sample throw away oldest sample. Circular addressing with MADS instructions also used support filter implementation. next example, current points oldest samples; BMAR points coefficient table. addition initiating repeat operation, RPTZ instruction also clears PREG. this example, stored temporary register while repeated operation executed. Next, loaded with value stored BMAR. program used address coefficients and, MADD instruction repeatedly executed, increments step through coefficient table. ARAU generates address sample data. Indirect addressing with decrement steps through sample data, starting with oldest data. data fetched, also written next higher location data memory. This operation aligns data next execution filter moving oldest sample past sample's array making room sample beginning sample array. previous product PREG added ACC, while fetched values multiplied product value loaded into PREG. Note that DMOV portion MACD MADD instructions does function with external data memory addresses.
RPTZ MADD APAC ;ACC PREG ;SUM XI+1 ;FINAL SUM.
MPYU instruction performs unsigned multiplication that facilitates extended-precision arithmetic operations. unsigned contents TREG0 multiplied unsigned contents addressed data memory location; result placed PREG. This allows operands larger than bits broken down into 16-bit words processed separately generate products larger than bits. square/add (SQRA) square/subtract (SQRS) instructions pass same value both inputs multiplier squaring data memory value. After multiplication 16-bit numbers, this 32-bit product loaded into PREG. product from PREG transferred data memory store product high (SPH) store product (SPL) instructions.
3-10
Central Arithmetic Logic Unit (CALU)
3.2.2
Arithmetic Logic Unit (ALU) Accumulators
32-bit general-purpose implement wide range arithmetic logical functions, majority which execute single clock cycle. Once operation performed ALU, result transferred ACC, where additional operations, such shifting, occur. Data that input scaled prescaler. following steps occur implementation typical instruction: Data fetched from memory data bus, Data passed through prescaler ALU, where arithmetic performed, result moved into ACC. operates 16-bit words taken from data memory derived from immediate instructions. addition usual arithmetic instructions, perform Boolean operations, thereby facilitating manipulation ability required high-speed controller. input always supplied ACC. other input transferred from PREG multiplier, ACCB, output prescaler (that been read from data memory from ACC). After performed arithmetic logical operation, result stored ACC. following example, assume that PREG 0022 2200h, 002, ACCB 0033 3300h:
LACC APAC ADDB #01111h,8 ;ACC 00111100h. Load from prescaling ;shifter ;ACC 00333300h. ;product register. ;ACC 00666600h. ;accumulator buffer.
32-bit split into 16-bit segments (ACCH ACCL) storage data memory (see Figure 3-2). postscaler output provides left shift places. This shift performed while data being transferred data storage. contents remain unchanged. When postscaler used high word (bits 31), MSBs lost LSBs filled with bits shifted from word (bits 15). When postscaler used word, LSBs zero filled. following example, assume that FF23 4567h:
SACL SACH TEMP1,7 TEMP2,7 ;TEMP1 B380h ;TEMP2 91A2h FF234567h. FF234567h.
3-11
Central Processing Unit (CPU)
Central Arithmetic Logic Unit (CALU)
'C5x supports floating-point operations applications requiring large dynamic range. performing left shifts, NORM (normalization) instruction normalizes fixed-point numbers contained ACC. four bits TREG1 define variable shift through prescaler to/load to/subtract from accumulator with shift specified TREG1 (ADDT/LACT/SUBT) instructions. These instructions denormalize number (convert from floating-point fixed-point) also execute automatic gain control (AGC) going into filter. single-cycle 1-bit 16-bit right shift efficiently align contents. This shift, coupled with 32-bit temporary buffer ACC, enhances effectiveness CALU extended-precision arithmetic. ACCB provides temporary storage place fast save ACC. ACCB also used input ALU. minimum maximum value string numbers found comparing contents ACCB with contents ACC. minimum maximum value placed both registers, and, condition met, carry set. minimum maximum functions executed CRLT CRGT instructions, respectively. These operations signed arithmetic operations. next example, assume that 1234 5678h ACCB 7654 3210h:
CRLT CRGT ;ACC ACCB 1234 5678h. ;ACC ACCB 7654 3210h.
overflow saturation mode enabled setting disabled clearing overflow mode (OVM) ST0. When overflow saturation mode overflow occurs, overflow flag loaded with either most positive most negative value representable ACC, depending upon direction overflow. value upon saturation 7FFF FFFFh (positive) 8000 0000h (negative). cleared overflow occurs, overflowed results loaded into without modification. Note that logical operations cannot result overflow. 'C5x execute variety branch instructions that depend status ACC. example, execution instruction BCND depend variety conditions ACC. BACC instruction allows branching address stored ACC. test instructions (BITT BIT) facilitate branching condition specified data memory.
3-12
Central Arithmetic Logic Unit (CALU)
associated carry that cleared, depending various operations within 'C5x. carry allows more efficient computation extended-precision products additions subtractions; also useful overflow management. carry affected most arithmetic instructions well single-bit shift rotate instructions. carry affected loading ACC, logical operations, other nonarithmetic control instructions. Examples carry operations shown Figure 3-3.
Figure 3-3. Examples Carry Operations
2(OVM (SUBB)
(OVM (ADDC)
value added subtracted from come from prescaler, ACCB, PREG. carry result addition accumulation process generates carry; cleared result subtraction generates borrow. Otherwise, cleared after addition after subtraction. with carry (ADDC) ACCB with carry (ADCB) instructions previous value carry their addition operation. subtract from with borrow (SUBB) subtract ACCB from with borrow (SBBB) instructions logical inversion previous value carry. exception operation carry with shift count (add ACCH) with shift count (subtract from ACCH). These instructions generate carry borrow, they will clear carry borrow, normally case carry borrow generated. This feature useful extended-precision arithmetic. conditional operands, provided branching, calling, returning, conditionally executing according status carry bit. CLRC, SETC instructions used load carry bit. carry reset. 1-bit shift left (SFL) right (SFR) rotate left (ROL) right (ROR) instructions shift rotate contents through
Central Processing Unit (CPU)
3-13
Central Arithmetic Logic Unit (CALU)
carry bit. affects definition shift accumulator right (SFR) instruction. When performs arithmetic right shift, maintaining sign data. When performs logical shift, shifting LSBs shifting MSB. shift accumulator left (SFL) instruction affected behaves same both cases, shifting shifting RPTZ instructions used with shift rotate instructions multiple-bit shifts. SFLB, SFRB, RORB, ROLB instructions shift rotate 65-bit combination ACC, ACCB, carry described above. also shifted 0-31 bits right instruction cycles 1-16 bits right cycle. bits shifted lost, bits shifted either copies original sign bit, depending value bit. shift count embedded instruction word BSAR instruction. example, 1234 5678h:
BSAR ;ACC 0246 8ACEh.
right shift also controlled TREG1. SATL instruction shifts 0-15 bits, defined bits TREG1. SATH instruction shifts bits right TREG1 following code sequence executes 31-bit right shift ACC, depending shift count stored SHIFT. example, consider value stored SHIFT 01Bh 1234 5678h:
LMMR SATH SATL TREG1,SHIFT ;TREG1 shift count TREG1 shift count then ;ACC 00001234 ;ACC shift count. 0000 0002
3.2.3
Scaling Shifters Temporary Register (TREG1)
prescaler 16-bit input connected data 32-bit output connected (see Figure 3-2). prescaler produces left shift bits input data. shift count specified constant embedded instruction word value TREG1. LSBs output filled with MSBs filled with sign-extended, depending upon value ST1. p-scaler postscaler make possible CALU perform numerical scaling, extraction, extended-precision arithmetic, overflow prevention. These shifters connected output PREG (see Figure page 3-8).
3-14
Parallel Logic Unit (PLU)
Parallel Logic Unit (PLU)
parallel logic unit (PLU) directly set, clear, test, toggle multiple bits control/status register data memory location. provides direct logic operation path data memory values without affecting contents PREG (see Figure 3-4). executes read-modify-write operation data stored data space. First, operand fetched from data memory space, second fetched from long immediate program from dynamic manipulation register (DBMR). Then, executes logical operation operands defined instruction. result written same data memory location from which first operand fetched.
Figure 3-4. Parallel Logic Unit Block Diagram
Data
DBMR
Note:
registers data lines 16-bits wide unless otherwise specified.
makes possible directly manipulate bits location data memory space ANDing, ORing, exclusive-ORing, loading 16-bit long immediate value data location. example, circular buffer circular buffer enable circular buffers, initialize circular buffer control register (CBCR) executing following code:
SPLK #021h,CBCR ;Store peripheral long immediate ;(DP
Next, enable circular buffers executing code:
#088h,CBCR ;Set CBCR.
Central Processing Unit (CPU)
3-15
Program
Parallel Logic Unit (PLU)
test individual bits specific register data word, instruction; however, test pattern bits, compare parallel long immediate (CPL) instruction. data value equal long immediate value, then test/control (TC) set. result instruction set, clear, toggle functions executed with 16-bit dynamic register value instead long immediate value. This done with following three instructions: DBMR register data (APL), DBMR register data (OPL), exclusive-OR DBMR register data (XPL). also APL, OPL, instructions result operation (value written back into data memory) This allows bits tested cleared simultaneously. example,
BCND #0FF00h,TEMP HIGH_BITS_SET,NTC ;Clear byte check ;bits high byte. bits active high byte, ;then branch.
BCND #1,TEMP BIT_SET,TC ;Toggle set, branch. not, ;bit now.
first example, byte flag word cleared while high byte checked active flags (bits none flags high byte set, then resulting operation yields TEMP set. flags high byte set, then resulting operation yields nonzero value TEMP cleared. Therefore, conditional branch (BCND) following instruction branches bits high byte nonzero. second example tests flag. flag low, flag high; flag high, flag cleared branch taken. instructions operate anywhere data address space, they operate with flags stored locations well control registers both off-chip peripherals. instructions listed Table page 6-14.
3-16
Auxiliary Register Arithmetic Unit (ARAU)
Auxiliary Register Arithmetic Unit (ARAU)
auxiliary register file contains eight memory-mapped auxiliary registers (AR0-AR7), which used indirect addressing data memory temporary data storage. Indirect auxiliary register addressing (see Figure 3-5) allows placement data memory address instruction operand into pointed 3-bit auxiliary register pointer (ARP) that loaded with value from 0-7, designating AR0-AR7, respectively. loaded from data memory, PREG immediate operand defined instruction. contents stored data memory used inputs CALU. memory-mapped reside data page described subsection 8.3.2, Local Data Memory Address Map, page 8-17. auxiliary register file (AR0-AR7) connected auxiliary register arithmetic unit (ARAU), shown Figure 3-6. ARAU autoindex current while data memory location being addressed; indexes either contents index register (INDX). result, CALU needed address manipulation when tables information accessed; free other operations parallel. more advanced address manipulation, such multidimensional array addressing, CALU directly read from write ARs.
Figure 3-5. Indirect Auxiliary Register Addressing Example
Auxiliary Register File Auxiliary Register Pointer ST0) FFFFh 3121h Data Memory Location
Central Processing Unit (CPU)
3-17
Auxiliary Register Arithmetic Unit (ARAU)
Figure 3-6. Auxiliary Register Arithmetic Unit
A15-A0 Program Control
ARP(3)
ARB(3)
Data
ARAU
SARAM DARAM
DARAM
Notes: registers data lines 16-bits wide unless otherwise specified.
ARAU updates during decode phase (second stage) pipeline, while CALU writes during execution phase (fourth stage). Therefore, instructions that immediately follow CALU write should same address generation. Chapter Pipeline, more details.
shown Figure 3-6, INDX, auxiliary register compare register (ARCR), eight LSBs instruction register (IREG) used inputs ARAU. other input provided contents current pointed ARP. Table defines functions ARAU.
3-18
Program
CBCR(8) CBSR1 CBSR2 CBER1 CBER2 INDX ARCR
IREG
Auxiliary Register Arithmetic Unit (ARAU)
Table 3-2. Auxiliary Register Arithmetic Unit Functions
Function Current INDX Current Current INDX Current Current Current Current Current Current Current Current IR(7-0) Current Current IR(7-0) Current Current rc(INDX) Current Current rc(INDX) Current (Current (ARCR), then (Current (ARCR), then (Current (ARCR), then (Current (ARCR), then (Current (CBER), then Current CBSR Description Index current adding unsigned 16-bit integer contained INDX. Example: Index current subtracting unsigned 16-bit integer contained INDX. Example: Increment current Example: Decrement current Example: modify current Example: 8-bit immediate value current Example: ADRK #55h Subtract 8-bit immediate value from current Example: SBRK #55h Bit-reversed indexing; INDX with reversed-carry (rc) propagation. Example: *BR0+ Bit-reversed indexing; subtract INDX with reversedcarry (rc) propagation. Example: *BR0- Compare current ARCR and, condition true, then status register ST1. false, then clear bit. Example: CMPR current circular buffer, reload start address. test this condition performed before execution modification. Example:
INDX added subtracted from current update cycle. INDX used increment decrement address steps larger than this useful operations such addressing down matrix column. ARCR limits blocks data supports logical comparisons between current ARCR conjunction with CMPR instruction. Note that 'C2x uses this implementation. After reset, load auxiliary register (LAR) instruction load AR0; enable extra index register (NDX) PMST set, also loads INDX ARCR maintain compatibility with 'C2x.
Central Processing Unit (CPU)
3-19
Auxiliary Register Arithmetic Unit (ARAU)
Because memory-mapped, CALU directly upon them more advanced indirect addressing techniques. example, multiplier calculate addresses 3-dimensional matrices. After CALU load there however, 2-instruction-cycle delay before used address generation. INDX ARCR accessible CALU, regardless condition (that SAMM ARCR writes only ARCR). ARAU serve additional general-purpose arithmetic unit because auxiliary register file directly communicate with data memory. ARAU implements 16-bit unsigned arithmetic, whereas CALU implements 32-bit 2s-complement arithmetic. BANZ BANZD instructions permit used loop counters. 3-bit auxiliary register pointer buffer (ARB), shown Figure 3-6, stores subroutine calls when automatic context switch feature 'C5x used. circular buffers operate given time controlled circular buffer control register (CBCR). Upon reset (rising edge RS), both circular buffers disabled. define circular buffer, load CBSR1 CBSR2 with start address buffer CBER1 CBER2 with address; then load used with circular buffer with address between start addresses. Finally, load CBCR with appropriate number enable (CENB1 CENB2) bit.
same access both circular buffers unexpected results will occur.
address stepping through circular buffer, value compared against value contained CBER prior update value. current value CBER equal modification occurs, value contained CBSR automatically loaded into values CBER equal, modified specified. Circular buffers used with either increment- decrement-type updates. increment used, then value CBER must larger than value CBSR. decrement used, value CBER must smaller than value CBSR. other indirect addressing modes used; however, ARAU tests only condition current CBER. ARAU does detect update that steps over value contained CBER. Section 5.6, Circular Addressing, page 5-21 more details.
3-20
Summary Registers
Summary Registers
registers (except ST1), peripheral registers, ports occupy data memory space.
3.5.1
Auxiliary Registers (AR0-AR7)
eight 16-bit auxiliary registers (AR0-AR7) accessed CALU modified ARAU PLU. primary function provide 16-bit address indirect addressing data space. However, also used general-purpose registers counters. Section 5.2, Indirect Addressing, page describes used indirect addressing. described Section page 3-17.
3.5.2
Auxiliary Register Compare Register (ARCR)
16-bit ARCR used address boundary comparison. CMPR instruction compares ARCR selected places result compare ST1. Section 5.2, Indirect Addressing, page describes ARCR used memory management. also Section page 3-17.
3.5.3
Block Move Address Register (BMAR)
16-bit BMAR holds address value used with block moves multiply/accumulate operations. This register provides 16-bit address indirect-addressed second operand. Section 5.4, Dedicated-Register Addressing, page 5-17.
3.5.4
Block Repeat Registers (RPTC, BRCR, PASR, PAER)
16-bit repeat counter register (RPTC) holds repeat count repeat single-instruction operation loaded RPTZ instructions. Section 4.6, Single Instruction Repeat Function, page 4-22.
Although RPTC memory-mapped register, should avoid writing this register. Writing this register cause undesired results.
Central Processing Unit (CPU)
3-21
Summary Registers
16-bit block repeat counter register (BRCR) holds count value block repeat feature. This value loaded before block repeat operation initiated. value changed while block repeat progress; however, take care avoid infinite loops. block repeat program address start register (PASR) indicates 16-bit address where repeated block code starts. block repeat program address register (PAER) indicates 16-bit address where repeated block code ends. PASR PAER loaded RPTB instruction. Block repeats described Section 4.7, Block Repeat Function, page 4-31.
3.5.5
Buffered Serial Port Registers (ARR, AXR, BKR, BKX, SPCE)
buffered serial port (BSP) available 'C56 'C57 devices. comprises full-duplex, double-buffered serial port interface autobuffering unit (ABU). 2K-word buffer, which resides 'C5x internal memory. Five registers control operate BSP. 16-bit control extension register (SPCE) contains mode control status bits BSP. 11-bit address receive register (ARR) 11-bit receive buffer size register (BKR) support address generation writing data receive register (DRR) 'C5x internal memory. 11-bit address transmit register (AXR) 11-bit transmit buffer size register (BKX) support address generation reading word from 'C5x internal memory data transmit register (DXR). described Section 9.8, Buffered Serial port (BSP) Interface, page 9-53.
3.5.6
Circular Buffer Registers (CBSR1, CBER1, CBSR2, CBER2, CBCR)
'C5x devices support concurrent circular buffers operating conjunction with user-specified auxiliary registers. 16-bit circular buffer start registers (CBSR1 CBSR2) indicate address where circular buffer starts. 16-bit circular buffer registers (CBER1 CBER2) indicate address where circular buffer ends. 16-bit circular buffer control register (CBCR) controls operation these circular buffers identifies auxiliary registers used. Section 5.6, Circular Addressing, page 5-21 describes circular buffers used memory management. Section page 3-17 describes circular buffer registers used addressing. also subsection 4.4.1, Circular Buffer Control Register (CBCR), page 4-6.
3.5.7
Dynamic Manipulation Register (DBMR)
16-bit DBMR used conjunction with dynamic (executiontime programmable) mask register. DBMR described Section page 3-15.
3-22
Summary Registers
3.5.8
Global Memory Allocation Register (GREG)
16-bit GREG allocates parts local data space global memory defines what amount local data space will overlayed global data space. Section 8.4, Global Data Memory, page 8-20.
3.5.9
Host Port Interface Registers (HPIC, HPIA)
8-bit wide parallel host port interface (HPI) available 'C57 device. interfaces host processor 'C57 device. control register (HPIC) holds control word. host processor addresses memory address register (HPIA). Section 9.10, Host Port Interface ('C57S 'LC57 only), page 9-87.
3.5.10 Index Register (INDX)
16-bit INDX used ARAU step value (addition subtraction more than modify address during indirect addressing. example, when ARAU steps across matrix, indirect address incremented However, when ARAU steps down column, address incremented dimension matrix. ARAU subtract value stored INDX from current part indirect address operation. INDX also dimension address block used bit-reversal addressing. Section 5.2, Indirect Addressing, page describes INDX used memory management. also Section page 3-17.
3.5.11 Space (PA0-PA15)
space makes possible address locations (50h-5Fh) space addressing modes local data space. This means that these locations read directly into CALU written from ACC. also means that these locations acted upon addressed memory-mapped addressing mode. locations also addressed with instructions.
3.5.12 Instruction Register (IREG)
16-bit IREG holds opcode instruction being executed. IREG used during program control.
3.5.13 Interrupt Registers (IMR, IFR)
16-bit interrupt mask register (IMR) individually masks specific interrupts required times. 16-bit interrupt flag register (IFR) indicates current status interrupts. status interrupts updated regardless INbit ST0. Interrupts described Section 4.8, Interrupts, page 4-36.
Central Processing Unit (CPU)
3-23
Summary Registers
3.5.14 Processor Mode Status Register (PMST)
16-bit PMST contains status control information 'C5x device. Subsection 8.2.1, Program Memory Configurability, page subsection 8.3.1, Local Data Memory Configurability, page 8-15 describe PMST configures memory. also subsection 4.4.2, Processor Mode Status Register (PMST), page 4-7.
3.5.15 Product Register (PREG)
32-bit PREG holds result multiply operation. high words PREG accessed individually. subsection 3.2.1 page 3-7.
3.5.16 Serial Port Interface Registers (SPC, DRR, DXR, XSR, RSR)
Five registers control operate serial port interface. 16-bit serial port control register (SPC) contains mode control status bits serial port. 16-bit data receive register (DRR) holds incoming serial data, 16-bit data transmit register (DXR) holds outgoing serial data. 16-bit data transmit shift register (XSR) controls shifting data from output pin. 16-bit data receive shift register (RSR) controls storing data from input DRR. serial port described Section 9.7, Serial Port Interface, page 9-23.
3.5.17 Software-Programmable Wait-State Registers (PDWSR, IOWSR, CWSR)
software wait states determined three registers. These registers serve different purposes different devices. most 'C5x devices 16-bit program/data wait-state register (PDWSR) contains wait-state count eight 16K-word blocks program data memory. PDWSR divided into eight 2-bit wait-state fields assigned each 16K-word block. space mapped into 16-bit wait-state register (IOWSR) under control 5-bit wait-state control register (CWSR). CWSR determines range wait states selected. CWSR determines space partitioned. cleared, IOWSR divided into eight pairs ports with 2-bit wait-state fields assigned each pair port addresses. set, space divided into eight 8K-word blocks with each having 2-bit wait-state field, similar PDWSR. 'C52, 'LC56, 'C57S, 'LC57 devices, program, data, space wait states each specified single (3-bit) wait-state value. Each memory space independently wait states 3-bit wait-state field PDWSR. Section 9.4, Software-Programmable Wait-State Generators, page 9-13.
3-24
Summary Registers
3.5.18 Status Registers (ST0, ST1)
16-bit status registers contain status control bits described subsection 4.4.3, Status Registers (ST0 ST1), page 4-10.
3.5.19 Temporary Registers (TREG0, TREG1, TREG2)
16-bit TREG0 holds multiplicands multiplier. TREG0 also loaded CALU with following instructions: LTA, LTD, LTP, LTS, SQRA, SQRS, MAC, MACD, MADS, MADD. 5-bit TREG1 holds dynamic (execution-time programmable) shift count prescaling shifter. 4-bit TREG2 holds dynamic address BITT instruction. TREG0
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