Hansbauer Rebecca Vassos Soteriou ABSTRACT This document describes mul

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TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
Hansbauer Rebecca Vassos Soteriou ABSTRACT This document describes multichannel buffered serial ports (McBSPs) Texas Instruments TMS320C6000 digital signal processor (DSP) digital controller audio codec 1997 device. McBSP connected stereo audio codec 1997 device. This application report uses TLV320AIC27 audio codec (AIC27) example. audio codec 1997 (AC'97) standard specifies five-signal digital connection between McBSP AIC27. These five signals SYNC, BITCLK, SDATAOUT, SDATAIN, RESETB signals AC'97 device. this AC'97 interface, McBSP operates audio codec controller. This application report discusses configuration these signals detail. hardware schematic discussed this document possible solution AC'97 interface. sample code, provided Appendix this application report, been tested specially configured Texas Instruments TMS320C6000 board connecting McBSP ports together: McBSPs been AC'97 device emulate presence AC'97 device interfaced McBSP port, been tested using actual TMS320C6000 McBSP-TLV320AIC27 interface. Digital Signal Processing Solutions
Contents Design Problem Overview Solution Hardware Interface McBSP Register Configuration Timing Diagram McBSP Initialization Sample Functions
Conclusion References
Appendix Sample Source Code AIC27 Interface
TMS320C6000 trademark Texas Instruments. trademarks property their respective owners.
SPRA528A
List Figures Figure Figure Figure Figure Figure Figure Figure AC'97 System Architecture Digital Interface Between McBSP AC'97 Device Receive Control Register (RCR) Transmit Control Register (XCR) Sample Rate Generator Register (SRGR) Control Register (PCR) Timing Diagram AC'97 Dual-Phase Frame Format List Tables Table McBSP AIC27 Interface Description Table Bit-Field Values McBSP Registers
Design Problem
multichannel buffered serial port (McBSP) TMS320C6000 used digital controller audio codec 1997 (AC'97) device?
Overview
McBSP operate digital controller audio codec device that compliant audio codec 1997 (AC'97) component specification. AC'97 standard specifies 5-wire digital serial link, "AC-Link", between audio codec device digital controller. Figure shows block diagram AC'97 system architecture. AC'97 device perform digital-to-analog conversion, analog-to-digital conversion, analog input mixing. supports different analog audio inputs/outputs communicate with digital controller through AC-Link, mentioned above. This application report discusses digital interface between AC'97 device, TLV320AIC27, McBSP TMS320C6000 digital controller. Analog input/output descriptions within scope this application report. (See Stereo Audio Codec data sheet (SLAS253) information concerning analog input/output audio codec.) Because TLV320AIC27 interface 3.3-V digital controller, voltage translation necessary interface McBSP AIC27. digital supply voltage, DVDD, AIC27 must
Link
C6000 McBSP Digital Controller
AC'97 Analog Analog Mixer Digital Interface
Analog Input Analog Output
Figure AC'97 System Architecture
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Solution
Hardware Interface
successfully McBSP audio codec digital controller, must configure five AC'97 signals: SYNC, SDATAOUT, RESETB, BITCLK, SDATAIN. audio codec AIC27 generates these AC'97 signals, BITCLK SDATAIN, which connected McBSP CLKS pins, respectively. McBSP generates remaining three AC'97 signals, SYNC, SDATAOUT, RESETB. Table summarizes signals this 5-wire digital serial link, AC-Link. audio codec device generates clock AC'97 interface. 24.576-MHz crystal connected TLV320AIC27 audio codec. AIC27 internally divides this fixed-rate clock signal factor produce 12.288-MHz clock signal output BITCLK pin. shown Figure this BITCLK signal connected CLKS McBSP used drive McBSP's sample rate generator. McBSP also derives frame sync signal from BITCLK. connected input SYNC AIC27. compliance with AC'97 protocol specification, must period McBSP sample rate generator BITCLK cycles generate frame sync signal every CLKS cycles, fixed rate kHz. width frame sync signal BITCLK cycles. period width frame sync signal defined FPER FWID fields sample rate generator register (SRGR) McBSP. SDATAOUT, SDATAIN pins AIC27 connected pins McBSP, respectively. McBSP receives transmits data dual-phase frames. each case, first phase consists 16-bit element; second phase consists twelve 20-bit elements. user configure receive transmit operation McBSP receive transmit control registers (RCR XCR). name implies, RESETB signal AIC27 resets audio codec brings TLV320AIC27 power-down mode. AC'97 standard specifies kinds reset-Cold AC'97 Reset Warm AC'97 Reset. Depending application, user freedom configure general-purpose outputs C6000 drive RESETB input AIC27. This application report shows TOUT0 general-purpose output McBSP RESETB signal AIC27. Figure shows 5-pin hardware interface between McBSP AC'97 audio codec. Table describes these AC-Link signals.
SYNC BITCLK SDATAOUT SDATAIN RESETB
C6000 McBSP AC'97 Compliant Controller
CLKS
TOUT0
TLV320AIC Digital Interface (AC-Link)
Figure Digital Interface Between McBSP AC'97 Device
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Table McBSP AIC27 Interface Description
C6000 McBSP (output) AIC27 SYNC (input) Description marks beginning each frame. generated McBSP fixed rate kHz. AIC27 generates BITCLK fixed rate 12.288 MHz. CLKS input clock McBSP's sample rate generator. Serial data goes from McBSP AIC27 device. Data captured AIC27 codec every falling edge BITCLK. Serial data goes from AIC27 codec McBSP. Data transmitted AIC27 codec every rising edge BITCLK. reset signal generated McBSP wakes AIC27 codec from power-down mode.
CLKS (input)
BITCLK (output)
(output)
SDATAOUT (input)
(input)
SDATAIN (output)
TOUT0 (output)
RESETB (input)
McBSP Register Configuration
setup programmable control registers McBSP McBSP AIC27 interface shown Figure through Figure Table lists describes register values interface. Note that although used hardware interface, FSRM field control register still must indicate that receive frame synchronization signals generated internally sample rate generator.
RPHASE Reserved RFRLEN1 RFRLEN2 0x0B RWDLEN1 RWDLEN2 RWDREVRS RFIG Reserved RDATDLY RCOMPAND
Figure Receive Control Register (RCR)
XPHASE Reserved XFRLEN1 XFRLEN2 0x0B XWDLEN1 XWDLEN2 XCOMPAND XWDREVRS XFIG Reserved XDATDLY
Figure Transmit Control Register (XCR)
GSYNC FWID 0x0F CLKSP CLKSM FSGM CLKGDV FPER 0xFF
Figure Sample Rate Generator Register (SRGR)
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Reserved 0x0000 Rsvd XIOEN RIOEN FSXM FSRM CLKXM CLKRM
Rsvd
CLKS_STAT
DX_STAT
DR_STAT
FSXP
FSRP
CLKXP
CLKRP
Figure Control Register (PCR) Table Bit-Field Values McBSP Registers
Register (Bit-Field No.) RCR[31] XCR[31] RCR[30:24] XCR[30:24] RCR[23:21] XCR[23:21] RCR[17:16] Field Name RPHASE XPHASE RFRLEN2 XFRLEN2 RWDLEN2 XWDLEN2 RDATDLY Value
Macro MCBSP_RCR_RPHASE_DUAL MCBSP_XCR_XPHASE_DUAL MCBSP_RCR_RFRLEN2_OF(0xB) MCBSP_XCR_XFRLEN2_OF(0xB) MCBSP_RCR_RWDLEN2_20BIT MCBSP_XCR_XWDLEN2_20BIT MCBSP_RCR_RDATDLY_1BIT
Function Description Dual phase receive frame Dual phase transmit frame Phase receive frame length elements Phase transmit frame length elements Phase receive elements bits Phase Transmit elements bits 1-bit receive data delay. phase data begins after BITCLK delay 1-bit transmit data delay. phase data begins after BITCLK delay Phase receive frame length element Phase transmit frame length element Phase receive elements bits Phase transmit elements bits Sample rate generator clock free running, driven external clock CLKS Sample rate generator clock derived from external clock source CLKS driven sample rate generator frame sync signal Frame period CLKS(12.288 MHz) periods 48-kHz FSX) Frame sync signal width BITCLK
XCR{17:16] RCR[14:8] XCR[14:8] RCR[7:5] XCR[7:5] SRGR[31]
XDATDLY RFRLEN1 XFRLEN1 RWDLEN1 XWDLEN1 GSYNC
MCBSP_XCR_XDATDLY_1BIT MCBSP_RCR_RFRLEN1_OF(0x0) MCBSP_XCR_XFRLEN1_OF(0x0) MCBSP_RCR_RWDLEN1_16BIT MCBSP_XCR_XWDLEN1_16BIT MCBSP_SRGR_GSYNC_FREE
SRGR[29]
CLKSM
MCBSP_SRGR_CLKSM_CLKS
SRGR[28]
FSGM
MCBSP_SRGR_FSGM_FSG
SRGR[27:16] SRGR[15:8]
FPER FWID
MCBSP_SRGR_FPER_OF(0xFF) MCBSP_SRGR_FWID_OF(0xF)
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Table Bit-Field Values McBSP Registers (Continued)
Register (Bit-Field No.) SRGR[7:0] PCR[11] PCR[10] PCR[3] Field Name CLKGDV FSXM FSRM FSXP Value
Macro MCBSP_SRGR_CLKDV_OF(0x0) MCBSP_PCR_FSXM_INTERNAL MCBSP_PCR_FSRM_INTERNAL MCBSP_PCR_FSXP_ACTIVEHIG MCBSP_PCR_FSRP_ACTIVEHIG
Function Description CLKG same frequency sample rate generator input clock CLKS Frame synchronization generated internally Frame synchronization generated internally active-high
PCR[2]
FSRP
active-high
bit-fields registers listed Table assume their default values. user responsible some register fields initial state different from default.
Timing Diagram
AC-Link architecture TLV320AIC27 audio codec employs dual-phase frame format. divides each 256-bit frame (both transmit receive) into phases. first phase 16-bit Phase. shown Figure audio output frame (SDATAOUT), where data goes from McBSP codec, first Phase Valid Frame bit. When Valid Frame one, indicates that there least slot containing valid data this frame. audio input frame (SDATAIN) where data goes from codec McBSP, first Phase indicates whether codec ready. next twelve bits Phase indicate whether there valid data corresponding slot second phase. second phase DATA Phase. DATA Phase consists twelve 20-bit slots, total transmission bits. These slots contain control audio data. (Refer Stereo Audio Codec data sheet (SLAS253) complete description frame contents.) Figure shows timing diagram this AC'97 dual-phase frame format.
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Phase bits
DATA Phase Slots Bits Bits
12.288MHz BITCLK (CLKS) SYNC (FSX)
cycle delay from SYNC
SDATAOUT (DX)
valid
Slot Slot
Slot
SDATAIN (DR)
Slot Slot
Slot
Slot
previous Audio Frame Transmission Phase data begins here Transmission DATA Phase data begins here
Slot
Slot
Slot
Figure Timing Diagram AC'97 Dual-Phase Frame Format signal, generated McBSP, synchronized rising edge BITCLK, sampled AIC27 falling edge BITCLK. phase data transfer begins immediately rising edge next BITCLK signal. this reason, RDATDLY XDATDLY bits registers, respectively, indicate BITCLK delay from rising edge beginning data transfer.
McBSP Initialization
Typically, EDMA (depending TMS320C6000 device used) service McBSP controlling internal data flow from McBSP. following steps describe procedures necessary initializing EDMA, McBSP, interrupts. Reset audio codec asserting AIC27 RESETB signal minimum 1us. this application report, C6000 general purpose output pin, TOUT0, used reset signal. McBSP reset state, XRST RRST SPCR Program McBSP configuration registers XCR, PCR, SRGR values shown Table GRST SPCR this step. Take sample rate generator (SRGR) reset setting GRST Hookup interrupt service routines EDMA (interrupt used EDMA transfers, interrupt used channel transfers, interrupt used channel transfers sample code provided). Enable interrupts that correspond EDMA channel that will used service McBSP. Note that EDMA controller generates single interrupt, CPU_INT8, (EDMA_INT) behalf channels (C621x/C671x) channels (C64x).
C6000 trademark Texas Instruments.
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
various control registers fields facilitate EDMA interrupt generation. default mapping channel-complete interrupts following: channel interrupt channel interrupt channel interrupt channel interrupt
Either should followed: used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses, their update modes, transfer complete interrupt, other feature suitable application. Lastly, START bit. START state waits synchronization events occur. Wake AIC27 codec setting AIC27 RESETB signal inactive-high. BITCLK AIC27 starts running after some delay. BITCLK drives McBSP's sample rate generator clock CLKG. Then, pull McBSP reset (Set XRST RRST enable McBSP). FRST start frame sync generator McBSP. first frame sync signal (FSX) generated McBSP after CLKG clocks. This signal captured AIC27 codec falling edge BITCLK. SDATAIN SDATAOUT transmitted next rising edge BITCLK. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Applications (SPRA529). enhanced (EDMA) used perform data transfers, channels associated McBSP transmit receive synchronization events should first configured with appropriate priority levels, element size, src/dst addresses, address update modes, transfer complete code, transfer-complete interrupt enable, source destination dimensions, other feature suitable application PaRAM parameter fields. events latched event register (ER), even events disabled. Enabling corresponding event event enable register (EER) starts data transfer setting this Wake AIC27 codec setting AIC27 RESETB signal inactive-high. BITCLK AIC27 starts running after some delay. BITCLK drives McBSP's sample rate generator clock CLKG. Then, pull McBSP reset (Set XRST RRST enable McBSP). FRST start frame sync generator McBSP. first frame sync signal (FSX) generated McBSP after CLKG clocks. This signal captured AIC27 codec falling edge BITCLK. SDATAIN SDATAOUT transmitted next rising edge BITCLK. details EDMA initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Enhanced DMA: Example Applications (SPRA636).
Sample Functions
Appendix contains sample code that sets TMS320C6000 digital controller audio codec 1997 device. (The TMS320C6000 Chip Support Library Reference Guide (SPRU401) provides detailed description header files Hardware Abstraction Language Macros used this code.) This code been tested specially configured Texas Instruments TMS320C6000 board connecting McBSP ports together, McBSPs AC'97 device, emulate presence AC'97 device interfaced McBSP port, been tested using actual TMS320C6000 McBSP-TLV320AIC27 interface.
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Conclusion
McBSP function AC'97 digital controller correctly connecting just five signals. This AC'97 interface runs fixed-sample rate kHz. McBSP generates this 48-kHz SYNC signal FSX) dividing 12.288-MHz BITCLK input 256. Each audio frames consists phases. first phase 16-bit phase that defines portion AC'97 signal. second phase, which consists twelve 20-bit elements, defines 240-bit DATA Phase. With signals configured described this application report, TMS320C6000 operates AC'97 digital controller.
References
Audio Codec Component Specification, Revision 2.2, Intel Corporation, September 2000. Stereo Audio Codec (SLAS253). TMS320C6000 Peripherals Reference Guide (SPRU190). TMS320C6211, TMS320C6211B Fixed-Point DSPs (SPRS073). TMS320C6203 Fixed-Point Digital Signal Processor (SPRS086). TMS320C6000 McBSP Initialization (SPRA488). TMS320C6000 Enhanced DMA: Example Applications (SPRA636). TMS320C6000 Chip Support Library Reference Guide (SPRU401).
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Appendix
ac97codec.c V1.00 6/12/01:
Sample Source Code AIC27 Interface
Copyright 2001 Texas Instruments Incorporated
Vassos Soteriou
ac97codec.c: This program sets McBSP TMS320C6000 devices digital controller Audio Codec 1997 device. This program supports Texas Instruments TMS320C6000 DSPs, those that controller Enhanced controller (EDMA). those that controller, channels service McBSP. CLKX, CLKR generated using CLKS clock. output that drives codec's frame syncs. case transfer, vecs.asm assembly code file used hookup c_int11() c_int09() ISRs corresponding interrupts. Channel hooked interrupt data receive, channel hooked interrupt data transmit, controller individual interrupts each channel. EDMA controller, however, generates single interrupt (EDMA_INT) behalf channels (C621x/C671x) channels (C64x). various control registers fields facilitate EDMA interrupt generation. CPU_INT8 responsible EDMA channels sample code based TI's 2.0. Please refer TMS320C6000 Chip Support Library User's Guide further information. Chip definition, change this accordingly #define CHIP_6415 Include files #include <c6x.h> #include <csl.h> #include <csl_dma.h> #include <csl_edma.h> #include <csl_irq.h> #include <csl_mcbsp.h> #include <csl_timer.h> library DMA_SUPPORT EDMA_SUPPORT IRQ_SUPPORT
MCBSP_SUPPORT TIMER_SUPPORT
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Define constants #define FALSE #define TRUE #define DMA_AC97 #define XFER_TYPE DMA_AC97 #define BUFFER_SIZE #define ELEMENT_COUNT change this, AC'97 protocol #define FRAME_COUNT Change this desired value Global variables used interrupt ISRs volatile recv0_done FALSE; volatile xmit0_done FALSE; Declare objects MCBSP_Handle hMcbsp0; (DMA_SUPPORT) DMA_Handle hDma1; DMA_Handle hDma2; #endif (EDMA_SUPPORT) EDMA_Handle hEdma1; EDMA_Handle hEdma2; EDMA_Handle hEdmadummy; #endif TIMER_Handle hTimer0; Handle TIMER0 External functions function prototypes void init_mcbsp0_ac97(void); void set_interrupts_dma(void); void set_interrupts_edma(void); Inlcude vector table call ISRs hookup extern void vectors(); main() void main(void) Declaration local variables static element_count, frame_count, xfer_type; delay_count Function prototypes Handles EDMA Handles Handles McBSP
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
static Uint32 dmaInbuff[BUFFER_SIZE]; static Uint32 dmaOutbuff[BUFFER_SIZE]; static Uint32 edmaInbuff[BUFFER_SIZE]; static Uint32 edmaOutbuff[BUFFER_SIZE];
buffer supporting devices
buffer EDMA supporting devices
IRQ_setVecs(vectors); point vector table element_count ELEMENT_COUNT; frame_count FRAME_COUNT; xfer_type XFER_TYPE; initialize library CSL_init(); Reset AC97 device Handle TIMER reset upon open hTimer0 TIMER_open(TIMER_DEV0, TIMER_OPEN_RESET); TIMER_setDataOut(hTimer0,0); TIMER_start(hTimer0); init_mcbsp0_ac97(); Enable sample rate generator MCBSP_enableSrgr(hMcbsp0); switch (xfer_type) case DMA_AC97: (DMA_SUPPORT) DMA_reset(INV); #endif (EDMA_SUPPORT) EDMA_clearPram(0x00000000); set_interrupts_edma(); #endif channels config structures (DMA_SUPPORT) Channel receives data hDma1 DMA_open(DMA_CHA1, DMA_OPEN_RESET); DMA_configArgs(hDma1, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE, DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_ENABLE, TCINT Handle channel supporting devices EDMA supporting devices Clear PaRAM EDMA supporting devices reset channels GRST=1 Handle SRGR Write TOUT0 Need least usec
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
DMA_PRICTL_PRI_DMA, DMA_PRICTL_WSYNC_NONE, DMA_PRICTL_RSYNC_REVT0, DMA_PRICTL_INDEX_NA, DMA_PRICTL_CNTRLD_NA,
high priority
synchronization event REVT1=01111
DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_DSTDIR_INC, DMA_PRICTL_SRCDIR_NONE, DMA_PRICTL_START_STOP DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, DMA_SECCTL_RSPOL_NA, DMA_SECCTL_FSIG_NA, DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_NOTHING, DMA_SECCTL_WSYNCSTAT_CLEAR, DMA_SECCTL_RSYNCCLR_NOTHING, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, DMA_SECCTL_FRAMEIE_DISABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR DRR)), DMA_DST_RMK((Uint32)dmaInbuff), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, number elements transfer /*only available 6202 6203 devices /*only available 6202 6203 devices /*only available 6202 6203 devices Element size bits Increment destination element size
frame_count) Optionally replace above lines with
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
Channel transmits data hDma2 DMA_open(DMA_CHA2, DMA_OPEN_RESET); DMA_configArgs(hDma2, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE, DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, DMA_PRICTL_WSYNC_XEVT0, DMA_PRICTL_RSYNC_NONE, DMA_PRICTL_INDEX_NA, DMA_PRICTL_CNTRLD_NA, DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_DSTDIR_NONE, DMA_PRICTL_SRCDIR_INC, DMA_PRICTL_START_STOP DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, DMA_SECCTL_RSPOL_NA, DMA_SECCTL_FSIG_NA, DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_NOTHING, DMA_SECCTL_WSYNCSTAT_CLEAR, DMA_SECCTL_RSYNCCLR_NOTHING, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, /*only available 6202 6203 devices /*only available 6202 6203 devices /*only available 6202 6203 devices Increment source element size Element size bits high priority synchronization event XEVT0=01100 Handle channel
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
DMA_SECCTL_FRAMEIE_DISABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR DXR)), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, number elements transfer frame_count) Optionally replace above lines with: set_interrupts_dma(); Initialize interrupts DMA_start(hDma1); DMA_start(hDma2); #endif supporting devices EDMA channels config structures (EDMA_SUPPORT) EDMA supporting devices Start channels
hEdma1 EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, (!C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(13), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO Destination increment element size Enable Transfer Complete Interrupt TCCINT 0xD, REVT0 Enable linking NULL table High priority EDMA Element size bits
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
#endif (C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(13), EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO #endif DRR)), DRR0 EDMA_CNT_RMK(0, frame_count element_count),/* elements Optionally replace above with following line EDMA_CNT_RMK(frame_count, element_count), addr edmaInbuff EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdma2 EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma2, #if(!C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, Source increment element size High priority EDMA Element size bits 671X 621x devices Enable linking NULL table Destination increment element size Enable Transfer Complete Interrupt TCCINT 0xD, REVT0 High priority EDMA Element size bits
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(12), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO #endif #if(C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(12), EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO #endif
Enable Transfer Complete Interrupt TCCINT 0xC, XEVT0 Enable linking NULL table
devices only High priority EDMA Element size bits Source increment element size
Enable Transfer Complete Interrupt TCCINT 0xC, XEVT0
Enable linking NULL table
/*src edmaOutbuff Optionally replace above with following line EDMA_CNT_RMK(frame_count, element_count), DXR)), addr DXR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0)
EDMA_CNT_RMK(0,frame_count element_count), elements
hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, 0x00000000, 0x00000000, 0x00000000, Terminate EDMA transfers linking this NULL table
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
0x00000000, 0x00000000 EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event EDMA_link(hEdma2, hEdmadummy); EDMA_enableChannel(hEdma1); EDMA_enableChannel(hEdma2); #endif make sure TOUT0 usec EDMA supporting devices Enable EDMA channels
(delay_count delay_count delay_count++); TIMER_setDataOut(hTimer0,1); wait BITCLK start (delay_count delay_count <100 delay_count++); MCBSP_enableRcv(hMcbsp0); Enable McBSP channel Write TOUT0
MCBSP_enableXmt(hMcbsp0); McBSP port transmitter/receiver MCBSP_enableFsync(hMcbsp0); Enable frame sync McBSP
flag interrupt when transfer/receive done (DMA_SUPPORT) while (!xmit0_done !recv0_done); #endif flag interrupt when EDMA transfer/receive done Transfer completion interrupt flag when (EDMA_SUPPORT) while (!xmit0_done !recv0_done); #endif MCBSP_close(hMcbsp0); (DMA_SUPPORT) DMA_close(hDma1); DMA_close(hDma2); #endif (EDMA_SUPPPORT) EDMA_close(hEdma1); EDMA_close(hEdma2); EDMA_close(hEdmadummy); #endif TIMER_close(hTimer0); close TIMER close EDMA channels close McBSP port close channels
main, progam ends here
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
init_mcbsp0_ac97() MCBSP Config structure Setup MCBSP_0 transfers with AC97 codec*/ void init_mcbsp0_ac97(void) MCBSP_Config mcbspCfg0 (EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_DEFAULT, MCBSP_SPCR_SOFT_DEFAULT, MCBSP_SPCR_FRST_DEFAULT, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_DXENA_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_DEFAULT, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT fields SPCR default values fields SPCR default values
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
#endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_DUAL, MCBSP_RCR_RWDLEN2_20BIT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, MCBSP_RCR_RWDLEN1_16BIT, MCBSP_RCR_RWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_DUAL, MCBSP_RCR_RWDLEN2_20BIT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, MCBSP_RCR_RWDLEN1_16BIT #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DUAL, MCBSP_XCR_XWDLEN2_20BIT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XWDLEN1_16BIT, MCBSP_XCR_XWDREVRS_DEFAULT #endif 1-bit transmit data delay receive elements 16bits MCBSP_XCR_XFRLEN1_OF(0x0), frame length element Dual phase transmit frame MCBSP_XCR_XFRLEN2_OF(0xB), frame length elements 1-bit receive data delay MCBSP_RCR_RFRLEN1_OF(0x0), frame length element receive elements 16bits Dual phase receive frame MCBSP_RCR_RFRLEN2_OF(0xB), frame length elements receive elements bits*/ 1-bit receive data delay MCBSP_RCR_RFRLEN1_OF(0x0), frame length element receive elements 16bits Dual phase receive frame MCBSP_RCR_RFRLEN2_OF(0xB), frame length elements receive elements bits*/
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
(DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DUAL, MCBSP_XCR_XWDLEN2_20BIT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XWDLEN1_16BIT #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE, MCBSP_SRGR_CLKSP_DEFAULT, MCBSP_SRGR_CLKSM_CLKS, MCBSP_SRGR_FSGM_FSG, External clock source, CLKS, deriv CLKSM driven frame sync signal MCBSP_SRGR_FPER_OF(0xFF), Frame period CLKS 12.288MHz periods MCBSP_SRGR_FWID_OF(0xF), MCBSP_SRGR_CLKGDV_OF(0) (C64_SUPPORT) MCBSP_MCR_RMK( MCBSP_MCR_XMCME_DEFAULT, MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RMCME_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #else MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_DEFAULT, fields default values MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, only fields default values Frame sync signal width BITCLK Free running driven CLKS 1-bit transmit data delay receive elements 16bits MCBSP_XCR_XFRLEN1_OF(0x0), frame length element Dual phase transmit frame 20bit elements MCBSP_XCR_XFRLEN2_OF(0xB), frame length elements MCBSP_XCR_XCOMPAND_DEFAULT,
CLKG same freq. SRGR input clock CLKS
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
MCBSP_MCR_RMCM_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_RCER_RMK( MCBSP_RCER_RCEB_DEFAULT, MCBSP_RCER_RCEA_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_XCER_RMK( MCBSP_XCER_XCEB_DEFAULT, MCBSP_XCER_XCEA_DEFAULT #endif (C64_SUPPORT) MCBSP_RCERE0_RMK(0), MCBSP_RCERE1_RMK(0), MCBSP_RCERE2_RMK(0), MCBSP_RCERE3_RMK(0), #endif (C64_SUPPORT) MCBSP_XCERE0_RMK(0), MCBSP_XCERE1_RMK(0), MCBSP_XCERE2_RMK(0), MCBSP_XCERE3_RMK(0), #endif MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_DEFAULT, MCBSP_PCR_RIOEN_DEFAULT, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_INTERNAL, MCBSP_PCR_CLKXM_DEFAULT, MCBSP_PCR_CLKRM_DEFAULT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_ACTIVEHIGH, active high MCBSP_PCR_FSRP_ACTIVEHIGH, active high MCBSP_PCR_CLKXP_DEFAULT, Frame sync generated internally Frame sync generated internally Additional registers only Additional registers only fields XCER default values fields RCER default values
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
MCBSP_PCR_CLKRP_DEFAULT hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); McBSP port MCBSP_config(hMcbsp0, &mcbspCfg0); set_interrupts_dma() (DMA_SUPPORT) void set_interrupts_dma(void) IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT2); IRQ_disable(IRQ_EVT_DMAINT1); IRQ_clear(IRQ_EVT_DMAINT2); IRQ_clear(IRQ_EVT_DMAINT1); IRQ_enable(IRQ_EVT_DMAINT2); IRQ_enable(IRQ_EVT_DMAINT1); return; #endif set_interrupts_edma() (EDMA_SUPPORT) void set_interrupts_edma(void) IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(12); EDMA_intDisable(13); IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(12); EDMA_intClear(13); McBSP transmit event XEVT0 McBSP receive event REVT0 interrupts device supports EDMA INT11 INT9 interrupts device supports
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(12); EDMA_intEnable(13); return; #endif DATA TRANSFER COMPLETION ISRs vecs.asm hooks this interrupt void c_int11(void) xmit0_done TRUE; return; interrupt void c_int09(void) recv0_done TRUE; return; interrupt void c_int08(void) (EDMA_SUPPORT) (EDMA_intTest(12)) xmit0_done TRUE; EDMA_intClear(12); else (EDMA_intTest(13)) recv0_done TRUE; EDMA_intClear(13); clear CIPR future interrupts recognized #endif return; /*-----------------------End clear CIPR future interrupts recognized vecs.asm hooks this EDMA vecs.asm hooks this
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
FILENAME. vecs.asm DATE CREATED. 12/06/2000 LAST MODIFIED. 12/06/2000 Global symbols defined here exported this file .global _vectors .global _vector0 .global _vector1 .global _vector2 .global _vector3 .global _vector4 .global _vector5 .global _vector6 .global _vector7 .global _c_int08 .global _c_int09 .global _vector10 .global _c_int11 .global _vector12 .global _vector13 .global _vector14 .global _vector15 Global symbols referenced this file defined somewhere else. Remember that your interrupt service routines need referenced here. .ref _c_int00 This macro that instantiates entry interrupt service table. VEC_ENTRY .macro addr MVKL MVKH B0,*--B15 addr,B0 addr,B0 Hookup c_int11 main() Hookup c_int08 main() EDMA Hookup c_int09 main() Copyright 2000 Texas Instruments Incorporated. Rights Reserved
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
SPRA528A
.endm
*B15++,B0
This dummy interrupt service routine used initialize IST. _vec_dummy:
This actual interrupt service table (IST). properly aligned located subsection .text:vecs. This means don't explicitly specify this section your linker command file, will default link into .text section. Remember ISTP register point this table. .sect ".text:vecs" .align 1024 _vectors: _vector0: _vector1: _vector2: _vector3: _vector4: _vector5: _vector6: _vector7: _vector8: _vector9: _vector10: _vector11: _vector12: _vector13: _vector14: _vector15: VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _c_int08 VEC_ENTRY _c_int09 VEC_ENTRY _vec_dummy VEC_ENTRY _c_int11 VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy VEC_ENTRY _vec_dummy Hookup c_int11 main() Hookup c_int08 main() EDMA Hookup c_int09 main()
vecs.asm
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27)
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Hansbauer Rebecca Vassos Soteriou ABSTRACT This document describes mul

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