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TMS320C6000 McBSP Interface ST-BUS Device
Jamon Bowen Shaku Anjanaiah ABSTRACT This document describes multichannel buffered serial ports (McBSPs) Texas Instruments TMS320C6000 digital signal processor (DSP) used communicate single-rate Serial Telecom (ST)-BUS-compliant device. McBSP receives framing signal, clock, data from ST-BUS device processes them generate internal frame syncs clocks correct data reception. highly programmable features McBSP make easy interface ST-BUS signals. This application report focuses single rate ST-BUS, wherein ST-BUS system clock data rate (number bits second) equal. Hence, name "single rate", which applies only 2.048 system clock. usage McBSP registers sample code perform above function described this document. Contents Design Problem ST-BUS Requirements McBSP Operation ST-BUS McBSP Register Configuration McBSP Initialization Sample Code Setup References List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure McBSP Connection 2.048-MHz Single-Rate Single-Rate ST-BUS Example Double-Rate ST-BUS Timing Diagram Receive Control Register (RCR) Sample Rate Generator Register (SRGR) Control Register (PCR) Serial Port Control Register (SPCR) ST-BUS Emulator McBSP Timing Diagram Example Single Rate ST-BUS Setup List Tables Table Field Values McBSP Registers
TMS320C6000 trademark Texas Instruments Incorporated. ST-BUS trademark Mitel. trademarks property their respective owners.
Digital Signal Processing Solutions
SPRA511B
Design Problem
multichannel buffered serial port TMS320C6201 communicate single-rate ST-BUS-compliant device?
ST-BUS Requirements
ST-BUS1 synchronous serial with data transfer rates 2.048, 4.096, 8.192 Mbps. interface ST-BUS device comprises clock, frame, data signals. These signals available McBSP programmable, thereby making glueless interface. ST-BUS data stream comprises frames with period frame rate 8000 frames sec. This sampling rate (twice highest signal frequency order retain information stream) corresponds voice band frequency. frame signal indicates start frame each frame carries blocks 8-bit data. clocks ST-BUS data 2.048, 4.096, 8.192, 16.384 MHz. Note that these clocks always twice data rate, except 2.048 MHz. Since 2.048 ST-BUS clock rate also data rate, referred single-rate ST-BUS. example double-rate ST-BUS would 2.048 Mbps data stream, clocked 4.096MHz clock. following sections describe hardware software interface C6000 McBSP single rate ST-BUS device.2
McBSP Operation ST-BUS
ST-BUS-compliant device that McBSP interfacing master frames clock. This means that ST-BUS device should provide 2.048 clock, which becomes external clock source McBSP CLKS pin. Also, framing signal, generated ST-BUS device, used receive frame sync (FSR) input McBSP. data transmitted ST-BUS device, received McBSP. These connections shown Figure
ST-BUSCompliant Device C6000 McBSP CLKS
Figure McBSP Connection 2.048-MHz Single-Rate
Mitel application note MSAN-126, ST-BUS Generic Device Specification (Rev. recommended that familiar with features C6000 McBSP reading TMS320C6000
Peripheral Reference Guide (SPRU190), especially section 12.5.5.
TMS320C6000 McBSP Interface ST-BUS Device
SPRA511B
order McBSP recognize ST-BUS data stream, GSYNC sample rate Generator register must set. ST-BUS-provided frame sync, FO,is active-low signal that one-half CLKS period. GSYNC causes external frame sync that arrives sampled rising edge CLKS and, turn, generates internal frame sync McBSP that active-high CLKS clock period. This internal frame sync, FSR_int, used reference data reception. This shown Figure
4.096 Sampled CLKS 2.048
External FS(R/X)_INT, CLK(R/X)_INT (First FSR) D(R/X) (First FSR) CLK(R/X)_INT (Subsequent FSR) D(R/X) (Subsequent FSR) ExBy Element E1B7 E1B6 E1B5 E1B0 E2B7
E32B0
E1B7
E1B6
E1B5
E1B0
E2B7
Figure Single-Rate ST-BUS Example 2.048 single-rate ST-BUS example shown Figure data stream comprises elements bits each, each frame. Each frame starts with frame sync signal, Since McBSP receiver does know when first frame will arrive FSR, therefore does know when reset receive data, special interrupts should used. This made easy with frame sync interrupt that available McBSP, which works even when receiver reset. receive interrupt (RINT) programmed detect frame sync pulse, after which safely take receiver reset. Further initialization details discussed section this document. case double-rate ST-BUS clock, 4.096, 8.192, 16.38-MHz clocks supported with data rates equal half ST-BUS clock rate. ST-BUS clock drives CLKS McBSP. frame sync provided ST-BUS (FO) active-low ST-BUS clock period, drives McBSP. This external frame sync sampled McBSP falling edge CLKS generate required internal frame sync. timing diagram double rate ST-BUS clock shown Figure
TMS320C6000 McBSP Interface ST-BUS Device
SPRA511B
Sampled CLKS=4.096/8.192 /16.384 External FS(R/X)_INT, CLK(R/X)_INT (First FSR) D(R/X) (First FSR) CLK(R/X)_INT (Subsequent FSR) D(R/X) (Subsequent FSR) ExBy Element E32B0 E1B7 E1B6 E1B5 E1B0 E2B7 E1B7 E1B6 E1B5 E1B0 E2B7
Figure Double-Rate ST-BUS Timing Diagram McBSP register setup double-rate operation same single rate, with following exceptions:
CLKGDV that data rate half clock rate (CLKS). CLKSP ensures that internal clocks CLKG, CLKR_int, CLKX_int generated falling edge CLKS; same edge that generates FSG, FSR_int, FSX_int.
McBSP Register Configuration
shown Figure FSR, CLKS, inputs.
Framing Signal: polarity incoming frame sync signal (FO) must inverted provide necessary active-high input signal McBSP. external frame sync pulse dictates arrival frame; therefore, frame period (FPER) frame width (FWID) used/programmed. Although treated input, FSRM FRST SPCR must FRST must enable frame sync signal generation. FSRM indicates that internally generated FSR_int will used detect arrival data, will output because GSYNC disables output buffer. Since single-phase frame, with each frame comprising elements with bits each, FRLEN1 WDLEN1
Data Delay: Since there delay between arrival first data generation internal frame sync FSR_int, receiver should data delay zero. Clocks: Although CLKR McBSP used this necessary configure output. Another important parameter polarity CLKS signal. CLKS polarity determines edge that samples incoming frame sync signal also edge that generates internal clocks CLKG, CLKR_int, CLKX_int, internal frame-sync signals FSG, FSR_int, FSX_int. single-rate ST-BUS case, rising edge CLKS does above function.
TMS320C6000 McBSP Interface ST-BUS Device
SPRA511B
various settings above requirements shown Figure through Figure Table
RPHASE
Legend: Read
RFRLEN2 RFRLEN1
RWDLEN2 RWDLEN1
RCOMPAND
RFIG
RDATDLY
Figure Receive Control Register (RCR)
GSYNC
CLKSP
CLKSM
FSGM
FPER
0x00 CLKGDV
FWID
Figure Sample Rate Generator Register (SRGR)
0x0000 R/W-0 XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP
CLKRP
Legend: Read; Read/write
Figure Control Register (PCR)
0x00 RJUST CLKSTP R/W-0
FRST
GRST R/W-0
XIN5 RIN
XSYNCERR
XEMPTY RFULL
XRDY RRDY
XRST RRST
R/W-0
RSYNCERR
Legend: Read/write
Figure Serial Port Control Register (SPCR)
TMS320C6000 McBSP Interface ST-BUS Device
SPRA511B
Table Field Values McBSP Registers
Register (Bit Field No.) RCR[17:16] SPCR[5:4] SPCR[23] SPCR[22] SRGR[31] SRGR[29] SRGR[7:0] PCR[10] PCR[8] PCR[2] Field Name RDATDLY RINFRST GRST GSYNC CLKSM CLKGDV FSRM CLKRM FSRP Value Binary) Slave (Receiver) (default) (default) (default)
McBSP Initialization
Typical applications (E)DMA service McBSP. Please refer TMS320C6000 McBSP Initialization (SPRA488) program McBSP control registers (E)DMA registers proper serial port operation. addition this, following step required since frame sync interrupt used wake McBSP. After (E)DMA been started, first frame sync that arrives will wake receiver. This done corresponding CPU_INT15. interrupt service routine (ISR) should also disable this interrupt, that subsequent frame syncs cause unnecessary enabling receiver that already been taken reset. When next frame sync arrives, receiver provides read sync event (E)DMA, which causes transfer data from specified destination address. receiver continues receive data until required number frames been received.
Sample Code Setup
example code included with this document tested McBSPs (McBSP0 McBSP1) TMS320C6211 device. block diagram this test setup shown Figure
TMS320C6000 McBSP Interface ST-BUS Device
SPRA511B McBSP0 ST-BUS Emulator FSX0 CLKS0 McBSP1 ST-BUSCompliant FSR1 CLKS1
fsx_in fsx_out 2.048 CLKS
Figure ST-BUS Emulator McBSP McBSP0 configured ST-BUS transmitter (master), which provides frame sync data. ST-BUS clock this example 2.048 MHz. uses FSX0 (fsx_in) generate active-low frame sync signal, fsx_out, appropriate rising edge CLKS 0/1. Signal fsx_out equivalent FSR_ext signal, shown Figure equations VHDL included with this document. resulting signals, above shown Figure
CLKS
FSX0/fsx_in
FSR1/fsx_out FSR1_int /FSG1_int RDATDLY1=0 XDATDLY0=1 DX0/DR1 E1B7 E1B6 E1B5
Figure Timing Diagram Example Single-Rate ST-BUS Setup
References
Mitel application note, MSAN-126, ST-BUS Generic Device Specification (Rev. TMS320C6000 Peripherals Reference Guide (SPRU190). TMS320C6000 McBSP Initialization (SPRA488).
TMS320C6000 McBSP Interface ST-BUS Device
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