Shaku Anjanaiah Scott Tater Digital Signaling Processing Solutions
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TMS320C6000 McBSP Highway
Shaku Anjanaiah Scott Tater Digital Signaling Processing Solutions
ABSTRACT This document describes multichannel buffered serial ports (McBSP) TMS320C6000digital signal processors (DSP) used communicate time-division multiplexed (TDM) data highway. provides multiple devices time slot perform data transfer. Thus, multiple users operate various channels; however, each user channel(s) assigned transmission reception. McBSP support channels multichannel mode. Each these channels enabled disabled software communicate only those necessary time slots. When multiple users connected same data lines, contention issue during transmission. Although each device connected this highway channel assignment, possible that next device getting onto contend with last bit(s) previous channel. workaround data contention problem addressed this document considering multiple McBSPs connected single data line. This document presents three workarounds applicable different C6000devices.
Contents Design Problem Application Multichannel Operation Overview Multichannel Selection Mode (All C6000 devices) Enhanced Multichannel Selection Mode (C64x only) Problem Description Solution Overview Solution Dummy Channel Insertion (Recommended C620x/C670x) 5.1.1 Transmission 5.1.2 Reception 5.1.3 McBSP Initialization Solution DXENA (Recommended C621x/C671x) Solution DXENA Enhanced Multichannel Selection Mode (Recommended C64x) Conclusion
Appendix Sample Code
TMS320C6000 C6000 trademarks Texas Instruments.
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Multiple McBSPs Time-Division Multiplexed Sub-Frames, Partitions, Channels Multichannel Frame Timing Multichannel Operation Three DSPs Dummy Channel Used Prevent Contention Timing Multichannel Operation Three DSPs with DXENA Three DSPs With DXENA Enhanced Multichannel Mode List Tables Table Table Table Table Table Table Channel Enable Bits RCEREx/XCEREx) 128-Channel Data Stream Switching Characteristics Output C6201 McBSP Data Transmission Setup Data Reception Setup Data Transmission Hardware Solution Data Reception Hardware Solution
Design Problem
multichannel buffered serial port (McBSP) communicate over time-division multiplexed (TDM) data highway without contention?
C6000 McBSP C6000 McBSP
Highway
C6000 McBSP
Figure Multiple McBSPs Time-Division Multiplexed
Application
Multiple DSPs connected single communicate specific information specific group DSPs. Typical applications would messaging, broadcasting passing channels processed data required DSPs further processing data input. data transfer achieved using programmable McBSP DMA. serial port pins used data transfer, whereas CLK(R/X) FS(R/X) serve control signals clocking synchronization. responsible retrieving data from McBSP receiver storing in_buffer. then process in_buffer data required make available out_buffer write transmitter.
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important configure each send receive channels data certain assigned time slots. This arrangement ensures proper allocation data particular channels retrieval this data required DSP. Since there address lines used, multichannel operation McBSP helps identifying destination data transit. DSP-specific messages sent known channel, destination listens this channel enabling appropriate receive channel enable bit(s).
Multichannel Operation Overview
McBSP perform multichannel selection operation single-phase frames. Single-phase frames characterized group elements that have same element size. maximum number elements frame same number channels, which equal 128. Therefore, each frame represents time-division multiplexed data stream with channels. C6000 devices capable implementing highway using multichannel serial port have potential transmit receive from channels. C64xMcBSP supports enhanced multichannel mode that allows greater channel selection flexibility requires fewer resources transmit receive over large number channels.
Multichannel Selection Mode (All C6000 devices)
C6000 devices, programmable control registers McBSP specific multichannel operation makes communication highway possible. They Multichannel Control Register (MCR), Transmit Channel Enable Register (XCER), Receive Channel Enable Register (RCER). These registers explained detail TMS320C6000 Peripherals Reference Guide (SPRU190). channels frame divided into eight 16-channel sub-frames shown Figure Each channel have programmable data sizes (8-, 12-, 16-, 20-, 32-bits). channels frame have same data size. Odd-numbered sub-frames constitute Partition (represented (R/X)PABLK), even-numbered belong Partition (represented (R/X)PBBLK). Each channels enabled disabled both transmit receive. This achieved 32-bit (R/X)CER register. Therefore, channels enabled consecutive sub-frames, Partition Partition Channels enabled disabled time long does belong current active) sub-frame. active sub-frame viewed that time slot where transmission reception taking place. example, data transfer ongoing sub-frame (channels 32-47 (R/X)PABLK=1), lower 16-bits channel enable registers (which correspond Partition should changed since they would affect enabling current channels. This ensured using current block status bits (R/X)CBLK MCR.
C64x trademark Texas Instruments.
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SUB-FRAME (R/X)PABLK PARTITION (R/X)PBBLK PARTITION FS(R/X)
0-15
32-47
64-79
97-111
0-15
16-31
48-63
80-95
112-127
Figure Sub-Frames, Partitions, Channels Multichannel Frame
Enhanced Multichannel Selection Mode (C64x only)
C64x series McBSP includes enhanced multichannel selection mode that enables greater channel allocation flexibility, allowing channels selected given time. This mode accessed through bits MCR, enhanced receive multichannel selection enable (RMCME) enhanced transmit multichannel selection enable (XMCME). This mode also adds enhanced receive/transmit enable registers (RCERE1, RCERE2, RCERE3, XCERE1, XCERE2, XCERE3) C64x McBSP. XCER RCER become XCERE0 RCERE0 respectively when enhanced mode enabled. enhanced multichannel mode, registers RCERE0-RCERE3 XCERE0-XCERE3 used enable channels. Thus, values (R/X)PABLK (R/X)PBBLK don't cares. Table shows channel enable bits 128-channel data stream. Table Channel Enable Bits RCEREx/XCEREx) 128-Channel Data Stream
Channel Number 128-Channel Data Stream 0-15 16-31 RCERE0 XCERE0 R/XCE16 R/XCE31 32-47 RCERE1 XCERE1 R/XCE32 R/XCE47 RCERE1 XCERE1 R/XCE48 R/XCE63 64-79 RCERE2 XCERE2 R/XCE64 R/XCE79 80-95 RCERE2 XCERE2 R/XCE80 R/XCE95 96-111 RCERE3 XCERE3 R/XCE96 R/XCE111 112-127 RCERE3 XCERE3 R/XCE112 R/XCE127 RCERE0 XCERE0 R/XCE0 R/XCE15
Register
Channel
Problem Description
When multiple devices transmit over same line, care should taken avoid contention simultaneous overlapped write accesses more devices. Contention during transmission avoided ensuring enough dead time between last write device first write access next device. avoid data collision, disable time (tdis(CKXH-DXZ)) output should much smaller than enable delay time (td(CKXH-DX)) output next device. This shown Tdead Figure defined Tdead td(CKXH-DX) tdis(CKXH-DXZ)
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CLKX tdis(CKXH-DXZ) Tdead td(CKXH-DX) CPU0: CPU2: Bit(n-1) td(CKXH-DX) CPU2: Bit(n-2) td(CKXH-DX) CPU2: Bit(n-3)
Figure Timing Multichannel Operation timing parameters their values C6000 McBSP output, datasheet, shown Table inferred from timing numbers McBSP that delay time disable time same. Therefore, there contention McBSPs transmit successive channels. following sections will describe workaround this problem using C6000 devices. Table Switching Characteristics Output C6201 McBSP
tdis(CKXH-DXZ) tdis(CKXH DXZ) PARAMETER Disable time, CLKX high high edance impedance following last data Delay time, valid after CLKX high. first data bit, this assured design delay time data become impedance. CLKX CLKX CLKX CLKX UNIT
td(CKXH-DX) td(CKXH
Solution Overview
contention problem lack control output buffer's turn-on (delay) turn-off (disable) time. This application report shows three solutions problem. Solution 1-dummy channel insertion-is applicable C6000 devices. Solution 2-DXENA-is recommended C621x/C671x. Solution 3-DXENA plus enhanced multichannel selection mode-is optimal solution C64x operations.
Solution Dummy Channel Insertion (Recommended C620x/C670x)
Contention avoided programming McBSP transfer extra (dummy) element channel than what necessary. This additional (dummy) channel should disabled XCER register since does represent data interest. disabled channel high-impedance state. dummy channel will provide necessary dead time between transfers from McBSPs thus prevent contention. Consider example where McBSP each three DSPs connected bus, shown Figure Assume that DSP1 clock frame master. result, DSP1 generates transmit receive clocks transmit receive frame syncs. Figure D(R/X)00 represents D(R/X) pins McBSP0 DSP0. Similarly D(R/X)01 D(R/X)02 correspond McBSP0 DSP1 DSP2. this example, DX00 occupies sub-frame DX01 occupies sub-frame DX02 occupies sub-frames receive side, DR00 listens sub-frame DR01 receives channels sub-frame lastly, DR02 receives sub-frames
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DSP0
DSP2
DR00 16-31, 48-71
DX00 ch0-15, dummy
DR02 0-15, 16-31
DX02 48-71 dummy
Highway
DX01 17-31
DR01 0-15, 48-63
DSP1 Clock Frame Master
Figure Three DSPs actual channels time slots) which each McBSPs transmit receive listed Table Table respectively. this available channels considered data transfer. Among these channels, only some enabled transmission reception. this example, some channels sub-frame enabled, whereas sub-frame corresponding channels 32-47 used therefore disabled. selectively choose channels, appropriate multichannel mode chosen. this example, XMCM RMCM will suit application. (R/X)MCM mode disables channels default. required channels enabled 16-channel sub-frames (R/X)P(A/B)BLK channel enable registers (R/X)CER.
5.1.1
Transmission
Since DSP1 clock frame master, will programmed generate frame sync every channels. frame period (FPER) depends serial element size frame number elements channels frame. DSP0 DSP2 slaves therefore will start their respective data transfer upon receiving frame clock from master DSP1.
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Table Data Transmission Setup
DSP# Sub-frame/ XP(A/B)BLK Sub-frame XPABLK XPBBLK Channels Transmitted Sub-frame channels: 0-15 Enabled channels (XPABLK): 0-15 Dummy channel: Disabled channels: others Sub-frame channels: 16-31 Enabled channels (XPBBLK): 20-23, 25,27, 28-31 Disabled channels: others Sub-frame channels: 48-63 64-79 Enabled channels (XPBBLK): 52-54, Enabled channels (XPABLK): 64-70 Dummy channel: Disabled channels: others Register Value
DSP#0 DX00
XCER 0x0000FFFF
DSP#1 DX01
Sub-frame XPBBLK
XCER 0xFAFA0000
DSP#2 DX02
Sub-frames XPBBLK XPABLK
XCER 0xB55B007F
Assume transmit receive data delay frame sync from master initiates data transmission DSP0, since DSP0 enabled transmission channels 0-15. first data available clock after frame sync active. same time, DSP1 DSP2 enabled receive some channels sub-frame Note that more than device receive same channel(s). next sub-frame (channels 16-31), DSP1 transmits starting from channel DSP0 programmed (channels 0-16) serial elements, last element will disabled that will driven high-impedance state. This configuration occurs because channel dummy channel prevent contention between DSP0
CLKX XDATDLY Tdea Ch71:Bn-B0 Ch70: Dummy (CPU Channel Ch0:(n-1) Dummy (CPU Channel Tdea Ch16:(n Ch17:(n-1) Dummy (CPU Channel Ch71:Bn-B0
Figure Dummy Channel Used Prevent Contention transmission reception continues enabled channels channel After channel transmitted DSP2, next frame starts channel This configuration occurs because FPER programmed ((data-size bits -1), also because data delay provides gaps between frames, which known maximum packet frequency. Since channel enabled, this again leads successive channels (channel channel being driven resulting contention. Therefore, channel dummy channel must disabled.
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5.1.2
Reception
receive section DSP0, receive channel interest without restrictions overlapping channels, shown Table Note, however, that DSP0 receives channels from sub-frames Sub-frame belong partition (RPBBLK) sub-frame RPABLK. Note that channels enabled sub-frame cannot changed when current transfer. Therefore, when DSP0 receiver sub-frame with particular channels enabled (via RCER RPBBLK RCER cannot changed ready next sub-frame which falls under same partition. Before sub-frame arrives, receiver should enabled appropriate channels (56, this case). this, current block status bits RCBLK multichannel control register (MCR) probed find current partition progress. RCBLK does point block then RCER programmed channel enabling sub-frame This also done transmit side using XCBLK, required. Table Data Reception Setup
DSP#
Sub-frame/ RP(A/B)BLK Sub-frames RPBBLK RPBBLK RPABLK Sub-frames RPABLK RPBBLK
Channels Received Sub-frame channels: 16-31, 48-63, 64-71 Enabled channels (RPBBLK): Enabled channels (RPBBLK): Enabled channels (RPABLK): 64-70 Disabled channels: others Sub-frame channels: 0-15, 48-63 Enabled channels (RPABLK): Enabled channels (RPBBLK): 52-54, Disabled channels: others Sub-frame channels: 0-15, 16-31 Enabled channels (RPABLK): 0-15 Enabled channels (RPBBLK): 20-23, 28-31 Disabled channels: others
Register Value
DSP#0 DR00
RCER 0x0A000000 RCER 0x05000000 RCER 0x0000007F
DSP#1 DR01
RCER 0xB05B00FF
DSP#2 DR02
Sub-frames RPABLK RPBBLK
RCER 0xF0FAFFFF
5.1.3
McBSP Initialization
typical applications, consider that (C620x/C670x) EDMA (C621x/C671x/C64x) services McBSP. McBSP initialization procedure other typical applications described TMS320C6000 McBSP Initialization (SPRA488). following steps describe setup interrupts, EDMA, McBSP required order example above: DSP0, DSP1, DSP2 McBSP0: Program sample rate generator register (SRGR), serial port control register (SPCR), control register (PCR), receive control register (RCR), multichannel control register (MCR) receive/transmit channel enable registers ((R/X)CER) required values. Caution: GRST SPCR this step. Take DSP1's sample rate generator reset setting GRST SPCR. GRST required DSP0 since clocks frames inputs. Therefore, sample rate generator used McBSP0.
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Enabling Interrupts: interrupts, have global interrupt enable (GIE), non-maskable interrupt enable (NMIE) bits IER. receiver DSP0, end-of-subframe interrupt (RIN= 01b) used determine 16-channel sub-frame, thereby change channel enabling odd- even-numbered sub-frame (see first Table DMA: Select channel want use. Enable interrupts corresponding channel that will used service McBSP. default mapping channel-complete interrupts used. EDMA: EDMA channels 12-15 each associated with specific McBSP transfer event. Unlike controller, EDMA interrupt shared channels. Choose EDMA channels based McBSP use. Enable EDMA interrupt CPU. initialization: Program source/destination registers primary control register required operation. Configure R/WSYNC fields primary control register receive requests from McBSP event-synchronized operation desired. EDMA initialization: EDMA initialization similar except that configuration data written parameter entry instead memory-mapped register. Configure event enable register (EER) desired receive requests from McBSP. Instruct necessary. example, START channel's primary control register start without auto-initialization. When McBSP synchronization events enabled, EDMA will respond automatically McBSP. Take transmitter receiver slave DSPs reset. They will await clock (CLKR/X) frame sync (FSR/X) from master DSP1. Take transmitter receiver master (DSP0) reset. FRST DSP1. This causes first frame sync output FS(R/X) after 8-bit clocks.
Solution DXENA (Recommended C621x/C671x)
C621x/C671x/C64x series devices provides hardware method control output buffer, called enabler (DXENA). DXENA field serial port control register (SPCR) controls high impedance enable pin. When DXENA turn-on time gains additional delay equal clock cycles. Because DXENA delay independent from data transmission, information seen Highway unchanged. only change that occurs when DXENA that amount time transmitter's first presented line decreased. Figure shows this extra delay time.
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CLKX
Extra delay DXENA (processor Disable time (processor Dead time
extra de;ay even with DXENA
(processor
(processor1)
(processor
Figure Timing Multichannel Operation Let's reconsider previous example with DXENA will keep same three DSPs used Figure with DSP1 clock frame master. There longer need insert wasted dummy channels. Notice that dummy channels used carry data. Figure summarizes channel assignments. enabler ensures that only transmitter active time; thus, dummy channels needed.
DSP0
DSP2
DR00 16-31, 48-71
DX00 ch0-16
DR02 0-15, 16-31
DX02 48-71
Highway
DX01 17-31
DR01 0-15, 48-63
DSP1 Clock Frame Master
Figure Three DSPs with DXENA
Solution DXENA Enhanced Multichannel Selection Mode (Recommended C64x)
third solution available C64x users. addition normal multichannel mode, this device adds enhanced multichannel mode features DXENA. Table Table have also been updated Table Table respectively, with channel assignment information. Enhanced multichannel mode eliminates need (R/X)P(A/B)BLK fields, these shown don't cares table. There need poll update these fields access multiple blocks.
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DSP0
DSP2
DR00 16-71
DX00 ch0-16
DR02 0-15, 16-31
DX02 48-71
Highway
DX01 17-31
DR01 0-16, 48-63
DSP1 Clock Frame Master
Figure Three DSPs With DXENA Enhanced Multichannel Mode Table Data Transmission Hardware Solution
DSP# DSP#0 DX00 Channels Transmitted Enabled channels: 0-16 Dummy channel: None Disabled channels: others Register Value XCERE0 0x0001FFFF XCERE1 0x00000000 XCERE2 0x00000000 XCERE3 0x00000000 XCERE0 0xFAFA0000 XCERE1 0x00000000 XCERE2 0x00000000 XCERE3 0x00000000 XCERE0 0x00000000 XCERE1 0xB57BFFFF XCERE2 0x000000FF XCERE3 0x00000000
DSP#1 DX01
Enabled channels: 20-23, 25,27, 28-31 Disabled channels: others
DSP#2 DX02
Enabled channels: 32-49, 51-54, 63-71 Dummy channel: None Disabled channels: others
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Table Data Reception Hardware Solution
DSP# DSP#0 DR00 Channels Received Enabled channels: 16,17, 19-23, 64-71 Disabled channels: others Register Value RCERE0 0x8AFB0000 RCERE1 0x05000000 RCERE2 0x000000FF RCERE3 0x00000000 RCERE0 0x000000FF RCERE1 0xB07B0000 RCERE2 0x00000000 RCERE3 0x00000000 RCERE0 0xF0FAFFFF RCERE1 0x00000000 RCERE2 0x00000000 RCERE3 0x00000000
DSP#1 DR01
Enabled channels: 0-7, 52-54, Disabled channels: others
DSP#2 DR02
Enabled channels: 0-15, 20-23, 28-31 Disabled channels: others
Notice that McBSP initialization steps remain same before with exceptions: DXENA SPCR step one; RINdoes have step three since subframes necessary enhanced multichannel mode.
Conclusion
Multiple C6xdevices connected multi-processor environment with them clock frame master. This achieved using time-division multiplexing McBSP interface through multichannel mode. Along with standard multichannel mode, additional solutions possible with certain C6000 family members. enabler C621x/C671x/C64x allows increased efficiency eliminating dummy channels, C64x enhanced multichannel mode improves channel selection flexibility while decreasing operational complexity.
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Appendix
Sample Code
Copyright 2000 Texas Instruments Incorporated. Rights Reserved
FILENAME. XXXXXXXX DATE CREATED. 11/28/2000 This program demonstrates McBSP multichannel mode based v2.0. Functions used configure EDMA service McBSP included. This program relies DSP/BIOS handle hardware software interupts. These interupts service Ping Pong buffers maintain count active frame multichannel operation. #include <std.h> #include <swi.h> #include <log.h> #include <clk.h>
#include <csl.h> #include <csl_cache.h> #include <csl_edma.h> #include <csl_dma.h> #include <csl_irq.h> #include <csl_mcbsp.h>
declare DSP/BIOS objects created with configuration tool extern SWI_Obj SwiMain; extern LOG_Obj LogMain; extern SWI_Obj swiProcess; extern LOG_Obj trace;
Pick which EDMA transfer completion interrupt want #define TCCINTNUM
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define some constants #define BUFF_SZ ping-pong buffer sizes ints
#define BUFF_SZ_DR #define BUFF_SZ_DX #define EDMA_EIX #define FCPU #define SRATE #define TPRD 150000000 8000 clock frequency data sample rate (simulated w/timer
(FCPU/(4*SRATE)) timer period
Create buffers. want align buffers cache friendly aligning them cache line boundary. #pragma DATA_ALIGN(pingDX,128); #pragma DATA_ALIGN(pongDX,128); #pragma DATA_ALIGN(pingDR,128); #pragma DATA_ALIGN(pongDR,128);
pingDX[BUFF_SZ]; pingDR[BUFF_SZ]; pongDX[BUFF_SZ]; pongDR[BUFF_SZ];
These variables serve data sources this example. Also want align these cache line boundary since they sources EDMA transfers. #pragma DATA_ALIGN(ping_data,128); #pragma DATA_ALIGN(pong_data,128); static ping_data; static pong_data;
global variable used track ping-pong'ing static pingpong i=0;
declare some objects (EDMA_SUPPORT) EDMA_Handle hEdmaDR; EDMA_Handle hEdmaDX; Handle EDMA channel Handle EDMA channel
EDMA_Handle hEdmaPing; Handle ping EDMA reload parameters
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EDMA_Handle hEdmaPong; Handle pong EDMA reload parameters EDMA_Config cfgEdma; EDMA configuration structure
EDMA_Handle hEdmaPingDR; Handle ping EDMA reload parameters EDMA_Handle hEdmaPongDR; Handle pong EDMA reload parameters EDMA_Config cfgEdmaDR; EDMA configuration structure
EDMA_Handle hEdmaPingDX; Handle ping EDMA reload parameters EDMA_Handle hEdmaPongDX; Handle pong EDMA reload parameters EDMA_Config cfgEdmaDX; #endif EDMA configuration structure
(DMA_SUPPORT) DMA_Handle hDmaDR; DMA_Handle hDmaDX; #endif
MCBSP_Handle hMcbsp;
Handle McBSP
Function prototype section void run_dma(); void run_edma(); void run_mcbsp(); void hwiEdmaIsr(int arg); void HWI_rpblk(int arg); void swiProcessFunc(); used track subframes multichannel mode
void main(){
initialize library CSL_init();
initialize input source data ping_data=0x00000000; pong_data=0x80000000;
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(i=0;i<BUFF_SZ; i++) pongDX[i]=i; pingDX[i]=i; pongDR[i]=0xF; pingDR[i]=0xF;
(EDMA_SUPPORT) run_edma(); #endif
#if(DMA_SUPPORT) run_dma(); #endif run_mcbsp();
void swiProcessFunc(){
*inbuff; *outbuff;
(pingpong){ pingpong then ping input buffer inbuff pingDR; outbuff pingDX; }else{ pingpong then pong input buffer inbuff pongDR; outbuff pongDX;
let's process input buffer, simplicity, we'll just copy output buffer. (x=0; x<BUFF_SZ; x++) outbuff[x] ping_data+x;
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ping_data++;
(EDMA_SUPPORT) this example enhanced actually something with output buffer such somewhere, will want flush cache first.
Since we're done processing input buffer, clean from cache, this invalidates from cache ensure read fresh version next time. #endif
void HWI_rpblk(int arg) This called after every McBSP subframe changing inactive RCER XCER, channels enabled LOG_printf(&trace,"Here where modify XCER RCER"); void hwiEdmaIsr(int arg){ Perform ping-pong pingpong (pingpong
(DMA_SUPPORT) Clear pending condition from secondary control register #endif
(EDMA_SUPPORT) Clear pending interrupt from EDMA interrupt pending register EDMA_intClear(TCCINTNUM);
Based ping'ed pong'ed, need EDMA channel link address NEXT frame. (pingpong){ filling pong link ping EDMA_link(hEdmaDR,hEdmaPingDR);
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EDMA_link(hEdmaDX,hEdmaPingDX); else{ filling ping link pong EDMA_link(hEdmaDR,hEdmaPongDR); EDMA_link(hEdmaDX,hEdmaPongDX); #endif Notify that just ping-pong'ed SWI_post(&swiProcess); void run_mcbsp() create config structure McBSP static MCBSP_Config ConfigLoopback (EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_NO, MCBSP_SPCR_GRST_NO, MCBSP_SPCR_XINTM_FRM, MCBSP_SPCR_XSYNCERR_NO, MCBSP_SPCR_XRST_NO, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_DISABLE, MCBSP_SPCR_DXENA_ON, MCBSP_SPCR_RINTM_FRM, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_NO MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, MCBSP_RCR_RFRLEN2_OF(0), MCBSP_RCR_RWDLEN2_8BIT, MCBSP_RCR_RCOMPAND_MSB, MCBSP_RCR_RFIG_YES, MCBSP_RCR_RDATDLY_0BIT, MCBSP_RCR_RPHASE2_NORMAL, MCBSP_RCR_RFRLEN1_OF(31), MCBSP_RCR_RWDLEN1_32BIT,
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MCBSP_RCR_RWDREVRS_DISABLE MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(0), MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XDATDLY_0BIT, MCBSP_XCR_XPHASE2_NORMAL, MCBSP_XCR_XFRLEN1_OF(31), MCBSP_XCR_XWDLEN1_32BIT, MCBSP_XCR_XWDREVRS_DISABLE #endif (DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_NO, MCBSP_SPCR_GRST_NO, MCBSP_SPCR_XINTM_FRM, MCBSP_SPCR_XSYNCERR_NO, MCBSP_SPCR_XRST_NO, MCBSP_SPCR_DLB_ON, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_DISABLE, MCBSP_SPCR_RINTM_EOS, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_NO MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, MCBSP_RCR_RFRLEN2_OF(0), MCBSP_RCR_RWDLEN2_8BIT, MCBSP_RCR_RCOMPAND_MSB, MCBSP_RCR_RFIG_YES, MCBSP_RCR_RDATDLY_0BIT, MCBSP_RCR_RFRLEN1_OF(31), MCBSP_RCR_RWDLEN1_32BIT MCBSP_XCR_RMK(
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MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(0), MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XDATDLY_0BIT, MCBSP_XCR_XFRLEN1_OF(31), MCBSP_XCR_XWDLEN1_32BIT #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE, MCBSP_SRGR_CLKSP_RISING, MCBSP_SRGR_CLKSM_INTERNAL, MCBSP_SRGR_FSGM_DXR2XSR, MCBSP_SRGR_FPER_OF(1023), MCBSP_SRGR_FWID_OF(127), MCBSP_SRGR_CLKGDV_OF(15) MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_SF1, MCBSP_MCR_XPABLK_SF0, MCBSP_MCR_XMCM_DISXP, MCBSP_MCR_RPBBLK_SF1, MCBSP_MCR_RPABLK_SF0, MCBSP_MCR_RMCM_ELDISABLE MCBSP_RCER_RMK( /*Change RCER reflect desired enabled receive channels
/*Example: Enable recv channs 31,30,28,27,26,25,23,22,19,17 Partition /*and recv channels 15,14,12,11,10,9,1,0 Partition
/*(Note that BUFF_SZ_DR should change reflect channels enabled*/ //MCBSP_RCER_RCEB_OF(0xDE03), //MCBSP_RCER_RCEA_OF(0xDECA), /*Default enable channels MCBSP_RCER_RCEB_OF(0xFFFF), MCBSP_RCER_RCEA_OF(0xFFFF) MCBSP_XCER_RMK( Change XCER reflect desired enabled receive channels
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Example: enable xmit channels 15,13,10,8,7,5,2,1 Partition xmit channels 31,28,27,26,24,23,21,19,18,16 Partition
(Note that BUFF_SZ_DX should change reflect channels enabled/ //MCBSP_XCER_XCEB_OF(0x9DAD), //MCBSP_XCER_XCEA_OF(0xA5A6) /*Default enable channels MCBSP_XCER_XCEB_OF(0xFFFF), MCBSP_XCER_XCEA_OF(0xFFFF) MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_SP, MCBSP_PCR_RIOEN_SP, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_EXTERNAL, MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_INPUT, MCBSP_PCR_CLKSSTAT_0, MCBSP_PCR_DXSTAT_0, MCBSP_PCR_DXSTAT_0, MCBSP_PCR_FSRP_ACTIVEHIGH, MCBSP_PCR_CLKXP_RISING, MCBSP_PCR_CLKRP_FALLING
Let's open serial port hMcbsp MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
We'll digital loopback, 32bit mode. have setup sample rate generator allow self clocking.
/*Configure McBSP Receive interupt /*We'll this count subframes enable channels multichannel mode IRQ_disable(IRQ_EVT_RINT1); IRQ_clear(IRQ_EVT_RINT1); IRQ_map(IRQ_EVT_RINT1,11); that port setup, let's enable steps. MCBSP_enableRcv(hMcbsp); MCBSP_enableXmt(hMcbsp);
TMS320C6000 McBSP Highway
SPRA491A
MCBSP_enableSrgr(hMcbsp); IRQ_enable(IRQ_EVT_RINT1); (DMA_SUPPORT) void run_dma() Uint32 Uint32 Uint32 Let's perform simple data copy from buffer another. start, need open channel. Let's channel also reset upon opening. hDmaDR hDmaDX /*Use allocate registers /*Use address registers reload ping buffer after each frame /*Use index register advance from ping pong /*Use count register reload transfer control register GblAddr0 GblAddr1 GblIdx0 (Uint32)pingDR (BUFF_SZ_DR 4)<<16)| GblCnt0 <<16) BUFF_SZ_DR));
Generate discrete parameters using 'make' macros PriCtlDR DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_OF(GblAddr0), DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_ENABLE, DMA_PRICTL_PRI_CPU, DMA_PRICTL_WSYNC_NONE, DMA_PRICTL_RSYNC_REVT1, DMA_PRICTL_INDEX_OF(GblIdx0), DMA_PRICTL_CNTRLD_OF(GblCnt0),
TMS320C6000 McBSP Highway
SPRA491A
DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_DSTDIR_IDX, DMA_PRICTL_SRCDIR_NONE, DMA_PRICTL_START_STOP SecCtlDR DMA_SECCTL_RMK( DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_CLEAR, DMA_SECCTL_WSYNCSTAT_CLEAR, DMA_SECCTL_RSYNCCLR_CLEAR, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_DISABLE, DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, DMA_SECCTL_FRAMEIE_ENABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR SrcAddrDR DstAddrDR (Uint32)pingDR; XfrCntDR DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_OF(2),
PriCtlDX
DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE, DMA_PRICTL_SRCRLD_OF(GblAddr1), DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_DISABLE, DMA_PRICTL_PRI_CPU, DMA_PRICTL_WSYNC_XEVT1,
TMS320C6000 McBSP Highway
SPRA491A
DMA_PRICTL_RSYNC_NONE, DMA_PRICTL_INDEX_OF(GblIdx0), DMA_PRICTL_CNTRLD_OF(GblCnt0), DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_DSTDIR_NONE, DMA_PRICTL_SRCDIR_IDX, DMA_PRICTL_START_STOP SecCtlDX DMA_SECCTL_RMK( DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_CLEAR, DMA_SECCTL_WSYNCSTAT_CLEAR, DMA_SECCTL_RSYNCCLR_CLEAR, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_DISABLE, DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, DMA_SECCTL_FRAMEIE_DISABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR SrcAddrDX (Uint32)pingDX; DstAddrDX XfrCntDX DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_OF(2), Configure channels
TMS320C6000 McBSP Highway
SPRA491A
Configure interupt IRQ_disable(IRQ_EVT_DMAINT1); IRQ_clear(IRQ_EVT_DMAINT1); IRQ_map(IRQ_EVT_DMAINT1,8);
Start operation DMA_autoStart(hDmaDR); DMA_autoStart(hDmaDX);
/*Enable Interupt IRQ_enable(IRQ_EVT_DMAINT1); #endif
(EDMA_SUPPORT) void run_edma() Create EDMA configuration structure ping transfers EDMA_Config cfgEdmaPingDX EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_NONE, EDMA_OPT_TCINT_NO, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_SRC_OF(pingDX), EDMA_CNT_OF(BUFF_SZ_DX), EDMA_DST_OF(0), /*Will later using EDMA_IDX_OF(EDMA_EIX), EDMA_RLD_OF(0x00000000)
TMS320C6000 McBSP Highway
SPRA491A
Create EDMA configuration structure pong transfers EDMA_Config cfgEdmaPongDX EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_NONE, EDMA_OPT_TCINT_NO, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_SRC_OF(pongDX), EDMA_CNT_OF(BUFF_SZ_DX), EDMA_DST_OF(0), /*Will later using EDMA_IDX_OF(EDMA_EIX), EDMA_RLD_OF(0x00000000)
Create EDMA configuration structure ping transfers EDMA_Config cfgEdmaPingDR EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_SRC_OF(0), /*Will later using EDMA_CNT_OF(BUFF_SZ_DR), EDMA_DST_OF(pingDR),
TMS320C6000 McBSP Highway
SPRA491A
EDMA_IDX_OF(EDMA_EIX), EDMA_RLD_OF(0x00000000)
Create EDMA configuration structure pong transfers EDMA_Config cfgEdmaPongDR EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_SRC_OF(0), /*Will later using EDMA_CNT_OF(BUFF_SZ_DR), EDMA_DST_OF(pongDR), EDMA_IDX_OF(EDMA_EIX), EDMA_RLD_OF(0x00000000)
cfgEdmaPingDR.src MCBSP_getRcvAddr(hMcbsp); cfgEdmaPongDR.src MCBSP_getRcvAddr(hMcbsp); cfgEdmaPingDX.dst MCBSP_getXmtAddr(hMcbsp); cfgEdmaPongDX.dst MCBSP_getXmtAddr(hMcbsp);
Although required, let's clear EDMA parameter RAM. This makes easier view changes configure EDMA_clearPram(0x00000000);
Lets open EDMA channel associated with timer hEdmaDR EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET); hEdmaDX EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);
TMS320C6000 McBSP Highway
SPRA491A
also need EDMA reload parameters each buffers sets
let's allocate them here. Notice this means allocate availale tale.*/ hEdmaPingDR EDMA_allocTable(-1); hEdmaPongDR EDMA_allocTable(-1); hEdmaPingDX EDMA_allocTable(-1); hEdmaPongDX EDMA_allocTable(-1);
Let's copy ping reload configuration structure intermediate configuration structure. cfgEdmaDR cfgEdmaPingDR; cfgEdmaDX cfgEdmaPingDX;
Let's initialize link fields configuration structures cfgEdmaPingDR.rld cfgEdmaPongDR.rld cfgEdmaDR.rld
cfgEdmaPingDX.rld cfgEdmaPongDX.rld cfgEdmaDX.rld
let's program EDMA channel with configuration structure EDMA_config(hEdmaDR, &cfgEdmaPongDR); EDMA_config(hEdmaDX, &cfgEdmaPongDX);
Let's also configure reload parameter tables EDMA PRAM with values configuration structures. EDMA_config(hEdmaPingDR, &cfgEdmaPingDR); EDMA_config(hEdmaPongDR, &cfgEdmaPongDR); EDMA_config(hEdmaPingDX, &cfgEdmaPingDX); EDMA_config(hEdmaPongDX, &cfgEdmaPongDX);
Let's disable/clear related interrupts just case they pending fram previous program. IRQ_reset(IRQ_EVT_EDMAINT); EDMA_intDisable(TCCINTNUM); EDMA_intClear(TCCINTNUM);
TMS320C6000 McBSP Highway
SPRA491A
Enable EDMA channel EDMA_enableChannel(hEdmaDX); EDMA_enableChannel(hEdmaDR); Enable related interrupts IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(TCCINTNUM); #endif
TMS320C6000 McBSP Highway
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