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TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Shaku Anjanaiah Vassos Soteriou ABSTRACT This document describes interface multichannel buffered serial port (McBSP) TMS320C6000 digital signal processor (DSP) voice band audio processor (VBAP). VBAP under discussion TLV320AC56, 2.048 audio processor which µ-law companding device. interface also applicable TI's TLV320AC57, A-law companding audio processor. highly programmable McBSP provides glueless interface VBAP. VBAP processes analog signals from audio sources such microphone, converts digital data choices), which then transmitted processing. turn will transmit digital data VBAP conversion analog data. VBAP outputs this analog data device such speaker. McBSP supports both companded (8-bit) linear (16-bit) form data that VBAP supports. Digital Signal Processing Solutions
Contents Design Problem Overview VBAP Operation Hardware Interface McBSP Register Configuration McBSP VBAP Initialization Timing Analysis Conclusion List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure C6000 McBSP VBAP Interface Block Diagram C6000 VBAP Schematic Fixed Rate Data Mode Fixed Data Rate Mode Timing Diagram Receive Control Register (RCR) Transmit Control Register (XCR) Sample Rate Generator Register (SRGR) Control Register (PCR) Serial Port Control Register (SPCR) McBSP Timing Internal Clocks Frames
TMS320C6000 trademark Texas Instruments. other trademarks property their respective owners.
SPRA489A
List Tables Table McBSP Register Configuration Values Table Timing Analysis McBSP VBAP
Design Problem
interface voice-band audio processor (VBAP) TMS320C6000 multichannel buffered serial port (McBSP)?
Overview
block diagram interface between McBSP VBAP shown Figure analog voice-band input from microphone processed analog-to-digital converter (ADC) VBAP. either compresses analog signal 8-bit data format compand operation chosen VBAP) transforms analog data 13-bit linear data linear data format chosen) with three LSBs padded with zeroes volume control data. VBAP thus performs transmit encoding analog data provides digital data McBSP receiver. process digital data necessary. McBSP either transmit 8-bit companded data µ-law A-law format) 16-bit linear data receive section VBAP. digital-to-analog converter (DAC) VBAP expands serial data analog form sends speaker. both cases transmit receive, McBSP programmed either transmit companded data A-law format interfacing TLV320AC57 µ-law format interfacing TLV320AC56. µ-law A-law companding standards part CCITT G.711 recommendation.
C6000 8(compand)/ 16(linear) TLV320AC56/7 VBAP
Receiver
Compress
Microphone
8(compand)/ 16(linear)
Transmitter
Expand
Speaker
Figure C6000 McBSP VBAP Interface Block Diagram
VBAP Operation
VBAP offers pin-selectable modes operation:
Fixed Data Rate Mode: single master clock (CLK) used clock both receive transmit data. Data transmitted rising edge clock receive data sampled falling edge CLK. master clock frequency 2.048 MHz. frame sync
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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signal inputs, FSR, active high period indicate starting frame. Frame syncs must have 8KHz sampling rate.
Variable Data Rate Mode: received data sampled falling edge DCLKR transmit data output rising edge DCLKX. These clocks slower than master rate 2.048MHz. DCLKR DCLKX have range between 64KHz 2.048MHz 8-bit compand mode 128KHz 2.048Mhz 16-b linear data. master clock used clocking data, internal filters. inputs remain high entire frame remain 8KHz sampling rate.
More information VBAP itself obtained from following literature:
Designing with Voice-Band Audio Processor, Application Report, February 1999, Literature Number SLWA001 TLV320AC56, TLV320AC57 Voice-Band Audio Processors (VBAP) Data Sheet, June 1996 revised October 1997, Literature Number SLWS044
Hardware Interface
This application note describes fixed data rate mode VBAP interface McBSP. Accordingly, interface schematic this shown Figure Since VBAP device, voltage translation necessary interface McBSP. Also, electret type microphone speaker headset) should part. interface includes:
Clock Generation: 2.048 clock generator drives master clock, CLK, VBAP external clock CLKS McBSP. McBSP uses this external clock source with CLKGDV=0 generate internal transmit receive clocks shift data. CLKR CLKX McBSP should configured outputs. DCLKR should tied left unconnected (logic high) fixed data rate mode. Alternatively, timer used generate 2.048MHz shift clock using (CPU clock/4) timer clock source. 200MHz DSP, timer CLKSRC would 50MHz. timer used clock mode (50% duty cycle). derive period shift clock, timer period register value calculated follows: sclk_period Period_register) f(CLKSRC) Hence, period_register 2*20 approx.
Frame Sync Generation: McBSP generates 8KHz sampling rate frame sync signal. frame sync parameters, FPER FWID programmable McBSP. order generate period (8kHz) frame sync based 2.048 clock, frame period (/FPER) should clocks. Therefore, FPER 255. FWID zero since frame sync bit-clock high beginning frame. Note that (FPER+1) (FWID+1) represent actual values. Both driven same internal frame sync generator signal (FSG).
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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TLV320AC56/57 C6000 FSX1 FSR1 CLKX1 CLKR1 CLKS1
2.048MHz Clock Generator
DOUT DCLKR DCLKX LINSEL EARA VMID MICBIAS MICGS MICIN MICMUTE
3.3V
0.1uF
470pF
3.3uF Microphone
EARGS
Speaker
EARB EARMUTE
Note: (R1+R2) 100K; refer TLV320AC56/7 datasheet
Figure C6000 VBAP Schematic Fixed Rate Data Mode
Data Format: McBSP drives data receives data to/from VBAP either 8-bit compand format 16-bit linear format. /LINSEL VBAP when pulled enables data linear format. Accordingly (R/X)COMPAND McBSP should programmed receiving non-companded data. schematic shows /LINSEL being driven therefore controlled software. Electret Microphone Interface: electret-type microphone chosen this interface. most effective noise cancellation produces clear voice transmission (compared carbon dynamic type). passive components chosen this interface based information provided VBAP datasheet. Speaker Interface: resistor network schematic controlling power amplifier gain. parallel combination (R1+R2) load resistance (RL) sets total loading. VBAP datasheet more details. Power Down: active /PDN VBAP driven when reduced power consumption required VBAP use. inverted provide this control. Alternatively, simple switch connected /PDN will also suffice.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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McBSP Register Configuration
timing diagram applicable fixed data rate mode VBAP shown Figure master clock from 2.048 clock generator drives McBSP's CLKS VBAP's pin. CLKS drives bit-clocks CLKR CLKX with divide-downs McBSP data transfer. Frame syncs generated rising edge CLKR/CLKX. first data (MSB) transmitted/received with bit-clock delay from FSX/FSR compliant with Fixed Data Rate Mode. Therefore (R/X)DATDLY=1.
CLKS/CLK CLKR/CLKX FSX/FSR DX/DR C7/L15 C6/L14 C5/L13 C0/L8 C7/L15
Cx/Ly: CompandData LinearData
Figure Fixed Data Rate Mode Timing Diagram above functional requirements drive values programmable McBSP registers. Figure through Figure Table show register values application.
RPHASE
RFRLEN2
RWDLEN2
RCOMPAND
RFIG
RDATDLY
reserved
RFRLEN1
RWDLEN1
RWDREVRS
reserved
Figure Receive Control Register (RCR)
XPHASE XFRLEN2 XWDLEN2 XCOMPAND XFIG XDATDLY
reserved
XFRLEN1
XWDLEN1
XWDREVRS
reserved
Figure Transmit Control Register (XCR)
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
SPRA489A
GSYNC CLKSP CLKSM FSGM FPER 0xFF
FWID
CLKGDV
Figure Sample Rate Generator Register (SRGR)
reserved Rsvd XIOEN RIOEN FSXM FSRM CLKXM CLKRM Rsvd CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Figure Control Register (PCR)
0x00
FRST
GRST-
XIN0
XSYNCERR
XEMPTY-
XRDY
XRST
RIN0
RSYNCERR
RFULL
RRDY
RRST
RJUST
CLKSTP
Figure Serial Port Control Register (SPCR)
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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Table McBSP Register Configuration Values
Register
RCR[20:19] RCR[17:16] XCR[20:19] XCR[17:16] SRGR[28] SRGR[27:16] SRGR[15:8] SRGR[7:0] PCR[11] PCR[10] PCR[9] PCR[8] SPCR[31:0]
Bit-field
RCOMPAND RDATDLY XCOMPAND XDATDLY FSGM FPER FWID CLKGDV FSXM FSRM CLKXM CLKRM
Value
0xFF default
Macro
MCBSP_RCR_RCOMPAND_ULAW MCBSP_RCR_RDATDLY_1BIT MCBSP_XCR_XCOMPAND_ULAW MCBSP_RCR_XDATDLY_1BIT MCBSP_SRGR_FSGM_FSG MCBSP_SRGR_FPER_OF(0xFF) MCBSP_SRGR_FWID_OF(0x0) MCBSP_SRGR_FWID_OF(0x0) MCBSP_PCR_FSXM_INTERNAL MCBSP_PCR_FSRM_INTERNAL MCBSP_PCR_CLKXM_OUTPUT MCBSP_PCR_CLKRM_OUTPUT MCBSP_SPCR_(FIELD)_DEFAULT
Description
Receive µ-law companding bit-clock data delay Transmit µ-law companding bit-clock data delay generated Frame period 2.048Mhz clock periods 8KHz frame sync sampling rate Generates clock period active-high pulse. 2.048 CLKS drives CLKR/X with divide- down output output CLKX output generated CLKS CLKR output generated CLKS Reset bits will driven initialization procedure
McBSP VBAP Initialization
Typically EDMA (depending TMS320C6000 device used) service McBSP controlling internal data flow from McBSP. VBAP (except when McBSP reset) assumed powered before following steps taken. Power applied clock sources connected. /PDN VBAP driven send power-down state when needed. following steps describe setup interrupts, DMA/EDMA, McBSP required order. C64x, C621x C671x devices EDMA. C620x C670x devices DMA. McBSP initialization procedure using (E)DMA also discussed Application Report SPRA488, TMS320C6000 McBSP Initialization. McBSP reset state, /XRST=/RRST=0 SPCR. Program McBSP configuration registers XCR, PCR, SRGR values shown Table /GRST SPCR this step. Take sample rate generator (SRGR) reset setting /GRST=1 Either should followed: used: Hook channels interrupt service routines. sample code provided, channel hooked interrupt data receive channel hooked interrupt data transmit. interrupts that correspond channels that will used service McBSP should then enabled. default mapping channel-complete interrupts following: channel interrupt channel interrupt
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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channel interrupt
channel interrupt EDMA used: Hook EDMA channels interrupt service routine. Note that EDMA controller generates single interrupt, CPU_INT8, (EDMA_INT) behalf channels (C621x/C671x) channels (C64x). various control registers fields facilitate EDMA interrupt generation. Interrupt that going service McBSP transfers EDMA should then enabled. Either should followed: used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses, their update modes, transfer complete interrupt, other feature suitable application. Lastly, START bit. START state waits synchronization events occur. Wake VBAP pulling /PDN logic high state this done using software) Alternatively, this done after power (before step above) using switch. assumed here that appropriate /LINSEL value chosen desired operation. VBAP ready frame sync pulses from McBSP start transmission reception. Then, take McBSP reset (Set /XRST=/RRST=1 enable McBSP). /FRST start frame sync generator McBSP. This causes frame sync pulses FSX/FSR pins which eventually drive VBAP. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Applications (SPRA529). Enhanced (EDMA) used perform data transfers, channels associated McBSP transmit receive synchronization events should first configured with appropriate priority levels, element size, src/dst addresses, address update modes, transfer complete code, transfer complete interrupt enable, source destination dimensions, other feature suitable application PaRAM parameter fields. events latched event register (ER), even events disabled. Enabling corresponding event event enable register (EER) starts data transfer setting this `1'. Wake VBAP pulling /PDN logic high state this done using software) Alternatively, this done after power (before step above) using switch. assumed here that appropriate /LINSEL value chosen desired operation. VBAP ready frame sync pulses from McBSP start transmission reception. Then, pull McBSP reset (Set /XRST=/RRST=1 enable McBSP). /FRST start frame sync generator McBSP. This causes frame sync pulses FSX/FSR pins which eventually drive VBAP. details EDMA initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Enhanced DMA: Example Applications (SPRA636).
Timing Analysis
shown Figure C6000 VBAP Schematic Fixed Data Rate Mode, outputs McBSP driving VBAP. CLKR CLKX generated internally external clock source CLKS without divide-down. Figure shows timing relation transmit data frame sync, receive data frame sync with respect their respective clocks.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
SPRA489A
CLKX(int) td(CKXH-FXV) (int) tdis(CKXH-DXZ) CLKR(int) td(CKRH-FRV) (int) th(CKRL-DR) tsu(DR-CKRL) Bit(n-1) (n-2) td(CKXH-DX) Bit(n-1) (n-2)
Figure McBSP Timing Internal Clocks Frames timing analysis shown Table satisfies hardware interface requirements. timing numbers McBSP match with that VBAP with sufficient timing margins. timing numbers VBAP correspond TLV320AC56/37 datasheet, Literature Number SLWS044B. McBSP timings found C6000 datasheets. Table uses McBSP timing parameters from TMS320C6701 Floating-Point Signal Processor Data Sheet, Literature Number SPRS067E, 1998, revised 2000.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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Table Timing Analysis McBSP VBAP
VBAP Timing Requirements
(DIN)min Data Setup Time (DIN)min Data Hold Time (FSR)min Setup Time (FSR)min Hold Time (FSX)min Setup Time (FSX)min Hold Time
C6701 Switching Characteristics
td(CKXH-DXV)max 244.14 td(CKXH-DXV)min 244.14 td(CKXH-FXV)max 244.14 td(CKXH-FXV)min 244.14 td(CKRH-FRV)max 244.14 td(CKRH-FRV)min 244.14 240.14 240.14 240.14 239.14 242.14 240.14
Unit
C6701 Timing Requirements
tsu(DRV-CKXL)min Data Setup Time th(CKXL-DRV)min Data Hold Time
VBAP Switching Characteristics
tpd2(max) 244.14 tpd2(min) 244.14 244.14 209.14
NOTE: following true above calculations: Since CLKGDV CLK(R/X) derived from clock will have duty cycle. Therefore where represents clock high duration represents clock duration. Period CLK(R/X), 488.28 2.048 CLKS clock.
Conclusion
programmability McBSP provides ease interface VBAP. Although this application note only describes fixed data rate mode VBAP, equally simple interface variable-data rate mode. Variable data rate mode allows varying data rates maximum 2.048MHz. example code appendix shows McBSP0 initialization operation.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
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Appendix
Sample Source Code
mcbsp_to_vbap.c V1.00 Copyright 2001 Texas Instruments Incorporated Original Shaku Anjanaiah Modified Vassos Soteriou mcbsp_to_vbap.c: This program uses McBSP TMS320C6000 devices communicate with VBAP 8-bit ulaw companded fixed data rate mode. This program supports Texas Instruments TMS320C6000 DSPs, those that controller Enhanced controller (EDMA). those that controller, channels service McBSP. CLKX, CLKR generated using CLKS (external) clock. outputs that drive VPAB's frame syncs. case transfer, vecs.asm assembly code file used hookup c_int11() c_int09() ISRs corresponding interrupts. Channel hooked interrupt data receive, channel hooked interrupt data transmit, controller individual interrupts each channel. EDMA controller, however, generates single interrupt (EDMA_INT) behalf channels (C621x/C671x) channels (C64x). various control registers fields facilitate EDMA interrupt generation. CPU_INT8 responsible EDMA channels sample code based TI's 2.0. Please refer TMS320C6000 Chip Support Library User's Guide further information. Chip definition, change this accordingly #define CHIP_6202 Include files #include <c6x.h> #include <csl.h> #include <csl_dma.h> #include <csl_edma.h> #include <csl_irq.h> #include <csl_mcbsp.h>
library DMA_SUPPORT EDMA_SUPPORT IRQ_SUPPORT MCBSP_SUPPORT
Define constants #define FALSE #define TRUE #define #define #define #define DMA_VBAP XFER_TYPE DMA_VBAP BUFFER_SIZE BUFFER_SIZE should ELEMENT_COUNT ELEMENT_COUNT Number 8-bit datum transfer
Global variables used interrupt ISRs volatile recv0_done FALSE; volatile xmit0_done FALSE; Declare objects MCBSP_Handle hMcbsp0; (DMA_SUPPORT) DMA_Handle hDma1; DMA_Handle hDma2; #endif (EDMA_SUPPORT) Handles McBSP Handles
Handles EDMA
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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EDMA_Handle hEdma1; EDMA_Handle hEdma2; EDMA_Handle hEdmadummy; #endif External functions function prototypes void init_mcbsp0_vbap(void); Function prototypes void set_interrupts_dma(void); void set_interrupts_edma(void); Include vector table call ISRs hookup extern void vectors(); main() void main(void) Declaration local variables static element_count, xfer_type; static static static static Uint32 Uint32 Uint32 Uint32 dmaInbuff[BUFFER_SIZE]; buffer supporting devices dmaOutbuff[BUFFER_SIZE]; edmaInbuff[BUFFER_SIZE]; buffer EDMA supporting devices edmaOutbuff[BUFFER_SIZE];
IRQ_setVecs(vectors); point vector table element_count ELEMENT_COUNT; xfer_type XFER_TYPE; initialize library CSL_init(); init_mcbsp0_vbap(); Enable sample rate generator MCBSP_enableSrgr(hMcbsp0); switch (xfer_type) case DMA_VBAP: (DMA_SUPPORT) DMA_reset(INV); #endif supporting devices Reset channels GRST=1 Handle SRGR
(EDMA_SUPPORT) EDMA_clearPram(0x00000000); set_interrupts_edma(); #endif
EDMA supporting devices Clear PaRAM EDMA
channels config structures (DMA_SUPPORT) supporting devices
Channel receives data hDma1 DMA_open(DMA_CHA1, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma1, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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DMA_PRICTL_WSYNC_DEFAULT, DMA_PRICTL_RSYNC_REVT0, synchronization event REVT0=01101 DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_INC, Increment destination element size DMA_PRICTL_SRCDIR_DEFAULT, DMA_PRICTL_START_DEFAULT DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only available 6202 6203 devices DMA_SECCTL_RSPOL_NA, only available 6202 6203 devices DMA_SECCTL_FSIG_NA, only available 6202 6203 devices DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT DRR)), DMA_DST_RMK((Uint32)dmaInbuff), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, xfer element count Channel transmits data hDma2 DMA_open(DMA_CHA2, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma2, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority DMA_PRICTL_WSYNC_XEVT0, synchronization event XEVT0=01100 DMA_PRICTL_RSYNC_DEFAULT, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_DEFAULT, DMA_PRICTL_SRCDIR_INC, Increment source element size DMA_PRICTL_START_DEFAULT DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only available 6202 6203 devices DMA_SECCTL_RSPOL_NA, only available 6202 6203 devices DMA_SECCTL_FSIG_NA, only available 6202 6203 devices DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT,
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT DXR)), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, xfer element count set_interrupts_dma(); DMA_start(hDma1); DMA_start(hDma2); #endif initialize interrupts enable interrupts after channels opened DMA_OPEN_RESET clears disables channel interrupt once specified clears corresponding interrupt bits IER. This applicable EDMA channel open case Start channels
supporting devices
EDMA channels config structures (EDMA_SUPPORT) EDMA supporting devices
hEdma1 EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, (!C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(13), EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO #endif (C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(13), EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT,
High priority EDMA Element size bits
Destination increment element size Enable Transfer Complete Interrupt TCCINT 0xD, REVT0 Enable linking NULL table
High priority EDMA Element size bits
Destination increment element size Enable Transfer Complete Interrupt TCCINT 0xD, REVT0
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif DRR)), DRR0 EDMA_CNT_RMK(0, element_count), count equal element_count addr edmaInbuff EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdma2 EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma2, #if(!C64_SUPPORT) 671X 621x devices EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, Source increment element size EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(12), TCCINT 0xC, XEVT0 EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif #if(C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(12), EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO #endif edmaOutbuff EDMA_CNT_RMK(0, element_count), count equal element_count DXR)), addr DXR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, Terminate EDMA transfers linking 0x00000000, this NULL table 0x00000000, 0x00000000, 0x00000000, 0x00000000 devices only High priority EDMA Element size bits
Source increment element size
Enable Transfer Complete Interrupt TCCINT 0xC, XEVT0
Enable linking NULL table
EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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EDMA_link(hEdma2, hEdmadummy); EDMA_enableChannel(hEdma1); EDMA_enableChannel(hEdma2); Enable EDMA channels
#endif EDMA supporting devices switch here MCBSP_enableRcv(hMcbsp0); Enable McBSP0 rcv/xmt channel MCBSP_enableXmt(hMcbsp0); McBSP port transmitter/receiver
MCBSP_enableFsync(hMcbsp0); Enable frame sync generation McBSP0 flag interrupt when transfer/receive done (DMA_SUPPORT) while (!xmit0_done !recv0_done); #endif
flag interrupt when EDMA transfer/receive done Transfer completion interrupt flag when (EDMA_SUPPORT) while (!xmit0_done !recv0_done); #endif MCBSP_close(hMcbsp0); (DMA_SUPPORT) DMA_close(hDma1); DMA_close(hDma2); #endif close McBSP port close channels
(EDMA_SUPPPORT) EDMA_close(hEdma1); close EDMA channels EDMA_close(hEdma2); EDMA_close(hEdmadummy); #endif main, program ends here init_mcbsp0_vbap() MCBSP Config structure Setup MCBSP_0 transfers with VBAP void init_mcbsp0_vbap(void) MCBSP_Config mcbspCfg0 (EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_DEFAULT, fields SPCR default values MCBSP_SPCR_SOFT_DEFAULT, MCBSP_SPCR_FRST_DEFAULT, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_DXENA_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_DEFAULT, fields SPCR default values
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
SPRA489A
MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase receive frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_ULAW, ULAW companding MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, 1-bit receive data delay MCBSP_RCR_RFRLEN1_OF(0x0), frame length elements MCBSP_RCR_RWDLEN1_8BIT, receive elements bits MCBSP_RCR_RWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase receive frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_ULAW, ULAW companding MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, 1-bit receive data delay MCBSP_RCR_RFRLEN1_OF(0x0), frame length elements MCBSP_RCR_RWDLEN1_8BIT receive elements bits #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, Single phase transmit frame MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_ULAW, ULAW companding MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, 1-bit transmit data delay MCBSP_XCR_XFRLEN1_OF(0x0), frame length elements MCBSP_XCR_XWDLEN1_8BIT, receive elements 8bits MCBSP_XCR_XWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, Single phase transmit frame MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_ULAW, ULAW companding MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, 1-bit transmit data delay MCBSP_XCR_XFRLEN1_OF(0x0), frame length elements MCBSP_XCR_XWDLEN1_8BIT receive elements 8bits #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE, Free running driven CLKS MCBSP_SRGR_CLKSP_RISING, rising clock edge MCBSP_SRGR_CLKSM_CLKS, External clock source, CLKS, MCBSP_SRGR_FSGM_FSG, driven frame sync
derives CLKSM signal
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
SPRA489A
MCBSP_SRGR_FPER_OF(0xFF), MCBSP_SRGR_FWID_OF(0x0), MCBSP_SRGR_CLKGDV_OF(0x0) (C64_SUPPORT) MCBSP_MCR_RMK( MCBSP_MCR_XMCME_DEFAULT, MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RMCME_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #else MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_RCER_RMK( MCBSP_RCER_RCEB_DEFAULT, MCBSP_RCER_RCEA_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_XCER_RMK( MCBSP_XCER_XCEB_DEFAULT, MCBSP_XCER_XCEA_DEFAULT #endif (C64_SUPPORT) MCBSP_RCERE0_RMK(0), MCBSP_RCERE1_RMK(0), MCBSP_RCERE2_RMK(0), MCBSP_RCERE3_RMK(0), #endif Frame period CLKS 12.288MHz periods Frame width zero CLKG same freq. SRGR input clock CLKS
only fields default values
fields default values
fields RCER default values
fields XCER default values
Additional registers only
(C64_SUPPORT) MCBSP_XCERE0_RMK(0), MCBSP_XCERE1_RMK(0), MCBSP_XCERE2_RMK(0), MCBSP_XCERE3_RMK(0), #endif MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_DEFAULT, MCBSP_PCR_RIOEN_DEFAULT, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_INTERNAL, MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_OUTPUT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_ACTIVEHIGH, MCBSP_PCR_FSRP_ACTIVEHIGH, MCBSP_PCR_CLKXP_DEFAULT, MCBSP_PCR_CLKRP_DEFAULT
Additional registers only
output output
output output generated CLKS generated CLKS
active high active high
hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); McBSP port MCBSP_config(hMcbsp0, &mcbspCfg0);
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
SPRA489A
set_interrupts_dma() (DMA_SUPPORT) void interrupts set_interrupts_dma(void) device supports IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT2); IRQ_disable(IRQ_EVT_DMAINT1); INT11 INT9 IRQ_clear(IRQ_EVT_DMAINT2); IRQ_clear(IRQ_EVT_DMAINT1); IRQ_enable(IRQ_EVT_DMAINT2); IRQ_enable(IRQ_EVT_DMAINT1); return; #endif set_interrupts_edma() (EDMA_SUPPORT) void set_interrupts_edma(void) IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(12); EDMA_intDisable(13); IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(12); EDMA_intClear(13); IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(12); EDMA_intEnable(13); return; #endif DATA TRANSFER COMPLETION ISRs interrupt void vecs.asm hooks this c_int11(void) xmit0_done TRUE; return; interrupt void c_int09(void) recv0_done TRUE; return; vecs.asm hooks this interrupts device supports EDMA
McBSP transmit event XEVT0 McBSP receive event REVT0
interrupt void vecs.asm hooks this c_int08(void) EDMA (EDMA_SUPPORT) (EDMA_intTest(12)) xmit0_done TRUE;
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
SPRA489A
EDMA_intClear(12); clear CIPR future interrupts recognized else (EDMA_intTest(13)) recv0_done TRUE; EDMA_intClear(13); clear CIPR future interrupts recognized #endif return; /*-----------------------End
Copyright 2000 Texas Instruments Incorporated. Rights Reserved FILENAME. vecs.asm DATE CREATED. 12/06/2000 LAST MODIFIED. 12/06/2000 Global symbols defined here exported this file .global _vectors .global _vector0 .global _vector1 .global _vector2 .global _vector3 .global _vector4 .global _vector5 .global _vector6 .global _vector7 .global _c_int08 Hookup c_int08 main() EDMA .global _c_int09 Hookup c_int09 main() .global _vector10 .global _c_int11 Hookup c_int11 main() .global _vector12 .global _vector13 .global _vector14 .global _vector15 Global symbols referenced this file defined somewhere else. Remember that your interrupt service routines need referenced here. .ref _c_int00 This mcros that instantiates entry inetrrupt service table. VEC_ENTRY .macro addr B0,*--B15 MVKL addr,B0 MVKH addr,B0 *B15++,B0 .endm This dummy interrupt service routine used initialize IST. _vec_dummy:
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
SPRA489A
This actual interrupt service table (IST). properly aligned located subsection .text:vecs. This means don't explicitly specify this section your linker command file, will default link into .text section. Remember ISTP register point this table. .sect ".text:vecs" .align 1024 _vectors: _vector0: _vector1: _vector2: _vector3: _vector4: _vector5: _vector6: _vector7: _vector8: _vector9: _vector10: _vector11: _vector12: _vector13: _vector14: _vector15:
VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY
_vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _c_int08 _c_int09 _vec_dummy _c_int11 _vec_dummy _vec_dummy _vec_dummy _vec_dummy
Hookup c_int08 main() EDMA Hookup c_int09 main() Hookup c_int11 main()
vecs.asm
TMS320C6000 McBSP Voice Band Audio Processor (VBA) Interface
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Shaku Anjanaiah Vassos Soteriou ABSTRACT This document describes inter

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