Shaku Anjanaiah Brad Cobb ABSTRACT TMS320C6000 multichannel buffered s
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TMS320C6000 McBSP Initialization
Shaku Anjanaiah Brad Cobb ABSTRACT TMS320C6000 multichannel buffered serial port (McBSP) operate variety modes, application requirements. proper operation, serial port must initialized specific order. This document describes initialization steps necessary when either EDMA used service McBSP data. Typically, EDMA used perform read/write transfers from/to McBSP. EDMA transfers read/write synchronized, McBSP provides these synchronization events. Alternatively, cases where reads from writes DXR, either polled interrupt method used. Digital Signal Processing Solutions
Contents Design Problem McBSP Introduction Servicing McBSP Initialization Requirements McBSP Initialization Cases Using Chip Support Library (CSL) References List Figures Figure McBSP Functional Block Diagram Figure McBSP Initialization Flowchart
Appendix
Design Problem
initialize McBSP correct frame synchronization data exchange? What important initialization steps their order execution?
McBSP Introduction
main functional blocks McBSP shown Figure They are:
TMS320C6000 trademark Texas Instruments. trademarks property their respective owners.
SPRA488C
Transmitter: transmitter section responsible serial transmission data that written DXR. contents copied transmit shift register XSR. transfer starts soon transmit frame sync (FSX) detected. data transmitted shifted every transmit clock CLKX. data written using either EDMA. Receiver: data received shifted into receive shift register (RSR) every receive clock (CLKR). Again, actual shifting data begins after detection receive frame sync (FSR). data copied receive buffer register (RBR), then data receive register (DRR). read either EDMA. Sample Rate Generator: name implies, this module generates control signals such transmit/receive clocks frame sync signals necessary data transfer from McBSP. Clock generation circuitry allows user choose either clock external source CLKS generate CLK(R/X). Frame sync signal properties, such frame period frame width, also programmable. FS(R/X), CLK(R/X) bidirectional pins, therefore, inputs outputs. Events/Interrupt Generation: McBSP generates sync events EDMA indicate that data ready DRR, that ready data. They read sync event, REVT, write sync event, XEVT. Similarly read/write McBSP based interrupts (RINT XINT) generated McBSP.
C6000 McBSP CLKX Transmitter
CLKR Receiver
CPUclk CLKS Sample Rate Generator
CLKG
XEVT REVT Events/ Interrupts
XINT RINT
Figure McBSP Functional Block Diagram
TMS320C6000 McBSP Initialization
SPRA488C
Servicing McBSP
TMS320C6000 service McBSP EDMA. control registers have programmed CPU, data registers accessed either EDMA. Typically, EDMA channel(s) used read/write data registers, thus relieving from servicing slow peripheral. more details EDMA servicing peripheral, please refer application reports TMS320C6000 Applications (SPRA529) TMS320C6000 Enhanced DMA: Example Applications (SPRA636).
EDMA: EDMA write accesses write synchronization event, XEVT, provided McBSP. Similarly, EDMA read synchronized internal REVT signal from McBSP. Therefore, EDMA reads from writes McBSP every serial element transfer. Once EDMA completes required number element transfers, programmed generate channel-complete interrupt CPU, required. CPU: When used service McBSP, done either interrupt-driven method polled method. Polling method ties while waiting data transmitted received. (R/X)RDY bits SPCR polled receive/transmit ready condition McBSP.
interrupt-driven case, performs other processing while interrupts from McBSP signal when needs served. default value (R/X)IN= causes McBSP interrupt (R/X)INT every element transfer interrupts enabled. XINT generated when ready accept data, RINT generated when serial element been received DRR. Other interrupt mode settings (R/X)INare meant servicing McBSP data reads/writes, diagnostic tracking purposes.
Initialization Requirements
Generation control signals such clock, frame sync, clock source McBSP programmable. order which respective modules activated important correct operation McBSP. Consider, example, case when transmitter clock frame master meaning responsible generation clocks frames itself device (receiver) communicating first step ensure that slave this case receiver) awake (taken reset), ready receive frame data from transmitter. This followed taking transmitter reset, then activating frame sync generator transmitter. This ensures that receiver does lose first frame data.
C6000 trademark Texas Instruments.
TMS320C6000 McBSP Initialization
SPRA488C
McBSP Initialization Cases
This section describes step-by-step procedure McBSP initialization based EDMA data transfers. following three methods initialization procedure summarized flowchart shown Figure
EDMA transfers: following steps describe setup interrupts, EDMA, McBSP required order.
GRST=XRST=RRST=FRST=0. coming device reset, this required. Program sample rate generator register (SRGR), serial port control register (SPCR), control register (PCR), receive control register (RCR) required values. CAUTION: bits described Step while programming these registers. Take sample rate generator reset setting GRST=1 SPCR. Internal clock CLKG driven chosen clock source programmed clock divide-down. NOTE: frame syncs clocks inputs both transmit receive sections McBSP, this step required. Wait clocks (CLKR/X). simple formula arrive this number terms clock cycles clock source: P=(1/CPUclock). number clocks equal data bit-clocks (1+CLKGDV) where min. value CLKGDV CLKS clock source: Ps=(1/CLKS frequency) P=(1/CPUclock). number clocks equal data bit-clocks (1+CLKGDV) /P), where min. value CLKGDV CLKS greater than (CPUclock/2) general, following formula used depending clock source: ((1+CLKGDV) CLKSM) ((1+CLKGDV) (!CLKSM)) Enabling Interrupts: interrupts, have Global Interrupt Enable (GIE) Non-Maskable Interrupt Enable (NMIE) bits IER. DMA, select channel want use. Enable interrupts that correspond channel that will used service McBSP. These interrupts used notify frame. default mapping channel-complete interrupts follows: channel interrupt channel interrupt channel interrupt channel interrupt
TMS320C6000 McBSP Initialization
SPRA488C
EDMA, enable only interrupt EDMA_INT. When using EDMA must also select appropriate EDMA channels service McBSP. Select from channels 12-15 TMS320C621x/TMS320C671x devices from channels 12-15 17-18 TMS320C64x devices. transfers, stop condition. Clear previous R/WSTAT bits that unwanted transfers occur. EDMA initialization: Program EDMA channels required operation. following would typical Source address reads memory location writes. Destination address memory location reads writes. Transfer counter number elements transferred. Receive synchronization event, R/WSYNC REVT from McBSP reads. Transmit synchronization event, R/WSYNC XEVT from McBSP writes. channel complete interrupt bit, TCINT enabled Priority bit, optional, recommended. Instruct EDMA run. DMA, START=01b channel's primary control register start without auto-initialization. EDMA, EDMA event enable register that corresponds desired channel. Take section (transmitter/receiver) that frame master (frame sync input) reset setting XRST RRST slave ready accept frame sync start data transfer. Alternatively, frame sync interrupt ((R/X)IN= 10b) used wake transmitter/receiver. Pull frame master (transmitter receiver) reset (XRST RRST FSGM (frame sync generated sample rate generator), enable frame sync generator setting FRST FSGM frames generated every copy, therefore, FRST used. case, master starts data transfer.
Interrupt-driven transfers: Setting (R/X)INTM=00b SPCR allows McBSP interrupt whenever data ready DRR, when data written DXR. initialization steps similar EDMA driven transfers, except that EDMA used. Therefore, replace steps through above with following:
required XINT(0/1/2) and/or RINT(0/1/2) interrupts interrupt multiplexer registers. Enable mapped interrupts. Once McBSP initialized (after step above), each element transfer will cause execution that writes reads from DRR.
Polled transfers: transmit receive ready (R/X)RDY bits SPCR polled determine readiness transmitter receiver. Here, check this condition, which might prevent from performing needed processing. McBSP initialization process some differences compared previous methods McBSP service. Since neither EDMA interrupt-driven transfer applicable this case, steps through required. steps are, therefore, followed polling loop.
TMS320C64x trademark Texas Instruments.
TMS320C6000 McBSP Initialization
SPRA488C
C6000 reset; McBSP reset; XRST RRST GRST FRST
Program McBSP Control registers; McBSP still reset state.
CLKXM CLKRM FSXM FSRM
Frame Master? (FSX output)
Pull reset; XRST FSXM RRST FSGM
GRST Wait data clocks
Ensure slave reset.
XRST and/or RRST FRST FSGM Data Transfer Starts
Interrupt-driven Transfer?
(Polled Transfer) interrupts CPU. Enable GIE, NMIE, required CPU_INTxx. Transfer? Clear RWSTAT bits. channel STOP state. registers transfer. START state.
EDMA Transfer? Select appropriate channels initiate read and/or write transfers. transfer parameters required Parameter RAM.
Figure McBSP Initialization Flowchart
TMS320C6000 McBSP Initialization
SPRA488C
Using Chip Support Library (CSL)
chip support library makes easier program McBSP's operation macros functions that streamline code. Below list basic components that needed program McBSP EDMA operation. operation, please sample code Appendix complete listing functions their syntax, refer TMS320C6000 Chip Support Library Reference Guide (SPRU401). Define chip wish
#define CHIP_6711
Include relevant header files
#include #include #include #include #include #include <c6x.h> <csl.h> <csl_dma.h> <csl_edma.h> <csl_irq.h> <csl_mcbsp.h> library DMA_SUPPORT EDMA_SUPPORT IRQ_SUPPORT MCBSP_SUPPORT
Declare objects
MCBSP_Handle hMcbsp DMA_Handle hDma EMDA_Handle hEdma EDMA_Handle hEdma_NULL
Setup vector table
IRQ_setVecs(vectors)
Initialize library
CSL_init()
Setup McBSP configuration structure
MCBSP_Config mcbspCfg
Open McBSP channel
hMcbsp MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
Apply configuration structure channel
MCBSP_config(hMcbsp, &mcbspCfg)
Enable sample rate generator
MCBSP_enableSrgr(hMcbsp)
Reset EDMA channels
DMA_reset(INV) EDMA_clearPram(0x00000000)
Enable interrupts
IRQ_nmiEnable() IRQ_globalEnable() IRQ_disable(IRQ_EVT_DMAINT0) IRQ_clear(IRQ_EVT_DMAINT0) IRQ_enable(IRQ_EVT_DMAINT0)
TMS320C6000 McBSP Initialization
SPRA488C
Open EDMA channels depending C6000 device
hDma DMA_open(DMA_CHA2, DMA_OPEN_RESET); hEdma EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);
Configure EDMA channels operation
DMA_configArgs(.) EDMA_configArgs(.)
EDMA, configure link terminating NULL parameter
hEdma_NULL EDMA_allocTable(-1); EDMA_reset(hEdma_NULL); EDMA_link(hEdma, hEdma_NULL); Link terminating event
Start enable EDMA
DMA_start(hDma) EDMA_enableChannel(hEdma)
Enable McBSP receive transmit
MCBSP_enableRcv(hMcbsp) MCBSP_enableXmt(hMcbsp)
Enable frame sync generator
MCBSP_enableFsync(hMcbsp)
Handle EDMA interrupts
EDMA_intTest(.) EDMA_intClear(.)
Close McBSP EDMA channels
MCBSP_close(hMcbsp) DMA_close(hDma) EDMA_close(hEdma)
References
TMS320C6000 Example Applications (SPRA529). TMS320C6000 Enhanced DMA: Example Applications (SPRA636). TMS320C6000 Chip Support Library Reference Guide (SPRU401).
TMS320C6000 McBSP Initialization
SPRA488C
Appendix
following sample code illustrates sequence programming McBSP control registers initialization data formats. Some functions code also show EDMA register setup reading/writing from/to McBSP. Note that this sample code digital loopback mode, where transmit receive pins McBSP C6000 connected internally software (DLB
/*-*/ Proprietary Information 08/03/01 mcbsp-init.c: McBSP0 used mode with (E)DMA service McBSP. CLKX generated using clock SRG.
/*-*/
Chip definition, change this accordingly #define CHIP_6711 Enter chip
Include files #include <c6x.h> #include <csl.h> #include <csl_dma.h> #include <csl_edma.h> #include <csl_irq.h> #include <csl_mcbsp.h> library DMA_SUPPORT EDMA_SUPPORT IRQ_SUPPORT
MCBSP_SUPPORT
/*-*/ Define constants #define FALSE #define TRUE
#define XFER_SIZE Number elements transfer
#define BUFFER_SIZE Global variables used interrupt ISRs volatile recv0_done FALSE; volatile xmit0_done FALSE;
TMS320C6000 McBSP Initialization
SPRA488C
/*-*/ Declare objects
MCBSP_Handle hMcbsp0;
Handles McBSP
(DMA_SUPPORT) DMA_Handle hDma1; DMA_Handle hDma2; #endif Handles
(EDMA_SUPPORT) EDMA_Handle hEdma1; EDMA_Handle hEdma2; EDMA_Handle hEdmadummy; #endif
Handles EDMA
/*-*/ External functions function prototypes
void init_mcbsp0(void); void set_interrupts_dma(void); void set_interrupts_edma(void);
Include vector table call ISRs hookup extern void vectors();
/*-*/ main()
/*-*/
void main(void) Declaration local variables Uint32 xfer_size; Uint32 wait Uint32 Counter initialize buffers
TMS320C6000 McBSP Initialization
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Create buffers. (DMA_SUPPORT) static Uint32 dmaInbuff[BUFFER_SIZE]; static Uint32 dmaOutbuff[BUFFER_SIZE]; #endif buffer supporting devices
(EDMA_SUPPORT) static Uint32 edmaInbuff[BUFFER_SIZE]; static Uint32 edmaOutbuff[BUFFER_SIZE]; #endif buffer EDMA supporting devices
IRQ_setVecs(vectors);
point vector table
xfer_size XFER_SIZE;
size transfer
initialize library CSL_init();
initialize McBSP init_mcbsp0();
Enable sample rate generator GRST=1
MCBSP_enableSrgr(hMcbsp0); (wait=0; wait<0x10; wait++); Wait states after starts
(DMA_SUPPORT) DMA_reset(INV); #endif
supporting devices reset channels
(EDMA_SUPPORT) EDMA_clearPram(0x00000000); set_interrupts_edma(); #endif
EDMA supporting devices Clear PaRAM EDMA
TMS320C6000 McBSP Initialization
SPRA488C
/*-*/ channels config structures (DMA_SUPPORT) supporting devices /*-*/
(y=0;y<xfer_size;y++) dmaOutbuff[y]=0x0000000+y; dmaInbuff[y]=0; Channel transmits data hDma2 DMA_open(DMA_CHA2, DMA_OPEN_RESET); DMA_configArgs(hDma2, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, DMA_PRICTL_WSYNC_XEVT0, DMA_PRICTL_RSYNC_DEFAULT, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_SRCDIR_INC, DMA_PRICTL_START_DEFAULT DMA_SECCTL_RMK( (!CHIP_6201) DMA_SECCTL_WSPOL_NA, only C6202(B)/C6203(B)/C6204/C6205 DMA_SECCTL_RSPOL_NA, only C6202(B)/C6203(B)/C6204/C6205 DMA_SECCTL_FSIG_NA, #endif DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, only C6202(B)/C6203(B)/C6204/C6205 Element size bits Increment source element size DMA_PRICTL_DSTDIR_DEFAULT, high priority synchronization event XEVT0=01100 Handle channel Initialize transmit buffer Initialize receive buffer
TMS320C6000 McBSP Initialization
SPRA488C
DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, Enables channel interrupt DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT source dmaOutbuff DXR)), destination DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(xfer_size) Channel receives data hDma1 DMA_open(DMA_CHA1, DMA_OPEN_RESET); DMA_configArgs(hDma1, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, DMA_PRICTL_WSYNC_DEFAULT, DMA_PRICTL_RSYNC_REVT0, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, DMA_PRICTL_DSTDIR_INC, DMA_PRICTL_START_DEFAULT Element size bits Increment destination element size synchronization event REVT0=01101 high priority Handle channel
DMA_PRICTL_SRCDIR_DEFAULT,
TMS320C6000 McBSP Initialization
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DMA_SECCTL_RMK( (!CHIP_6201) DMA_SECCTL_WSPOL_NA, only C6202(B)/C6203(B)/C6204/C6205 DMA_SECCTL_RSPOL_NA, only C6202(B)/C6203(B)/C6204/C6205 DMA_SECCTL_FSIG_NA, #endif DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, Enables channel interrupt DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT DRR)), source DMA_DST_RMK((Uint32)dmaInbuff), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(xfer_size) set_interrupts_dma(); initialize interrupts DMA_start(hDma1); DMA_start(hDma2); #endif supporting devices Start channels destination dmaInbuff only C6202(B)/C6203(B)/C6204/C6205
TMS320C6000 McBSP Initialization
SPRA488C
/*-*/ EDMA channels config structures /*-*/ (EDMA_SUPPORT) EDMA supporting devices
(y=0;y<xfer_size;y++) edmaInbuff[y]=0;
Initialize Outbuff
edmaOutbuff[y]=0x00000000+y;
hEdma1 EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(13), (C64_SUPPORT) EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, #endif EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO DRR)), source EDMA_CNT_RMK(0,xfer_size), destination edmaInbuff EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) Enable linking NULL table*/ Destination increment element size Enable Transfer Complete Interrupt TCCINT 0xD, REVT0 High priority EDMA Element size bits
TMS320C6000 McBSP Initialization
SPRA488C
hEdma2 EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma2, EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_NONE, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(12), (C64_SUPPORT) EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, #endif EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO source edmaOutbuff EDMA_CNT_RMK(0,xfer_size), DXR)), destination DXR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 this NULL table Terminate EDMA transfers linking Enable linking NULL table*/ Enable Transfer Complete Interrupt TCCINT 0xC, XEVT0 Source increment element size High priority EDMA Element size bits
TMS320C6000 McBSP Initialization
SPRA488C
EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event EDMA_link(hEdma2, hEdmadummy); EDMA_enableChannel(hEdma1); EDMA_enableChannel(hEdma2); #endif EDMA supporting devices Enable EDMA channels
MCBSP_enableRcv(hMcbsp0); Enable McBSP port receiver MCBSP_enableXmt(hMcbsp0); Enable McBSP port transmitter MCBSP_enableFsync(hMcbsp0); Wait interrupt when transfer/receive done while (!xmit0_done !recv0_done); MCBSP_close(hMcbsp0); (DMA_SUPPORT) DMA_close(hDma1); DMA_close(hDma2); #endif (EDMA_SUPPPORT) EDMA_close(hEdma1); EDMA_close(hEdma2); EDMA_freeTable(hEdmadummy); #endif main /*-*/ init_mcbsp0() MCBSP Config structure Setup MCBSP_0 master void init_mcbsp0(void) MCBSP_Config mcbspCfg0 /*-*/ close EDMA channels close McBSP port close channels
TMS320C6000 McBSP Initialization
SPRA488C
(EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_DEFAULT, MCBSP_SPCR_SOFT_DEFAULT, MCBSP_SPCR_FRST_YES, Frame sync reset MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_XRDY, XINT driven XRDY MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_ON, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_DXENA_OFF, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RRST_DEFAULT #endif (DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_NO, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_XRDY, XINT driven XRDY MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_ON, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RRST_DEFAULT #endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_MSB, MCBSP_RCR_RFIG_YES, companding Ignore unexpected sync pulses Digital Loopback Mode enabled Right-justify zero-fill MSBs RINT driven RRDY RINT driven RRDY MCBSP_SPCR_RSYNCERR_DEFAULT, Digital Loopback Mode enabled Right-justify zero-fill MSBs
MCBSP_SPCR_CLKSTP_DEFAULT,
MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT,
TMS320C6000 McBSP Initialization
SPRA488C
MCBSP_RCR_RDATDLY_1BIT,
1-bit delay
MCBSP_RCR_RFRLEN1_OF(0), word phase MCBSP_RCR_RWDLEN1_32BIT, 32-bit receive element length MCBSP_RCR_RWDREVRS_DISABLE #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_MSB, MCBSP_RCR_RFIG_YES, MCBSP_RCR_RDATDLY_1BIT, MCBSP_RCR_RWDLEN1_32BIT #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, Single phase frame MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XDATDLY_1BIT, companding 1-bit delay Ignore unexpected sync pulses companding 1-bit delay 32-bit receive element length Ignore unexpected sync pulses
MCBSP_RCR_RFRLEN1_OF(0), word phase
MCBSP_XCR_XFRLEN1_OF(0), word phase MCBSP_XCR_XWDLEN1_32BIT, 32-bit receive element length MCBSP_XCR_XWDREVRS_DISABLE #endif (DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, Single phase frame MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XWDLEN1_32BIT companding 1-bit delay 32-bit receive element length Ignore unexpected sync pulses
MCBSP_XCR_XFRLEN1_OF(0), word phase
TMS320C6000 McBSP Initialization
SPRA488C
#endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_DEFAULT, MCBSP_SRGR_CLKSP_DEFAULT, MCBSP_SRGR_CLKSM_INTERNAL, clock derived internally MCBSP_SRGR_FSGM_DXR2XSR, MCBSP_SRGR_FPER_DEFAULT, MCBSP_SRGR_FWID_DEFAULT, MCBSP_SRGR_CLKGDV_OF(7) MCBSP_MCR_DEFAULT, MCBSP_RCER_DEFAULT, MCBSP_XCER_DEFAULT, MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_DEFAULT, MCBSP_PCR_RIOEN_DEFAULT, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_INTERNAL, MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_OUTPUT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_ACTIVEHIGH, MCBSP_PCR_FSRP_ACTIVEHIGH, MCBSP_PCR_CLKXP_RISING, MCBSP_PCR_CLKRP_FALLING hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp0, &mcbspCfg0); /*-*/ set_interrupts_dma() (DMA_SUPPORT) void set_interrupts_dma(void) interrupts device supports /*-*/ Internal frame sync signals used Internal frame sync signals used
TMS320C6000 McBSP Initialization
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IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT2); IRQ_disable(IRQ_EVT_DMAINT1); IRQ_clear(IRQ_EVT_DMAINT2); IRQ_clear(IRQ_EVT_DMAINT1); IRQ_enable(IRQ_EVT_DMAINT2); IRQ_enable(IRQ_EVT_DMAINT1); return; #endif INT11 INT9
/*-*/ set_interrupts_edma()
/*-*/ (EDMA_SUPPORT) void set_interrupts_edma(void) IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(12); EDMA_intDisable(13); IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(12); EDMA_intClear(13); IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(12); EDMA_intEnable(13); McBSP transmit event XEVT0 McBSP receive event REVT0 interrupts device supports EDMA
return; #endif
TMS320C6000 McBSP Initialization
SPRA488C
/*-*/ DATA TRANSFER COMPLETION ISRs vecs.asm hooks this /*-*/ interrupt void c_int11(void) (DMA_SUPPORT) xmit0_done TRUE; return; #endif interrupt void c_int09(void) (DMA_SUPPORT) recv0_done TRUE; return; #endif interrupt void c_int08(void) (EDMA_SUPPORT) (EDMA_intTest(12)) xmit0_done TRUE; EDMA_intClear(12); clear CIPR future interrupts recognized else (EDMA_intTest(13)) recv0_done TRUE; EDMA_intClear(13); clear CIPR future interrupts recognized #endif return; /*-End mcbsp-init.c-*/ vecs.asm hooks this EDMA vecs.asm hooks this
TMS320C6000 McBSP Initialization
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