Shaku Anjanaiah Vassos Soteriou ABSTRACT TMS320C6000 (C6000) Multichan
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TMS320C6000 McBSP Interface
Shaku Anjanaiah Vassos Soteriou ABSTRACT TMS320C6000 (C6000) Multichannel Buffered Serial Port (McBSP) designed interface device that supports synchronous Serial Peripheral Interface (SPI). This document describes hardware interface between McBSP ROM. McBSP operates master user-specified clock stop (CLKSTP) mode order communicate with ROM. McBSP initialization control register programming also discussed. Digital Signal Processing Solutions
Contents Design Problem Solution Configuration McBSP Initialization Timing Analysis List Figures Figure Figure Figure Figure Figure Figure Figure Figure McBSP Master Interface Slave Device Receive Control Register (RCR Master) Transmit Control Register (XCR Master) Sample Rate Generator Register (SRGR Master) Control Register (PCR Master) Serial Port Control Register (SPCR Master) Clock Stop Mode Options C6000 Timing, CLKSTP 11b, CLKXP List Tables Table McBSP Register Values Clock Table Timing Numbers McBSP Master Table Timing Analysis Master Slave
TMS320C6000 C6000 trademarks Texas Instruments. trademarks property their respective owners.
SPRA487C
Design Problem
interface Serial Peripheral Interface (SPI) TMS320C6000?
Solution
multichannel buffered serial port (McBSP) TMS320C6000 interfaces with glue logic. system typically 4-wire interface comprising serial data serial data out, serial clock, device select. McBSP provides this 4-wire interface CLKX, pins, respectively. McBSP supports interface synchronous, full-duplex, variable element length (element length fixed given transfer), master slave mode back-to-back transmission reception. This feature achieved using clock-stop (CLKSTP) mode McBSP. This document discusses McBSP interface Atmel serial CMOS EEPROM, which only slave. McBSP master, generates required control signals clocking slave.
Configuration
McBSP master interface, must configure CLKX pins serial port outputs only. CLKX generated either C6000 clock external clock source input CLKS pin. mode, system clock other clock source drive CLKS present. clock divide down programmed application needs.
C6000 McBSP master CLKX SPI-compliant slave MOSI MISO HOLD
Figure McBSP Master Interface Slave Device signal connectivity shown Figure connecting Atmel serial CMOS EEPROM AT25 series which maximum clock rate range from This slave device organized 1k/2k/4k/8k 8-bit data only supports modes shown Figure Mode supports simultaneous transmission reception utilizing signals that correspond transmitter. McBSP simultaneously receive data since CLKR signals driven CLKX signals (respectively) internally. good practice, CLKR should programmed inputs.
TMS320C6000 McBSP Interface
SPRA487C
McBSP Initialization
various McBSP control registers shown Figure through Figure have initialized operation. serial port initialization procedure mode follows: McBSP reset state, XRST RRST SPCR. Program McBSP configuration registers XCR, RCR, SRGR, PCR, SPCR parameters required. Write desired value into CLKSTP bit-fields SPCR. Figure shows various CLKSTP modes that supported McBSP. GRST SPCR sample rate generator reset. Wait clocks McBSP reinitialize. Either should followed. This step should performed used service McBSP. XRST RRST enable serial port. Note that value written SPCR this time should have only reset bits changed remaining bit-fields should have same value Step above. used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses, their update modes, transfer complete interrupt, other feature suitable application. Lastly, START bit. START state waits synchronization events occur. Then, pull McBSP reset. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Applications (SPRA529). enhanced (EDMA) used perform data transfers, channels associated McBSP transmit receive synchronization events should first configured with appropriate priority levels, element size, src/dst addresses, address update modes, transfer complete code, transfer complete interrupt enable, source destination dimensions, other feature suitable application PaRAM parameter fields. events latched event register (ER), even events disabled. Enabling corresponding event event enable register (EER) starts data transfer setting this `1'. Then, pull McBSP reset. details EDMA initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Enhanced DMA: Example Applications (SPRA636).
RFRLEN2 R/W-0
RFIG R/W-0
RPHASE R/W-0
RWDLEN2 R/W-0
RCOMPAND R/W-0
RDATDLY R/W-0
RFRLEN1 R/W-0
RWDREVRS R/W-0
reserved
RPHASE2 R/W-0
RWDLEN1 R/W-0
Legend: Read only; Read/Write Available only C621x/C671x C64x devices.
Figure Receive Control Register (RCR Master)
TMS320C6000 McBSP Interface
SPRA487C
XFRLEN2 R/W-0 XFRLEN1 R/W-0
XFIG R/W-0
XPHASE R/W-0
XWDLEN2 R/W-0
XCOMPAND R/W-0 XWDREVRS R/W-0
XDATDLY R/W-0
XPHASE2 R/W-0
XWDLEN1 R/W-0
reserved
Legend: Read only; Read/Write Available only C621x/C671x C64x devices.
Figure Transmit Control Register (XCR Master)
GSYNC R/W-0 FWID R/W-0
Legend: Read/Write
CLKSP R/W-0
CLKSM R/W-1
FSGM R/W-0
FPER R/W-0 CLKGDV R/W-1
Figure Sample Rate Generator Register (SRGR Master)
Reserved Rsvd XIOEN R/W-0 RIOEN R/W-0 FSXM R/W-0 FSRM R/W-0 CLKXM R/W-0 CLKRM R/W-0 Rsvd CLKS_STAT R/W-0 DX_STAT R/W-0 DR_STAT FSXP R/W-0 FSRP R/W-0 CLKXP R/W-0 CLKRP R/W-0
Legend: Read only; Read/Write
Figure Control Register (PCR Master)
TMS320C6000 McBSP Interface
SPRA487C Reserved R/W-0 FREE} R/W-0 SOFT} R/W-0 FRST R/W-0 DXENA R/W-0 GRST R/W-0 Reserved XSYNCERR R/W-0 RSYNCERR R/W-0 XEMPTY RFULL XRDY RRDY XRST R/W-0 RRST R/W-0
XINR/W-0
RJUST R/W-0
CLKSTP R/W-0
Reserved
RINR/W-0
Legend: Read only; Read/Write Writing XSYNCERR RSYNCERR will error condition when transmiter receiver (XRST=1 RRST=1),
respectively, enabled. Thus, used mainly testing purposes this operation desired.
Available C621x/C671x/C64x only. R/W-x Read/write-reset value
Figure Serial Port Control Register (SPCR Master) Table McBSP Register Values Clock
Register SRGR Value 0x000100A0 0x000100A0 0x2000005F Description Single phase, 32-bit element frame, bit-clock delay Single phase, 32-bit element frame, bit-clock delay Serial clock CLKX generated internal clock (CLKSM internal clock source clock C620x/C670x, CPU/2 clock C621x/C671x CPU/4 clock C64x. Frame sync generated DXR-to-XSR transfer (FSGM Clock divide down clock generate 2.08 shift clock (CLKGDV 0x5F). CLKGCV should adjusted accordingly other internal clock source rate. active-low (FSXP output (FSXM active-low (FSRP input (FSRM CLKX output (CLKXM starts with rising edge (CLKXP CLKSTP 11b. Since CLKXP=0, this refers data transmitted rising edge received falling edge CLKX master. This parameter changed application needs.
0x00000A0C
SPCR
0x00001800
example code initializes McBSP0 correct order SPI-mode communication between McBSP serial EEPROM. file code available with this application report.
CLKX (CLKSTP=10b, CLKXP=0) CLKX (CLKSTP=11b, CLKXP=0) CLKX (CLKSTP=10b, CLKXP=1) CLKX (CLKSTP=11b, CLKXP=1) D(R/X) FS(R/X)
Figure Clock Stop Mode Options
TMS320C6000 McBSP Interface
SPRA487C
Timing Analysis
mode (0,0) corresponds McBSP mode with CLKSTP CLKXP master (McBSP) shifts data falling edge CLKX slave (SPI ROM) samples receive data rising edge CLKX. slave transmits/shifts data falling edge CLKX master samples receive data rising edge CLKX.
CLKX Bit(n-1) Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-2)
(n-3)
(n-4)
Figure C6000 Timing, CLKSTP 11b, CLKXP timing diagram CLKSTP=11b, CLKXP=0 shown Figure corresponding values timing requirements switching characteristics operation shown Table values derived from formula/numbers available TMS320C6201 datasheet. timing different C6000 devices also differ. Please refer specific device data sheet replace values Table timing analysis particular device. Table Timing Numbers McBSP Master Switching Characteristics
th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) td(FXL-DXV) Parameter Hold time, after CLKX high Delay time, CLKX Delay time, CLKX high valid Disable time, high impedance following last data from CLKX high Delay time, valid =243 UNIT
=244
Timing Requirements
tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX Unit
TMS320C6000 McBSP Interface
SPRA487C
NOTE: following true above calculations: Since CLKGDV CLKX derived from clock will have duty cycle therefore Period CLKX, CLKGDV) where clock. Hence, shown Table timing numbers McBSP match with that with sufficient timing margins. Note that timings correspond V-5.5 range devices. Therefore voltage translation buffer (for example, SN54LVT16373) will have used between McBSP ROM. buffers will still meet necessary timing requirements/margins. Table Timing Analysis Master Slave Switching Characteristics
Parameter twl(min) tv(max) ;;where twh(min) tho(min) where Value
Timing Requirements
Value tsu(min) Setup time, data th(min) Hold time, data
tcss(min) Setup time,
C6201 Switching Characteristics
Parameter td(FXL-CKXL)min td(FXL-DXV)max td(CKXH-DXV)min td(FXL-CKXL)min Value
C6201 Timing Requirements
Value tsu(DRV-CKXL)min Setup time, data th(CKXL-DRV)min Hold time, data
applications where McBSP used slave, please ensure that internal clock, CLKG runs least eight times that master clock. Typically, programming CLKGDV using clock (CLKSM (when McBSP slave) should suffice since clocks very slow.
TMS320C6000 McBSP Interface
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