Shaku Anjanaiah Vassos Soteriou ABSTRACT This document describes mulit
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Using TMS320C6000 McBSP High Speed Communication Port
Shaku Anjanaiah Vassos Soteriou ABSTRACT This document describes mulit-channel buffered serial ports (McBSP) Texas Instruments (TI) TMS320C6000 digital signal processor (DSP) high-speed data communication port. McBSP C6000 device connected McBSP another C6000 device serve high-speed data communication port. Typically, McBSPs similar device numbers interconnected achieve inter-communication high speeds. This application note describes maximum speed achieved using similar setup each C6000 devices. This necessary since timing numbers vary between devices process technology speed grades. achieve maximum data rate, necessary connect serial ports such that device behaves both clock master frame master. term master refers device that generates required signal (such clocks frames). Based assumptions made this application report, Timing Analysis Section this report provides list timing constraints maximum clock transfer rates McBSPs C6000 device series. Digital Signal Processing Solutions
Contents Design Problem Solution McBSP Register Configuration Timing Analysis Conclusion
References
Appendix Sample Code McBSP Master (Transmitter) Appendix Sample Code McBSP Slave (Receiver) List Figures Figure Figure Figure Figure Figure McBSP Connection Maximum Data Rate Receive Control Register (RCR) Transmit Control Register (XCR) Sample Rate Generator Register (SRGR) Control Register (PCR)
Trademarks property their respective owners. TMS320C6000 C6000 trademarks Texas Instruments.
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Figure Signal Relationship C6000 McBSP McBSP Data Transfer With (R/X)DATDLY=1 List Tables Table Table Table Table Table Bit-Field Values McBSP Registers Timing Requirements Switching Characteristics C6201 Timing Requirements Switching Characteristics C6211/C6711 Timing Requirements Switching Characteristics C64x McBSP Maximum Transfer Rates TMS320C6000 Devices
Design Problem
multi-channel buffered serial ports (McBSP) TMS320C6000 used high-speed data communication port?
Solution
Either more McBSPs TMS320C6000 devices connected McBSP different C6000 device serve high-speed data communication port. achieve maximum data rate necessary connect serial ports that device behaves both clock master frame master. other words, McBSP transmitter that generates clocks data transfer should also generate necessary frame synchronization signals. other McBSP portion then acts slave awaiting these control signals from master. Figure shows block diagram this arrangement. transmit portion McBSP0 CPU0 master clocks frames receiver McBSP1 CPU1. Similarly, McBSP1 CPU1 transmitter configured clock frame master McBSP0 CPU0. (CPU0) McBSP0 CLKX0 FSX0 FSR0 CLKR0 (CPU1) McBSP1 CLKR1 FSR1 FSX1 CLKX1
Figure McBSP Connection Maximum Data Rate
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McBSP Register Configuration
setup bit-fields control registers this operation shown Figure through Figure listed Table Note that this example master derives clock from clock (CLKOUT1) with divide ratio achieve maximum rate. Since master transmitter responsible generating clocks frame synchronization signals, CLKX programmed outputs. data delay between output first data non-zero value, because data delay zero does provide maximum packet frequency. Therefore, both transmitter receiver (R/X)DATDLY=1 this example.
RPHASE reserved
RFRLEN2 RFRLEN1
RFIG
RWDLEN2
RCOMPAND RWDREVRS
RDATDLY reserved
RWDLEN1
Figure Receive Control Register (RCR)
XPHASE reserved XFRLEN1 XFRLEN2 XFIG reserved
XWDLEN2
XCOMPAND XWDREVRS
XDATDLY
XWDLEN1
Figure Transmit Control Register (XCR)
Using TMS320C6000 McBSP High Speed Communication Port
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Figure Sample Rate Generator Register (SRGR)
reserved reserved reserved CLKSSTAT XIOEN DXSTAT RIOEN DRSTAT FSXM FSXP FSRM FSRP CLKXM CLKXP CLKRM CLKRP
Figure Control Register (PCR) Table Bit-Field Values McBSP Registers
Register [bit-field Bit-field Name RCR[17:16] XCR[17:16] SRGR[29] SRGR[28] SRGR[7:0] PCR[11] PCR[10] PCR[9] PCR[8] RDATDLY XDATDLY CLKSM FSGM CLKGDV FSXM FSRM CLKXM CLKRM Master (Transmitter) Macro MCBSP_ RCR_RDATDLY_DEFAULT XCR_XDATDLY_1BIT SRGR_CLKSM_INTERNAL SRGR_FSGM_FSG SRGR_CLKGDV_OF(0x0) PCR_FSXM_INTERNAL PCR_FSRM_DEFAULT PCR_CLKXM_OUTPUT PCR_CLKRM_DEFAULT Slave (Receiver) Macro MCBSP_ RCR_RDATDLY_1BIT XCR_XDATDLY_DEFAULT SRGR_CLKSM_DEFAULT SRGR_FSGM_ DEFAULT SRGR_CLKGDV_ DEFAULT PCR_FSXM_ DEFAULT PCR_FSRM_ DEFAULT PCR_CLKXM_ DEFAULT PCR_CLKRM_ DEFAULT
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bit-fields listed Table assume their default values. Note that above macros merely sample code. user also some other register field values, such number phases, frame lengths, number elements frame, clock polarities other parameters required specific application. Appendices provide full sample code, which uses above macros, setting McBSP transfer data another McBSP similar C6000 device. sample program Appendix sets McBSP0 master device transmitter. sample code Appendix sets McBSP0 slave device receiver. This code C6000 devices, both EDMA support provided. DMA/EDMA transfer data to/from these McBSPs. Again, this just sample code, therefore user modify different macros entire McBSP/DMA/EDMA/IRQ structures program) specific application. Please refer TMS320C6000 Chip Support Library User's Guide (SPRU401) further information functions macros used code Appendices
Timing Analysis
parameters that need satisfied achieve maximum data rates listed Table Table Table C6201, C6211/C6711, TMS320C64x devices respectively. CLKPER clock period master clock this case, CLKX0/1), which varied analysis verify frequency which design margins met. Note that board route delay about inches, considered propagation delay from source destination. Table through Table show timing analysis McBSP C6201, C6211/C6711, C64x DSPs respectively, indicating maximum transfer rates achieved before timing violations (refer conclusion), satisfying timing requirements negative margins).
TMS320C64x C64x trademarks Texas Instruments.
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Table Timing Requirements Switching Characteristics C6201
Parameter Type Constraint Constraint Constraint Constraint Delay Delay Parameter Name tsu(FRH-CKRL) (CKRL-FRH) tsu(DRV-CKRL) (CKRL-DRV) (CKXH-FXV) tdis (CKXH-DXHZ) [Min, Max] (ns) [2,] [3,] [0,] [4,] [-2, [-1, Margin (ns) Description Setup time, valid CLKR Hold time, valid after CLKR Setup time, valid CLKR Hold time, valid after CLKR Delay time, valid after CLKX Disable time, CLKX high high impedance following last data bit. Delay time, valid after CLKX high Master clock period. varied satisfy parametric requirements. Wire delay from system needs. Wire delay from FSR. system needs. Wire delay from CLKX CLKR. system needs.
Delay Variable
(CKXH-DXV) CLKPER
[10,
Variable delay Variable delay Variable delay
(DX-DR) (FSX-FSR) (CLKX-CLKR)
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Table Timing Requirements Switching Characteristics C6211/C6711
Parameter Type Constraint Constraint Constraint Constraint Delay Delay Parameter Name tsu(FRH-CKRL) (CKRL-FRH) tsu(DRV-CKRL) (CKRL-DRV) (CKXH-FXV) tdis (CKXH-DXHZ) [Min, Max] (ns) [1,] [3,] [3,] [4,] [-11, [-9, Margin (ns) <10> Description Setup time, valid CLKR Hold time, valid after CLKR Setup time, valid CLKR Hold time, valid after CLKR Delay time, valid after CLKX Disable time, CLKX high high impedance following last data bit. Delay time, valid after CLKX high Master clock period. varied satisfy parametric requirements. Wire delay from system needs. Wire delay from FSR. system needs. Wire delay from CLKX CLKR. system needs.
Delay Variable
(CKXH-DXV) CLKPER
[-9, [28,
Variable delay Variable delay Variable delay
(DX-DR) (FSX-FSR) (CLKX-CLKR)
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Table Timing Requirements Switching Characteristics C64x
Parameter Type Constraint Constraint Constraint Constraint Delay Delay
Parameter Name tsu(FRH-CKRL) (CKRL-FRH) tsu(DRV-CKRL) (CKRL-DRV) (CKXH-FXV) tdis (CKXH-DXHZ)
[Min, Max] (ns) [1,] [3,] [0,] [3,] [-1, [-1,
Margin (ns)
Description Setup time, valid CLKR Hold time, valid after CLKR Setup time, valid CLKR Hold time, valid after CLKR Delay time, valid after CLKX Disable time, CLKX high high impedance following last data bit. Delay time, valid after CLKX high Master clock period. varied satisfy parametric requirements. Wire delay from system needs. Wire delay from FSR. system needs. Wire delay from CLKX CLKR. system needs.
Delay Variable
(CKXH-DXV) CLKPER
[-1,
Variable delay Variable delay Variable delay
(DX-DR) (FSX-FSR) (CLKX-CLKR)
CLKX(int) td(CKXH-FXV) (int) tdis(CKXH-DXZ) CLKR(ext) wire delay th(CKRL-FRH) tsu(FRH-CKRL) wire delay (ext) th(CKRL-DR) wire delay wire delay tsu(DR-CKRL) Bit(n-1) (n-2) td(CKXH-DX) Bit(n-1) td(CKXH-DX) (n-2) td(CKXH-FXV)
Figure Signal Relationship C6000 McBSP McBSP Data Transfer With (R/X)DATDLY=1
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Conclusion
Using McBSP configuration stated assumption, following maximum transfer rates C6000 DSPs achieved: Table McBSP Maximum Transfer Rates TMS320C6000 Devices
Device C6201, C6202/B, C6203 C6204, C6205 C6211/B, C6711, C6712 C6701 C64x 83.33 35.71 55.56 Maximum Transfer Rate (Mbps)
McBSPs used high-speed communication port, with data transfer rate that affected following factors:
Method data processing: example, interrupt-driven transfer slower than DMA/EDMA transfer. Therefore, data transfer rate will have reduced that data processed without missing any. Priority data processing: DMA/EDMA lower priority than CPU, channel used servicing McBSP lower priority than other channels DMA/EDMA. Thus, time taken service write read to/from McBSP extended, causing data over-write and/or receiver full error condition. avoid this, either bit-clock rate should reduced, appropriate priorities should assigned each channel.
NOTE: This application report discusses only TMS320C6000 McBSPs communicating with each other. Higher speeds achieved McBSP connected other device that meets timing parameters listed TMS320C6000 Digital Signal Processor data sheets found www.ti.com.
References
TMS320C6000 Digital Signal Processor data sheets, found www.ti.com TMS320C6000 Peripherals Reference Guide (SPRU190).
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Appendix
Sample Code McBSP Master (Transmitter)
mcbsp_xmit_master.c V1.00 Copyright 2001 Texas Instruments Incorporated --*/ 6/26/01: Vassos Soteriou mcbsp_xmit_master.c: This program sets McBSP0 TMS320C6000 devices data transmit mode, transfer data McBSP another C6000 device. This program supports Texas Instruments TMS320C6000 DSPs, those that controller Enhanced controller (EDMA). those that controller, channel services McBSP data transfer. vecs.asm assembly code file used hookup c_int11() corresponding interrupt. Channel hooked interrupt data transmit, controller individual interrupts each channel. EDMA controller, however, generates single interrupt (EDMA_INT) behalf channels (C621x/C671x) channels(C64x). various control registers fields facilitate EDMA interrupt generation. CPU_INT8 responsible EDMA channels. sample code based TI's 2.0. Please refer TMS320C6000 Chip Support Library User's Guide further information. Note that channel with interrupt McBSP used this transfer, this just sample code that used reference. Chip definition, change this accordingly #define CHIP_6414 Include files #include <c6x.h> #include <csl.h> library #include <csl_dma.h> DMA_SUPPORT #include <csl_edma.h> EDMA_SUPPORT #include <csl_irq.h> IRQ_SUPPORT #include <csl_mcbsp.h> MCBSP_SUPPORT Define constants #define FALSE #define TRUE #define DMA_XFER #define XFER_TYPE DMA_XFER #define BUFFER_SIZE #define ELEMENT_COUNT element_count buffer_size Global variables used interrupt ISRs volatile xmit0_done FALSE; Declare objects MCBSP_Handle hMcbsp0; Handles McBSP (DMA_SUPPORT) DMA_Handle hDma2; Handle
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#endif (EDMA_SUPPORT) Handles EDMA EDMA_Handle hEdma1; EDMA_Handle hEdmadummy; #endif External functions function prototypes void init_mcbsp0_master(void); Function prototypes void set_interrupts_dma(void); void set_interrupts_edma(void); Include vector table call ISRs hookup extern void vectors(); main() void main(void) Declaration local variables static element_count, xfer_type; static Uint32 dmaOutbuff[BUFFER_SIZE]; buffer supporting devices static Uint32 edmaOutbuff[BUFFER_SIZE]; buffer EDMA supporting devices IRQ_setVecs(vectors); point vector table element_count ELEMENT_COUNT; xfer_type XFER_TYPE; initialize library CSL_init(); init_mcbsp0_master(); Enable sample rate generator GRST=1 MCBSP_enableSrgr(hMcbsp0); Handle SRGR switch (xfer_type) case DMA_XFER: (DMA_SUPPORT) supporting devices DMA_reset(INV); reset channels #endif (EDMA_SUPPORT) EDMA supporting devices EDMA_clearPram(0x00000000); Clear PaRAM EDMA set_interrupts_edma(); #endif channel config structure (DMA_SUPPORT) supporting devices Channel transmits data hDma2 DMA_open(DMA_CHA2, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma2, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT,
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DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority DMA_PRICTL_WSYNC_XEVT0, synchronization event XEVT0=01100*/ DMA_PRICTL_RSYNC_DEFAULT, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_DEFAULT, DMA_PRICTL_SRCDIR_INC, Increment source element size DMA_PRICTL_START_DEFAULT DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only 6202 6203 devices DMA_SECCTL_RSPOL_NA, only 6202 6203 devices DMA_SECCTL_FSIG_NA, only 6202 6203 devices DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT DXR)), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, xfer element count set_interrupts_dma(); initialize interrupt(s) enable interrupt after channels opened DMA_OPEN_RESET clears disables channel interrupt once specified clears corresponding inetrrupt bits IER. This applicable EDMA channel open case DMA_start(hDma2); Start channel #endif supporting devices EDMA channel config structure
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(EDMA_SUPPORT)
EDMA supporting devices
hEdma1 EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, #if(!C64_SUPPORT) 671X 621x devices EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, Source increment element size EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(12), TCCINT 0xC, XEVT0 EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif #if(C64_SUPPORT) EDMA_OPT_RMK( devices only EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_INC, Source increment element size EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_DEFAULT, EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(12), TCCINT 0xC, XEVT0 EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif
addr edmaOutbuff EDMA_CNT_RMK(0, element_count), count equal element_count DXR)), DXR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table*/ EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, Terminate EDMA transfers linking 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 this NULL table
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EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event*/ EDMA_enableChannel(hEdma1); Enable EDMA channel #endif EDMA supporting devices Enable McBSP channel MCBSP_enableXmt(hMcbsp0); McBSP port transmitter MCBSP_enableFsync(hMcbsp0); Enable frame sync McBSP flag interrupt when transmit done (DMA_SUPPORT) while (!xmit0_done); #endif flag interrupt when EDMA transfer done Transfer completion interrupt sets flag when (EDMA_SUPPORT) while (!xmit0_done); #endif MCBSP_close(hMcbsp0); close McBSP port (DMA_SUPPORT) close channels DMA_close(hDma2); #endif (EDMA_SUPPPORT) EDMA_close(hEdma1); close EDMA channel EDMA_close(hEdmadummy); #endif main, program ends here init_mcbsp0_master() MCBSP Config structure Setup MCBSP_0 data transfer void init_mcbsp0_master(void) MCBSP_Config mcbspCfg0 (EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_DEFAULT, fields SPCR default values MCBSP_SPCR_SOFT_DEFAULT, MCBSP_SPCR_FRST_DEFAULT, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_DXENA_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT
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#endif (DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_DEFAULT, fields SPCR default values MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_DEFAULT, fields default values MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_DEFAULT, MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_DEFAULT, MCBSP_RCR_RWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_DEFAULT, fields default values MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_DEFAULT, MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_DEFAULT #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, Single phase transmit frame MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, 1-bit transmit data delay MCBSP_XCR_XFRLEN1_DEFAULT,
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MCBSP_XCR_XWDLEN1_DEFAULT, MCBSP_XCR_XWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XFRLEN1_DEFAULT, MCBSP_XCR_XWDLEN1_DEFAULT #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_DEFAULT, MCBSP_SRGR_CLKSP_DEFAULT, MCBSP_SRGR_CLKSM_INTERNAL, MCBSP_SRGR_FSGM_FSG, MCBSP_SRGR_FPER_DEFAULT, MCBSP_SRGR_FWID_DEFAULT, MCBSP_SRGR_CLKGDV_OF(0x0) (C64_SUPPORT) MCBSP_MCR_RMK( MCBSP_MCR_XMCME_DEFAULT, MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RMCME_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #else MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_RCER_RMK( MCBSP_RCER_RCEB_DEFAULT,
Single phase transmit frame
1-bit transmit data delay
Internal clock source driven frame sync signal*/
CLock divide
only fields default val-
fields default val-
fields RCER default val-
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MCBSP_RCER_RCEA_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_XCER_RMK( MCBSP_XCER_XCEB_DEFAULT, MCBSP_XCER_XCEA_DEFAULT #endif (C64_SUPPORT) MCBSP_RCERE0_RMK(0), MCBSP_RCERE1_RMK(0), MCBSP_RCERE2_RMK(0), MCBSP_RCERE3_RMK(0), #endif
fields XCER default val-
Additional registers only
(C64_SUPPORT) MCBSP_XCERE0_RMK(0), Additional registers only MCBSP_XCERE1_RMK(0), MCBSP_XCERE2_RMK(0), MCBSP_XCERE3_RMK(0), #endif MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_DEFAULT, MCBSP_PCR_RIOEN_DEFAULT, MCBSP_PCR_FSXM_INTERNAL, Frame sync generated internally MCBSP_PCR_FSRM_DEFAULT, MCBSP_PCR_CLKXM_OUTPUT, tans. clock mode from internal SRGR MCBSP_PCR_CLKRM_DEFAULT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_DEFAULT, MCBSP_PCR_FSRP_DEFAULT, MCBSP_PCR_CLKXP_DEFAULT, MCBSP_PCR_CLKRP_DEFAULT hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); McBSP port MCBSP_config(hMcbsp0, &mcbspCfg0); set_interrupts_dma() (DMA_SUPPORT) void interrupts set_interrupts_dma(void) device supports IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT2); INT11 IRQ_clear(IRQ_EVT_DMAINT2); IRQ_enable(IRQ_EVT_DMAINT2);
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return; #endif set_interrupts_edma() (EDMA_SUPPORT) void interrupt set_interrupts_edma(void) device supports EDMA IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(12); McBSP transmit event XEVT0 IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(12); IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(12); return; #endif DATA TRANSFER COMPLETION ISRs interrupt void vecs.asm hooks this c_int11(void) xmit0_done TRUE; return; interrupt void vecs.asm hooks this c_int08(void) EDMA (EDMA_SUPPORT) (EDMA_intTest(12)) xmit0_done TRUE; EDMA_intClear(12); clear CIPR future interrupts recognized #endif return; /*------------------------End Copyright 2000 Texas Instruments Incorporated. Rights Reserved FILENAME. vecs.asm DATE CREATED. 06/27/2001
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Global symbols defined here exported this file .global _vectors .global _vector0 .global _vector1 .global _vector2 .global _vector3 .global _vector4 .global _vector5 .global _vector6 .global _vector7 .global _c_int08 Hookup c_int08 main() EDMA .global _vector9 .global _vector10 .global _c_int11 Hookup c_int11 main() .global _vector12 .global _vector13 .global _vector14 .global _vector15 Global symbols referenced this file defined somewhere else. Remember that your interrupt service routines need referenced here. .ref _c_int00 This macro that instantiates entry interrupt service table.* VEC_ENTRY .macro addr B0,*--B15 MVKL addr,B0 MVKH addr,B0 *B15++,B0 .endm This dummy interrupt service routine used initialize IST. _vec_dummy: This actual interrupt service table (IST). properly aligned located subsection .text:vecs. This means don't explicitly specify this section your linker command file, will default link into .text section. Remember ISTP register point this table. .sect ".text:vecs" .align 1024
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_vectors: _vector0: VEC_ENTRY _vec_dummy _vector1: VEC_ENTRY _vec_dummy _vector2: VEC_ENTRY _vec_dummy _vector3: VEC_ENTRY _vec_dummy _vector4: VEC_ENTRY _vec_dummy _vector5: VEC_ENTRY _vec_dummy _vector6: VEC_ENTRY _vec_dummy _vector7: VEC_ENTRY _vec_dummy _vector8: VEC_ENTRY _c_int08 Hookup c_int08 main() EDMA _vector9: VEC_ENTRY _vec_dummy _vector10: VEC_ENTRY _vec_dummy _vector11: VEC_ENTRY _c_int11 Hookup c_int11 main() _vector12: VEC_ENTRY _vec_dummy _vector13: VEC_ENTRY _vec_dummy _vector14: VEC_ENTRY _vec_dummy _vector15: VEC_ENTRY _vec_dummy Title
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Appendix
Sample Code McBSP Slave (Receiver)
mcbsp_recv_slave.c V1.00 Copyright 2001 Texas Instruments Incorporated 6/26/01: Vassos Soteriou mcbsp_recv_slave.c: This program sets McBSP0 TMS320C6000 devices data receive mode,to receive data from McBSP another C6000 device. This program supports Texas Instruments TMS320C6000 DSPs, those that controller Enhanced controller (EDMA). those that controller, channel services McBSP data receive. vecs.asm assembly code file used hookup c_int09() corresponding interrupt. Channel hooked interrupt data receive, controller individual interrupts each channel. EDMA controller, however, generates single interrupt (EDMA_INT) behalf channels (C621x/C671x) channelS (C64x). various control registers fields facilitate EDMA interrupt generation. CPU_INT8 responsible EDMA channels. sample code based TI's 2.0. Please refer TMS320C6000 Chip Support Library User's Guide further information. Note that channel with interrupt McBSP used this transfer, this just sample code that used reference. Chip definition, change this accordingly #define CHIP_6202 Include files #include <c6x.h> #include <csl.h> library #include <csl_dma.h> DMA_SUPPORT #include <csl_edma.h> EDMA_SUPPORT #include <csl_irq.h> IRQ_SUPPORT #include <csl_mcbsp.h> MCBSP_SUPPORT Define constants #define FALSE #define TRUE #define DMA_XFER #define XFER_TYPE DMA_XFER #define BUFFER_SIZE same value xmit #define ELEMENT_COUNT element_count buffer_size, same value xmit*/ Global variables used interrupt ISRs volatile recv0_done FALSE; Declare objects MCBSP_Handle hMcbsp0; Handles McBSP (DMA_SUPPORT) DMA_Handle hDma1; Handle
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
#endif (EDMA_SUPPORT) Handles EDMA EDMA_Handle hEdma1; EDMA_Handle hEdmadummy; #endif External functions function prototypes void init_mcbsp0_slave(void); Function prototypes void set_interrupts_dma(void); void set_interrupts_edma(void); Include vector table call ISRs hookup extern void vectors(); main() void main(void) Declaration local variables static element_count, xfer_type; static Uint32 dmaInbuff[BUFFER_SIZE]; buffer supporting devices static Uint32 edmaInbuff[BUFFER_SIZE]; buffer EDMA supporting devices*/ IRQ_setVecs(vectors); point vector table element_count ELEMENT_COUNT; xfer_type XFER_TYPE; initialize library CSL_init(); init_mcbsp0_slave(); Enable sample rate generator GRST=1 MCBSP_enableSrgr(hMcbsp0); Handle SRGR switch (xfer_type) case DMA_XFER: (DMA_SUPPORT) supporting devices DMA_reset(INV); reset channels #endif (EDMA_SUPPORT) EDMA supporting devices EDMA_clearPram(0x00000000); Clear PaRAM EDMA set_interrupts_edma(); #endif channel config structure (DMA_SUPPORT) supporting devices Channel receives data hDma1 DMA_open(DMA_CHA1, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma1, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
DMA_PRICTL_WSYNC_REVT0, synchronization event REVT0=01101*/ DMA_PRICTL_RSYNC_DEFAULT, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_DEFAULT, DMA_PRICTL_SRCDIR_INC, Increment source element size DMA_PRICTL_START_DEFAULT DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only available 6202 6203 devices DMA_SECCTL_RSPOL_NA, DMA_SECCTL_FSIG_NA, DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT DRR)), DMA_DST_RMK((Uint32)dmaInbuff), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, recv element count set_interrupts_dma(); initialize interrupt(s) enable interrupt after channels opened DMA_OPEN_RESET clears disables channel interrupt once specified clears corresponding interrupt bits IER. This applicable EDMA channel open case DMA_start(hDma1); Start channel #endif supporting devices EDMA channel config structure only available 6202 6203 devices only available 6202 6203 devices
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
(EDMA_SUPPORT)
EDMA supporting devices
hEdma1 EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, (!C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, Destination increment element size EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(13), TCCINT 0xD, REVT0 EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif (C64_SUPPORT) EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_DEFAULT, EDMA_OPT_SUM_DEFAULT, EDMA_OPT_2DD_DEFAULT, EDMA_OPT_DUM_INC, Destination increment element size EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(13), TCCINT 0xD, REVT0 EDMA_OPT_TCCM_DEFAULT, EDMA_OPT_ATCINT_DEFAULT, EDMA_OPT_ATCC_DEFAULT, EDMA_OPT_PDTS_DEFAULT, EDMA_OPT_PDTD_DEFAULT, EDMA_OPT_LINK_YES, Enable linking NULL table EDMA_OPT_FS_NO #endif DRR)), addr edmaInbuff EDMA_CNT_RMK(0, element_count), count equal element_count DRR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table*/ EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, Terminate EDMA transfers linking 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 this NULL table
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event*/ EDMA_enableChannel(hEdma1); Enable EDMA channel #endif EDMA supporting devices Enable McBSP channel MCBSP_enableRcv(hMcbsp0); McBSP port transmitter flag interrupt when transfer/receive done (DMA_SUPPORT) while (!recv0_done); #endif flag interrupt when EDMA transfer done Transfer completion interrupt sets flag when (EDMA_SUPPORT) while (!recv0_done); #endif MCBSP_close(hMcbsp0); close McBSP port (DMA_SUPPORT) close channels DMA_close(hDma1); #endif (EDMA_SUPPPORT) EDMA_close(hEdma1); close EDMA channel EDMA_close(hEdmadummy); #endif main, program ends here init_mcbsp0_slave() MCBSP Config structure Setup MCBSP_0 data receive void init_mcbsp0_slave(void) MCBSP_Config mcbspCfg0 (EDMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_DEFAULT, fields SPCR default values MCBSP_SPCR_SOFT_DEFAULT, MCBSP_SPCR_FRST_DEFAULT, MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_DXENA_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (DMA_SUPPORT)
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_DEFAULT, fields SPCR default values MCBSP_SPCR_GRST_DEFAULT, MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT, MCBSP_SPCR_XRST_DEFAULT, MCBSP_SPCR_DLB_DEFAULT, MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DEFAULT, MCBSP_SPCR_RINTM_DEFAULT, MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_DEFAULT #endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase receive frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, 1-bit receive data delay MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_DEFAULT, MCBSP_RCR_RWDREVRS_DEFAULT #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, Single phase receive frame MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_DEFAULT, MCBSP_RCR_RDATDLY_1BIT, 1-bit receive data delay MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_DEFAULT #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DEFAULT, fields default values MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_DEFAULT, MCBSP_XCR_XFRLEN1_DEFAULT, MCBSP_XCR_XWDLEN1_DEFAULT, MCBSP_XCR_XWDREVRS_DEFAULT
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
#endif (DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DEFAULT, fields default values MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_DEFAULT, MCBSP_XCR_XFRLEN1_DEFAULT, MCBSP_XCR_XWDLEN1_DEFAULT #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_DEFAULT, fields SRGR default values MCBSP_SRGR_CLKSP_DEFAULT, MCBSP_SRGR_CLKSM_DEFAULT, MCBSP_SRGR_FSGM_DEFAULT, MCBSP_SRGR_FPER_DEFAULT, MCBSP_SRGR_FWID_DEFAULT, MCBSP_SRGR_CLKGDV_DEFAULT (C64_SUPPORT) MCBSP_MCR_RMK( only MCBSP_MCR_XMCME_DEFAULT, fields default values MCBSP_MCR_XPBBLK_DEFAULT, MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RMCME_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #else MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_DEFAULT, fields default values MCBSP_MCR_XPABLK_DEFAULT, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_DEFAULT, MCBSP_MCR_RPABLK_DEFAULT, MCBSP_MCR_RMCM_DEFAULT #endif #if(!C64_SUPPORT) MCBSP_RCER_RMK( MCBSP_RCER_RCEB_DEFAULT, fields RCER default values MCBSP_RCER_RCEA_DEFAULT
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
#endif #if(!C64_SUPPORT) MCBSP_XCER_RMK( MCBSP_XCER_XCEB_DEFAULT, MCBSP_XCER_XCEA_DEFAULT #endif (C64_SUPPORT) MCBSP_RCERE0_RMK(0), MCBSP_RCERE1_RMK(0), MCBSP_RCERE2_RMK(0), MCBSP_RCERE3_RMK(0), #endif
fields XCER default val-
Additional registers only
(C64_SUPPORT) MCBSP_XCERE0_RMK(0), Additional registers only MCBSP_XCERE1_RMK(0), MCBSP_XCERE2_RMK(0), MCBSP_XCERE3_RMK(0), #endif MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_DEFAULT, MCBSP_PCR_RIOEN_DEFAULT, MCBSP_PCR_FSXM_DEFAULT, MCBSP_PCR_FSRM_DEFAULT, MCBSP_PCR_CLKXM_DEFAULT, MCBSP_PCR_CLKRM_DEFAULT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_DEFAULT, MCBSP_PCR_FSRP_DEFAULT, MCBSP_PCR_CLKXP_DEFAULT, MCBSP_PCR_CLKRP_DEFAULT hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); McBSP port MCBSP_config(hMcbsp0, &mcbspCfg0); set_interrupts_dma() (DMA_SUPPORT) void interrupts set_interrupts_dma(void) device supports IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT1); INT09 IRQ_clear(IRQ_EVT_DMAINT1); IRQ_enable(IRQ_EVT_DMAINT1); return;
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
#endif set_interrupts_edma() (EDMA_SUPPORT) void interrupt set_interrupts_edma(void) device supports EDMA IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(13); McBSP receive event REVT0 IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(13); IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(13); return; #endif DATA TRANSFER COMPLETION ISRs interrupt void vecs.asm hooks this c_int09(void) recv0_done TRUE; return; interrupt void vecs.asm hooks this c_int08(void) EDMA (EDMA_SUPPORT) (EDMA_intTest(13)) recv0_done TRUE; EDMA_intClear(13); clear CIPR future interrupts recognized #endif return; /*-----------------------End Copyright 2000 Texas Instruments Incorporated. Rights Reserved FILENAME. vecs.asm DATE CREATED. 06/27/2001 Global symbols defined here exported this file
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
.global _vectors .global _vector0 .global _vector1 .global _vector2 .global _vector3 .global _vector4 .global _vector5 .global _vector6 .global _vector7 .global _c_int08 Hookup c_int08 main() EDMA .global _c_int09 Hookup c_int09 main() .global _vector10 .global _vector11 .global _vector12 .global _vector13 .global _vector14 .global _vector15 Global symbols referenced this file defined somewhere else. Remember that your interrupt service routines need referenced here. .ref _c_int00 This macro that instantiates entry interrupt service table.* VEC_ENTRY .macro addr B0,*--B15 MVKL addr,B0 MVKH addr,B0 *B15++,B0 .endm This dummy interrupt service routine used initialize IST. _vec_dummy: This actual interrupt service table (IST). properly aligned located subsection .text:vecs. This means don't explicitly specify this section your linker command file, will default link into .text section. Remember ISTP register point this table. .sect ".text:vecs" .align 1024 _vectors: _vector0: VEC_ENTRY _vec_dummy _vector1: VEC_ENTRY _vec_dummy
Using TMS320C6000 McBSP High Speed Communication Port
SPRA455A
_vector2: VEC_ENTRY _vec_dummy _vector3: VEC_ENTRY _vec_dummy _vector4: VEC_ENTRY _vec_dummy _vector5: VEC_ENTRY _vec_dummy _vector6: VEC_ENTRY _vec_dummy _vector7: VEC_ENTRY _vec_dummy _vector8: VEC_ENTRY _c_int08 Hookup c_int08 main() EDMA _vector9: VEC_ENTRY _c_int09 Hookup c_int09 main() _vector10: VEC_ENTRY _vec_dummy _vector11: VEC_ENTRY _vec_dummy _vector12: VEC_ENTRY _vec_dummy _vector13: VEC_ENTRY _vec_dummy _vector14: VEC_ENTRY _vec_dummy _vector15: VEC_ENTRY _vec_dummy *--------------------------End
Using TMS320C6000 McBSP High Speed Communication Port
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