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Kyle Castille ABSTRACT Interfacing external SDRAM Texas Instruments TM


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TMS320C6000 EMIF-to-External SDRAM Interface
Kyle Castille ABSTRACT Interfacing external SDRAM Texas Instruments TMS320C6000 digital signal processor (DSP) simple, compared previous generations DSPs, because advanced external memory interface (EMIF). EMIF glueless interface variety external memory devices. This application report describes EMIF's control registers SDRAM signals along with SDRAM functionality, including functions supported EMIF performance considerations when used with EMIF. General examples include several SDRAM configurations supported EMIF, including timing analysis. addition, specific examples provided using Micron SDRAM. Digital Signal Processing Solutions
Contents Interface C6000 EMIF With SDRAM C620x/C670x Compatible Memory Types C621x/C671x Compatible Memory Types C64x Compatible Memory Types C6000 EMIF-to-SDRAM Physical Interface Overview C6000 EMIF C620x/C670x SDRAM Interface Summary C621x/C671x SDRAM Interface Summary C64x SDRAM Interface Summary C6000 EMIF Signal Descriptions 2.4.1 C621x/C671x Byte-Lane Alignment 2.4.2 C64x Byte-Lane Alignment 2.4.3 C621x/C671x/C64x Clocking 2.4.4 C6000 Clock-to-Output Relationship C6000 EMIF Registers 2.5.1 EMIF Global Control Register 2.5.2 Space Control Registers 2.5.3 SDRAM Control Register (SDCTL) 2.5.4 SDRAM Timing Register (SDTIM) 2.5.5 C621x/C671x/C64x SDRAM Extension Register (SDEXT) Interchangeable SDRAM Devices Upgrading (C64x only) SDRAM SDRAM Commands
TMS320C6000 trademark Texas Instruments. trademarks property their respective owners.
SPRA433D
3.1.1 Timing Requirements 3.1.2 Deactivation (DCAB DEAC) 3.1.3 Activate (ACTV) 3.1.4 SDRAM Read (READ) 3.1.5 SDRAM Write (WRT) 3.1.6 Mode Register (MRS) 3.1.7 Refresh SDRAM Initialization Monitoring Page Boundaries 3.3.1 C620x/C670x Page Boundaries 3.3.2 C621x/C671x Page Boundaries 3.3.3 C64x Page Boundaries Address Shift Timing Constraints 3.5.1 C6000 Outputs (ED, SDCAS, SDRAS, SDWE) 3.5.2 C6000 Inputs (Output Data From SDRAM, Read 3.5.3 Timing Comparisons Four SDRAMs
Complete Example Using C6201B Micron's MT48LC4M16A2-10 Register Configuration C6201B MT48LC4M16A2 4.1.1 EMIF Global Control Registers C6201B MT48LC4M16A2 4.1.2 EMIF Space Control Register C6201B MT48LC4M16A2 4.1.3 EMIF SDRAM Control Register C6201B MT48LC4M16A2 4.1.4 EMIF SDRAM Refresh Period C6201B MT48LC4M16A2 Complete Example Using C6211 Micron's MT48LC16M8A2-8 Register Configuration C6211 MT48LC16M8A2 5.1.1 EMIF Global Control Registers C6211 MT48LC16M8A2 5.1.2 EMIF Space Control Register C6211 MT48LC16M8A2 5.1.3 EMIF SDRAM Control Register C6211 MT48LC16M8A2 5.1.4 EMIF SDRAM Refresh Period C6211 MT48LC16M8A2 5.1.5 EMIF SDRAM Extension Register C6211 MT48LC16M8A2 Complete Examples Using C6414 Micron's MT48LC4M32B2-7 Register Configuration C6414 MT48LC4M32B2 6.1.1 EMIF Global Control Register C6414 MT48LC4M32B2 6.1.2 EMIF Space Control Register C6414 MT48LC4M32B2 6.1.3 EMIF SDRAM Control Register C6414 MT48LC4M32B2 6.1.4 EMIF SDRAM Refresh Period C6414 MT48LC4M32B2 6.1.5 EMIF SDRAM Extension Register C6414 MT48LC4M32B2
References
Appendix Code Example C6201B Micron MT48LC4M16A2-10 Appendix Code Example C6211 Micron MT48LC16M8A2-8
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
List Figures C6000 EMIF-to-16M-Bit SDRAM Interface Using 16-Bit-Wide Chips C6000 EMIF-to-16M-Bit SDRAM Interface Using Four 8-Bit-Wide Chips C6000 EMIF1-to-64M-Bit SDRAM Interface Using 16-Bit-Wide Chips C6000 EMIF-to-64M-Bit SDRAM Interface Using 32-Bit-Wide Chip C621x/C671x EMIF-to-64M-Bit SDRAM Interface Using 16-Bit-Wide Chip (Big Endian) Figure C64x EMIFA-to64M-Bit SDRAM Interface Using 32-Bit-Wide Chips Figure C64x EMIFA-to-512M SDRAM Interface Using Four 16-bit Wide Chips Figure C6201/C6701 EMIF Block Diagram Figure C6202/C6203/C6204/C6205 EMIF Block Diagram Figure C621x/C671x EMIF Block Diagram Figure C64x EMIF Block Diagram Figure C621x/C671x Byte-Lane Alignment Endianness Figure Byte Alignment Endianness Figure C6201/C6202/C6203/C6204/C6205 C6201B/C6701 Output Timing Figure C621x/C671x/C64x Output Timing Figure C620x/C670x EMIF Global Control Register Diagram Figure C64x EMIF Global Control Register Diagram Figure C621x/C671x EMIF Global Control Register (GBLCTL) Figure C620x/C670x EMIF Space Control Register Diagram Figure C621x/C671x/C64x EMIF Space Control Register Diagram Figure EMIF SDRAM Control Register Figure EMIF SDRAM Timing Register Figure C621x/C671x/C64x SDRAM Extension Register Figure SDRAM Logical Address Bits Figure Modified Type Logical Address Bits Figure EMIFA SDRAM Interface x16-Bit SDRAM Figure EMIFA SDRAM Interface SDRAM Figure SDRAM DCAB-Closes Banks Space Figure C621x/C671x/C64x SDRAM DEAC-Closes Single Bank Specified Figure C620x/C670x SDRAM Read-CAS Latency Figure C621x/C671x SDRAM Read-CAS Latency Figure C621x/C671x SDRAM Read With DEAC Figure C64x SDRAM Read-CAS Latency Figure C620x/C670x SDRAM Burst Length Write Figure C621x/C671x SDRAM Burst Length Write Figure C64x SDRAM Burst Length Write Figure SDRAM Mode Register Set: Command Figure SDRAM Refresh Figure Figure Figure Figure Figure
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Logical Address Breakdown Bank Bit, Bits, Column Bits Logical Address Breakdown Bank Bits, Bits, Column Bits Outputs From C620x/C670x (Write Data [ED], Control, Address Signals) Outputs From C621x/C671x/C64x (Write Data [ED], Control, Address Signals) Input C6000 (Read Data) EMIF Global Control Register Diagram C6201B MT48LC4M16A2 EMIF Space Control Register Diagram C6201B MT48LC4M16A2 EMIF SDRAM Control Register C6201B MT48LC4M16A2 EMIF SDRAM Refresh Period C6201B MT48LC4M16A2 EMIF Global Control Register Diagram C6211 MT48LC16M8A2 EMIF Space Control Register Diagram C6211 MT48LC16M8A2 EMIF SDRAM Control Register C6211 MT48LC16M8A2 EMIF SDRAM Refresh Period C6211 MT48LC16M8A2 EMIF Global Control Register Diagram C6414 MT48LC4M32B2 EMIF Space Control Register Diagram EMIF SDRAM Control Register C6414 MT48LC4M32B2 EMIF SDRAM Refresh Period C6414 MT48LC4M32B2 List Tables
Table C620x/C670x Compatible Memory Type Characteristics Table C621x/C671x Compatible Memory Type Characteristics Table C64x Compatible Memory Type Characteristics Table TMS320C6000 SDRAM Signal Descriptions Table C6000 EMIF Memory Mapped Registers Table EMIF Global Control Register Field Description Table C6000 EMIF Space Control Register Field Description SDRAM Table EMIF SDRAM Control Register Field Description Table EMIF SDRAM Refresh Period Field Description Table C621x/C671x/C64x EMIF SDRAM Extension Register Field Description Table Upgradeable Compatible SDRAM Devices Table EMIF SDRAM Commands Table Truth Table SDRAM Commands Table C620x/C670x SDRAM Timing Parameters Table C621x/C671x/C64x SDRAM Timing Parameters Table C621x/C671x/C64x Recommended Values Parameters Table Mode Register Value Table Implied SDRAM Configuration Value Table C620x/C670x Byte Address Mapping SDRAM Table C621x/C671x Byte Address Mapping SDRAM Table C64x Byte Address Mapping SDRAM
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Table Table Table Table Table Table Table Table Table Table Table Table Table
MT48LC4M16A2-8 C6202/C6203/C6204/C6205-250 Timing Parameters MT48LC16M8A2-8 C6414-500 Timing Parameters SDRAM Registers Timing Parameter Calculation SDRAM Control Register C6201B MT48LC4M16A2 Period Calculation SDRAM Refresh Period C6201B MT48LC4M16A2 SDRAM Registers C6211 MT48LC16M8A2 Timing Parameter Calculation SDRAM Control Register C6211 MT48LC16M8A2 Period Calculation SDRAM Refresh Period C6211 MT48LC16M8A2 SDRAM Extension Register Values C6211 MT48LC16M8A2 SDRAM Registers C6414 Global Control Register C6414 Timing Parameter Calculation SDRAM Control Register C6414 MT48LC4M32B2 Period Calculation SDRAM Refresh Period C6414 MT48LC16M8A2 SDRAM Extension Register Values C6414 MT48LC4M32B2
Interface C6000 EMIF With SDRAM
EMIF C6000 devices offer glueless interface industry-standard SDRAM most commonly available configurations, including bits bits bits bits devices. Depending specific C6000 device, additional configurations supported.
C620x/C670x Compatible Memory Types
C620x/C670x EMIF supports glueless interface 16M-bit, 2-bank 64M-bit, 4-bank SDRAM, offering system designers interface high-speed high-density memory. Table lists possible SDRAM configurations that fully supported EMIF. Table shows, SDRAM supported C620x/C670x EMIF either eight nine column address bits maps into memory space equal smaller than bytes. Because C620x/C670x EMIF 32-bit word size, four 8-bit 16-bit devices must used parallel create 32-bit word.
C6000 trademark Texas Instruments.
complete list Texas Instruments devices, site http://www.ti.com
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C620x/C670x Compatible Memory Type Characteristics
SDRAM Size
bits Devices/ Addressable Space Bytes) SDRAM EMIF Column Address A8-A0 EA10-EA2 Address A10-A0 SDA10, EA11-EA2 A10-A0 SDA10, EA11-EA2 A11-A0 SDA10, EA13-EA2 A10-A0 SDA10, EA11-EA2 A11-A0 EA13, SDA10, EA11-EA2 Bank Select EA13
Banks
Width
Depth
Pre-charge SDA10
512K
SDRAM EMIF
A7-A0 EA9-EA2
EA13
SDA10
bits
SDRAM EMIF
A7-A0 EA9-EA2
BA1-BA0 EA15-EA14
SDA10
512K
SDRAM EMIF
A7-A0 EA9-EA2
BA1-BA0 EA14-EA13
SDA10
128M bits
SDRAM EMIF
A7-A0 EA9-EA2
BA1-BA0 EA15-EA14
SDA10
Table summarizes page characteristics fully supported SDRAM memory types illustrates EMIF-to-SDRAM mapping. SDRAM uses addresses A[x:0]. These pins mapped EA[x+2:2] EMIF because EMIF assumes that SDRAM memory spaces bits wide. four signals serve LSBs (least significant bits) external address. element supported SDRAM memory types that always precharge pin. support this functionality, EMIF's SDRAM interface uses named SDA10, instead EA12 map, support necessary SDRAM operations. During activate, SDA10 logically equivalent EA12. other SDRAM operations, SDA10 used precharge pin.
C621x/C671x Compatible Memory Types
C621x/C671x EMIF supports glueless interface almost configuration SDRAM memory types, including those supported C620x/C670x EMIF. This possible because larger spaces programmable SDRAM page characteristics. Table lists common configurations SDRAM that fully supported C621x/C671x EMIF. Table exhaustive listing supported SDRAM configurations. C621x/C671x EMIF supports glueless interface SDRAM memory with following configuration:
Pre-charge A10. number column address bits 8,9, number address bits 11,12,
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
number total banks (requiring bits).
Table summarizes page characteristics fully supported SDRAM memory types illustrates EMIF-to-SDRAM mapping. SDRAM uses addresses A[x:0]. These pins mapped EA[x+2:2] EMIF because C621x/C671x EMIF assumes that SDRAM memory spaces bits wide. four signals serve LSBs external address. element supported SDRAM memory types that always precharge pin. Because hidden refresh supported C621x/C671x EMIF, EA12 maps directly SDRAM. C621x/C671x EMIF does SDA10 signal, does C620x/C670x EMIF. Note that C621x/C671x EMIF also supports SDRAM memory space widths 16-bits wide.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C621x/C671x Compatible Memory Type Characteristics
Devices/ Addressable Space Bytes) SDRAM EMIF SDRAM EMIF 512K SDRAM EMIF bits SDRAM EMIF SDRAM EMIF SDRAM EMIF 512K SDRAM EMIF 128M bits SDRAM
SDRAM Size Banks Width
bits
Depth
Column Address A9-A0 EA11-EA2 A8-A0 EA10-EA2 A7-A0 EA9-EA2 A9-A0 EA11-EA2 A8-A0 EA10-EA2 A7-A0 EA9-EA2 A7-A0 EA9-EA2 A9-A0
Address A10-A0 EA12-EA2 A10-A0 EA12-EA2 A10-A0 EA12-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A10-A0 EA12-EA2 A11-A0
Bank Select EA13 EA13 EA13 BA1-BA0 EA15-EA14 BA1-BA0 EA15-EA14 BA1-BA0 EA15-EA14 BA1-BA0 EA14-EA13 BA1-BA0
Pre-charge EA12 EA12 EA12 EA12 EA12 EA12 EA12
EMIF SDRAM EMIF SDRAM EMIF 256M bits 128M SDRAM EMIF
EA11-EA2 A8-A0 EA10-EA2 A7-A0 EA9-EA2 A9-A0 EA11-EA2
EA13-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A12-A0 EA14-EA2
EA15-EA14 BA1-BA0 EA15-EA14 BA1-BA0 EA15-EA14 BA1-BA0 EA16-EA15
EA12 EA12 EA12 EA12
SDRAM EMIF
A8-A0 EA10-EA2 A8-A0 EA10-EA2 A9-A0
A12-A0 EA14-EA2 A11-A0 EA13-EA2 A12-A0
BA1-BA0 EA16-EA15 BA1-BA0 EA15-EA14 BA1-BA0
EA12 EA12
SDRAM EMIF
512M bits
128M
SDRAM
EMIF
EA11-EA2
EA14-EA2
EA16-EA15
EA12
width does apply C6712/12C/12D C6713/13B package.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
C64x Compatible Memory Types
TMS320C64x EMIFA EMIFB support glueless interface almost configuration SDRAM memory types, including those supported C620x/C670x C621x/C671x EMIF. Like C621x/C671x, this possible because larger spaces programmable SDRAM page characteristics. Table lists common configurations SDRAM that fully supported C64x EMIF. Table exhaustive listing supported SDRAM configurations. C64x EMIF supports glueless interface SDRAM memory with following configuration:
Pre-charge A10. number column address bits 8,9, number address bits 11,12, number total banks (requiring bits). Table C64x Compatible Memory Type Characteristics
SDRAM Size bits
Banks
Width
Depth
Devices/
Addressable Space Bytes) SDRAM
Column Address A9-A0 EA12-EA3 EA10-EA1 A8-A0 EA11-EA3 EA9-EA1 A7-A0 EA10-EA3 EA8-EA1 A9-A0 EA12-EA3 EA10-EA1 A8-A0 EA11-EA3 EA9-EA1 A7-A0 EA10-EA3 EA8-EA1 A7-A0 EA10-EA3
Address A10-A0 EA13-EA3 EA11-EA1 A10-A0 EA13-EA3 EA11-EA1 A10-A0 EA13-EA3 EA11-EA1 A11-A0 EA14-EA3 EA12-EA1 A11-A0 EA14-EA3 EA12-EA1 A11-A0 EA14-EA3 EA12-EA1 A10-A0 EA13-EA3
Bank Select EA14 EA12 EA14 EA12 EA14 EA12 A13-A12 EA16-EA15 EA14-EA13 BA1-BA0 EA16-EA15 EA14-EA13 BA1-BA0 EA16-EA15 EA14-EA13 BA1-BA0 EA15-EA14
Pre-charge EA13 EA11 EA13 EA11 EA13 EA11 EA13 EA11 EA13 EA11 EA13 EA11 EA13
512K bits 512K
EMIFA EMIFB SDRAM
EMIFA EMIFB SDRAM
EMIFA EMIFB SDRAM
128M
EMIFA EMIBA SDRAM
EMIFA EMIFB SDRAM
EMIFA EMIFB SDRAM
EMIFA
TMS320C64x trademark Texas Instruments.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C64x Compatible Memory Type Characteristics (Continued)
SDRAM Size Devices/ Addressable Space Bytes) EMIFB 128M bits SDRAM Column Address A9-A0 Address A11-A0 Bank Select BA1-BA0
Banks
Width
Depth
Pre-charge
128M
EMIFA EMIFB SDRAM
EA12-EA3 EA10-EA1 A8-A0 EA11-EA3 EA9-EA1 A7-A0 EA10-EA3 A9-A0 EA12-EA3 EA10-EA1 A8-A0 EA11-EA3 EA9-EA1 A8-A0 EA11-EA3 A9-A0 EA12-EA3 EA10-EA1
EA14-EA3 EA12-EA1 A11-A0 EA14-EA3 EA12-EA1 A11-A0 EA14-EA3 A12-A0 EA15-EA3 EA13-EA1 A12-A0 EA15-EA3 EA13-EA1 A11-A0 EA14-EA3 A12-A0 EA15-EA3 EA13-EA1
EA16-EA15 EA14-EA13 BA1-BA0 EA16-EA15 EA14-EA13 BA1-BA0 EA16-EA15 BA1-BA0 EA17-EA16 EA15-EA14 BA1-BA0 EA17-EA16 EA15-EA14 BA1-BA0 EA16-EA15 BA1-BA0 EA17-EA16 EA15-EA14
EA13 EA11 EA13 EA11 EA13 EA13 EA11 EA13 EA11 EA13 EA13 EA11
EMIFA EMIFB SDRAM
EMIFA EMIFB
256M-bit
256M
SDRAM EMIFA EMIFB SDRAM 128M EMIFA EMIFB SDRAM EMIFA EMIFB
512M-bit
256M
SDRAM EMIFA EMIFB
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
C6000 EMIF-to-SDRAM Physical Interface
Figure through illustrate EMIF SDRAM interface C6000 devices. SDRAM interfaces shown Figure Figure 64M-bit interfaces shown Figure Figure Table describes connection related signals specific SDRAM operations. 16-bit interface C621x/C671x (big-endian) shown Figure Although every possible interface shown C621x/C671x, these figures used reference. interfaces denser SDRAMs (such 128M-bit 256M-bit), only difference that additional address bits used. control data interfaces identical figures shown here. Figure shows C64x EMIFA interfaced 64M-bit SDRAMs, shows C64x EMIFA interfaced 64-bit-wide chip.
SDRAS SDCAS SDWE BE[3] BE[2] BE[1] BE[0] EA[y] Precharge EA[x] ED[31:16] ED[15:0] DQMU DQML A[a] A[b] A[c] DQ[15:0] 16M-bit SDRAM
External Memory Interface (EMIF)
16M-bit SDRAM
DQMU DQML A[a] A[b] A[c] DQ[15:0]
SDCLK C6701/C6701 CLKOUT2 C6202 ECLKOUT C621x/C671x ECLKOUT1 C64x Table Table Table appropriate addresses precharge pin.
Figure C6000 EMIF-to-16M-Bit SDRAM Interface Using 16-Bit-Wide Chips
C64x trademark Texas Instruments.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
16M-bit SDRAM A[a] A[b] A[c] DQ[7:0] A[a] A[b] A[c] DQ[7:0] A[a] A[b] A[c] DQ[7:0] Mbit SDRAM (2Mx8) 16M-bit SDRAM
SDRAS SDCAS SDWE BE[3] BE[2] BE[1] BE[0] EA[y] Precharge EA[x] ED[31:24] ED[23:16] ED[15:8] ED[7:0]
External Memory Interface (EMIF)
16M-bit SDRAM
16M-bit SDRAM A[a] A[b] A[c] DQ[7:0] SDCLK C6701/C6701 CLKOUT2 C6202 ECLKOUT C621x/C671x ECLKOUT1 C64x Table Table Table appropriate addresses precharge pin.
Figure C6000 EMIF-to-16M-Bit SDRAM Interface Using Four 8-Bit-Wide Chips
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
SDRAS SDCAS SDWE External Memory Interface (EMIF) BE[3] BE[2] BE[1] BE[0] EA[y] Precharge EA[x] ED[31:16] ED[15:0] DQMU DQML A[a] A[b] A[c] DQ[15:0] 64M-bit SDRAM DQMU DQML A[a] A[b] A[c] DQ[15:0] 64M-bit SDRAM
SDCLK C6701/C6701 CLKOUT2 C6202 ECLKOUT C621x/C671x ECLKOUT1 C64x Table Table Table appropriate addresses precharge pin.
Figure C6000 EMIF1-to-64M-Bit SDRAM Interface Using 16-Bit-Wide Chips
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
SDRAS SDCAS SDWE External Memory Interface (EMIF) DQM[3:0] A[12:11] A[10] A[9:0] DQ[31:0] 64M-bit SDRAM
BE[3]
EA[y] Precharge EA[x] ED[31:0]
SDCLK C6701/C6701 CLKOUT2 C6202 ECLKOUT C621x/C671x ECLKOUT1 C64x Table Table Table appropriate addresses pre-charge pin. (C6712, C6712C, C6712D EMIFB C64x does support 32-bit interface)
Figure C6000 EMIF-to-64M-Bit SDRAM Interface Using 32-Bit-Wide Chip
ECLKIN ECLKOUT SDRAS SDCAS SDWE External Memory Interface (EMIF) BE[3] BE[2] BE[1] BE[0] External Clock DQMU DQML A[13:0] DQ[15:0] 64M-bit SDRAM
EA[15:2] ED[31:16] ED[15:0]
Figure C621x/C671x EMIF-to-64M-Bit SDRAM Interface Using 16-Bit-Wide Chip (Big Endian)
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
External Clock ECLKIN ECLKOUT1 SDRAS SDCAS SDWE SDCKE BE[7:4] BE[3:0] EA[13] EA[15:14] EA[12:3] ED[63:32] ED[31:0]
External Memory Interface (EMIFA)
DQM[3:0] A[10] A[12:11] A[9:0] DQ[31:0]
64M-bit SDRAM (512K
64M-bit SDRAM DQM[3:0] (512K A[10] A[12:11] A[9:0] DQ[31:0]
Figure C64x EMIFA-to64M-Bit SDRAM Interface Using 32-Bit-Wide Chips
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D External clock 512M-bit SDRAM (8Mx16) DQM[1:0] BA1-BA0 A[12:0] DQ[15:0] 512M-bit SDRAM (8Mx16) DQM[1:0] BA1-BA0 A[12:0] DQ[15:0] 512M-bit SDRAM (8Mx16) DQM[1:0] BA1-BA0 A[12:0] DQ[15:0] 512M-bit SDRAM (8Mx16) DQM[1:0] BA1-BA0 A[12:0] DQ[15:0]
ECLKIN ECLKOUT1 SDRAS SDCAS SDWE External memory interface (EMIFA) BE[7:6] BE[5:4] BE[3:2] BE[1:0] EA[17:16] EA13 EA[15:3] ED[63:48] ED[47:32] ED[31:16] ED[15:0]
Figure C64x EMIFA-to-512M SDRAM Interface Using Four 16-bit Wide Chips
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Overview C6000 EMIF
C620x/C670x SDRAM Interface Summary
Supports 32-bit-wide SDRAM interface 16M-byte spaces Operates 1/2x clock speed. Clock generated internal DSP. Includes three programmable SDRAM controller values (TRC, TRCD, TRP). Other values static. Supports single open page SDRAM each space Column size programmable either 9-column address bits. Four configurations SDRAM supported. Does support SDRAM burst mode. Performs bursts issuing back-to-back commands. C6201/C6701 SDCLK used SDRAM clock. Includes dedicated SDRAM control signals. combination synchronous memory types allowed.
C6202/C6203/C6204/C6205 CLKOUT2 used SDRAM clock. SDRAM control signals MUXed with SBSRAM control signals. Only type synchronous memory allowed system.
C621x/C671x SDRAM Interface Summary Supports 32-bit, 16-bit, 8-bit-wide SDRAM interfaces 128M-byte addressable reach spaces Clock speed independent internal speed maximum
MHz. C6211/C6711/C6711B, ECLKIN must provided system. other C621x/C671x devices EMIF clock rate generated internal provided system (via ECLKIN). ECLKIN used, ECLKIN input completely independent clock. Very flexible programming SDRAM timing parameters Supports four open pages SDRAM. These different spaces, single space, combination two. program SDRAM configuration (column size, size, bank size). Almost SDRAM configuration used. Supports SDRAM burst mode with 4-word burst ECLKOUT must used synchronous memory clock delayed version ECLKIN, which must provided system. SDRAM control signals MUXed with SBSRAM Async control signals. combination synchronous memory types allowed.
EMIF width varies C621x/C671x devices. Please device specific datasheet supported widths.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
C64x SDRAM Interface Summary
Supports 64-bit, 32-bit, 16-bit, 8-bit-wide SDRAM interfaces1 256M-byte spaces Flexible clock selection allows EMIF clock rate generated internal (1/4th 1/6th clock rate) provided system (via ECLKIN). ECLKIN used, ECLKIN input completely independent clock. both cases (internal external clock source), EMIF clock rate must exceed MHz. Very flexible programming SDRAM timing parameters Supports four open pages SDRAM. These different spaces, single space, combination two. program SDRAM configuration (column size, size, bank size). Almost SDRAM configuration used. Supports SDRAM burst mode with 4-word burst ECLKOUT1 must used synchronous memory clock mirror image ECLKIN. SDRAM control signals MUXed with Programmable Synchronous Async control signals. combination synchronous memory types allowed. Supports self-refresh mode through SLFRFR SDRAM control register2
C6000 EMIF Signal Descriptions
Figure Figure Figure Figure show block diagrams C6201/C6701, C6202/C6203/C6204/C6205, C621x/C671x, C64x, respectively. Note that clocks control signals slightly different each four different style EMIFs. signals listed describe SDRAM interface shared interface signals.
64-bit 32-bit interface supported EMIFA only Supported EMIFA only
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
CLKOUT1 CLKOUT2 Interface SDCLK C6201/ C6701 ED[31:0] EA[21:2] CE[3:0] Data Access BE[3:0] SDRAS External memory interface (EMIF) SDCAS SDWE SDA10 HOLD HOLDA Shared external Interfaces Shared External Interfaces Hold Interface SDRAM Interface Hold Interface SDRAM Interface
Program Access
Internal Peripheral Interface
Figure C6201/C6701 EMIF Block Diagram
CLKOUT1 CLKOUT2 Interface
C6202
ED[31:0] EA[21:2] CE[3:0]
Data Access
BE[3:0] External memory interface (EMIF)
SDCAS/SSADS SDRAS/SSOE SDWE/SSWE SDA10 HOLD HOLDA
Program Access
Internal Peripheral Interface
Figure C6202/C6203/C6204/C6205 EMIF Block Diagram
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
CLKOUT1 CLKOUT2 ECLKIN Enhanced Data Memory Controller Shared External Interfaces C621x C671x ECLKOUT ED[31:0] EA[21:2] CE[3:0] External memory interface (EMIF) BE[3:0]
ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE Hold Interface HOLD HOLDA BUSREQ
Internal Peripheral Interface
Figure C621x/C671x EMIF Block Diagram
TMS320C6000 EMIF-to-External SDRAM Interface
SDRAM Interface
SPRA433D
ECLKIN ECLKOUT1 ECLKOUT2 Enhanced Data Memory Controller C64x CE[3:0] ARDY ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE AWE/SDWE/SSWE HOLD HOLDA BUSREQ SDCKE2 Control Registers Shared External Interfaces
EXTERNAL MEMORY INTERFACE (EMIF)
Internal Peripheral Interface NOTES: pins EMIFA EMIFB. SDCKE applies EMIFA only.
Figure C64x EMIF Block Diagram
MUXed Aysnch/ SDRAM/ Synchronous Memory Control
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table TMS320C6000 SDRAM Signal Descriptions
C62x/C67x EMIF
SDRAM Signal [x:0] [13:0] C6201/C6701 ED[31:0] EA[15:2] SDA10 C621x/C671x [31:0] [15:2] EA12
C64x EMIF EMIFA EMIFB
C641xT/ C6416/15/14 BED[15:0] BEA[14:1] BEA11
Other C620x/C670x ED[31:0] EA[15:2] SDA10
C6712/12C/12D C6713/13B [15:0] [15:2] EA12
C6416/15/14/12, DM642,C641xT [63:0] [16:3] AEA13
C6411, DM640/641 [31:0] [16:3] AEA13
CE2, BE[3:0] SDRAS
CE2, BE[3:0] SDRAS/ SSOE
CE0/CEI/CE2/
CE0/CEI/CE2/
ACEO,ACE1, ACE2,ACE3
ACEO,ACE1, ACE2,ACE3
BCE0, BCE1, BCE2, BCE3 BBE[1:0] BAOE/ BSDRAS/ BSOE BARE/ BSDCAS/ BSADS/ BSBE BAWE/ BSDWE/ BSWE BECLKOUT1 3.3V
[3:0]
[1:0] AOE/SDRAS/ SSOE
[3:0] AOE/SDRAS/ SSOE
[7.0] AOE/ASDRAS/ ASOE
[3:0] AOE/ASDRAS/ASOE
SDCAS
SDCAS/ SSADS
ARE/SDCAS/SSADS
ARE/SDCAS/ SSADS
AARE/ASDCAS/ASADS/ ASRE
AARE/ASDCAS/ASADS/ ASRE
SDWE
SDWE/ SSWE
AWE/SDWE/ SSWE
AWE/SDWE/ SSWE
AAWE/ASDWE/ ASWE
BAWE/ BSDWE/ BSWE AECLKOUT1 ASDCKE
SDCLK 3.3V
CLKOUT2 3.3V
ECLKOUT 3.3V
ECLKOUT 3.3V
AECLKOUT1 ASDCKE
This column applies C620x/C670x devices, except C6201/C6701 DSP. C6713/13B devices, this column applies only package type. This column applies C621x/C67 devices, except C6712/C6712C/C6712D C6713/13B package type.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
2.4.1
C621x/C671x Byte-Lane Alignment
C621x/C671x EMIF offers capability interface 32-bit, 16-bit, 8-bit SDRAM. Depending endianness system, different byte lane used SDRAM interface. alignment required shown Figure Note that always corresponds ED[31:24], always corresponds ED[23:16], always corresponds ED[15:8], always corresponds ED[7:0], regardless endianness.
32-bit
TMS320C621x/C671x ED[23:16] ED[15:8] ED[7:0]
ED[31:24]
32-bit MTYPE
16-bit MTYPE endian 16-bit MTYPE little endian
8-bit MTYPE endian
8-bit MTYPE little endian
C6713B C6711D devices allow flexibility changing EMIF data placement EMIF bus. device specific data sheet more details.
16-bit TMS320C621x/C671x ED[15:8] ED[7:0]
16-bit MTYPE
8-bit MTYPE
C6712/C6712C support big-endian byte alignment. C6712D supports both big-endian little endian with above data alignment. more details, device specific datasheet. Denotes total EMIF width, MTYPE configuration.
Figure C621x/C671x Byte-Lane Alignment Endianness
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
2.4.2
C64x Byte-Lane Alignment
C64x EMIFA offers capability interface 64-bit, 32-bit, 16-bit, 8-bit SDRAM. EMFIB supports interfaces 16-bit 8-bit SDRAM. show byte lanes used C64x EMIFA EMIFB. Unlike previous C6000 devices, external memory C64x always right aligned ED[7:0] side bus. endianness mode determines whether byte lane (ED[7:0]) accessed byte address (little endian) byte address (big endian), where memory width bytes.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D EMIFA (64-bit bus):
TMS320C64x EMIFA ED[63:56] ED[55:48] ED[47:40] ED[39:32] ED[31:24] ED[23:16] ED[15:8] ED[7:0]
64-bit MTYPE
32-bit MTYPE
16-bit MTYPE
8-bit MTYPE
EMIFA (32-bit bus):
TMS320C64x EMIFA ED[31:24] ED[23:16] ED[15:8] ED[7:0]
32-bit MTYPE
16-bit MTYPE
8-bit MTYPE
EMIFB (16-bit bus):
TMS320C64x EMIFB ED[15:8] ED[7:0]
16-bit MTYPE
8-bit MTYPE Denote total EMIF width, MTYPE configuration.
Figure Byte Alignment Endianness
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
2.4.3
C621x/C671x/C64x Clocking
EMIF C6211/C6711 requires external clock provided ECLKIN input. simplicity C6211/C6711, CLKOUT2 routed into ECLKIN avoid extra hardware required create clock externally. This method restriction only allowing memory interface 1/2x clock speed 150-MHz device). C64x C621x/C671x (excluding C6211/C6711) devices, internally provided clock simplify clocking. C64x devices, when Internal clock selected EMIF input clock source, rate configured either CPU14 CPU16. C621x/C671x devices, when internal clock selected EMIF input clock source, clock rate configured fast CPUx1 slow CPU/32. more details, device datasheet. data sheets each device specify that rise/fall time externally provided clock must within very specific range. This prove difficult with most off-the-shelf oscillators. recommended approach ICS501 multiplier chip, which produce wide range frequency outputs with standard crystals.
2.4.4
C6000 Clock-to-Output Relationship
optimize synchronous memory interfaces various C6000 devices, output signals triggered different internal clocks C6000 DSP. Figure Figure show clock relationship used various C6000 DSPs. Because C621x/C671x/C64x SDRAM interface timed reference externally provided clock, C621x,C671x, C64x data sheets provide tdmax tdmin, tosu toh, parameters. fact that tosu parameters factor equations allows user unconcerned about output edge being used internally C6000. this way, tosu parameter compared directly against tisu parameter memory given operating speed. tdmax tdmin parameters reference actual clock edge C6000 from which data driven out. tosu terms notation used C6000 data sheets, except those C621x,C671x, C64x. tosu term shows setup time rising edge clock. term shows hold time from rising edge memory clock. refers clock period. Notice that data sheet notation directly implies clocking relationship device. example, data sheet C6201B SDRAM interface states that tosu 1.5P Referring diagram Figure seen that tdmax relative point from rising edge SDCLK, providing setup time 1.5P tdmax. other C6000 data sheets analyzed same way.
SDCLK tosu tdmax tdmin
C6201/C6202 C6203/C6204 C6205 C6201B/C6701
tdmax
tdmin
tosu 1.5P tdmax tdmax
tosu 0.5P tdmax tdmin
Figure C6201/C6202/C6203/C6204/C6205 C6201B/C6701 Output Timing
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Figure shows clock relationship used C621x/C671x/C64x SDRAM interface. Because this interface timed reference externally provided clock, C621x/C671x, C64x data sheets provide tdmax tdmin tosu parameters.
ECLKOUTx tdmax tdmin
C6211/C6711/C64xC
Figure C621x/C671x/C64x Output Timing
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
C6000 EMIF Registers
Control EMIF memory interfaces supports maintained through memory-mapped registers within EMIF. memory-mapped registers shown Table Table C6000 EMIF Memory Mapped Registers
Byte Address
EMIF EMIFA 0x01800000 0x01800004 0x01800008 0x0180000C 0x01800010 0x01800014 0x01800018 0x0180001C 0x01800020 0x01800044 0x01800048 0x0180004C 0x01800050 0x01800054
EMIFB 0x01A80000 0x01A80004 0x01A80008 0x01A8000C 0x01A80010 0x01A80014 0x01A80018 0x01A8001C 0x01A80020 0x01A80044 0x01A80048 0x01A8004C 0x01A80050 0x01A80054
Abbreviation GBLCTL CE1CTL CE0CTL
Description EMIFx Global Control EMIFx Space Control EMIFx Space Control Reserved
CE2CTL CE3CTL SDCTL SDTIM SDEXT CE1SEC CE0SEC
EMIFx Space Control EMIFx Space Control EMIFx SDRAM Control EMIFx SDRAM Refresh Period EMIFx SDRAM extension EMIFx Space Secondary Control EMIFx Space Secondary Control Reserved
CE2SEC CE3SEC
EMIFx Space Secondary Control EMIFx Space Secondary Control
EMIFB applies C64x only Applies C621x, C671x, C64x only. Reserved other devices.
2.5.1
EMIF Global Control Register
EMIF global control register configures parameters common spaces (see Figure Figure 17). Table lists only those parameters relevant with SDRAM.3
Reserved R/W-0 SDCEN R/W-1 SSCEN R/W-1 Reserved R/W-1 CLK1EN R/W-1 Reserved R/W-1 ARDY SSCRT R/W-0 HOLD RBTR8 R/W-0 HOLDA
HOLD R/W-0
Legend: Read, R/W= Read/Write Fields exist C6202/C6203/C6204/C6205.
Figure C620x/C670x EMIF Global Control Register Diagram
description parameters EMIF global control register, TMS320C6000 Peripherals Reference
Guide.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Reserved HOLD EK1HZ R/W-0 BRMODE R/W-1 EK1EN R/W-1 Reserved CLK4EN R/W-1 BUSREQ CLK6EN R/W-1 ARDY Reserved R/W-1 EK2HZ R/W-0 HOLDA Reserved EK2EN
EK2RATE R/W-0 HOLD
Legend: Read, R/W= Read/Write
Figure C64x EMIF Global Control Register Diagram
Reserved R/W-0 Reserved R/W-0 NOHOLD R/W-0 R/W-0 Reserved R/W-1 R/W-1 EKEN R/W-1 R/W-1 BUSREQ CLK2EN R/W-1 Reserved R/W-0 ARDY HOLD
HOLDA
reserved fields should always written with their default values when modifying GBLCTL. Writing value other than default value these fields cause improper operation. Available C6713, C6712C, C6711C devices only; other C621x/C671x devices, this field reserved with R/W-1. This reserved C6713, C6712C, C6711C devices with R/W-0. Writing value other than this cause improper operation. Legend: Read/Write; Read only; value after reset
Figure C621x/C671x EMIF Global Control Register (GBLCTL)
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table EMIF Global Control Register Field Description
Field Description SDRAM clock enable (for C620x/C670x) C6201/C6701: SDCEN SDCLK held high SDCEN SDCLK enabled clock C6202/C6203/C6204/C6205: SDCEN CLKOUT2 held high MemType SDRAM
SDCEN
EKEN
ECLKOUT enable EKEN ECLKOUT held ECKEN ECLKOUT enabled clock ECLKOUT1 enable EK1EN ECLKOUT1 held EK1EN ECLKOUT1 enabled clock ECLKOUT2 Rate. ECLKOUT2 runs EK2RATE EMIF input clock (ECLKIN, CPU/4 clock, CPU/6 clock) rate EK2RATE 1/2x EMIF input clock (ECLKIN, CPU/4 clock, CPU/6 clock) rate EK2RATE 1/4x EMIF input clock (ECLKIN, CPU/4 clock, CPU/6 clock) rate
EK1EN
EK2RATE
Applies C64x control register only Applies C621x/C671x devices, excluding C6211/C6711.
Note that CLK2EN available C6202/C6203/C6204/C6205. CLKOUT2 disabled either SSCEN SDCEN, depending MemType used. This possible because only synchronous MemType allowed system.
2.5.2
Space Control Registers
Figure Figure show four space control registers, which correspond four spaces supported EMIF. MTYPE field identifies memory type corresponding space. MTYPE selects SDRAM SBSRAM, remaining fields register apply. asynchronous type selected (ROM asynchronous), remaining fields specify shaping address control signals access that space. only field interest SDRAM MTYPE field. Modification space control register should done until that space inactive.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table lists field descriptions Figure Figure
WRITE SETUP R/W-1111 READ STROBE R/W-111111 WRITE STROBE R/W-111111 MTYPE R/W-010 READ SETUP R/W-1111 WRITE HOLD R/W-11
Reserved R-11
Reserved
READ HOLD R/W-11
Legend: Read, R/W= Read/Write
Figure C620x/C670x EMIF Space Control Register Diagram
WRITE SETUP R/W-1111 R/W-11 READ STROBE R/W-111111 WRITE STROBE R/W-111111 MTYPE R/W-010 READ SETUP R/W-1111 Write Hold R/W-0 READ HOLD R/W-011
WRITE HOLD R/W-11
Legend: Read, R/W= Read/Write
Figure C621x/C671x/C64x EMIF Space Control Register Diagram Table C6000 EMIF Space Control Register Field Description SDRAM
Field MTYPE Description Memory Type corresponding Spaces MTYPE C620x/C670x MTYPE 011b: 32-bit-wide SDRAM MTYPE C621x/C671x/C64x MTYPE 0011b: 32-bit-wide SDRAM MTYPE 1000b: 8-bit-wide SDRAM MTYPE 1001b: 16-bit-wide SDRAM MTYPE 1101b: 64-bit-wide SDRAM
32-bit 64-bit interfaces apply C6712, C6712C, C6712D, well package type C6713 C6713B, C64x EMIFB. 64-bit interface applies C64x EMIFA only.
2.5.3
SDRAM Control Register (SDCTL)
SDRAM control register controls SDRAM parameters spaces that specify SDRAM memory type MTYPE field associated space control register (see Figure 21). Because SDRAM control register controls SDRAM spaces, each space should contain SDRAM with same timing page characteristics ensure compatibility; however, absolutely necessary have same page characteristics. following section, entitled Interchangeable SDRAM Devices Upgrading (C64x only), more information.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
timing fields EMIF SDRAM control register terms EMIF clock period. C620x/C670x, tcyc twice period because SDCLK CLKOUT2 1/2x frequency. C621x/C671x, tcyc equals ECLKOUT period. C64x, tcyc equals ECLKOUT1 period. Table lists field descriptions Figure
Reserved SDBSZ Reserved R/W-0 TRCD R/W-0100 R/W-1111
Refers C621x/C671x C64x only. Refers C620x/C670x only. Refers C64x only.
SDRSZ
SDCSZ
SDWID R/W-0
RFEN R/W-1
INIT
R/W-1000
Reserved R/W-0
SLFRFR R/W-0
Reserved
Figure EMIF SDRAM Control Register Table EMIF SDRAM Control Register Field Description
Field Description Specifies value SDRAM EMIF clock cycles. (tRC/tcyc) Specifies value SDRAM EMIF clock cycles. (tRP/tcyc) Specifies tRCD value SDRAM EMIF clock cycles. TRCD (tRCD/tcyc) Forces initialization SDRAM present. INIT effect. INIT initialize SDRAM each space configured SDRAM. Refresh enable. RFEN SDRAM refresh disabled. RFEN SDRAM refresh enabled. SDRAM width select. (C620x/C670x) SDWID page size words (9-column address pins) SDWID page size words (8-column address pins)
TRCD
INIT
RFEN
SDWID
C64x, TRCD specifies number ECLKOUT1 cycles between ACTV command READ command (CAS). separation maintained while driving write data cycle earlier.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table EMIF SDRAM Control Register Field Description (Continued)
Field SDCSZ Description SDRAM column size. (C621x/C671x/C64x) SDCSZ 9-column address pins (512 elements row) SDCSZ 8-column address pins (256 elements row)) SDCSZ 10-column address pins (1024 elements row) SDCSZ reserved SDRAM size. (C621x/C671x/C64x) SDRSZ address pins (2048 rows bank) SDRSZ address pins (4096 rows bank) SDRSZ address pins (8192 rows bank) SDRSZ reserved SDRAM bank size. (C621x/C671x/C64x) SDBSZ bank-select (two banks) SDBSZ bank-select pins (four banks)
SDRSZ
SDBSZ
C64x, TRCD specifies number ECLKOUT1 cycles between ACTV command READ command (CAS). separation maintained while driving write data cycle earlier.
2.5.4
SDRAM Timing Register (SDTIM)
SDRAM timing register controls refresh PERIOD SDRAM terms EMIF clock cycles, tcyc. tcyc twice clock period C620x/C670x. tcyc equal ECLKOUT period C621x/C671x/C64x. When counter reaches zero, automatically reloaded with PERIOD continues decrementing. Figure shows register configuration SDTIM, Table describes fields. C621x/C671x C64x control number refreshes performed when refresh counter expires XRFR field. four refreshes performed when refresh counter expires. This field useful because C621x/C671x C64x does differentiate between trickle urgent refreshes. When refresh counter expires, C621x/C671x C64x EMIF interrupts accesses soon possible execute required number refreshes. Figure EMIF SDRAM Timing Register
Reserved
COUNTER R-0000 0100 0000 R-0101 1101 1100
PERIOD R/W-0000 0100 0000 R/W-0101 1101 1100
XRFR R/W-00
Legend: Read, R/W= Read/Write Applies C620x/C670x only Applies C621x/C671x/C64x only
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table EMIF SDRAM Refresh Period Field Description
Field PERIOD Description C620x/C670x, refresh period CLKOUT2 cycles C621x/C671x, refresh period ECLKOUT cycles C64x, refresh period ECLKOUT1 cycles Current value refresh counter. Extra refreshes: controls number refreshes performed SDRAM when refresh counter expires
COUNTER XRFR
Applies C621x/C671x/C64x only
2.5.5
C621x/C671x/C64x SDRAM Extension Register (SDEXT)
SDRAM extension register C621x/C671x/C64x allows programming many SDRAM timing parameters. This programmability allows C621x/C671x/C64x interface wide variety SDRAMs. Also, timing register allows interface tweaked characteristics specific SDRAM rather than default parameters that generally apply worst-case parameters broad range SDRAMs. SDRAM extension register applies SDRAM memory spaces system, SDRAMs with identical timing characteristics must used. Alternatively, register programmed according worst-case timings SDRAMs system that system works correctly.
Reserved R2WDQM R/W-1 RD2WR R/W-111 RD2RD R/W-0 THZP TW,+11
WR2RD R/W-0 TRRD R/W-1
WR2WR R/W-0
R2WDQM R/W-1 R/W-1
WR2DEAC R/W-11
RD2DEAC R/W-11
R/W-11
TRAS R/W-111
Legend: Read, R/W= Read/Write
Figure C621x/C671x/C64x SDRAM Extension Register Table C621x/C671x/C64x EMIF SDRAM Extension Register Field Description
Field Description Specified latency SDRAM ECLKOUT cycles latency ECLKOUT cycles latency ECLKOUT cycles Specifies tRAS value SDRAM ECLKOUT cycles tRAS Specifies tRRD value SDRAM ECLKOUT cycles TRRD then tRRD ECLKOUT cycles TRRD then tRRD ECLKOUT cycles
TRAS
TRRD
C64x, ECLKOUT referenced this table equivalent ECLKOUT1.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C621x/C671x/C64x EMIF SDRAM Extension Register Field Description (Continued)
Field Description Specifies value SDRAM ECLKOUT cycles Specifies tHZP value SDRAM ECLKOUT cycles THZP tHZP Specifies number cycles between READ READ command (same space) SDRAM ECLKOUT cycles RD2RD READ READ ECLKOUT Cycle RD2RD READ READ ECLKOUT Cycle Specifies number cycles between READ DEAC/DCAB SDRAM ECLKOUT cycles RD2DEAC cycles READ DEAC/DCAB) Specifies number cycles between READ WRITE command SDRAM ECLKOUT cycles RD2WR cycles READ WRITE) Specifies number cycles that signals must high preceding WRITE interrupting READ R2WDQM cycles high) Specifies minimum number cycles between WRITE WRITE command SDRAM ECLKOUT cycles WR2WR cycles WRITE WRITE) Specifies minimum number cycles between WRITE DEAC/DCAB command SDRAM ECLKOUT cycles WR2DEAC cycles WRITE DEAC/DCAB) Specifies minimum number cycles between WRITE READ command SDRAM ECLKOUT cycles WR2RD cycles WRITE READ)
THZP
RD2RD
RD2DEAC
RD2WR
R2WDQM
WR2WR
WR2DEAC
WR2RD
C64x, ECLKOUT referenced this table equivalent ECLKOUT1.
Interchangeable SDRAM Devices Upgrading (C64x only)
improved features addressing C64x allows device manipulated that interface multiple SDRAM devices with slightly different page characteristics from each other. This capability allow user swap upgrade current SDRAM devices system with newer devices, given that specifications met. C64x page register always stores bits address, instead being limited number address bits plus number bank address bits C621x/C671x. Also, C64x interface 256M bytes memory space, compared C6x0x that only interface bytes memory space, which limits number compatible memories market today. Even though EMIF only SDCTL register four spaces, extra bits page register manipulated allow multiple SDRAM devices allow future upgrades.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
first constraint this configuration that SDRAMs connected four spaces must have same number COLUMN bits. Also, with SDRAM interface, number column, row, bank bits must fall within those specified device. order upgrade SDRAM device, footprint memory device must match old. upgrade existing SDRAM device additional, larger SDRAM device, memories should connected such that their BANK SELECTS always common. EMIF should then configured according smallest row/bank combination. Figure example logical addresses types SDRAM devices.
Type
Space
nbb=2
Type
Space
nbb=2
Figure SDRAM Logical Address Bits Given memory types with different page characteristics, such Type Type seen Figure EMIF must configured match that Type Using this configuration bank select bits, BA1, connected logical address bits Type memory device, since connected logical address bits most significant address will then driven Figure shows configuration logical address bits non-linearly ordered bits (rb[x] figure). This will allow take advantage banks SDRAM access parts memory both SDRAMs.
Type rb[11] [10:1]
Space
nbb=2
Figure Modified Type Logical Address Bits This logical address will allow bank select pins EMIF always connect with bank select pins SDRAM, which will driven logical address bits Type Figure Type Figure Figure shows this configuration should pins allow interchangeability between different SDRAM devices. Note 256M-bit device Figure that connected address after A11, rather placed between two. same occurs 128M-bit device Figure except that placed after BA1.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
128M-bit EMIFA 256M-bit
EMIFB uses pins EA[x-2], where number EMIFA.
EA14 EA15 EA16 EA17
Figure EMIFA SDRAM Interface x16-Bit SDRAM
bits EMIFA 128M bits
EMIFB uses pins EA[x-2], where number EMIFA.
EA13 EA14 EA15 EA16
Figure EMIFA SDRAM Interface SDRAM Table shows different SDRAM configurations that compatible with previous method. Table Upgradeable Compatible SDRAM Devices
SDRAM Width Column Addressing A[0:7] A[0:8] Interchangeable Sizes
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
SDRAM
SDRAM Commands
EMIF supports SDRAM commands described Table These commands detailed following sections. Table EMIF SDRAM Commands
Command ACTV READ REFR DCAB DEAC SLFREFR
Function Activate selected bank select row. Input starting column address begin read operation. Input starting column address begin write operation. Mode register set. Configure SDRAM mode register. Auto refresh cycle with internal address Deactivate (also known precharge) banks. Deactivate single bank. Selected bank-select address outputs. Self-refresh mode
DEAC supported C621x/C671x/C64x only. C64x only
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Truth Table SDRAM Commands
SDRAM: 16-bit EMIF: 32-bit EMIF: 64-bit EMIF: ACTV A[19:16] A[15:11] A[9:0]
SDCKE
SDRAS
SDCAS
SDWE
EA[20:17] EA[16:12] EA[17:13] EA[22:19] EA[18:14] 0001b Bank/Row
EA11 EA12#
EA[10:1] EA[11:2]k EA[12:3]||
SDRAS
SDCAS
SDWE
SDCKE
SDRAS
SDCAS
SDWE
EA13
READ
Bank/ Column Bank/ Column L/Mode Bank/X
Column
Column
DCAB DEAC REFR SLFREFR
Mode
Mode
Legend: Bank Bank Address; Address; Column Column Address; High Previous value; Mode Mode Select 16-bit EMIF includes C64x EMIFB; 32-bit EMIF includes C62x/C67x EMIF, both 32-bit 16-bit interfaces; 64-bit EMIF includes C64x EMIFA, both 64-bit 32-bit interfaces. C64x DSP, upper address bits used during ACTV indicate non-PDT (0001b) (0000b) access. During other accesses, address bits indicated with hold previous value. SDCKE does exist C62x/C67x DSP, EMIFB. C62x/C67x DSP, upper address bits reserved future use. Undefined. SDA10 used C620x/C670x DSP. EA12 used C621x/C671x DSP. EMIF address numbering C64x 32-bit EMIFA begins with maintain signal name compatibility with C64x 64-bit EMIFA. EMIF address numbering C6712/C6712C 16-bit EMIF begins with maintain signal name compatibility with C62x/C67x 32-bit EMIF.
3.1.1
Timing Requirements
Several SDRAM timing parameters decouple EMIF from SDRAM speed limitations. three these parameters programmable EMIF SDRAM control register; remaining assumed static values, shown Table three programmable values assure that EMIF control SDRAM obeys these minimum timing requirements. Consult manufacturer's data sheet particular SDRAM.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C620x/C670x SDRAM Timing Parameters
Parameter tRCD tRAS tnEP Description REFR command ACTV, MRS, subsequent REFR command ACTV command READ command DCAB command ACTV, MRS, REFR command ACTV command DCAB command Overlap between read data DCAB command Value EMIF Clock Cycles TRCD
NOTE: Cycles shown following timing diagrams have TRCD (tRCD CLKOUT2 cycles).
C621x/C671x/C64x additional programmable timing parameters that programmable SDRAM control register SDRAM extension register. These parameters superset parameters C620x/C670x (see Table 15). Consult manufacturer's data sheet particular SDRAM. Table C621x/C671x/C64x SDRAM Timing Parameters
Value EMIF Clock Cycles TRCD TRAS TRRD THZP
Parameter tRCD tRAS tRRD tHZP
Description REFR command ACTV, MRS, subsequent REFR command ACTV command READ command DCAB/DEAC command ACTV, MRS, REFR command Latency SDRAM ACTV command DEAC/DCAB command ACTV bank ACTV bank (same space) Write recovery, time from last data C6000 (write data) DEAC/DCAB command High from precharge, time from DEAC/DCAB SDRAM outputs (read data) high
C621x/C671x/C64x also allows user program other functional parameters SDRAM controller. These parameters explicitly spelled timing parameters data sheet, user must ensure that parameters programmed valid value. most common SDRAMs, following values used (see Table 16). user must ensure that these values appropriate specific SDRAM.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C621x/C671x/C64x Recommended Values Parameters
Value EMIF Clock Cycles Suggested Suggested Value Value RD2RD RD2RD
Parameter READ READ READ DEAC READ WRITE
Description
READ command READ command. Used RD2RD interrupt READ burst random READ addresses. Used conjunction with tHZP. Specifies minimum RD2DEAC amount time between READ command DEAC/DCAB command. READ WRITE command. value programmed RD2WR this parameter depends tCL. READ WRITE should latency plus cycles EMIF clock cycles) provide turnaround cycle before WRITE command. Specifies number cycles that outputs R2WDQM should high before write allowed interrupt read. This related READ WRITE parameter.
RD2DEAC
RD2DEAC
RD2WR
RD2WR
high before write interrupting read WRITE WRITE WRITE DEAC WRITE READ
R2WDQM
R2WDQM
Number cycles between WRITE interrupting WR2WR WRITE. Used random WRITEs. Number cycles between WRITE command WR2DEAC DEAC/DCAB command Number cycles between WRITE command WR2RD READ command
WR2WR
WR2WR
WR2DEAC
WR2DEAC
WR2RD
WR2RD
3.1.2
Deactivation (DCAB DEAC)
DCAB command issued close active pages memory (shown Figure 28). SDRAM deactivation (DCAB) performed after hardware reset when INIT EMIF SDRAM control register. This cycle required SDRAMs prior REFR MRS. C620x/C670x, DCAB also issued when page boundary crossed. During DCAB command, SDA10 (for C6201/C6202/C6203/C6204/ C6205/C6211), EA12 (C621x/C671x), EA13 (C64x EMIFA), EA11 (C64x EMIFB) driven high ensure that SDRAM banks deactivated. C621x/C671x/C64x also supports DEAC command (shown Figure 29). C621x/C671x/C64x ability have more than page open space simultaneously. DEAC command allows C621x/C671x/C64x close only desired page. When page boundary crossed, DEAC command used close open page. C621x/C671x/C64x still supports DCAB command close open pages before REFR command issued.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
DCAB Clock BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE C621x/C671x, EA12 used. C64x EMIFA, EA13 used. C64x EMIFB, EA11 used.
Figure SDRAM DCAB-Closes Banks Space
DEAC ECLKOUT BE[3:0] EA[21:13] EA12 EA[11:2] ED[31:0] SDRAS SDCAS SDWE C64x, ECLKOUT1 used. C64x EMIFA, EA13 used. C64x EMIFB, EA11 used. Bank Select
Figure C621x/C671x/C64x SDRAM DEAC-Closes Single Bank Specified
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.1.3
Activate (ACTV)
Activate (ACTV) command issued before read write SDRAM. ACTV command opens page memory, allowing future accesses (reads writes) with minimum latency. shown Figure Figure when ACTV command issued EMIF, delay tRCD incurred before read write command issued this example, tRCD EMIF clock cycles). Reads writes currently active bank SDRAM achieve much higher throughput than reads writes random areas because every time page accessed, ACTV command must issued.
3.1.4
SDRAM Read (READ)
SDRAM read, selected bank activated with address during ACTV command. this example, three read commands performed three successive column addresses same page.
3.1.4.1
C620x/C670x Read
C620x/C670x EMIF uses latency burst length three-cycle read latency causes data appear three cycles after corresponding column address, shown Figure Refresh cycle access different page memory required, DCAB cycle performed following last column access deactivate bank. idle cycle inserted between final read command DCAB command meet SDRAM timing requirements. transfer data completes during past DCAB command (controlled tnEP). access pending, DCAB command performed until page information becomes invalid.
tRCD cycles ACTV Clock BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Address Bank Activate/Row Address Latency cycles Read Read Read C6000 Latches data
Figure C620x/C670x SDRAM Read-CAS Latency
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.1.4.2
C621x/C671x Read
C621x/C671x EMIF programmed latency either three cycles. burst length fixed four words both reads writes. general, using faster latency results slightly slower timings SDRAM device. This require running EMIF slower clock frequency. Depending requirements system, this acceptable. example shown Figure three-word read uses latency three cycles. three-cycle read latency causes data appear three cycles after corresponding column address. This example assumes that accesses pending SDRAM. this case, allowed driven SDRAM, C6000 ignores this data because only three words required this example. access pending, DEAC command performed until page information becomes invalid.
tRCD cycles ACTV ECLKOUT BE[3:0] EA[15:2] ED[31:0] EA12 SRAS SDCAS SDWE Address Bank Activate/Row Address Bank/Column Read Latency cycles C6000 Latches data ignored
Figure C621x/C671x SDRAM Read-CAS Latency refresh cycle pending, DCAB cycle will performed deactivate bank. access different page memory same bank SDRAM required (that page miss), DEAC command will issued following last column access, followed ACTV open correct page. DEAC/DCAB command timing controlled THZP RD2DEAC. These parameters ideally programmed that transfer data completes during after DCAB/DEAC command. example Figure shows same example shown Figure with access pending different page same bank. With THZP (tHZP cycles), DEAC command issued same time latched, causing outputs SDRAM stop driving data before This good because only three words were needed. Because next access same bank SDRAM, ACTV command issued soon possible controlled parameter, which three cycles this example.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
tHZP cycles cycles tRCD cycles Latency cycles DEAC C6000 Latches data ACTV ECLKOUT Read
BE[3:0] EA[15:2] ED[31:0] EA12 SDRAS SDCAS SDWE Address Bank Activate/Row Address
Bank/Column
Bank Bank Activate/.
Figure C621x/C671x SDRAM Read With DEAC 3.1.4.3 C64x Read
C64x also uses burst length four. basic SDRAM read, read almost identical that C621x/C671x. example shown Figure three doubleword (EMIFA) half-word (EMIFB) read burst from SDRAM. latency three cycles used, which causes data appear three cycles after corresponding column address. example assumes that accesses pending SDRAM. ACTV command issued future accesses same open page.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
tRCD cycles
Latency cycles Read
C64x Latches Data
ACTV ECLKOUT1 BE[7:0] EA[22:14] EA[12:3] ED[63:0] EA13 SDRAS SDCAS SDWE EA19 Address Bank/Row
Bank Column
EMIFB, BE[1:0], EA[20:12], EA[10:1], ED[15:0], EA11, respectively, used.
Figure C64x SDRAM Read-CAS Latency refresh cycle pending, DCAB cycle will performed deactivate bank. access different page memory same bank SDRAM required (that page miss), DEAC command will issued following last column access, followed ACTV open correct page.
3.1.5
SDRAM Write (WRT)
SDRAM write, selected bank activated with address during ACTV command. this example, three write commands performed three successive column addresses same page.
3.1.5.1
C620x/C670x SDRAM Writes
SDRAM writes have burst length (see Figure 34). bank activated with address during ACTV command. There latency writes, data output same cycle column address. Byte half-word writes enabled appropriate inputs. Following final write command, idle cycle inserted meet SDRAM timing requirements. required, bank then deactivated with DCAB command ,and memory interface begin page access. access pending, access pending same page, DCAB command performed until page information becomes invalid.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
tRCD cycles ACTV Clock BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Address Bank Activate/Row Address WRITE WRITE WRITE
Figure C620x/C670x SDRAM Burst Length Write 3.1.5.2 C621x/C671x SDRAM Writes
C621x/C671x, SDRAM writes have burst length (see Figure 35). bank activated with address during ACTV command. There latency writes, data output same cycle column address. Byte half-word writes enabled appropriate inputs. less than four-word burst required, write data masked outputs (tied inputs SDRAM). Following final write command, idle cycles inserted according TWR, WR2DEAC, and/or WR2RD parameters meet SDRAM timing requirements. refresh pending, banks then deactivated with DCAB command. page miss occurred, DEAC command issued followed ACTV correct page. DEAC/DCAB command performed until page information becomes invalid.
tRCD cycles ACTV ECLKOUT BE[3:0] EA[15:2] ED[31:0] EA12 SDRAS SDCAS SDWE Address Bank Activate/Row Address WRITE blocked
Bank/Column
Figure C621x/C671x SDRAM Burst Length Write
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.1.5.3
C64x SDRAM Writes
C64x also uses burst length four. write almost identical that C621x/C671x with following exception:
Write data driven cycle early
example shown Figure three doubleword (EMIFA) half-word (EMIFB) write C64x. There latency writes data output same cycle column address. example assumes that accesses pending SDRAM. ACTV command issued future accesses same open page.
tRCD cycles ACTV ECLKOUT1 BE[7:0] EA[22:14] EA[12:3] ED[31:0] EA13 SDRAS SDCAS SDWE Address Bank/Row WRITE blocked
Bank Column
EA19
EMIFB, BE[1:0], EA[20:12], EA[10:1], ED[15:0], EA11, respectively, used.
Figure C64x SDRAM Burst Length Write
3.1.6
Mode Register (MRS)
mode register located external SDRAM memory that dictates operating characteristics. When initializing SDRAM, EMIF must this register value described here before normal read write accesses occur. EMIF automatically performs DCAB command followed eight refreshes, followed command whenever INIT field EMIF SDRAM control register set. INIT device reset user write. with DCAB REFR commands, commands sent spaces configured SDRAM. Following cycle, INIT cleared prevent multiple cycles. C620x/C670x EMIF always uses mode register value 0x0030 during command. C621x/C671x/C64x uses value either 0x0032 0x0022, depending latency interface. Figure shows mapping between mode register bits, EMIF pins, mode register value.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table shows SDRAM configuration selected this mode register value, Table shows mplied SDRAM configuration value.
Clock BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Clock SDCLK C6201/C6701. CLKOUT2 C620x/C670x except C6201/C6701. ECLKOUT C621x/C671x. ECLKOUT1 C64x. C64x EMIFA, EA[16:3] used instead. C64x EMIFB, EA[14:1] used instead. C621x/C671x, EA12 used. C64x EMIFA, EA13 used. C64x EMIFB, EA11 used. value
Figure SDRAM Mode Register Set: Command Table Mode Register Value
Mode Register EMIF Pins Field EA11 Write Burst Length EA10
EA15 EA14 EA13 SDA10 Reserved
Reserved
Read Latency
Burst Length
C6201/C6202 /C6203/C6204/ C6205/ C6701 C621x/C671x/ C64x w/CL C621x/C671x/ C64x w/CL
C64x EMIFA, EA[16:3] used instead. NOTE: C64x EMIFB, EA[14:1] used instead.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Implied SDRAM Configuration Value
C621x/C671x/C64x Selection Serial C621x/C671x/C64x Selection Serial
Field Write burst length Read latency Serial/interleave burst type Burst length
C620x/C670x Selection Serial
3.1.7
Refresh
RFEN SDRAM control register, shown Figure selects SDRAM refresh mode EMIF. value RFEN field disables EMIF refreshes; user must ensure that refreshes implemented external device. value RFEN field enables EMIF perform refreshes SDRAM described this section. refresh command (REFR) sent spaces configured SDRAM MTYPE field corresponding space control register. REFR automatically preceded DCAB command. This ensures that spaces selected with SDRAM deactivated before refresh occurs. Page information always invalid before after REFR command; thus refresh cycle always forces page miss next access. Figure
REFR Clock BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE
*Clock SDCLK C6201/C6701. CLKOUT2 C620x/C670x except C6201/C6701. ECLKOUT C621x/C671x. ECLKOUT1 C64x. C64x EMIFA, EA[16:3] used instead. C64x EMIFB, EA[14:1] used instead. C621x/C671x, EA12 used. C64x EMIFA, EA13 used. C64x EMIFB, EA11 used.
Figure SDRAM Refresh
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.1.7.1
C620x/C670x Refresh Operation
Following DCAB command, EMIF begins performing trickle refreshes rate defined PERIOD value EMIF SDRAM control register, provided other SDRAM access pending. SDRAM interface monitors number refresh requests posted performs them. Within EMIF SDRAM control block, 2-bit counter monitors backlog refresh requests. counter increments once each refresh request, decrements once each refresh cycle performed. counter saturates values reset, counter automatically ensure that several refreshes occur before accesses begin. value indicates urgent refresh condition, causing page information register invalidated forcing controller close current SDRAM page. Thus, EMIF SDRAM controller performs three REFR commands, decrementing counter following DCAB command before proceeding with remainder current access. SDRAM present multiple spaces, DCAB-refresh sequence occurs spaces containing SDRAM. During idle times SDRAM interface(s), request pending from EMIF, SDRAM interface performs REFR commands long counter value nonzero. This feature reduces likelihood having perform urgent refreshes during actual SDRAM accesses later. Note that SDRAM present multiple spaces, this refresh occurs only interfaces idle with invalid page information. 3.1.7.2 C621x/C671x/C64x Refresh Operation
C621x/C671x/C64x EMIF does concept urgent versus trickle refresh. refresh requests considered high priority. refresh request issued while transfer progress, EMIF will complete current burst data (see TMS320C64x EDMA Architecture (SPRA994) default burst size), then perform required number refreshes (controlled XRFR field). Once refreshes have been completed, transfer progress will resumed. XRFR field allows four requests issued succession each time refresh counter expires. This gives system designer option allowing requests happen less often while still meeting requirements SDRAM. 3.1.7.3 Self Refresh Mode (C64x Only)
SLFRFR SDRAM control register (SDCTL) allows user force EMIF place external SDRAM low-power mode, called Self Refresh. SDRAM maintains valid data consumes minimal amount power while Self Refresh mode. Self Refresh mode begins when written SLFRFR SDRAM exists system. refresh enable bit, RFEN, SDCTL must written with simultaneously. When SLFRFR asserted, open pages SDRAM closed ,and REFRESH command issued same cycle that SDCKE signal driven low. exit SLFRFR mode, write SLFRFR then immediately read back before performing other accesses. While SLFRFR asserted, user should ensure that SDRAM accesses performed. Also, while self refresh mode, SDRAM clock (ECLKOUT1) turned used elsewhere system ,and system does Hold interface.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
effects SLFRFR with SDRAM system summarized here:
write SLFRFR while hold allows self refresh mode entry/exit. write SLFRFR while hold will ignored will written. HOLD request occurs while SLFRFR EMIF ensures device been self refresh mode least TRAS cycles, where TRAS defined SDEXT register. Then EMIMF exits self refresh mode after ECLKOUT1 cycles, EMIF will acknowledge HOLD request.
SDRAM Initialization
After reset, none spaces configured SDRAM. should initialize space control registers SDRAM extension register before performing SDRAM initialization setting INIT SDRAM does exist system, should write INIT bit. EMIF performs following steps when INIT Sends DCAB command spaces configured SDRAM. Sends eight refresh commands. Sends command spaces configured SDRAM. duration SDRAM initialization, signals inactive high. SDRAM initialization noninterruptible other EMIF accesses.
Monitoring Page Boundaries
Because SDRAM paged memory type, EMIF SDRAM controller monitors active SDRAM that boundaries crossed during course access. accomplish this monitoring, EMIF stores address open page performs compares against that address subsequent accesses SDRAM bank.
3.3.1
C620x/C670x Page Boundaries
C620x/C670x allows single page open each space. number address bits compared function page size programmed SDWID field EMIF SDRAM control register. SDWID SDRAM control register, EMIF expects spaces configured SDRAM have page sizes words. Thus, logical byte address bits compared 25:11. SDWID EMIF expects spaces with SDRAM have SDRAMs that have page sizes 256. Thus, logical byte address bits compared 25:10.4 page boundary crossed during course access, EMIF performs DCAB command starts access. Note that simply ending current access condition that forces active SDRAM closed. EMIF speculatively leaves active open until becomes necessary close This feature decreases deactivate-reactivate overhead allows interface fully capitalize address locality memory accesses.
Note that upper address bit, both 8-bit- 16-bit-wide SDRAM used indicate logical
address range accessible EMIF, that CE3, which address 0x03FFFFFF. Thus, logical address lines (0:25) needed.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.3.1.1
Crossing Page Boundary
already stated above, write burst extends across page boundary within same space, previous page must closed before correct page opened write continued. When this happens, signals will transition high, cycle after last write performed. This occurs before page closed. signals will transition high immediately after last write performed. This blocks additional write that would allowed signals staying high additional cycle. This behavior true C620x/C670x devices.
3.3.2
C621x/C671x Page Boundaries
C621x/C671x allows four pages open simultaneously. Open pages distributed across spaces located same space. example, pages open four pages open CE0. maximum number open pages single space limited number banks SDRAM, which programmed into SDBSZ field. Only page open bank time. combination SDCSZ, SDRSZ, SDBSZ control which logical address bits compared determine page open. example, typical 2-bank 512K 16-bit SDRAM settings banks, eleven address bits, eight column address bits. 32-bit-wide SDRAM access uses logical address bits A[9:2] (two-bit offset word addressing) specify column being accessed (that address within page). Bits A[20:10] specify offset (that page within bank) A[21] specifies bank. Logical address bits A[31:28] determine space used. page boundary crossed during access same bank space, C621x/C671x performs DEAC command starts access. access different bank performed, C621x/C671x EMIF does always close first page. Each bank SDRAM space simultaneously have open page pages closed with random replacement strategy. page miss occurs access bank that currently page open, that bank must closed open correct page. However, access occurs bank that does have page open, four page registers use, four pages randomly closed with DEAC command, page opened. example, assume that SDRAM that banks (such 2-bank 512K 16-bit device) CE0. Therefore, CE0, Bank0 CE0, Bank1 simultaneously have open pages. Assume Bank0 open page Bank1 does not. access Bank0 results page miss, that page must closed before correct page Bank0 opened. access Bank1 must first open correct page. four page registers internal C6000 (assuming that other spaces have open pages), single page closed random correct page CE0, Bank1 opened. four page registers use, CE0, Bank1, Pagex opened immediately. Figure
Bank
Address
space
Column Address (Address within Page)
Byte
(Page within bank)
Figure Logical Address Breakdown Bank Bit, Bits, Column Bits
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.3.3
C64x Page Boundaries
C64x performs very similar C621x/C671x SDRAM paging scheme. Both allow four pages SDRAM opened simultaneously, space spread across multiple spaces. Also, like C621x/C671x, number column address bits controls number least significant address stored page resister. maximum number open pages single space limited number banks SDRAM, which programmed into SDBSZ field. Unlike C621x/C671x, C64x page register always stores bits address (instead being limited number address bits plus number bank address bits (NRB_NBB)). logical address bits above bank address used part page comparison. Also, address bits above bank bits used when issuing row/column commands external SDRAM. This provides device with more flexible designs external visibility into internal address aliasing. C64x EMIF employs least recently used (LRU) page replacement strategy when necessary. When total number external SDRAM banks (not devices) exceeds four (since EMIF only four page registers) then strategy used. total number banks SDRAM less than equal four, then page replacement strategy fixed since SDRAM required that only page open within given bank. page miss detected, then C64x performs DEAC command starts access. Figure shows example 4-bank 32-bit SDRAM with bank 645, twelve address bits, eight column address bits that mapped EMIFA.
space
nbb=2
Address (nrb (Page within bank)
Column Address (ncb (Address within page)
Page Register bits
Figure Logical Address Breakdown Bank Bits, Bits, Column Bits
Address Shift
Because same EMIF pins address column address, EMIF interface appropriately shifts address column address selection. Table Table Table shows translation between bits logical byte address they appear pins column addresses. SDRAMs address inputs control well address. With this consideration, following items clarify figure:
address line that corresponds SDRAM's bank-select latched internally SDRAM controller. This ensures that bank select remains correct during READ commands. Thus, EMIF maintains these values shown both column addresses. EMIF forces precharge disable (SDA10 C620x/C670x, EA12 C621x/C671x, EA13 C64x EMIFA, EA11 C64x EMIFB) unless active low, high during DCAB commands page accesses. This prevents auto precharge from occurring following READ command.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C620x/C670x Byte Address Mapping SDRAM CAS5
EMIF Pins
SDRAM Pins Address Address Legend: SDRAM Width SDWID DRAM [21:17]
internally latched during ACTV command. Reserved future use. Undefined.
Note: values indicate byte address present corresponding during cycle. Low; SDA10 driven during READ commands disable autoprecharge.
Table C621x/C671x Byte Address Mapping SDRAM CAS6
Column Address Bits Interface Width [21:17] DRAM Legend:
internally latched during ACTV command. Reserved future use. Undefined.
driven. number address bits driven during cycle equal number (row bits bank-select bits).
Low; EA12 driven during READ commands disable autoprecharge. During cycle READ command, only bank select address bits bits, controlled SDBSZ) driven valid values. address bit(s) used determined number address bits number bank address bits. values indicate byte address present corresponding during cycle. values indicate byte address present corresponding during cycle.
Bank Bank Bank Bank Bank Bank Bank Bank Bank
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table C64x Byte Address Mapping SDRAM CAS7
EMIFB Interface Width DRAM Legend:
Column Address Bits
EMIFA
internally latched during ACTV command.
Low; logical address driven during READ commands disable autoprecharge. EA19 (EMIFA) EA17 (EMIFB) used during ACTV indicate non-PDT access. non-PDT access, this access, this during ACTV.
values indicate byte address present corresponding during cycle.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Timing Constraints
This section discusses timing constraints used determine SDRAM operate with C6000 given clock frequency. methods discussed have provide rough, error prone, estimate time margin present given system. recommended method performing timing analysis buffer specification (IBIS) models. properly IBIS models attain accurate timing analysis given system, Using IBIS Models Timing Analysis (SPRA839). following constraint calculations, time tmargin calculated representing margin system after taking into account worst-case numbers from memory C6000 data sheets. After calculating time tmargin, system-level issue determine proper amount margin been met. required timing margin extremely system dependent, depending primarily trace length loading, other factors come into play. Therefore, this parameter should determined particular system question. following discussion, used denote memory specifications. additional designators used denote C6000 timing specifications.
3.5.1
3.5.1.1
C6000 Outputs (ED, SDCAS, SDRAS, SDWE)
C620x/C670x Output Comparison
simplicity, C620x/C670x data sheets specify outputs setup time (tosu) next rising edge hold time (toh) from previous rising edge. Thus, comparison between C6000 specifications memory specifications extremely straightfoR/Ward. This also allows user unconcerned with which clock edge triggers output data. following equations derived from Figure calculate timing margin between C6000 desired SDRAM.
Setup
time: output setup time (tosu) from inactive active must provide ample setup time (tisu(m)) input. Therefore, margin available tmargin tosu tisu(m)
Hold time: output hold time (toh) from active inactive must greater than hold time required input (tih(m)). margin then: tmargin tih(m)
SBSRAM Latches Signal tcyc
tcyc EMIF Clock tosu tisu(m) 'C6000 Output
tih(m)
Figure Outputs From C620x/C670x (Write Data [ED], Control, Address Signals)
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
3.5.1.2
C621x/C671x/C64x Output Comparison
C621x/C671x, C64x data sheets specify outputs minimum delay maximum delay from rising edge ECLKOUT8. When comparing these parameters against specification particular SDRAM, maximum delay (tdmax) used verify that input setup time (tis(m)) memory met. minimum delay (tdmin) used verify that input hold time (tih(m)) memory met. following equations derived from Figure calculate timing margin between C621x/C671x/C64x desired SDRAM.
Setup time: maximum delay (tdmax) from clock output signal valid must provide ample setup time (tisu(m)) input. Therefore, margin available tmargin tcyc (tdmax tisu(m)) Hold time: minimum delay (tdmin) from clock output signal invalid must greater than hold time required input (tih(m)). margin then: tmargin tdmin tih(m)
SDRAM Latches Data tcyc EMIF Clock tih(m) tisu tdmax tdmin tcyc
'C6000 Outputs
Figure Outputs From C621x/C671x/C64x (Write Data [ED], Control, Address Signals)
3.5.2
C6000 Inputs (Output Data From SDRAM, Read
Figure shows output data from SDRAM occurs during read cycle. situation similar outputs from C6000 except that SDRAM must provide ample setup input hold C6000. constraints expressed follows:
Setup times: access time (tacc(m)) SDRAM must provide large enough input setup time (tsu) input C6000. tmargin tcyc (tacc(m) tsu) Hold times: output hold time (toh(m)) data output from SDRAM must provide hold time greater than hold time required input (tih) C6000. tmargin toh(m)
C64x, ECLKOUT referenced this section equivalent ECLKOUT1.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
tCYC EMIF Clock tacc(m) Read Data tacc(m)
'C6x Latches Data tCYC
toh(m)
Figure Input C6000 (Read Data)
3.5.3
Timing Comparisons Four SDRAMs
This section summarizes comparisons listed above four different SDRAMs with four different C6000 devices. Although every C6000 device shown following examples, approach same current C6000 devices. following examples, notice that more margin achieved with faster memory. example, 100-MHz interface desired, 125-MHz SDRAM will provide more margin than 100-MHz SDRAM. Although C6000 DSPs designed operate with SDRAMs rated speeds, sometimes extra margin worth extra cost faster memories. SDRAM data sheets should compared C6000 data sheet verify operation with desired margins.
3.5.3.1
C6202/C6203/C6204/C6205 Micron's MT48LC4M16A2-8
MT48LC4M16A2-8 64M-bit 16-bit device. C6202/C6203/C6204/C6205 interface, these devices used parallel, resulting addressable space bytes. This example uses C6202/C6203/C6204/C6205-250 running maximum clock speed ns). Because C6202/C6203/C6204/C6205 EMIF uses CLKOUT2 (which 1/2x speed) synchronous memory interfaces, Tcyc timing parameters MT48LC4M16A2-8 C6202/C6203/C6204/C6205-250 summarized shown Table Table MT48LC4M16A2-8 C6202/C6203/C6204/C6205-250 Timing Parameters
C6202/C6203/C6204/C6205-250 Tosu Outputs Tisu Inputs Outputs -0.2 Inputs Tacc Tcyc Tacc tisu MT48LC1M16A1-8 Tisu Tmargin Tosu Tisu
3.5.3.2
C6414 Micron's MT48LC32M8A2-7
MT48LC32M8A2-7 256M-bit 8-bit device, which results addressable space 128M bytes. This example uses C6414-500 running maximum clock speed ns). Because speed independent EMIF clock speed, externally provided clock synchronous memory interface, resulting Tcyc latency programmed
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
timing parameters MT48LC16M8A2-8 C6414-500 summarized shown Table Table MT48LC16M8A2-8 C6414-500 Timing Parameters
C6414-500 Tdmax Outputs Tdmin Tisu Inputs Outputs Inputs Tacc Tdmin Tcyc Tacc tisu MT48LC32M8A2-7 Tisu Tmargin Tcyc Tdmax Tisu
Complete Example Using C6201B Micron's MT48LC4M16A2-10
This section walks through register configuration interfacing C6201B with Micron's MT48LC4M16A2-10, which 512K 16-bit 4-bank SDRAM capable operating MHz. additional timing margin needed, this device available provides additional timing margin. Because memory bits wide, devices parallel complete 32-bit word, giving total addressable space bytes. block diagram interface schematic identical that shown Figure Assumptions:
CLKOUT1 frequency 100-MHz SDRAM clock frequency. (SDCLK CLKOUT2 CLKOUT1 frequency) Tcyc SDRAM located (logical address 0x02000000) Driven SDCLK SSCLK CLKOUT1 used other memory system CLKOUT2 system.
Register Configuration C6201B MT48LC4M16A2
Table shows registers bitfields that configured control C6201B MT48LC4M16A2 SDRAM interface. Table SDRAM Registers
Register Name EMIF global control EMIF space control EMIF SDRAM control EMIF SDRAM timing
Fields Required SDCEN, CLK2EN, SSCEN, CLK1EN MTYPE TRC, TRP, TRCD, INIT, RFEN, SDWID PERIOD
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
4.1.1
EMIF Global Control Registers C6201B MT48LC4M16A2
Because MT48LC4M16A2-10 SDRAM driven SDCLK, must then following, shown Figure
ARDY
HOLD
HOLDA
NOHOLD
SDCEN
SSCEN
CLK1EN
CLK2EN
SSCRT
RBTR8
Reserved
Reserved
NOTE: SDCEN indicates that SDCLK enabled clock because assume driving SDRAM interface. SSCEN indicates that SSCLK enabled because assume system. CLK1EN indicates that SSCLK enabled because assume system. CLK2EN indicates that CLKOUT2 disabled because assume system.
Figure EMIF Global Control Register Diagram C6201B MT48LC4M16A2 Thus, valid setting EMIF global control register 0x00003371. additional information remainder fields, TMS320C6000 Peripherals Reference Guide.
4.1.2
EMIF Space Control Register C6201B MT48LC4M16A2
shown Figure MTYPE indicates that 32-bit-wide SDRAM located address space. rest fields irrelevant because they refer asynchronous memory SDRAM configured this space. valid setting EMIF space control 0xFFFFFF33.
WRITE SETUP 1111
WRITE STROBE 111111
READ SETUP 1111
WRITE HOLD
READ STROBE 111111
MTYPE
Reserved
READ HOLD
Figure EMIF Space Control Register Diagram C6201B MT48LC4M16A2
4.1.3
EMIF SDRAM Control Register C6201B MT48LC4M16A2
SDRAM control register (Figure 46), values must actually calculated based clock frequency used (100 this example, tCYC 10ns) parameters SDRAM used. Table summarizes values.
Reserved 00000
SDWID
RFEN
INIT
0001
TRCD 0001
0110
Reserved
000000000000
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
NOTE: SDWID indicates that wide SDRAM used. RFEN indicates that SDRAM refresh enabled. INIT forces initialization SDRAM. TRCD 0010b from previous calculation. 0010b from previous calculation. 1000b from previous calculation
Figure EMIF SDRAM Control Register C6201B MT48LC4M16A2 shows registers bitfields that configured control C6201B MT48LC4M16A2 SDRAM interface. Table Timing Parameter Calculation SDRAM Control Register C6201B MT48LC4M16A2
Field Name TRCD Formula (tRC tCYC) (tRP tCYC) TRCD (tRCD tCYC) Value from Micron Data Sheet (min) (min) tRCD (min) Value Calculated Field TRCD Value Recommended
Based above calculations, value 0x07228000 should written EMIF SDRAM control register.
4.1.4
EMIF SDRAM Refresh Period C6201B MT48LC4M16A2
Based this result (see Figure Table 26), value 0x61A should written refresh period field EMIF SDRAM timing register. Figure EMIF SDRAM Refresh Period C6201B MT48LC4M16A2
Reserved
COUNTER
PERIOD
00000000 NOTE: Period 0x61A from previous calculation.
0000 0000 0000 R-0000 0100 0000
0110 0001 1010 (0x61A) R/W-0000 0100 0000
Table Period Calculation SDRAM Refresh Period C6201B MT48LC4M16A2
Field Name PERIOD Formula Value From TMS626812B Data Sheet Value Calculated Field Period 1562cycles 0x61A cycles
PERIOD tRefresh/tCYC tRefresh 4096 15.625µS
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Complete Example Using C6211 Micron's MT48LC16M8A2-8
This section walks through register configuration interfacing C6211 with Micron's MT48LC16M8A2-8, which 8-bit 4-bank SDRAM capable operating MHz. Because memory bits wide, four devices parallel complete 32-bit word, total addressable space bytes. block diagram interface schematic identical that shown Figure except that ECLKOUT used memory clock, EA12 used instead SDA10. This 125-MHz SDRAM featured because offers additional timing margin compared typical 100-MHz SDRAMs used system that requires extra margin. Assumptions:
100-MHz SDRAM clock frequency. (ECLKIN ECLKOUT MHz). Tcyc SDRAM located (logical address 0xB0000000) CLKOUT1 CLKOUT2 system
Register Configuration C6211 MT48LC16M8A2
Table shows registers bitfields that configured control C6211 MT48LC16M8A2 SDRAM interface.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table SDRAM Registers C6211 MT48LC16M8A2
Register Name EMIF global control EMIF space control EMIF SDRAM control EMIF SDRAM timing EMIF SDRAM extension Fields Required CLK1EN, CLK2EN MTYPE TRC, TRP, TRCD, INIT, RFEN, SDCSZ, SDRSZ, SDBSZ PERIOD
5.1.1
EMIF Global Control Registers C6211 MT48LC16M8A2
Because none programmable clocks system, must following, shown Figure
ARDY
HOLD
HOLDA
NOHOLD
CLK1EN
CLK2EN
Reserved
Reserved
Reserved
Reserved
NOTE: CLK1EN indicates that SSCLK enabled because assume system. CLK2EN indicates that CLKOUT2 disabled because assume system.
Figure EMIF Global Control Register Diagram C6211 MT48LC16M8A2 Thus, valid setting EMIF global control register 0x00003300. additional information remainder fields, TMS320C6000 Peripherals Reference Guide (SPRU190).
5.1.2
EMIF Space Control Register C6211 MT48LC16M8A2
shown Figure MTYPE indicates that 32-bit-wide SDRAM located address space. rest fields irrelevant because they refer asynchronous memory, SDRAM configured this space. valid setting EMIF space control 0xFFFFFF33.
WRITE SETUP 1111
WRITE STROBE 111111
READ SETUP 1111
WRITE HOLD
READ STROBE 111111
MTYPE 0011
Reserved
READ HOLD
NOTE: MTYPE 0011 indicates that 32-bit-wide SDRAM located address space. rest fields irrelevant because they refer asynchronous memory, SDRAM configured this space.
Figure EMIF Space Control Register Diagram C6211 MT48LC16M8A2 valid setting EMIF space control 0xFFFFFF33.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
5.1.3
EMIF SDRAM Control Register C6211 MT48LC16M8A2
SDRAM control register (Figure 50), values must actually calculated based clock frequency used (100 this example, tCYC parameters SDRAM used. Table summarizes values.
SDBSZ
SDRSZ
SDCSZ
RFEN
INIT
TRCD 0001
0001
0110
Reserved 000000000000
NOTE: SDCSZ indicates that column address bits used. SDRSZ indicates that address bits used. SDBSZ indicates that bank address bits used banks). RFEN indicates that SDRAM refresh enabled. INIT forces initialization SDRAM. TRCD 0001b from previous calculation. 0001b from previous calculation. 0110b from previous calculation.
Figure EMIF SDRAM Control Register C6211 MT48LC16M8A2 Table Timing Parameter Calculation SDRAM Control Register C6211 MT48LC16M8A2
Field Name TRCD Formula (tRC tCYC) (tRP tCYC) TRCD (tRCD tCYC) Value From KM416S4030 Data Sheet (min) (min) tRCD (min) Value Calculated Field TRCD Value Recommended
Based above calculations, value 0x5B116000 should written EMIF SDRAM control register.
5.1.4
EMIF SDRAM Refresh Period C6211 MT48LC16M8A2
Based this result, value 0x61A should written refresh period field EMIF SDRAM timing register. Figure Table
Reserved
COUNTER
PERIOD
00000000 NOTE: Period 0x61A from previous calculation.
000000000000
11000011010 (0x61A)
Figure EMIF SDRAM Refresh Period C6211 MT48LC16M8A2
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Period Calculation SDRAM Refresh Period C6211 MT48LC16M8A2
Field Name PERIOD Formula PERIOD tRefresh/tCYC Value From Micron Data Sheet tRefresh 4096 15.625µS Value Calculated Field Period 1562cycles 0x61A cycles
5.1.5
EMIF SDRAM Extension Register C6211 MT48LC16M8A2
SDRAM extension register, values must calculated based clock frequency used (100 this example, tCYC 10ns) parameters SDRAM used. Table summarizes values. Table SDRAM Extension Register Values C6211 MT48LC16M8A2
Field Name TRAS TRRD THZP RD2RD RD2DEAC RD2WR R2WDQM WR2WR WR2DEAC WR2RD
Formula (tCL) TRAS (tRAS tCYC) TRRD (tRRD tCYC) (tWR tCYC) THZP (tHZP) Recommended value from
Value From SDRAM Data Sheet cycles tRAS tRRD tHZP cycles
Value Calculated Field TRAS TRRD THZP
Value Recommended TRAS TRRD THZP RD2RD RD2DEAC RD2WR R2WDQM WR2WR WR2DEAC WR2RD
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Complete Examples Using C6414 Micron's MT48LC4M32B2-7
This section first walks through register configuration interfacing C6414 with Micron's MT48LC4M32B2-7, which 32-bit 4-bank SDRAM capable operating speeds MHz. Because memory bits wide, devices parallel complete 64-bit doubleword. block diagram interface schematic very similar that Figure except with previously noticed differences C64x EMIFA interface. interface will full speed interface speed MHz, maximum current speed EMIF interface. This DRAM featured because offers additional timing margin compared typical slower SDRAMs. Assumptions:
SDRAM clock frequency (ECLKIN ECLKOUT1 MHz) Tcyc SDRAM located EMIFA (logical address 0xA0000000) ECLKOUT2 system (EK2EN
Register Configuration C6414 MT48LC4M32B2
Table shows registers bitfields that configured control C6414 MT48LC4M32B2 SDRAM interface. Table SDRAM Registers C6414
Register Name EMIF global control EMIF space control EMIF SDRAM control EMIF SDRAM timing EMIF SDRAM extension
Fields Required EK1EN, EK2EN, EK2RATE MTYPE TRC, TRP, TRCD, INIT, RFEN, SDCSZ, SDRSZ, SDBSZ PERIOD
6.1.1
EMIF Global Control Register C6414 MT48LC4M32B2
Because ECLKOUT1 system driven ECLKIN, must following, shown Figure Table summarizes values.
Reserved 111111111111 EK2HZ CLK6EN EK2EN EK2RATE HOLDA NOHOLD EK1HZ EK1EN CLK4EN
BRMODE
BUSREQ
ARDY
HOLD
Figure EMIF Global Control Register Diagram C6414 MT48LC4M32B2
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Global Control Register C6414
Formula EK1EN EK2EN EK2RATE Description Indicates that ECLKOUT1 enabled clock used clock SBSRAM. Indicates that ECLKOUT2 disabled system. Indicates that ECLKOUT2 would EMIF input clock enabled system
Thus, valid setting EMIF global control register 0x00000010. additional information remainder fields, TMS320C6000 Peripherals Reference Guide.
6.1.2
EMIF Space Control Register C6414 MT48LC4M32B2
MTYPE 1101, shown Figure indicates that 32-bit-wide SDRAM located address space. other fields irrelevant because they refer asynchronous memory. additional settings SDRAM found space secondary control register. valid setting EMIF Space Control 0xFFFFFF33.
WRITE SETUP 1111 WRITE STROBE 111111 READ STROBE 111111 MTYPE 0011 WRITE HOLD WRITE HOLD READ SETUP 1111
READ HOLD
Figure EMIF Space Control Register Diagram
6.1.3
EMIF SDRAM Control Register C6414 MT48LC4M32B2
SDRAM control register (Figure 54), values must actually calculated based clock frequency used (133 this example, tCYC parameters SDRAM used. Table summarizes values.
SDBSZ
SDCSZ
RFEN
INIT
TRCD
SDRSZ
0001
0001
Reserved
SLFRFR
1001 NOTE: SDCSZ indicates that column address bits used. SDRSZ indicates that address bits used. SDBSZ indicates that bank address bits used banks). RFEN indicates that SDRAM refresh enabled. INIT forces initialization SDRAM. TRCD 0001b from previous calculation. 0001b from previous calculation. 1001b from previous calculation. SLFRFR indicates that self-refresh mode enabled
00000000000
Figure EMIF SDRAM Control Register C6414 MT48LC4M32B2
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
Table Timing Parameter Calculation SDRAM Control Register C6414 MT48LC4M32B2
Field Name tRCD Formula (tRC tCYC) (tRP tCYC) tRCD (tRCD tCYC) Value From Data Sheet (min) (min) tRCD (min) Value Calculated Field 8.33 1.66 tRCD 1.66 Value Recommended
Based above calculations, value 0x57119000 should written EMIF SDRAM control register.
6.1.4
EMIF SDRAM Refresh Period C6414 MT48LC4M32B2
Based this result (Figure 55), value 0x446 should written refresh period field EMIF SDRAM timing register (see Table 34).
Reserved 00000000
COUNTER 000000000000
PERIOD 010001000110(0x446)
NOTE: Period 0x446 from previous calculation.
Figure EMIF SDRAM Refresh Period C6414 MT48LC4M32B2 Table Period Calculation SDRAM Refresh Period C6414 MT48LC16M8A2
Field Name PERIOD Formula PERIOD tRefresh/tCYC Value From Micron Data Sheet tRefresh 4096 15.625µS Value Calculated Field Period 2084 cycles cycles
6.1.5
EMIF SDRAM Extension Register C6414 MT48LC4M32B2
SDRAM extension register, values must calculated based clock frequency used (133 this example, tCYC 7ns) parameters SDRAM used. Table summarizes values. Table SDRAM Extension Register Values C6414 MT48LC4M32B2
Field Name TRAS TRRD THZP
Formula (tCL) TRAS (tRAS tCYC) TRRD (tRRD tCYC) (tWR tCYC) THZP (tHZP)
Value From SDRAM Data Sheet cycles tRAS tRRD tHZP cycles
Value Calculated Field TRAS TRRD THZP
Value Recommended TRAS TRRD THZP
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D Value From SDRAM Data Sheet Value Calculated Field Value Recommended RD2RD RD2DEAC RD2WR R2WDQM WR2WR WR2DEAC WR2RD
Field Name RD2RD RD2DEAC RD2WR R2WDQM WR2WR WR2DEAC WR2RD
Formula Recommended value from
tHZP also known TROH
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433D
References
TMS320C6000 Peripherals Reference Guide (SPRU190). TMS320C6x Peripheral Support Library Programmers Reference (SPRU273). TMS320C6201 Digital Signal Processor (SPRS051). TMS320C6202 Fixed-Point Digital Signal Processor (SPRS072). TMS320C6211, TMS320C6211B DSPs (SPRS073). TMS320C6701 Floating-Point (SPRS067) TMS320C6711, TMS320C6711B Floating-Point DSPs (SPRS088). MT48LC4M16A2 Data Sheet, Micron Technology, Inc. MT48LC1M16A1 Data Sheet, Micron Technology, Inc. MT48LC16M8A2 Data Sheet, Micron Technology, Inc.
TMS320C6000 EMIF-to-External SDRAM Interface
SPRA433C
Appendix Code Example C6201B Micron MT48LC4M16A2-10
following code segment sets EMIF described above, using TMS320C6000 Chip Support Library.
#include <csl.h> #include <csl_emif.h> void set_EMIF(); void main() initialize library CSL_init(); set_EMIF(); void set_EMIF() //Set value global control register Uint32 global EMIF_GBLCTL_RMK( EMIF_GBLCTL_NOHOLD_OF(0), EMIF_GBLCTL_SDCEN_ENABLE, EMIF_GBLCTL_SSCEN_ENABLE, EMIF_GBLCTL_CLK1EN_ENABLE, EMIF_GBLCTL_CLK2EN_DISABLE, EMIF_GBLCTL_SSCRT_OF(0), EMIF_GBLCTL_RBTR8_HPRI //Set value control register Field interest MTYPE field (other field default values) Uint32 control3 EMIF_CECTL_RMK( EMIF_CECTL_WRSETUP_DEFAULT, EMIF_CECTL_WRSTRB_DEFAULT, EMIF_CECTL_WRHLD_DEFAULT, EMIF_CECTL_RDSETUP_DEFAULT, EMIF_CECTL_RDSTRB_DEFAULT, EMIF_CECTL_MTYPE_SDRAM32, EMIF_CECTL_RDHLD_DEFAULT //Set value SDRAM control rgister Fields interest are: TRC,TRP,TRCD,INIT,RFEN, SDWID Uint32 sdcontrol EMIF_SDCTL_RMK( EMIF_SDCTL_SDWID_DEFAULT, EMIF_SDCTL_RFEN_ENABLE, EMIF_SDCTL_INIT_YES, EMIF_SDCTL_TRCD_OF(1), EMIF_SDCTL_TRP_OF(1), EMIF_SDCTL_TRC_OF(6)
TMS320C6000 EMIF External SDRAM Interface
SPRA433C
//Set value SDRAM timing register with refresh period Field interest Period Field Uint32 sdtim EMIF_SDTIM_RMK( EMIF_SDTIM_PERIOD_OF(1562) EMIF_configArgs( EMIF_GBLCTL_OF(global), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(control3), EMIF_SDCTL_OF(sdcontrol), EMIF_SDTIM_OF(sdtim)
global control 32-bit async control control control SDRAM control SDRAM timing
TMS320C6000 EMIF External SDRAM Interface
SPRA433C
Appendix
Code Example C6211 Micron MT48LC16M8A2-8
following code segment sets EMIF described above, using TMS320C6000 Chip Support Library.
#include <csl.h> #include <csl_emif.h> void set_EMIF(); void main() initialize library CSL_init(); set_EMIF(); void set_EMIF() //Set value global control register Uint32 global EMIF_GBLCTL_RMK( EMIF_GBLCTL_NOHOLD_OF(0), EMIF_GBLCTL_CLK1EN_DISABLE, EMIF_GBLCTL_CLK2EN_DISABLE //Set value control register Field interest MTYPE field (other field default values) Uint32 control3 EMIF_CECTL_RMK( EMIF_CECTL_WRSETUP_DEFAULT, EMIF_CECTL_WRSTRB_DEFAULT, EMIF_CECTL_WRHLD_DEFAULT, EMIF_CECTL_RDSETUP_DEFAULT, EMIF_CECTL_TA_DEFAULT, EMIF_CECTL_RDSTRB_DEFAULT, EMIF_CECTL_MTYPE_SDRAM32, EMIF_CECTL_RDHLD_DEFAULT //Set value SDRAM control rgister Fields interest are: TRC,TRP,TRCD,INIT,RFEN, SDWID Uint32 sdcontrol EMIF_SDCTL_RMK( EMIF_SDCTL_SDBSZ_4BANKS, EMIF_SDCTL_SDRSZ_12ROW, EMIF_SDCTL_SDCSZ_10COL, EMIF_SDCTL_RFEN_ENABLE, EMIF_SDCTL_INIT_YES, EMIF_SDCTL_TRCD_OF(1), EMIF_SDCTL_TRP_OF(1), EMIF_SDCTL_TRC_OF(6)
TMS320C6000 EMIF External SDRAM Interface
SPRA433C
//Set value SDRAM timing register with refresh period Field interest Period Field Uint32 sdtim EMIF_SDTIM_RMK( EMIF_SDTIM_XRFR_DEFAULT, EMIF_SDTIM_PERIOD_OF(1562) EMIF_configArgs( EMIF_GBLCTL_OF(global), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(0x00000018), EMIF_CECTL_OF(control3), EMIF_SDCTL_OF(sdcontrol), EMIF_SDTIM_OF(sdtim), EMIF_SDEXT_OF(0x00000000)
global control 32-bit async control control control SDRAM control SDRAM timing SDRAM extension
TMS320C6000 EMIF External SDRAM Interface
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