David Bell Scott Chen ABSTRACT This document describes provide Texas I

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TMS320C6000 System Clock Circuit Example
David Bell Scott Chen ABSTRACT This document describes provide Texas Instruments TMS320C6000 with system clock. clocks internal C6000 generated from single source through CLKIN pin. This source clock device external signal that, depending clock mode, either drives on-chip Phase-Locked Loop (PLL) circuit, which multiplies source clock frequency generate internal clock, bypasses become internal clock. source clock derived from either oscillator chip clock synthesizer circuit should generated from 3.3V source. This document further describes provide EMIF Texas Instruments (TI) TMS320C6000 through ECLKIN. Digital Signal Processing Solutions
Contents Design Problem Solution Providing System Clock Through CLKIN 2.1.1 Modes 2.1.2 Component Selection 2.1.3 CLKIN External Clock Source Providing Clock EMIF Through ECLKIN 2.2.1 Clock Sources C6000 EMIF References List Figures Figure Figure Figure Figure Figure Figure Figure Oscillator Circuit CLKIN Clock Synthesizer Circuit CLKIN Clock Signals TMS320C6201/C6701 Clock Signals TMS320C6202/C6202B/C6203/C6204 Clock Signals TMS320C6205 Clock Signals TMS320C621x/C671x Clock Signals TMS320C64x List Tables Table Mode C6000 Devices
Trademarks property their respective owners. TMS320C6000 C6000 trademarks Texas Instruments.
SPRA430A
Table Table Table Table Table
Component Selection Table C62x/C67x Component Selection Table C64x Compatible CLKIN External Clock Sources CLKOUT1 Frequency Ranges C6201/C6701 Multiplier Configurations C6202/C6202B/C6203/C6204
Design Problem
provide TMS320C6000 with system clock?
2.1.1
Solution
Providing System Clock Through CLKIN Modes
internal clock C6000 generated from single source through CLKIN pin. This source clock device external signal that, depending clock mode, either drives on-chip Phase-Locked Loop (PLL) circuit, which multiplies source clock frequency generate internal clock, bypasses become internal clock. source clock derived from either oscillator chip clock synthesizer circuit should generated from 3.3V source. Ensure that clock traces short possible minimize distortion clock signal. Each C6000 device different modes device operation. Table summary existing devices:
TMS320C6000 System Clock Circuit Example
SPRA430A
Table Mode C6000 Devices
CLKMODE (CLKIN Frequency Multiplier) Device C6201 C6202 C6202B C6202B C6203 C6203 C6204 C6205 C6701 C6211 C6211B C6711 C6712 C6414 C6415 C6416 Package
CLKMODE bypassed external components removed. this case, 3.3-V supply PLLV must from same 3.3-V power plane supplying voltage, DVDD. addition, PLLG PLLF terminals should tied together.
2.1.2
Component Selection
Table Table summarize component selection external circuitry TMS320C62x (C62x), TMS320C67x (C67x), TMS320C64x (C64x) devices. Notice that under some operating conditions, maximum lock time vary much 150% from specified typical value. example, typical lock time specified maximum value long
TMS320C62x, TMS320C67x, TMS320C64x, C62x, C67x C64x trademarks Texas Instruments.
TMS320C6000 System Clock Circuit Example
SPRA430A
Table Component Selection Table C62x/C67x
CLKIN RANGE (MHz) 12.5-50 32.5-62.5 32.5-62.5 21.7-41.7 18.6-35.7 16.3-31.3 14.4-27.8 13-25 11.8-22.7 32.5-75 21.7-50 18.6-42.9 16.3-37.5 14.4-33.3 13-30 11.8-27.3 32.5-50 32.5-50 21.7-33.3 18.6-28.6 16.3-25 14.4-22.2 13-20 11.8-18.2 12.5-41.7 16.3-41.6 16.3-37.5 16.3-37.5 CLKOUT RANGE (MHz) 50-200 130-250 CLKOUT2 RANGE (MHz) 25-100 65-125 60.4 60.4 (nF) (pF) TYPICAL LOCK TIME (ms)
DEVICE C6201 C6202
C6202B
C6203
C6204
C6205
C6701 C6211 C6711 C6712
CLKMODE
130-250
65-125
60.4
130-300
65-150
60.4 (1.x) 45.3 (2.x)
(1.x) (2.x)
(1.x) (2.x)
130-200
65-100
60.4
130-200
65-100
60.4
50-167 65-167 65-150 65-150
25-83.5 32.5-83 32.5-75 32.5-75
60.4 60.4 60.4 60.4
Table Component Selection Table C64x
Speed (MHz) CLKIN RANGE (MHz) 30-75 30-66.7 30-33.3 30-75 30-75 30-41.7 30-75 30-75 30-50 CLOCK FREQUENCY RANGE (MHz) 30-75 180-400 360-400 30-75 180-450 360-500 30-75 180-450 360-600 CLKOUT4 RANGE (MHz) 7.5-18.8 45-100 90-100 7.5-18.8 45-112.5 90-125 7.5-18.8 45-112.5 90-150 CLKOUT6 RANGE (MHz) 5-12.5 30-66.7 60-66.7 5-12.5 30-75 60-83.3 5-12.5 30-75 60-100 TYPICAL LOCK TIME (ms)
CLKMode Bypass (x1) Bypass (x1) Bypass (x1)
recommended that resistors used circuit, although resistors expected work well. Also, 10%-tolerance ceramic chip capacitors should used their inductance.
TMS320C6000 System Clock Circuit Example
SPRA430A
best performance, recommended that external components single side board without jumpers, switches, components other than ones shown Figures below. reduce jitter, lead length number vias should kept minimum, while spacing between switching signals external components should maximum. Also, external components should placed close C6000 possible isolated from high-speed digital signal traces. 3.3-V supply filter must from same 3.3-V power plane supplying voltage, DVDD. multiple-C6000 designs, important provide separate filter circuit each DSP. Multiple chips single filter will work properly. will function properly (except mode) without filter. filter used figures below part number ACF451832333, 223, 153, Panasonic part number EXCCET103U.
2.1.3
CLKIN External Clock Source
Figure shows simple oscillator circuit providing CLKIN signal C6000. oscillator used, output connected CLKIN through series resistor.
DVDD
JITO-2A
CLKIN
Figure Oscillator Circuit CLKIN When selecting oscillator, important note that rise/fall timings C6000 data sheet based 80%, while most oscillators base their timings range. Table lists some examples compatible CLKIN external clock sources. Table Compatible CLKIN External Clock Sources
COMPATIBLE PARTS EXTERNAL CLOCK SOURCES (CLKIN) Oscillators
PART NUMBER JITO-2 series, ST4100 series SG-636 MK1711-S, ICS525-02
MANUFACTURER Electronix SaRonix Corporation Epson America Corning Frequency Control Integrated Circuit Systems
circuit shown Figure demonstrates generate CLKIN signal using clock synthesizer circuit rather than oscillator chip. synthesizer circuit used, internal must bypassed mode. MicroClock1 developed clock customized with TI's products. requires single 20MHz crystal generates high quality clock signal with frequency 118MHz 200MHz based value CLK_SEL[2:0] (000b 200MHz).
TMS320C6000 System Clock Circuit Example
SPRA430A
DVDD
CLK_SEL0 CLK_SEL1 CLK_SEL2
VDDP SEL3VCLK INVCLKNC MK171101
CLKIN
20MHz HC49U
Figure Clock Synthesizer Circuit CLKIN
Block Diagrams
following figures show locations within device where each C6000 clock generated. Essentially, input clock either bypasses multiplied factor (CLKIN Frequency Multiplier) within generate output clock (CLKOUT1), which serves internal clock device. This output clock (CLKOUT1) then used generate external clocks such CLKOUT2, CLKOUT4, CLKOUT6, SSCLK, SDCLK. Figure shows that C6201/C6701, CLKOUT1 serves internal clock rest used generate three other clock signals memory interface: CLKOUT2, SDCLK, SSCLK.
PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV Filter CLKMODE0 CLKMODE1 (see Table
3.3V
PLLMULT PLLCLK
Internal C6201/C6701
CLKIN
CLKIN LOOP FILTER
CLOCK
Available Multiply Factors CLKMODE1 CLKMODE0 Multiply Factors x1(BYPASS) Reserved Reserved Clock Frequency f(CPUCLOCK) f(CLKIN) Reserved Reserved f(CLKIN)
Figure Clock Signals TMS320C6201/C6701
more details MicroClock, their website http://www.microclock.com.
TMS320C6000 System Clock Circuit Example
PLLG
PLLF
SPRA430A
C6201/C6701, target range CLKOUT1 frequency configured. values PLLFREQ[3:1] pins determine frequency range when using mode. Even though frequency ranges given Table overlap, lowest frequency range including desired frequency that should used maximize performance. example, CLKOUT1 133MHz, PLLFREQ value 000b should used. Frequency ranges slightly different C6201 C6701 device speed. Table CLKOUT1 Frequency Ranges C6201/C6701
PLLFREQ3 (A9) PLLFREQ2 (D11) PLLFREQ1 (B10) CLKOUT1 Frequency Range (MHz) C6201 50-140 65-200 130-233 CLKOUT1 Frequency Range (MHz) C6701 50-140 65-167 130-167
C6202/C6202B/C6203/C6204/C6205, CLKOUT1 serves internal clock rest used generate CLKOUT2, which used synchronous memory interface. C621x/C671x EMIF requires separate external clock input (ECLKIN) generate memory clock (ECLKOUT). This allows memory interface operate frequency independent frequency. drive EMIF using CLKOUT2, this signal must externally routed ECLKIN. Figure Figure Figure show differences among C6202/02B/6203/6204, C6205, C621x/C671x. circuitry diagrams same C6202/C6202B/C6203/C6204, there some differences operation modes, shown Table Notice that:
CLKMODE2 CLKMODE1 internally unconnected C6202 package C6204 package. CLKMODE2 CLKMODE1 available C6204 package. CLKMODE2 available C6202B/C6203 package, which means only (Bypass), applicable. Table Multiplier Configurations C6202/C6202B/C6203/C6204
Multiply Factors C6202B C6203 Bypass (x1) Bypass (x1)
CLKMODE2
CLKMODE1
CLKMODE0
C6202 Bypass (x1) Bypass (x1) Bypass (x1) Bypass (x1)
C6204 Bypass (x1) Bypass (x1) Bypass (x1) Bypass (x1)
TMS320C6000 System Clock Circuit Example
SPRA430A
3.3V PLLV Filter CLKMODE0 CLKMODE1 CLKMODE2 CLKIN
PLLMULT PLLCLK CLKIN LOOP FILTER
Internal C6202/02B/6203/6204
CLOCK
Figure Clock Signals TMS320C6202/C6202B/C6203/C6204 C6205, CLKMODE0 equal denotes on-chip bypassed while CLKMODE0 equal denotes on-chip used, except when configuration bits (ED[31], ED[27], ED[13]) reset. These on-chip configuration bits (ED[31], ED[27], ED[13]) latched during device reset, along with other boot configuration bits ED[31:0].
3.3V PLLV Internal C6205 Filter ED[31,27,23] CLKMODE0 CLKIN PLLMULT CLKIN LOOP FILTER
PLLG
PLLF
PLLCLK
CLOCK
CLKMODE0
ED[31]
ED[27]
ED[23]
Multiply Factors (Bypass) (Bypass)
Figure Clock Signals TMS320C6205
TMS320C6000 System Clock Circuit Example
PLLG
PLLF
SPRA430A
3.3V PLLV Filter
CLKMODE0 CLKIN CLKIN LOOP FILTER PLLMULT PLLCLK
Internal C6211/C6211B/C6711
CLOCK
Available Multiply Factors CLKMODE0 Multiply Factors x1(BYPASS) Clock Frequency f(CPUCLOCK) f(CLKIN) f(CLKIN)
Figure Clock Signals TMS320C621x/C671x C64x device, external clocks, CLKOUT4 CLKOUT6, generated from internal clock. These pins muxed with GPIO port pins default function output clocks. these pins externally routed back ECLKIN synchronous memory interface. aware ECLKIN speed limit discussed next section. recommended change multiply clock modes with external pullup resistors. CLKMODE1 CLKMODE0 feature internal pulldown resistors. change default multiply clock mode Bypass) either x12, external pullup resistors CLKMODE pins pull either signal logic `1'.
PLLG
PLLF
TMS320C6000 System Clock Circuit Example
SPRA430A
3.3V PLLV Filter CLKMODE0 CLKMODE1 CLKIN CLKIN
PLLMULT PLLCLK
Internal C64x
CLOCK
CLKMODE1
CLKMODE0
CLKMODE (PLL Multiply Factors)
Bypass (x1) Reserved
Figure Clock Signals TMS320C64x
2.2.1
Providing Clock EMIF Through ECLKIN Clock Sources C6000 EMIF
external memory interface (EMIF) C6000 acquires clock signals from various sources. C6201/C6701 provides SDCLK SDRAM SSCLK SBSRAM. remaining C620x devices, SDRAM SBSRAM (only these memory types used system) CLKOUT2 (EMIF clock cycle), which equal half clock rate (CPU/2). C621x/C671x EMIF requires that external clock source (ECLKIN) provided system. memories interfacing with C621x/C671x should operate ECLKOUT (EMIF clock cycle) signal, which produced internally (based ECLKIN). desired, CLKOUT2 output routed back ECLKIN input. There EMIFs (EMIFA EMIFB) C64x. These EMIFs enhanced version EMIF C621x/C671x devices. addition ECLKIN, both EMIFs configured device reset pullup/pulldown resistors) internal clock rate divide divide input clock. ECLKIN default EMIF input clock. memories interfacing with C64x should operate ECLKOUT1 ECLKOUT2 (EMIF clock cycle). ECLKOUT1 frequency equals EMIF input clock frequency. ECLKOUT2 frequency programmable EMIF input clock frequency divided 1,2, ECLKIN called AECLKIN EMIFA BECLKIN EMIFB, while ECLKOUTx called AECLKOUTx EMIFA BECLKOUTx EMIFB. According device datasheets, C621x/C671x devices, ECLKIN speed limited 67MHz (15ns cycle time) 100MHz devices 100MHz (10ns cycle time) 150MHz/160MHz devices, while C64x devices, ECLKIN speed limited 133MHz (7.5ns cycle time) 400MHz/500MHz/600MHz devices. With this limitation, connecting CLKOUT1 ECLKIN applicable only when running lower than ECLKIN speed limit.
TMS320C6000 System Clock Circuit Example
SPRA430A
References
TMS320C6000 Peripherals Reference Guide (SPRU190). JITO-2 Specifications, Electronics. MK1711-01 Selectable Clock Source Specifications, MicroClock Division ICS. TMS320C6201 Digital Signal Processor (SPRS051). TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors (SPRS104). TMS320C6203 Fixed-Point Digital Signal Processor (SPRS086). TMS320C6204 Fixed-Point Digital Signal Processor (SPRS152). TMS320C6205 Fixed-Point Digital Signal Processor (SPRS106). TMS320C6701 Floating-Point Digital Signal Processor (SPRS067). TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors (SPRS073). TMS320C6712 Floating-Point Digital Signal Processor (SPRS148). TMS320C6414 Fixed-Point Digital Signal Processor (SPRS134). TMS320C6415 Fixed-Point Digital Signal Processor (SPRS146). TMS320C6416 Fixed-Point Digital Signal Processor (SPRS164).
TMS320C6000 System Clock Circuit Example
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David Bell Scott Chen ABSTRACT This document describes provide Texas I

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