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TMS320C6000 Manufacturing Considerations
David Bell C6000 Applications Team
Abstract
When designing with high-density package, important aware different techniques that quality manufacture. important match copper land diameter printed circuit board (PCB) ensure reliability. processes available copper lands: solder mask defined (SMD) non-solder mask defined (NSMD). Each advantages disadvantages. Signal routing serious concern when designing with finepitch packages. standard method connect balls inner signal layers place plated through hole (PTH) vias interstitial between copper lands. Another method, which allows less copper present both bottom layers PCB, blind buried vias, with large vias present only inner layers PCB. addition designing land area, necessary properly attach board. BGAs inherently offer self-correction slightly misplaced during reflow. This document contains recommended reflow profile.
Digital Signal Processing Solutions
February 2001
Contents
TMS320C6000 Manufacturing Considerations
Solder Land Areas Conductor Width/Spacing. High Density Routing Techniques. Density Conventional Design Advanced Design Methods. Component placement Reflow Summary. References
Figures
Figure Effect Via/Land Ratios Figure Optimum Land Configuration Figure Conventional Structure Figure Buried Structure Figure Example Reflow Profile.
Tables
Table Reflow Oven Zones
TMS320C6000 Manufacturing Considerations
TMS320C6000 Manufacturing Considerations
Solder Land Areas
Design both itself printed circuit board (PCB) important achieving manufacturability reliability. particular, diameter package vias board lands critical. While actual sizes these dimensions important, their ratio more critical. Figure illustrates package-to-PCB configuration ratio critical.
Figure Effect Via/Land Ratios
Package Package
Package
Package
Package
Package
view, package larger, solder ball prone crack prematurely interface. middle view, larger, leading cracks package surface. bottom view, where ratio almost 1:1, stresses more equally distributed across height solder connection. Solder lands generally simple round pads. There methods defining solder lands: solder mask defined (SMD), non-solder mask defined (NSMD). With method, copper made larger than desired land area, opening size defined opening solder mask material. advantages normally associated with this technique include more closely controlled size better copper adhesion laminate. Better size control result photoimaging stencils masks. chief disadvantage this method that larger copper spot make routing more difficult.
TMS320C6000 Manufacturing Considerations
With NSMD method, land area etched inside solder mask area. While size control dependent copper etching accurate method, overall pattern registration dependent copper artwork, which quite accurate. tradeoff between accurate placement accurate size. NSMD lands recommended small-pitch packages because more space left between copper lands signal traces. Figure example optimum land diameters configurations common pitch.
Figure Optimum Land Configuration
Non-Solder Mask Defined Solder Mask Ball Pitch Non-Solder Mask Defined Diameter Copper 0.35mm 0.40mm 0.65mm Mask 0.50mm 0.55mm 0.85mm
0.80mm 1.00mm 1.27mm
Solder Mask Defined Solder Mask
Solder Mask Defined Non-Solder Mask Defined Ball Pitch 0.80mm 1.00mm 1.27mm Diameter Copper 0.48mm 0.55mm 0.90mm Mask 0.38mm 0.45mm 0.70mm
Conductor Width/Spacing
Many today's circuit board layouts based most 100-micron conductor line width 200-micron spacing. route between 0.8-mm pitch balls, given clearance roughly microns between ball lands, only signal routed between ball pads. 380-micron ball spacing worst case calculated assuming diameter solder ball land microns. Conventionally, pads connected wide copper traces other devices plated through holes (PTH). rule, mounting pads must isolated from PTH. Placing interstitial between, connected land with trace) land pads often achieves this.
TMS320C6000 Manufacturing Considerations
High Density Routing Techniques
challenge when designing with packages that available space contracts, space available signal fanout also decreases. using high-density routing techniques, designer minimize many these design manufacturing challenges. This section focuses designators (384-pin) package, with 0.8mm pitch. package solid six-row array configuration, with signals located outer three rows.
Density
density, mentioned earlier, limiting factor when designing high-density boards. density defined number vias particular board area. Using smaller vias increases routability board requiring less board space increasing density. invention microvia solved many problems associated with density. Microvias often created using laser penetrate first layers dielectric. laser penetrate 4-mil thick dielectric layer. layout designer route first internal board layer. layers (each thick) laser-drilled, creating 200-micron microvia diameter. this case, routing first internal layers possible. number board layers increases board chip density functional count increase. example, Texas Instruments (TITM) TMS320C6202 digital signal processor (DSP) available 384-pin package uses balls power ground. Routing signals accomplished little layers. power ground planes increase board four layers. increasing board layer stack-up eight layers, high-density applications possible with only mils between chips.
Conventional Design
relatively large density package periphery, mentioned earlier, caused limited options when routing signal from ball. reduce density problem periphery package, designers build vertically from through internal layers board, shown Figure working vertically mechanical drilling 250-micron vias between pads board internal layers, designers create "pick-and-choose" method. They pick layer choose route. bone method used connect through-hole pad. This method requires very small mechanical drill create vias package.
TMS320C6000 Manufacturing Considerations
Figure Conventional Structure
Cross Section View View
Layer Layer Layer Layer Layer Layer
Advanced Design Methods
Another option combination blind buried vias. Blind vias connect either bottom side board inner layers shown Figure Buried vias usually connect only inner layers. This method uses 4-mil laser-drilled microvias center pads burying bone layer Since buried does extend through underside board, designer another laserdrilled blind microvias, needed, connect bypass capacitors other discrete components bottom-side.
Figure Buried Structure
Cross Section View View
Layer Layer Layer Layer Layer Layer
TMS320C6000 Manufacturing Considerations
Component placement
Component placement next operation followed solder paste printing. components exhibit self-centering phenomena. self-centering will correct some amount misplacement process. surface tension molten solder wetting nature solder contribute self-centering component. general rule, placement offset much normally allowed case placement. Component placement normally performed using equipment capable placing with reference balls. ball vision available BGAs placed aligning component edges. this type placement, offset could much higher component component variability. preferred method balls placement. While placing component, care should exercised splatter solder paste. placement force 200-300 grams normally adequate making contact solder paste.
Reflow
boards with components placed then sent reflow oven. BGAs require special process reflowing. important check reflow profiles components board. important that devices soldered experience adequate reflow. Depending type oven used there temperature difference from center board edges. Multiple thermocouples should mounted various parts board broader spectrum temperature profiles. needed, temperature should re-adjusted achieve good soldering parts. While measuring temperature profile beneficial have thermocouples mounted joint order measure actual temperature solder experiencing. Table illustrates typical profile that used reflow.
Table Reflow Oven Zones
Reflow Oven Zones Characteristics Initial heating component/board Solder paste drying flux activation zone Solder ring zone, Above Degree Assembly cooling zone Process window seconds /second 120-140 Degree Peak Temp 120-180 seconds soak 120-170 Degree Peak temp 60-120 seconds above 220+/- peak component temperature Degree/Second room temp
heat
Soak
Reflow Cool down
TMS320C6000 Manufacturing Considerations
preheat zone slowly heats component rest assembly around 120-140°C. heating rate maintained around 1.5°C this stage. soak zone where excessive volatiles driven flux activated. This zone highly dependent type solder paste used. assembly should maintained this zone long enough drive volatiles, ensuring minimum voiding during assembly. flux activation occurs around 150°C 170°C towards soak zone. This zone normally 120- seconds long. third zone consists reflow zone. this zone temperature ramped fast rate above liquidous temperature solder. maximum component temperature this zone normally maintained around 220°C. Time above 183°C range from 60°C- 120°C depending board. Once soldering complete board passed cooling zone. assembly rapidly cooled (2-3°/second) this zone. Figure illustrates typical reflow profile that used assembly.
Figure Example Reflow Profile
Pre-heat zone Soak Zone Refow Zone Cooling zone
Summary
understanding manufacturing processes available, well impact different techniques have design, reliable systems designed. reliability, should attention physical properties copper lands PCB. matching land diameter those package, solder connection will robust. must also keep signal routing mind when designing with fine-pitch devices. There several methods available connect balls inner layers PCB. Microvia buried technology allow more space left each layer signal routing. addition properly designing PCB, necessary understand reflow process accurately attach device PCB. sample reflow process provided, which should followed this. understanding these design considerations, designed quickly attached reliably.
TMS320C6000 Manufacturing Considerations
References
Texas Instruments MicroStar BGAPackaging Reference Guide, Texas Instruments, (SSYZ015).
TMS320C6000 Manufacturing Considerations
Contact Numbers
INTERNET Semiconductor Home Page www.ti.com/sc Distributors www.ti.com/sc/docs/distmenu.htm PRODUCT INFORMATION CENTERS Americas Phone +1(972) 644-5580 +1(972) 480-7800 Email sc-infomaster@ti.com Europe, Middle East, Africa Phone Deutsch +49-(0) 8161 3311 English +44-(0) 1604 3399 +34-(0) Francais +33-(0) 1-30 Italiano +33-(0) 1-30 +44-(0) 1604 Email epic@ti.com Japan Phone International +81-3-3344-5311 Domestic 0120-81-0026 International +81-3-3344-5317 Domestic 0120-81-0036 Email pic-japan@ti.com
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trademark Texas Instruments Incorporated. Other brands names property their respective owners.
TMS320C6000 Manufacturing Considerations
Application Report SPRA429A
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty, endorsement thereof. Copyright 1999 Texas Instruments Incorporated
TMS320C6000 Manufacturing Considerations
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such products services might used. TI's publication information regarding third party's products services does constitute TI's approval, license, warranty endorsement thereof. Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations notices. Representation reproduction this information with alteration voids warranties provided associated product service, unfair deceptive business practice, responsible liable such use. Resale TI's products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service, unfair deceptive business practice, responsible liable such use. Also see: Standard Terms Conditions Sale Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated

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