MPC601UM/AD PowerPC RISC Microprocessor User's Manual C
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MPR601UM-01
MPC601UM/AD
PowerPC
RISC Microprocessor User's Manual
CONTENTS
Paragraph Number Title Page Number
About This Book
Audience xlii Organization. xlii Additional Reading xliv Conventions xliv Acronyms Abbreviations xliv Terminology Conventions xlvii Chapter
Overview
1.1.1 1.1.2 1.1.3 1.1.3.1 1.1.4 1.1.4.1 1.1.4.2 1.1.4.3 1.1.5 1.1.6 1.1.7 1.1.8 1.3.1 1.3.2 1.3.2.1 1.3.2.1.1 1.3.2.1.2 1.3.2.1.3 1.3.2.1.4 1.3.2.1.5 PowerPC Microprocessor Overview. Features. Block Diagram. Instruction Unit Instruction Queue. Independent Execution Units. Branch Processing Unit (BPU) Integer Unit (IU) Floating-Point Unit (FPU) Memory Management Unit (MMU) Cache Unit Memory Unit. System Interface 1-10 Levels PowerPC Architecture. 1-10 PowerPC Implementation. 1-11 Features. 1-12 Registers Programming Model 1-13 PowerPC Registers Programming Model 1-13 General-Purpose Registers (GPRs). 1-13 Floating-Point Registers (FPRs) 1-14 Condition Register (CR) 1-14 Floating-Point Status Control Register (FPSCR) 1-14 Machine State Register (MSR). 1-14
Contents
CONTENTS
Paragraph Number 1.3.2.1.6 1.3.2.1.7 1.3.2.1.8 1.3.2.1.9 1.3.2.2 1.3.3 1.3.3.1 1.3.3.1.1 1.3.3.1.2 1.3.3.2 1.3.4 1.3.4.1 1.3.4.2 1.3.5 1.3.5.1 1.3.5.2 1.3.6 1.3.6.1 1.3.6.2 1.3.7 1.3.8 1.3.8.1 1.3.8.2 1.3.8.3 1.3.8.4 1.3.8.5 Title Page Number
Segment Registers (SRs) .1-14 Special-Purpose Registers (SPRs).1-14 User-Level SPRs .1-14 Supervisor-Level SPRs .1-15 Additional Registers .1-16 Instruction Addressing Modes.1-18 PowerPC Instruction Addressing Modes.1-18 PowerPC Instruction .1-18 Calculating Effective Addresses .1-19 Instruction Set.1-20 Cache Implementation.1-20 PowerPC Cache Characteristics .1-21 Cache Implementation.1-21 Exception Model .1-22 PowerPC Exception Model .1-23 Exception Model .1-24 Memory Management .1-27 PowerPC Memory Management .1-27 Memory Management .1-28 Instruction Timing .1-29 System Interface .1-31 Memory Accesses.1-32 Controller Interface Operations .1-33 Signals .1-33 Signal Configuration .1-34 Real-Time Clock .1-35 Chapter
Registers Data Types
2.1.1 2.2.1 2.2.2 2.2.3 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.5 2.2.5.1 Normal Instruction Execution State .2-1 Changing Privilege Levels .2-6 User-Level Registers .2-6 General Purpose Registers (GPRs).2-6 Floating-Point Registers (FPRs).2-7 Floating-Point Status Control Register (FPSCR) .2-8 Condition Register (CR).2-11 Condition Register Field Definition.2-12 Condition Register Field Definition.2-12 Condition Register Field-Compare Instruction .2-12 User-Level SPRs .2-13 Register (MQ) .2-13
PowerPC RISC Microprocessor User's Manual
CONTENTS
2.2.5.2 2.2.5.3 2.2.5.3.1 2.2.5.3.2 2.2.5.3.3 2.2.5.3.4 2.2.5.4 2.2.5.5 2.3.1 2.3.2 2.3.3 2.3.3.1 2.3.3.1.1 2.3.3.1.2 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.5.1 2.3.3.5.2 2.3.3.6 2.3.3.7 2.3.3.8 2.3.3.9 2.3.3.10 2.3.3.11 2.3.3.12 2.3.3.13 2.3.3.13.1 2.3.3.13.2 2.3.3.13.3 2.3.3.13.4 2.3.3.13.5 2.4.1 2.4.1.1 2.4.2 2.4.2.1 2.4.2.2 2.4.2.3 2.4.3 2.4.3.1 Integer Exception Register (XER) .2-15 Real-Time Clock (RTC) Registers (User-Level) .2-16 Real-Time Clock Lower (RTCL) Register .2-17 Real-Time Clock Upper (RTCU) Register .2-18 Reading RTC.2-18 Synchronization Multiprocessor System.2-19 Link Register (LR) .2-19 Count Register (CTR) .2-20 Supervisor-Level Registers .2-20 Machine State Register (MSR) .2-20 Segment Registers.2-22 Supervisor-Level SPRs .2-24 Synchronization Supervisor-Level SPRs Segment Registers.2-25 Context Synchronization.2-25 Other Synchronization Requirements Register.2-29 DAE/Source Instruction Service Register (DSISR).2-29 Data Address Register (DAR).2-30 Real-Time Clock (RTC) Registers (Supervisor-Level) .2-30 Decrementer (DEC) Register .2-30 Decrementer Operation .2-31 Writing Reading .2-31 Table Search Description Register (SDR1) .2-32 Machine Status Save/Restore Register (SRR0) .2-32 Machine Status Save/Restore Register (SRR1) .2-33 General SPRs (SPRG0-SPRG3).2-33 External Access Register (EAR).2-34 Processor Version Register (PVR).2-35 Registers.2-36 Implementation-Specific Registers .2-38 Checkstop Sources Enables Register-HID0 .2-38 Debug Modes Register-HID1.2-41 Instruction Address Breakpoint Register (IABR)-HID2.2-42 Data Address Breakpoint Register (DABR)-HID5 .2-42 Processor Identification Register (PIR)-HID15 .2-44 Operand Conventions.2-44 Data Organization Memory Data Transfers .2-44 Alignment Misaligned Accesses .2-45 Effect Operand Placement Performance.2-45 Instruction Restart .2-46 Atomicity .2-47 Access Order .2-47 Byte Ordering .2-47 Little-Endian Address Manipulation.2-48
Contents
CONTENTS
Paragraph Number 2.4.3.2 2.4.3.3 2.4.3.4 2.4.3.5 2.4.4 2.4.4.1 2.4.4.2 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.5.3.1 2.4.5.3.2 2.4.6 2.4.7 2.5.1 2.5.1.1 2.5.2 2.5.2.1 2.5.2.2 2.5.2.3 2.5.2.4 2.5.2.5 2.5.2.6 2.5.2.7 2.5.3 2.5.4 2.5.5 2.5.6 2.7.1 2.7.2 Title Page Number
Little-Endian Alignment Exceptions.2-49 Little-Endian Instruction Fetching .2-49 Big-Endian Byte Ordering.2-50 Little-Endian Byte Ordering.2-50 Structure Mapping Examples .2-50 Big-Endian Mapping .2-50 Little-Endian Mapping .2-51 PowerPC Byte Ordering .2-51 Aligned Scalars.2-52 Misaligned Scalars .2-53 Non-Scalars .2-54 String Operations.2-54 Load Store Multiple Instructions.2-55 PowerPC Instruction Memory Addressing Little-Endian Mode.2-55 PowerPC Input/Output Little-Endian Mode.2-57 Floating-Point Execution Models.2-57 Execution Model IEEE Operations.2-58 Execution Model Multiply-Add Type Instructions .2-60 Floating-Point Data Format.2-61 Value Representation .2-63 Binary Floating-Point Numbers .2-64 Normalized Numbers (±NORM).2-64 Zero Values (±0) .2-65 Denormalized Numbers (±DENORM).2-65 Infinities (±).2-66 Numbers (NaNs).2-66 Sign Result .2-68 Normalization Denormalization .2-68 Data Handling Precision .2-69 Rounding .2-70 PowerPC Registers Unimplemented .2-73 Reset .2-74 Hard Reset .2-74 Soft Reset.2-75 Chapter
Addressing Modes Instruction Summary
3.1.1 3.1.2 Memory Addressing .3-2 Effective Address Calculation.3-2 Context Synchronization .3-3 Exception Summary .3-3
PowerPC RISC Microprocessor User's Manual
CONTENTS
3.3.1 3.3.2 3.3.3 3.3.4 3.3.4.1 3.3.4.2 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.8.1 3.5.8.2 3.5.9 3.5.9.1 3.5.10 3.5.10.1 3.5.11 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.1.5 3.6.1.6 3.6.2 3.6.3 3.6.4 Integer Instructions.3-4 Integer Arithmetic Instructions .3-4 Integer Compare Instructions.3-15 Integer Logical Instructions .3-16 Integer Rotate Shift Instructions.3-18 Integer Rotate Instructions .3-21 Integer Shift Instructions.3-24 Floating-Point Instructions.3-31 Floating-Point Arithmetic Instructions .3-31 Floating-Point Multiply-Add Instructions.3-34 Floating-Point Rounding Conversion Instructions.3-38 Floating-Point Compare Instructions .3-39 Floating-Point Status Control Register Instructions.3-40 Load Store Instructions.3-42 Integer Load Store Address Generation .3-42 Register Indirect with Immediate Index Addressing .3-42 Register Indirect with Index Addressing .3-43 Register Indirect Addressing.3-44 Integer Load Instructions .3-44 Integer Store Instructions .3-47 Integer Load Store with Byte Reversal Instructions .3-49 Integer Load Store Multiple Instructions .3-49 Integer Move String Instructions .3-50 Memory Synchronization Instructions.3-53 Floating-Point Load Store Address Generation .3-56 Register Indirect with Immediate Index Addressing .3-57 Register Indirect with Index Addressing .3-57 Floating-Point Load Instructions.3-58 Double-Precision Conversion Floating-Point Load Instructions .3-60 Floating-Point Store Instructions .3-61 Double-Precision Conversion Floating-Point Store Instructions .3-62 Floating-Point Move Instructions .3-62 Branch Flow Control Instructions .3-63 Branch instruction Address Calculation.3-63 Branch Relative Address Mode .3-64 Branch Conditional Relative Address Mode .3-64 Branch Absolute Address Mode .3-65 Branch Conditional Absolute Address Mode .3-66 Branch Conditional Link Register Address Mode.3-66 Branch Conditional Count Register .3-67 Conditional Branch Control .3-68 Basic Branch Mnemonics .3-70 Branch Mnemonics Incorporating Conditions .3-73
Contents
CONTENTS
Paragraph Number 3.6.5 3.6.6 3.6.7 3.6.8 3.6.9 3.7.1 3.7.2 3.8.1 3.8.2 3.8.3 3.8.4 3.10 3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 Title Page Number
Branch Instructions.3-75 Condition Register Logical Instructions.3-76 System Linkage Instructions .3-78 Simplified Mnemonics Branch Processor Instructions.3-78 Trap Instructions Mnemonics .3-79 Processor Control Instructions.3-81 Move to/from Machine State Register Condition Register Instructions .3-81 Move to/from Special-Purpose Register Instructions.3-82 Memory Control Instructions .3-86 Supervisor-Level Cache Management Instruction .3-86 User-Level Cache Instructions .3-87 Segment Register Manipulation Instructions .3-90 Translation Lookaside Buffer Management Instruction.3-91 External Control Instructions.3-92 Miscellaneous Simplified Mnemonics .3-93 No-Op .3-94 Load Immediate.3-94 Load Address.3-94 Move Register .3-94 Complement Register .3-95 Chapter
Cache Memory Unit Operation
4.4.1 4.4.2 4.4.3 4.4.4 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.5.1 4.7.5.2 Cache Organization .4-2 Cache Arbitration .4-3 Cache Access Priorities .4-4 Basic Cache Operations.4-4 Cache Reloads .4-4 Cache Cast-Out Operation.4-4 Cache Sector Push Operation .4-5 Optional Cache Sector Line-Fill Operation.4-5 Cache Data Transactions .4-5 Access Controller Interface Segments .4-6 Cache Coherency.4-6 Memory Management Access Mode Bits-W, M.4-7 MESI Protocol .4-8 MESI State Diagram.4-9 MESI Hardware Considerations.4-10 Coherency Precautions .4-11 Coherency Single-Processor Systems .4-12 Coherency Multiprocessor Systems .4-12
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PowerPC RISC Microprocessor User's Manual
CONTENTS
4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 4.7.11 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.8.8 4.8.9 4.10 4.10.1 4.10.2 4.10.3 4.11 Memory Loads Stores .4-13 Atomic Memory References .4-14 Snoop Response Operations .4-14 Cache Reaction Specific Operations.4-15 Internal ARTRY Scenarios .4-17 Enveloped High-Priority Cache Sector Push Operation .4-17 Cache Control Instructions.4-17 Cache Line Compute Size Instruction (clcs).4-18 Data Cache Block Touch Instruction (dcbt).4-18 Data Cache Block Touch Store Instruction (dcbtst) .4-19 Data Cache Block Zero Instruction (dcbz).4-19 Data Cache Block Store Instruction (dcbst) .4-19 Data Cache Block Flush Instruction (dcbf) .4-20 Enforce In-Order Execution Instruction (eieio) .4-20 Instruction Cache Block Invalidate Instruction (icbi).4-21 Instruction Synchronize Instruction (isync).4-21 Operations Caused Cache Control Instructions .4-21 Memory Unit .4-22 Memory Unit Queuing Structure .4-24 Memory Unit Queuing Priorities .4-24 Interface .4-25 MESI State Transactions.4-25 Chapter
Exceptions
5.1.1 5.1.1.1 5.1.1.2 5.1.1.3 5.1.2 5.1.3 5.1.3.1 5.1.3.2 5.2.1 5.2.2 5.2.3 5.4.1 Exception Classes.5-2 Precise Exceptions .5-5 Synchronous/Precise Exceptions .5-6 Asynchronous/Precise Exceptions .5-6 Asynchronous, Imprecise Exceptions .5-7 Exception Priorities.5-7 Recognition Exceptions .5-8 Recognition Asynchronous, Imprecise Exceptions .5-9 Recognition Precise Exceptions .5-9 Exception Processing .5-10 Enabling Disabling Exceptions .5-13 Steps Exception Processing.5-14 Returning from Supervisor Mode .5-14 Process Switching .5-15 Exception Definitions.5-15 Reset Exceptions (x'00100') .5-16
Contents
CONTENTS
Paragraph Number 5.4.1.1 5.4.1.2 5.4.2 5.4.2.1 5.4.2.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.6.1 5.4.6.1.1 5.4.6.1.2 5.4.6.1.3 5.4.6.1.4 5.4.6.2 5.4.6.3 5.4.6.4 5.4.7 5.4.7.1 5.4.7.2 5.4.7.2.1 5.4.7.3 5.4.7.3.1 5.4.7.4 5.4.7.4.1 5.4.7.5 5.4.7.5.1 5.4.7.6 5.4.7.6.1 5.4.8 5.4.9 5.4.10 5.4.11 5.4.12 5.4.12.1 5.4.12.2 Title Page Number
Soft Reset .5-16 Hard Reset .5-17 Machine Check Exception (x'00200').5-19 Machine Check Exception Enabled (MSR[ME] .5-20 Checkstop State (MSR[ME] .5-20 Data Access Exception (x'00300').5-21 Instruction Access Exception (x'00400') .5-23 External Interrupt (x'00500') .5-24 Alignment Exception (x'00600').5-25 Integer Alignment Exceptions.5-26 Direct-Translation Access .5-27 Controller Interface Access.5-27 Memory-Forced Controller Interface Access .5-27 Page Address Translation Access.5-28 Floating-Point Alignment Exceptions .5-29 Little-Endian Mode Alignment Exceptions .5-29 Interpretation DSISR Alignment Exception .5-29 Program Exception (x'00700') .5-32 Floating-Point Enabled Program Exceptions .5-33 Invalid Operation Exception Conditions .5-39 Action Invalid Operation Exception Conditions .5-40 Zero Divide Exception Condition .5-41 Action Zero Divide Exception Condition.5-41 Overflow Exception Condition .5-42 Action Overflow Exception Condition.5-42 Underflow Exception Condition .5-43 Action Underflow Exception Condition.5-43 Inexact Exception Condition .5-44 Action Inexact Exception Condition .5-44 Floating-Point Unavailable Exception (x'00800') .5-44 Decrementer Exception (x'00900') .5-45 Controller Interface Error Exception (x'00A00') .5-46 System Call Exception (x'00C00').5-47 Mode/Trace Exception (x'02000').5-48 Mode Exception.5-48 Trace Exception.5-50 Chapter
Memory Management Unit
6.1.1 Overview .6-2 Memory Addressing .6-3
PowerPC RISC Microprocessor User's Manual
CONTENTS
6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.3.1 6.3.2 6.3.3 6.3.4 6.5.1 6.5.1.1 6.5.1.2 6.5.2 6.5.2.1 6.5.2.2 6.5.2.3 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.8.1 6.8.2 6.8.2.1 6.8.2.2 6.8.3 6.8.3.1 6.8.3.2 6.8.4 Organization.6-3 Address Translation Mechanisms .6-5 Memory Protection Facilities.6-7 Page History Information.6-8 General Flow Address Translation .6-8 Memory/MMU Coherency Model .6-10 Effects Instruction Fetch MMU.6-11 Breakpoint Facility.6-12 Exceptions Summary .6-12 Instructions Register Summary .6-14 Entry Invalidation .6-14 ITLB Description .6-15 Memory/Cache Access Modes.6-16 Write-Through .6-16 Caching Inhibited .6-17 Memory Coherence (M).6-17 Combinations .6-18 General Memory Protection Mechanism .6-19 Selection Address Translation Type .6-21 Address Translation Selection Instruction Accesses .6-21 Instruction Address Translation Disabled: MSR[IT] 0.6-22 Instruction Address Translation Enabled: MSR[IT] 1.6-22 Address Translation Selection Data Accesses.6-23 Controller Interface Address Translation: Segment Register 6-23 Data Translation Disabled: MSR[DT] 0.6-23 Data Translation Enabled: MSR[DT] .6-23 Direct Address Translation.6-24 Block Address Translation .6-24 Array Organization.6-25 Recognition Addresses Array .6-26 Register Implementation Array .6-27 Block Memory Protection .6-29 Block Physical Address Generation.6-29 Block Address Translation Summary .6-30 Memory Segment Model.6-33 Page Address Translation Resources .6-33 Recognition Addresses Segments.6-34 Selection Memory Segments .6-35 Selection Controller Interface Segments .6-35 Page Address Translation.6-36 Segment Register Definition .6-37 Page Table Entry (PTE) Format.6-38 Page History Recording .6-40
Contents
CONTENTS
Paragraph Number 6.8.4.1 6.8.4.2 6.8.5 6.8.6 6.9.1 6.9.1.1 6.9.1.2 6.9.1.3 6.9.1.4 6.9.1.5 6.9.1.5.1 6.9.1.5.2 6.9.2 6.9.3 6.9.3.1 6.9.3.2 6.9.3.2.1 6.9.3.2.2 6.9.3.2.3 6.9.3.3 6.9.4 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.10.6 6.10.7 Title Page Number
Reference .6-41 Change Bit.6-41 Page Memory Protection .6-41 Page Address Translation Summary .6-42 Hashed Page Tables.6-42 Page Table Definition.6-44 Table Search Description Register (SDR1).6-45 Page Table Size .6-46 Hashing Functions.6-47 Page Table Addresses.6-48 Page Table Structure .6-50 Page Table Structure Example .6-51 PTEG Address Mapping Example .6-52 Page Table Search Operation .6-55 Page Table Updates .6-58 Adding Page Table Entry .6-59 Modifying Page Table Entry .6-60 General Case .6-60 Clearing Reference Bit.6-60 Modifying Virtual Address .6-61 Deleting Page Table Entry.6-61 Segment Register Updates.6-61 Controller Interface Address Translation.6-62 Segment Register Format Controller Interface.6-62 Controller Interface Accesses .6-63 Controller Interface Segment Protection.6-63 Memory-Forced Controller Interface Accesses .6-63 Instructions Supported Controller Interface Segments .6-64 Instructions with Effect Controller Interface Segments.6-64 Controller Interface Summary Flow .6-65 Chapter
Instruction Timing
7.1.1 7.1.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 Terminology Conventions .7-1 Definition Terms .7-1 Timing Tables.7-3 Pipeline Description .7-4 Processor Core.7-4 Dispatch Stage Logic.7-9 Integer Unit (IU).7-10 Floating-Point Unit (FPU).7-11
PowerPC RISC Microprocessor User's Manual
CONTENTS
7.2.1.4 7.2.1.5 7.2.2 7.2.2.1 7.2.2.2 7.2.2.2.1 7.2.2.2.2 7.2.2.2.3 7.2.2.2.4 7.2.2.3 7.2.2.3.1 7.2.2.3.2 7.2.2.3.3 7.2.2.3.4 7.2.2.3.5 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.4.1 7.3.1.4.2 7.3.1.4.3 7.3.1.4.4 7.3.1.4.5 7.3.2 7.3.2.1 7.3.2.2 7.3.3 7.3.3.1 7.3.3.2 7.3.3.2.1 7.3.3.2.2 7.3.3.3 7.3.3.3.1 7.3.3.3.2 7.3.3.3.3 7.3.3.3.4 7.3.3.3.5 7.3.3.3.6 Branch Processing Unit (BPU) .7-12 Memory Subsystem Pipeline Stages .7-13 Memory Subsystem.7-14 Memory Management Unit (MMU) .7-14 Interface Unit .7-14 Write Queue .7-15 Read Queue .7-15 Interface Arbitration .7-16 Parking .7-17 Cache Unit.7-17 Cache Arbiter .7-17 Cache Timing.7-17 Cache Miss Timing .7-18 Timings When Processor Clock Frequency Equals Clock Frequency .7-18 Timings When Processor Clock Frequency Does Equal Clock Frequency.7-20 Pipeline Timing .7-22 Common Stages/BPU Pipeline Stages .7-23 Common Stages-Fetch Arbitration (FA) Stage .7-23 Common Stages-Cache Arbitration (CARB) Stage .7-24 Common Stages-Cache Access (CACC) Stage.7-24 Common Stages-Dispatch (DS) Stage .7-25 Branch Dispatch.7-25 Integer Dispatch .7-25 Floating-Point Dispatch .7-26 Synchronization Tags Precise Exception Model.7-26 Dispatch Considerations Related IU/FPU Synchronization .7-28 Pipeline Stages .7-29 Speculative Execution Mispredict Recovery Mechanism.7-29 Branch Pipeline Timing .7-31 Integer Pipeline Stages.7-35 Integer Pipeline-Integer Decode (ID) Stage .7-37 Integer Pipeline-Integer Execute (IE) Stage.7-38 Stage-ALU Instruction Operation .7-38 Stage-Basic Load Store Instruction Operation .7-39 Integer Operations that Access Memory Subsystem .7-39 Integer Pipeline-CARB Stage .7-39 Integer Floating-Point Store Buffer Stages (ISB FPSB) .7-40 Address Translation .7-40 Unaligned Load/Store Operations.7-40 Load/Store String/Multiple Operations.7-41 Integer Pipeline-Cache Access (CACC) Stage .7-41
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CONTENTS
Paragraph Number 7.3.3.4 7.3.3.5 7.3.3.5.1 7.3.3.5.2 7.3.3.5.3 7.3.3.5.4 7.3.3.5.5 7.3.3.5.6 7.3.3.5.7 7.3.3.5.8 7.3.3.5.9 7.3.3.5.10 7.3.3.5.11 7.3.3.5.12 7.3.3.5.13 7.3.3.5.14 7.3.3.5.15 7.3.3.5.16 7.3.3.5.17 7.3.3.5.18 7.3.3.5.19 7.3.3.5.20 7.3.3.5.21 7.3.3.5.22 7.3.3.5.23 7.3.4 7.3.4.1 7.3.4.2 7.3.4.3 7.3.4.4 7.3.4.5 7.3.4.5.1 7.3.4.5.2 7.3.4.5.3 7.3.4.5.4 7.3.4.5.5 7.3.4.5.6 7.3.4.5.7 Title Page Number
Integer Pipeline-Integer Writeback Stages (IWA IWL) .7-42 Integer Pipeline Instruction Timings .7-42 Arithmetic Instructions.7-42 Boolean Logic Instruction Timings.7-46 Rotate, Shift, Mask Instruction Timings .7-47 Condition Register (CR) Instruction Timings .7-49 Move (mtspr) Instruction Timings.7-51 Move (mtmsr) Instruction.7-52 Move Segment Register Instructions .7-53 Move from Special Purpose Register (mfspr) .7-54 Move from Machine State Register (mfmsr) Instruction Timing .7-55 Move from Segment Register Instruction Timing .7-55 System Call (sc) Return from Interrupt (rfi) Instruction Timings.7-56 Cache Instruction Timings .7-56 Load Instruction Timing.7-58 Load with Update Instruction Timing .7-59 Load Multiple Word (lmw) Load String Word Immediate (lswi).7-60 Load String Word Indexed (lswx) Load String Compare Byte Indexed (lscbx) Instruction Timing .7-61 Integer Store Instruction Timings.7-63 Store with Update Instruction Timing.7-64 Floating-Point Store Instruction Timing .7-64 Update-Form Floating-Point Store Instruction Timings .7-66 Store Multiple Word (stmw) Store String Word Immediate (stswi) .7-68 Store String Word Indexed (stswx) Instruction Timings .7-69 Store Conditional Word Indexed Instruction .7-71 Floating-Point Pipeline Stages .7-72 Floating-Point Decode Stage (FD) .7-73 Floating-Point Multiply Stage (FPM) .7-74 Floating-Point Stage (FPA) .7-74 Floating-Point Write-Back Stage (FWA).7-75 Floating-Point Pipeline Timing .7-75 Single-Precision Instructions.7-75 Double-Precision Instruction Timing.7-77 Floating-Point Move/Store Instruction Timing.7-80 Convert-to-Integer Instruction Timing.7-80 Special Instructions Implemented FPU.7-80 Floating-Point Special-Case Number-Handling Stalls.7-81 Floating-Point Normalization Stalls.7-83 Execute Stage Delay Summary .7-84
PowerPC RISC Microprocessor User's Manual
CONTENTS
Chapter
Signal Descriptions
8.2.1 8.2.1.1 8.2.1.2 8.2.1.3 8.2.1.3.1 8.2.1.3.2 8.2.2 8.2.2.1 8.2.2.1.1 8.2.2.1.2 8.2.2.2 8.2.2.2.1 8.2.2.2.2 8.2.3 8.2.3.1 8.2.3.1.1 8.2.3.1.2 8.2.3.1.3 8.2.3.1.4 8.2.3.2 8.2.3.2.1 8.2.3.2.2 8.2.3.3 8.2.4 8.2.4.1 8.2.4.1.1 8.2.4.1.2 8.2.4.2 8.2.4.2.1 8.2.4.2.2 8.2.4.3 8.2.4.3.1 8.2.4.3.2 8.2.4.4 8.2.4.5 8.2.4.6 8.2.4.7 8.2.4.7.1 Signal Configuration .8-2 Signal Descriptions .8-3 Address Arbitration Signals.8-3 Request (BR)-Output .8-4 Grant (BG)-Input.8-4 Address Busy (ABB) .8-5 Address Busy (ABB)-Output .8-5 Address Busy (ABB)-Input .8-5 Address Transfer Start Signals.8-6 Transfer Start (TS) .8-6 Transfer Start (TS)-Output .8-6 Transfer Start (TS)-Input.8-6 Extended Address Transfer Start (XATS) .8-6 Extended Address Transfer Start (XATS)-Output .8-7 Extended Address Transfer Start (XATS)-Input.8-7 Address Transfer Signals .8-7 Address (A0-A31) .8-7 Address (A0-A31)-Output (Memory Operations).8-7 Address (A0-A31)-Input (Memory Operations) .8-8 Address (A0-A31)-Output (I/O Controller Interface Operations).8-8 Address (A0-A31)-Input (I/O Controller Interface Operations) .8-8 Address Parity (AP0-AP3) .8-8 Address Parity (AP0-AP3)-Output.8-9 Address Parity (AP0-AP3)-Input .8-9 Address Parity Error (APE)-Output.8-9 Address Transfer Attribute Signals.8-10 Transfer Type (TT0-TT4) .8-10 Transfer Type (TT0-TT4)-Output .8-10 Transfer Type (TT0-TT3)-Input .8-10 Transfer Size (TSIZ0-TSIZ2).8-12 Transfer Size (TSIZ0-TSIZ2)-Output.8-12 Transfer Size (TSIZ0-TSIZ2)-Input .8-13 Transfer Burst (TBST) .8-13 Transfer Burst (TBST)-Output .8-13 Transfer Burst (TBST)-Input.8-14 Transfer Code (TC0-TC1)-Output.8-14 Cache Inhibit (CI)-Output .8-14 Write-Through (WT)-Output .8-15 Global (GBL) .8-15 Global (GBL)-Output .8-15
Contents
CONTENTS
Paragraph Number 8.2.4.7.2 8.2.4.8 8.2.4.9 8.2.5 8.2.5.1 8.2.5.2 8.2.5.2.1 8.2.5.2.2 8.2.5.3 8.2.5.3.1 8.2.5.3.2 8.2.6 8.2.6.1 8.2.6.2 8.2.6.3 8.2.6.3.1 8.2.6.3.2 8.2.7 8.2.7.1 8.2.7.1.1 8.2.7.1.2 8.2.7.2 8.2.7.2.1 8.2.7.2.2 8.2.7.3 8.2.8 8.2.8.1 8.2.8.2 8.2.8.3 8.2.9 8.2.9.1 8.2.9.2 8.2.9.3 8.2.9.4 8.2.9.4.1 8.2.9.4.2 8.2.9.5 8.2.9.6 8.2.9.7 8.2.9.8 8.2.9.9 8.2.10 8.2.11 Title Page Number
Global (GBL)-Input .8-15 Cache Element (CSE0-CSE2)-Output .8-15 High-Priority Snoop Request (HP_SNP_REQ).8-16 Address Transfer Termination Signals.8-16 Address Acknowledge (AACK)-Input.8-16 Address Retry (ARTRY).8-17 Address Retry (ARTRY)-Output.8-17 Address Retry (ARTRY)-Input .8-18 Shared (SHD).8-18 Shared (SHD)-Output.8-18 Shared (SHD)-Input .8-19 Data Arbitration Signals.8-19 Data Grant (DBG)-Input .8-19 Data Write Only (DBWO)-Input .8-20 Data Busy (DBB) .8-20 Data Busy (DBB)-Output .8-20 Data Busy (DBB)-Input.8-20 Data Transfer Signals .8-21 Data (DH0-DH31, DL0-DL31) .8-21 Data (DH0-DH31, DL0-DL31)-Output .8-22 Data (DH0-DH31, DL0-DL31)-Input.8-22 Data Parity (DP0-DP7).8-22 Data Parity (DP0-DP7)-Output.8-22 Data Parity (DP0-DP7)-Input .8-23 Data Parity Error (DPE)-Output.8-23 Data Transfer Termination Signals .8-23 Transfer Acknowledge (TA)-Input.8-24 Data Retry (DRTRY)-Input .8-24 Transfer Error Acknowledge (TEA)-Input.8-25 System Status Signals.8-25 Interrupt (INT)-Input.8-25 Checkstop Input (CKSTP_IN)-Input .8-26 Checkstop Output (CKSTP_OUT)-Output.8-26 Reset Signals .8-26 Hard Reset (HRESET)-Input.8-27 Soft Reset (SRESET)-Input .8-27 System Quiesced (SYS_QUIESC).8-27 Resume (RESUME) .8-28 Quiesce Request (QUIESC_REQ) .8-28 Reservation (RSRV)-Output.8-28 Driver Mode (SC_DRIVE) .8-29 COP/Scan Interface .8-29 Clock Signals.8-30
PowerPC RISC Microprocessor User's Manual
CONTENTS
8.2.11.1 8.2.11.2 8.2.11.3 8.2.11.4 Double-Speed Processor Clock (2X_PCLK)-Input .8-30 Clock Phase (PCLK_EN)-Input .8-31 Phase (BCLK_EN)-Input.8-32 Real-Time Clock (RTC)-Input .8-35 Clocking Multiprocessor System .8-35 Chapter
System Interface Operation
9.1.1 9.1.2 9.1.3 9.1.4 9.2.1 9.2.2 9.3.1 9.3.2 9.3.2.1 9.3.2.2 9.3.2.2.1 9.3.2.2.2 9.3.2.3 9.3.2.3.1 9.3.2.4 9.3.3 9.3.3.1 9.4.1 9.4.1.1 9.4.2 9.4.3 9.4.3.1 9.4.3.2 9.4.4 9.6.1 9.6.1.1 9.6.1.2 PowerPC Microprocessor System Interface Overview.9-1 Operation On-Chip Cache.9-2 Operation Memory Unit Loads Stores .9-4 Operation System Interface.9-4 Controller Interface Accesses .9-5 Memory Access Protocol .9-6 Arbitration Signals .9-8 Address Pipelining Split-Bus Transactions.9-9 Address Tenure .9-10 Address Arbitration.9-10 Address Transfer .9-12 Address Parity.9-13 Address Transfer Attribute Signals.9-13 Transfer Type (TT0-TT4) Signals.9-13 Transfer Size (TSIZ0-TSIZ2) Signals.9-14 Effect Alignment Data Transfers.9-15 Alignment External Control Instructions.9-17 Transfer Code (TC0-TC1) Signals .9-18 Address Transfer Termination .9-19 Address Retry Sources .9-21 Data Tenure.9-21 Data Arbitration .9-22 Using Signal .9-22 Data Transfer.9-23 Data Transfer Termination.9-24 Normal Single-Beat Termination.9-24 Data Transfer Termination Error.9-26 Memory Coherency-MESI Protocol.9-28 Timing Examples .9-30 Memory- I/O-Mapped Operations.9-37 Controller Interface Transactions .9-39 Store Operations.9-40 Load Operations .9-40
Contents
xvii
CONTENTS
Paragraph Number 9.6.2 9.6.2.1 9.6.2.2 9.6.3 9.6.4 9.7.1 9.7.2 9.7.3 9.7.4 9.8.1 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.10 Title Page Number
Controller Interface Transaction Protocol Details .9-41 Packet .9-42 Packet .9-43 Reply Operations.9-43 Controller Interface Operation Timing .9-45 Interrupt, Checkstop, Reset Signals.9-47 External Interrupt.9-47 Checkstops.9-47 Reset Inputs .9-48 Soft Stop Control Signals .9-48 Processor State Signals.9-48 Support lwarx/stwcx. Instruction Pair.9-48 IEEE 1149.1-Compatible Interface .9-49 Deviations from IEEE 1149.1 Boundary-Scan Specifications.9-49 Additional Information about IEEE 1149.1 Interface .9-50 IEEE 1149.1 Interface Description.9-50 IEEE Interface Clock Requirements .9-50 IEEE 1149.1 Interface Reset Requirements .9-52 IEEE Interface Instruction Set.9-53 IEEE 1149.1 Interface Boundary-Scan Chain.9-53 Using DBWO (Data Write Only) .9-60 Chapter
Instruction
10.1 10.1.1 10.1.2 10.1.3 10.2 10.3 Instruction Formats.10-1 Split-Field Notation .10-1 Instruction Fields .10-2 Notation Conventions .10-4 Instruction Set.10-6 Instructions Implemented .10-219 Appendix Instruction Listings
Complete Instruction List Sorted Mnemonic .A-1 Complete Instruction List Sorted Opcode.A-10 Instructions Grouped Functional Categories.A-18 Complete Instruction List Sorted Form.A-28
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PowerPC RISC Microprocessor User's Manual
CONTENTS
Appendix POWER Architecture Cross Reference
B.10 B.11 B.12 B.13 B.14 B.15 B.16 B.17 B.18 B.19 B.20 B.21 B.22 B.23 B.24 B.24.1 B.24.2 B.25 B.26
Instructions, Formerly Supervisor-Level Instructions.B-1 Newly Supervisor-Level Instructions .B-1 Reserved Bits Instructions .B-2 Reserved Bits Registers .B-2 Alignment Check .B-2 Condition Register .B-2 Inappropriate bits .B-3 Field.B-3 Branch Conditional Count Register.B-4 System Call/Supervisor Call .B-4 Integer Exception Register (XER) .B-4 Update Forms Memory Access .B-4 Multiple Register Loads.B-5 Alignment Load/Store Multiple .B-5 Load String Instructions.B-5 Synchronization .B-5 Move to/from .B-6 Effects Exceptions FPSCR Bits .B-6 Floating-Point Store Instructions .B-6 Move from FPSCR .B-6 Clearing Bytes Data Cache .B-7 Segment Register Instructions .B-7 Entry Invalidation.B-7 Timing Facilities .B-7 Real-Time Clock .B-7 Decrementer .B-8 Deleted Instructions .B-8 POWER Instructions Supported PowerPC Architecture .B-10
Appendix PowerPC Instructions Implemented
Contents
CONTENTS
Paragraph Number Title Appendix Classes Instructions Page Number
D.1.1 D.1.1.1 D.1.2 D.1.3
Classes Instructions.D-1 Defined Instruction Class .D-1 Invalid Instruction Forms .D-2 Illegal Instruction Class .D-2 Reserved Instructions .D-3
Appendix Multiple-Precision Shifts
Multiple-Precision Shift Examples
Appendix Floating-Point Models
F.3.1 F.3.2
Conversion from Floating-Point Number Signed Fixed-Point Integer Word Conversion from Floating-Point Number Unsigned Fixed-Point Integer Word Floating-Point Models. Floating-Point Round Single-Precision Model Floating-Point Convert Integer Model
Appendix Synchronization Programming Examples
G.2.1 G.2.2 G.2.3 G.2.4 G.2.5
General Information .G-1 Synchronization Primitives .G-2 Fetch No-Op .G-2 Fetch Store .G-2 Fetch Add.G-3 Fetch AND.G-3 Test .G-3 Compare Swap.G-4 Lock Acquisition Release.G-4 List Insertion .G-5
PowerPC RISC Microprocessor User's Manual
CONTENTS
Appendix Implementation Summary Programmers
POWER Extensions Variances. Implementation-Dependent Extensions Options PowerPC Architecture.
Appendix Instruction Timing Examples
I.1.1 I.1.1.1 I.1.1.2 I.1.1.3 I.1.1.4 I.1.1.5 I.1.1.6 I.1.1.6.1 I.1.1.6.2 I.1.1.6.3 I.1.1.6.4 I.1.1.6.5 I.1.1.7 I.1.1.7.1 I.1.1.7.2 I.1.1.7.3 I.1.1.7.4 I.2.1 I.2.1.1 I.2.1.2 I.2.1.3 I.2.1.4 I.2.1.5 I.2.2 I.2.2.1 I.2.2.1.1
Branch Instruction Timing Examples .I-1 General Branch Timing.I-1 Dispatch Considerations.I-1 Integer Instruction Dependencies.I-3 Dependencies with CTR.I-5 Stalls Caused when Link Shadow Register Full.I-7 Performance Considerations when Instruction Cannot Dispatched Order-Link Count Dependencies .I-10 Conditional Branch Timing.I-12 Conditional Operations-Case .I-12 Conditional Operations-Case .I-16 Conditional Operations-Case .I-20 Conditional Operations-Case .I-26 Conditional Operations-Case .I-37 Conditional Loop Closure Examples .I-48 Conditional Loop Closure-Case 1.I-48 Conditional Loop Closure-Case 2.I-52 Conditional Loop Closure-Case 3.I-58 Conditional Loop Closure-Case 1.I-70 Integer Instruction Timing Examples .I-83 Instruction Timings.I-83 Data Dependencies .I-83 Condition Register (CR) Dependencies .I-88 Dependencies.I-97 Dependencies .I-104 Other Register Dependencies Instructions .I-106 Load/Store Instruction Timings .I-111 Load Target Dependencies.I-111 Load Instructions Followed Independent Operation Body I-111
Contents
CONTENTS
Paragraph Number Title Page Number
I.2.2.1.2 I.2.2.1.3 I.2.2.1.4 I.2.2.1.5 I.2.3 I.2.3.1 I.2.3.2 I.3.1 I.3.2
Load Instruction Followed Dependent Operation. I-112 Load Instruction Followed Dependent Operation with Intervening Independent Instruction. I-113 Consecutive Load Instructions without Register Dependencies. I-114 Consecutive Load Instructions with Dependency. I-114 Store Source Dependencies I-119 Load Store Operations that Update Option. I-121 Load/Store Collisions I-125 Floating-Point Instruction Timing Examples. I-126 Floating-Point Data Dependency Stalls. I-126 Timing Examples Involving Floating-Point Code Sequences. I-130 Additional Code Sequence Timings. I-150 Glossary Terms Abbreviations Index
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PowerPC RISC Microprocessor User's Manual
Appendix Instruction Listings
This appendix lists instruction implemented PowerPC microprocessor additional PowerPC instructions implemented sorted mnemonic, opcode, form, grouped functional categories.
Complete Instruction List Sorted Mnemonic
Table lists instructions implemented plus those defined PowerPC architecture that implemented alphabetical order mnemonic.
Table A-1. Complete Instruction List Sorted Mnemonic
Key: Reserved bits Instruction implemented
Name absx addx addcx addex addi addic addic. addis addmex addzex andx andcx andi. andis.
00000
SIMM SIMM SIMM SIMM
00000 00000
UIMM UIMM
Appendix Instruction Listings
Name bcctrx bclrx clcs cmpi cmpl cmpli cntlzd
crfD crfD crfD crfD crbD crbD crbD crbD crbD crbD crbD crbD 00000 00000 00000 00000 00000 00000 crbA crbA crbA crbA crbA crbA crbA crbA
00000 00000 00000 SIMM UIMM 00000 00000 crbB crbB crbB crbB crbB crbB crbB crbB SIMM 1014
cntlzwx crand crandc creqv crnand crnor cror crorc crxor dcbf dcbi dcbst dcbt dcbtst dcbz divx divd divdu divsx divwx divwux dozx dozi
PowerPC RISC Microprocessor User's Manual
Name eciwx ecowx eieio eqvx extsbx extshx extsw fabsx faddx faddsx fcfid fcmpo fcmpu fctid
crfD crfD
00000
00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
fctidz fctiwx fctiwzx fdivx fdivsx fmaddx fmaddsx fmrx fmsubx fmsubsx fmulx fmulsx fnabsx fnegx fnmaddx fnmaddsx fnmsubx fnmsubsx fresx
Appendix Instruction Listings
Name frspx frsqrte fselx fsqrtx fsqrts fsubx fsubsx icbi isync lbzu lbzux lbzx
00000 00000
00000 00000 00000 00000 00000
00000 00000 00000 00000 00000 00000
ldarx
ldux
lfdu lfdux lfdx lfsu lfsux lfsx lhau lhaux lhax lhbrx lhzu
PowerPC RISC Microprocessor User's Manual
Name lhzux lhzx lscbxx
crbD crfD crfD crfS
crbD crbD
crfS crfS
00000 00000 00000 00000 00000 00000
lswi lswx
lwarx lwaux lwax
lwbrx lwzu lwzux lwzx maskgx
maskirx mcrf mcrfs mcrxr mfcr mffsx mfmsr mfspr
00000 00000 00000 00000
mfsr mfsrin mftb mtcrf mtfsb0x mtfsb1x mtfsfx mtfsfix mtmsr
00000
00000
00000 00000
00000 00000
00000 00000
00000
Appendix Instruction Listings
Name mtspr mtsr
00000 00000 00000
00000 SIMM 00000 00000 UIMM UIMM 00000
mtsrin mulx
00000 00000 00000 00000
mulhd mulhdu
mulhwx mulhwux mulld mulli mullwx nabsx
nandx negx norx orcx oris
rldcl rldcr
rldic rldicl
rldicr rldimi rlmix rlwimix rlwinmx rlwnmx rribx slbia
000000000000000 00000
PowerPC RISC Microprocessor User's Manual
Name slbie
00000
00000
slex sleqx
sliqx slliqx
sllqx slqx
slwx srad
sradi sraiqx
sraqx srawx srawix
srex sreax
sreqx sriqx srliqx srlqx
srqx srwx stbu stbux stbx stdcx. stdu stdux stdx
Appendix Instruction Listings
Name stfd stfdu stfdux stfdx stfiwx stfs stfsu stfsux stfsx sthbrx sthu sthux sthx stmw stswi
00000 00000
00000 00000 00000 00000 00000 00000
SIMM SIMM
stswx stwbrx stwcx. stwu stwux stwx subfx subfcx subfex subfic subfmex subfzex sync tlbia
PowerPC RISC Microprocessor User's Manual
Name tlbie tlbsync
00000 00000
00000 00000
00000 SIMM UIMM UIMM
xorx xori xoris
Supervisor-level instruction. Supervisor- user-level instruction. Non-PowerPC instruction implemented POWER architecture compatibliity. Load store string multiple word instruction. 64-bit instruction.
Appendix Instruction Listings
Complete Instruction List Sorted Opcode
Table lists instructions implemented plus those defined PowerPC architecture that implemented numerical order opcode.
Table A-2. Complete Instruction List Sorted Opcode
Key: Reserved bits Name mulli subfic dozi
Instruction implemented
0000 0000 0001 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100
crfD crfD 00000
00000
SIMM SIMM SIMM SIMM SIMM UIMM SIMM SIMM SIMM SIMM SIMM 000000000000000 0000 0010 0100 0110 0000 0010 1000 1100 0000 0100 0100 1000 0010
cmpli cmpi addic addic. addi addis mcrf bclrx crnor crandc isync crxor crnand crand creqv crorc cror bcctrx
crfD crbD
crfS crbA
00000 00000 crbB 00000 crbB 00000 crbB crbB crbB crbB crbB crbB 00000
00000 crbD 00000 crbD crbD crbD crbD crbD crbD
00000 crbA 00000 crbA crbA crbA crbA crbA crbA
0100
A-10
PowerPC RISC Microprocessor User's Manual
Name rlwimix rlwinmx rlmix rlwnmx oris xori xoris andi. andis. rldicl rldicrx
0101 0101 0101 0101 0110 0110 0110 0110 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 crfD crfD
00000
UIMM UIMM UIMM UIMM UIMM UIMM
00000 00000
0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0011 0100 0101
1000 1001
rldicx rldimi
rldclx rldcr
subfcx mulhdux
addcx mulhwux mfcr lwarx lwzx slwx cntlzwx sldx andx maskgx cmpl subfx
Appendix Instruction Listings
A-11
Name ldux dcbst lwzux cntlzdx andcx
0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111
00000 00000
00000
00000 00000 00000 00000 00000 00000 00000
0110 0110 0110 0111 0111
0001000100 1001 1001 1010 1010 1010 1010 1101 1101 1110 1111 0001 0001 0010 0010 0010 0010 0010 0011 0011 0110 0110 0111 1001 1001 1010 1010 1010
mulhdx mulhwx mfmsr ldarx
dcbf lbzx negx mulx
lbzux norx subfex addex mtcrf mtmsr stdx stwcx. stwx slqx
00000
slex stdux stwux sliqx subfzex addzex mtsr stdcx. stbx
A-12
PowerPC RISC Microprocessor User's Manual
Name sllqx sleqx
0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111
00000 00000 00000 00000
00000 00000 00000
00000 00000
1011 1011 1101 1101 1101 1101 1110 1110 1110 1111 0001 0001 0010 0010 0010 0011 0110 0110 0110 0111 1001 1010 1010 1010 1101 1101 1110 1110 1110 1110 0010 0011 0111
subfmex mulld
addmex mullwx mtsrin dcbtst stbux slliqx
dozx addx lscbxx dcbt lhzx eqvx tlbie eciwx lhzux xorx divx mfspr lwax lhax absx divsx tlbia mftb lwaux lhaux sthx orcx sradix
00000 00000
Appendix Instruction Listings
A-13
Name slbie ecowx sthux divdux divwux mtspr dcbi nandx nabsx
0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111
00000 00000 00000 crfS 00000 00000
00000 00000 00000 00000
0110 0110 0110 0111 1001 1001 1010 1010 1011 1101 1101 1101 1110 0000 0010 0010 0010 0010 0011 0011 0011 0011 0110 0110 1010 1010 1010 1010 1110 0010 0010 0010 0010
00000 00000 00000 00000 00000 00000 00000
divdx divwx slbia mcrxr clcs lswx
lwbrx lfsx srwx rribx
srdx maskirx
tlbsync lfsux mfsr lswi sync lfdx lfdux mfsrin stswx stwbrx stfsx
00000 00000
A-14
PowerPC RISC Microprocessor User's Manual
Name srqx srex
0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 1000 1000 1000 1000 1001 1001 1001 1001
00000 00000 00000
00000
00000 00000 00000 00000
0011 0011 0110 0111 1010 1010 1011 1011 1110 1111 0010 0011 0011 0111 1010 0010 0011 0011 0011 0111 0111 1010 1010 1011 1110
stfsux sriqx stswi stfdx srlqx sreqx stfdux srliqx
lhbrx srawx sradx srawix eieio sthbrx sraqx sreax
extshx sraiqx
extsbx icbi stfiwx extsw
dcbz lwzu lbzu stwu stbu
Appendix Instruction Listings
A-15
Name lhzu lhau sthu stmw
1010 1010 1010 1010 1011 1011 1011 1011 1100 1100 1100 1100 1101 1101 1101 1101 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1111 1111 1111 crfD
00000 00000 00000 00000
10010 10100 10101 10110 11000 11001 11100 11101 11110 11111 0000 0001
lfsu lfdu stfs stfsu stfd stfdu
fdivsx fsubsx faddsx fsqrtsx fresx fmulsx fmsubsx fmaddsx fnmsubsx fnmaddsx stdu fcmpu frspx
00000 00000 00000 00000 00000
A-16
PowerPC RISC Microprocessor User's Manual
Name fctiwx fctiwzx fdivx fsubx faddx fsqrtx fselx fmulx frsqrtex fmsubx fmaddx fnmsubx fnmaddx fcmpo mtfsb1x fnegx mcrfs mtfsb0x fmrx mtfsfix fnabsx fabsx mffsx mtfsfx fctidx fctidzx fcfidx
1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 crbD crfD crfD
00000 00000 00000 00000 00000 00000 crfS
00000 00000 00000 00000
00000 00000 00000 00000 00000
0001 0001
10010 10100 10101 10110 10111 11001 11010 11100 11101 11110 11111
0100 0100 0101 1000 1000 1001 0000 0001 0001 1000 1000 0101 0101 1001
crbD
crbD
00000 00000 00000 00000 00000 00000 00000 00000 00000
00000
Supervisor-level instruction. Supervisor- user-level instruction. Non-PowerPC instruction implemented POWER architecture compatibliity. Load store string multiple word instruction. 64-bit instruction.
Appendix Instruction Listings
A-17
Instructions Grouped Functional Categories
Table through Table A-30 list instructions grouped functional categories.
Table A-3. Integer Arithmetic Instructions
Key: Reserved bits Name absx addcx addex addi addic addic. addis addmex addx addzex divx divsx
Instruction implemented
00000
SIMM SIMM SIMM SIMM
00000 00000
SIMM
divwx divwux dozx dozi
mulx mulhwx mulhwux mulli mullwx nabsx negx subfx subfcx subfex subfmex
SIMM
00000 00000 00000
A-18
PowerPC RISC Microprocessor User's Manual
subfzex
00000
Table A-4. Integer Compare Instructions
Name cmpi cmpl cmpli
crfD crfD crfD crfD
SIMM UIMM
Table A-5. Integer Logical Instructions
Name andx andcx andi. andis. cntlzwx eqvx extsbx extshx nandx norx orcx oris xorx xori xoris
UIMM UIMM 00000 00000 00000 UIMM UIMM UIMM UIMM
Appendix Instruction Listings
A-19
Table A-6. Integer Rotate Instructions
Name maskgx maskirx
rlmix rlwimix rlwinmx rlwnmx rribx
Table A-7. Integer Shift Instructions
Name slex sleqx sliqx
slliqx sllqx
slqx slwx sraqx sraiqx
srawx srawix srex sreax
sreqx sriqx srliqx srlqx
srqx srwx
A-20
PowerPC RISC Microprocessor User's Manual
Table A-8. Floating-Point Arithmetic Instructions
Name
faddx faddsx fdivx fdivsx fmulx fmulsx fsubx fsubsx
00000 00000
00000 00000 00000 00000 00000 00000
Table A-9. Floating-Point Rounding Conversion Instructions
Name
fctiwx fctiwzx frspx
00000 00000 00000
Table A-10. Floating-Point Compare Instructions
Name
fcmpo fcmpu
crfD crfD
Table A-11. Floating-Point Status Control Register Instructions
Name
mcrfs mffsx mtfsb0x mtfsb1x mtfsfx mtfsfix
crfD crbD crbD
crfS
00000 00000 00000 00000
00000 00000 00000
00000
crbD
Appendix Instruction Listings
A-21
Table A-12. Integer Load Instructions
Name lbzu lbzux lbzx lhau lhaux lhax lhzu lhzux lhzx lwzu lwzux lwzx
Table A-13. Integer Store Instructions
Name stbu stbux stbx sthu sthux sthx stwu stwux stwx
A-22
PowerPC RISC Microprocessor User's Manual
Table A-14. Integer Load Store with Byte Reversal Instructions
Name lhbrx lwbrx sthbrx stwbrx
Table A-15. Integer Load Store Multiple Instructions
Name stmw
Table A-16. Integer Move String Instructions
Name lscbxx lswi lswx stswi stswx
Table A-17. Memory Synchronization Instructions
Name eieio isync lwarx stwcx. sync
00000 00000 00000
00000 00000 00000
00000 00000 00000
Appendix Instruction Listings
A-23
Table A-18. Floating-Point Load Instructions
Name
lfdu lfdux lfdx lfsu lfsux lfsx
Table A-19. Floating-Point Store Instructions
Name
stfd stfdu stfdux stfdx stfs stfsu stfsux stfsx
Table A-20. Floating-Point Move Instructions
Name
fabsx fmrx fnabsx fnegx
00000 00000 00000 00000
A-24
PowerPC RISC Microprocessor User's Manual
Table A-21. Branch Instructions
Name
bcctrx bclrx
00000 00000
Table A-22. Condition Register Logical Instructions
Name crand crandc creqv crnand crnor cror crorc crxor mcrf
crbD crbD crbD crbD crbD crbD crbD crbD crfD
crbA crbA crbA crbA crbA crbA crbA crbA crfS
crbB crbB crbB crbB crbB crbB crbB crbB 00000
Table A-23. System Linkage Instructions
Name
00000 00000
00000 00000
00000
000000000000000
Table A-24. Trap Instructions
Name
SIMM
Appendix Instruction Listings
A-25
Table A-25. Move to/from Special Purpose Register Instructions
Name mcrxr mfcr mfmsr mfspr
crfS
00000 00000 00000 00000
00000 00000 00000
mtcrf mtmsr
00000
mtspr
Table A-26. Cache Management Supervisor-Level Instruction
Name dcbi
00000
Table A-27. User-Level Cache Instructions
Name clcs dcbf dcbst dcbt dcbtst dcbz
00000 00000 00000 00000 00000
00000
1014
Table A-28. Segment Register Manipulation Instructions
Name mfsr mfsrin mtsr mtsrin
00000 00000
00000
00000
Table A-29. Translation Lookaside Buffer Management Instruction
Name tlbie
00000
00000
A-26
PowerPC RISC Microprocessor User's Manual
Table A-30. External Control Instructions
Name eciwx ecowx
Supervisor-level instruction. Supervisor- user-level instruction. Non-PowerPC instruction implemented POWER architecture compatibility. Load store string multiple word instruction. 64-bit instruction.
Appendix Instruction Listings
A-27
Complete Instruction List Sorted Form
Table A-31 through Table A-45 list instructions grouped form.
Key: Reserved bits Instruction implemented
Table A-31. I-Form
OPCD Specific Instruction Name
Table A-32. B-Form
OPCD Specific Instruction Name
Table A-33. SC-Form
OPCD 00000 00000 Specific Instruction Name
000000000000000
00000
00000
000000000000000
Table A-34. D-Form
OPCD OPCD OPCD OPCD OPCD OPCD OPCD crfD crfD SIMM UIMM SIMM UIMM SIMM
A-28
PowerPC RISC Microprocessor User's Manual
OPCD OPCD
Specific Instructions
Name addi addic addic. addis andi. andis. cmpi cmpli dozi lbzu lfdu lfsu lhau lhzu
crfD crfD
SIMM SIMM SIMM SIMM UIMM UIMM SIMM UIMM SIMM SIMM UIMM UIMM
lwzu mulli oris stbu stfd stfdu stfs
Appendix Instruction Listings
A-29
stfsu sthu stmw stwu subfic xori xoris
SIMM SIMM SIMM UIMM UIMM
Table A-35. DS-Form
OPCD Specific Instructions Name
stdu
Table A-36. X-Form
OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD 00000 00000 00000 00000
00000 00000 00000 00000
A-30
PowerPC RISC Microprocessor User's Manual
OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD crfD crfD crfD crfS crbD
00000 00000
00000 00000
crfS
00000 00000
00000 00000 00000
00000 00000
00000
Specific Instructions Name andx andcx cmpl cntlzd cntlzwx dcbf dcbi
crfD crfD
00000 00000 00000 00000 00000 00000 00000
00000 00000
00000 00000 00000 00000 00000 00000
1014
dcbst dcbt dcbtst dcbz eciwx ecowx eieio eqvx extsbx extshx extsw fabsx
Appendix Instruction Listings
A-31
fctid fctidz fcfid
crfD crfD
00000
00000 00000 00000 00000 00000 00000 00000 00000 00000
0000000000
fctiwx fctiwzx fcmpo fcmpu fmrx fnabsx fnegx frspx icbi lbzux lbzx ldux
ldarx
lfdux lfdx lfsux lfsx lhaux lhax lhbrx lhzux lhzx lscbxx lswi lswx lwarx lwbrx lwzux lwzx lwaux lwax
A-32
PowerPC RISC Microprocessor User's Manual
maskgx maskirx mcrfs mcrxr mfcr mffsx mfmsr
crfD crfS
crbD crbD crbD 00000 00000 crfS
00000 00000 00000 00000 00000 00000 00000 00000
00000 00000 00000 00000
mfsr mfsrin
00000 00000 00000 00000 00000
mtfsb0x mtfsb1x mtfsfix mtmsr
00000 00000 00000
mtsr mtsrin
00000 00000 00000
nandx norx orcx rribx slbia
slbie slex sleqx sliqx slliqx sllqx slqx slwx srad sraqx sraiqx srawx srawix
Appendix Instruction Listings
A-33
srex sreax
00000 00000 00000 00000
00000 00000 00000 00000
00000 00000 00000
sreqx sriqx srliqx srlqx
srqx srwx stbux stbx stdcx. stdux
stdx stfdux stfdx stfsux stfiwx stfsx sthbrx sthux sthx stswi stswx stwbrx stwcx. stwx stwux sync tlbia tlbie tlbsync xorx
A-34
PowerPC RISC Microprocessor User's Manual
Table A-37. XL-Form
OPCD OPCD OPCD OPCD crbD crfD crbA crfS 00000 crbB 00000 00000 0000000000
00000
00000
Specific Instructions Name bcctrx bclrx crand creqv crnand crnor cror crorc crxor isync mcrf
crbD crbD crbD crbD crbD crbD crbD 00000 crfD
crbA crbA crbA crbA crbA crbA crbA 00000 crfS
00000 00000 crbB crbB crbB crbB crbB crbB crbB 00000 00000 00000
0000000000
00000
00000
Table A-38. XFS-Form
OPCD OPCD OPCD
Specific Instructions
Name mfspr mtspr
mtcrf mftb
Appendix Instruction Listings
A-35
Table A-39. XFL-Form
OPCD
Specific Instruction Name mtfsfx
Table A-40. XS-Form
OPCD
Specific Instruction Name sradi
Table A-41. XO-Form
OPCD OPCD OPCD 00000
Specific Instructions Name absx addx addcx addex addmex addzex divx
00000 00000 00000
divd divdu
divsx divwx divwux dozx
mulx mulhd
A-36
PowerPC RISC Microprocessor User's Manual
mulhdu mulhwx mulhwux mulld mullwx nabsx negx subfx subfcx subfex subfmex subfzex
00000 00000 00000 00000
Table A-42. A-Form
OPCD OPCD OPCD OPCD 00000 00000 00000 00000
Specific Instructions Name faddx faddsx fdivx fdivsx fmaddx fmaddsx fmsubx fmsubsx fmulx fmulsx fnmaddx fnmaddsx fnmsubx fnmsubsx fresx
00000
00000 00000
00000 00000 00000 00000 00000
Appendix Instruction Listings
A-37
frsqrte fselx fsqrtx fsqrts fsubx fsubsx
00000 00000 00000
00000 00000 00000 00000 00000
Table A-43. M-Form
OPCD OPCD
Specific Instructions Name rlmix rlwimix rlwinmx rlwnmx
Table A-44. MD-Form
OPCD OPCD
Specific Instructions Name rldic rldicl rldicr rldimi
A-38
PowerPC RISC Microprocessor User's Manual
Table A-45. MDS-Form
OPCD OPCD
Specific Instructions Name rldcl rldcr
Supervisor-level instruction. Supervisor- user-level instruction. Non-PowerPC instruction implemented POWER architecture compatibility. Load store string multiple word instruction. 64-bit instruction.
Appendix Instruction Listings
A-39
A-40
PowerPC RISC Microprocessor User's Manual
Appendix POWER Architecture Cross Reference
This appendix identifies incompatibilities that must managed migration from POWER architecture PowerPC architecture. Some incompatibilities can, least principle, detected processor, which traps lets software simulate POWER operation. Others cannot detected processor. general, incompatibilities identified here those that affect POWER application program. Incompatibilities instructions that used only POWER system programs discussed. Note that this appendix describes incompatibilities with respect PowerPC architecture general. PowerPC microprocessor more closely compatible with POWER architecture. POWER instructions implemented listed Table B-4.
Instructions, Formerly Supervisor-Level Instructions
Instructions PowerPC architecture typically opcode values (including extended opcode) that illegal POWER architecture. instructions that supervisor-level POWER architecture (for example, dclz, called dcbz PowerPC architecture) have been made non-supervisor-level PowerPC architecture. POWER program that executes these now-valid now-non-supervisor-level instructions, expecting cause system illegal instruction error handler (program exception) system supervisor-level instruction error handler invoked, will execute correctly PowerPC processors.
Newly Supervisor-Level Instructions
following instructions user-level POWER architecture supervisorlevel PowerPC processors. mfmsr mfsr
Appendix POWER Architecture Cross Reference
Reserved Bits Instructions
These shown with '/'s instruction opcode definitions. POWER architecture such bits ignored processor. PowerPC architecture they must instruction form invalid. several cases PowerPC architecture assumes that such bits POWER instructions indeed cases include following: cmpi, cmp, cmpli, cmpl assume that POWER instructions mtspr mfspr assume that bits 16-20 POWER instructions
Reserved Bits Registers
POWER architecture defines these bits when read, either when written PowerPC architecture implementation-dependent, each register, whether these bits when read ignored when written copied from source target when read written
Alignment Check
POWER machine-state register, MSR[24], supported PowerPC architecture. reserved PowerPC architecture. low-order bits always used. Notice that value 0-the normal value reserved bit-means "ignore low-order bits" POWER architecture, value means "use low-order bits." However, MSR[24] assigned meaning PowerPC architecture.
Condition Register
following instructions specify field explicitly (via field) also have record option. PowerPC architecture, these instructions instruction form invalid. POWER architecture, instructions execute normally except shown Table B-1.
Table B-1. Condition Register Settings
Instruction cmpl mcrxr fcmpu fcmpo mcrfs Setting undefined undefined undefined undefined undefined undefined
PowerPC RISC Microprocessor User's Manual
Inappropriate bits
instructions listed below, POWER processors execute instruction normally with exception setting link register condition register field undefined value. PowerPC architecture, such instruction forms invalid. PowerPC instruction form invalid (svc POWER architecture) Condition register logical instructions mcrf isync (ics POWER architecture)
PowerPC instruction form invalid Rc=1: Integer X-form load store instructions Integer X-form compare instructions X-form trap instruction mtspr, mfspr, mtcrf, mcrxr, mfcr, mtmsr, mfmsr, mtsr, mtsrin, tlbi, eciwx, ecowx, clcs, mfsr, mfsrin, sync, eieio, icli Floating-point X-form load store instructions floating-point compare instructions mcrfs dcbz (dclz POWER architecture)
Field
POWER architecture shows certain bits field-used branch conditional instructions-as without indicating these bits interpreted. These bits ignored POWER processors. PowerPC architecture treats these bits differently, shown Table B-2.
Table B-2. Differences Field
Field BO[0-3] BO[4] Description PowerPC architecture shows bits cleared, instruction form invalid. This bit, which shown POWER architecture independent other four bits-is shown PowerPC architecture gives hint about whether branch likely taken. POWER program wrong value this bit, program runs correctly performance suffer.
Appendix POWER Architecture Cross Reference
Branch Conditional Count Register
case which count register decremented tested (that case which BO[2] POWER architecture specifies only that branch target address undefined, implying that count register, link register updated normal way. PowerPC architecture considers this instruction form invalid.
B.10 System Call/Supervisor Call
System Call (sc) instruction PowerPC architecture called Supervisor Call (svcx) POWER architecture. Differences implementations follows: POWER architecture provides version Supervisor Call instruction (bit that allows instruction fetching continue locations. used "fast SVCs." PowerPC architecture provides such version POWER architecture provides version Supervisor Call instruction (bits 30-31 b'11') that resumes instruction fetching location sets link register address next instruction. PowerPC architecture provides such version; instruction instruction form invalid. POWER architecture, information from saved count register. PowerPC architecture, this information saved SRR1. POWER architecture permits bits 16-29 Supervisor Call (sc) instruction nonzero, while PowerPC architecture, such instruction form invalid. Because bits 16-29 instruction regarded reserved POWER architecture, they ignored 601. POWER architecture saves low-order bits Supervisor Call instruction count register; PowerPC architecture does save them. settings bits system call exception differ between POWER architecture PowerPC architecture.
B.11 Integer Exception Register (XER)
Bits 18-23 reserved PowerPC architecture, whereas POWER architecture they defined contain comparison byte lscbx instruction, which included PowerPC architecture.
B.12 Update Forms Memory Access
PowerPC architecture requires that equal either (integer load only) restriction violated, instruction form invalid. Appendix "Classes Instructions," information about invalid instructions. POWER architecture permits these cases simply avoids saving
PowerPC RISC Microprocessor User's Manual
B.13 Multiple Register Loads
PowerPC architecture requires that present instruction format, range registers loaded, while POWER architecture permits this does alter this case. (The PowerPC architecture restriction applies even although there obvious benefit restriction this case since used compute effective address PowerPC architecture restriction violated, instruction form invalid. instructions affected listed follows: POWER architecture) lswi (lsi POWER architecture) lswx (lsx POWER architecture)
Thus, example, instruction that loads registers valid POWER architecture invalid form PowerPC architecture.
B.14 Alignment Load/Store Multiple
PowerPC architecture requires word-aligned yields alignment exception boundedly undefined results not. POWER architecture specifies that alignment exception occurs
B.15 Load String Instructions
PowerPC architecture, lswx instruction with zero length leaves content undefined, while POWER architecture corresponding instruction (lsx) does alter
B.16 Synchronization
sync instruction (called POWER architecture) causes much more pervasive synchronization PowerPC architecture than POWER architecture. more information, refer Chapter "Instruction Set."
Appendix POWER Architecture Cross Reference
B.17 Move to/from
Differences Move to/from Special Purpose Register (mtspr mfspr) instructions follows: field bits long PowerPC architecture, only POWER architecture. mfspr instruction used read decrementer (DEC) register userlevel mode POWER architecture, only supervisor state PowerPC architecture. value specified instruction defined values, PowerPC architecture considers instruction form invalid. user mode, allowed values exclude those accessible only supervisor mode.) POWER architecture does alter architected registers this case generates program exception instruction executed user mode SPR[0]=1.
PowerPC processors except processor, program exception generated attempt execute mtspr mfspr instruction with SPR[0-4]=0 (which denotes register). Similarly, program exception generated attempts execute mfspr instruction with SPR[0-4] (which denotes reading decrementer register POWER architecture).
B.18 Effects Exceptions FPSCR Bits
following cases, POWER architecture does specify bits set, while PowerPC architecture preserves them illegal operation exceptions caused compare instructions clears them otherwise: Invalid operation exception (enabled disabled) Zero divide exception (enabled disabled) Disabled overflow exception
B.19 Floating-Point Store Instructions
POWER architecture uses FPSCR[UE] help determine whether denormalization should done, while PowerPC architecture does not. Using FPSCR[UE] fact incorrect: PowerPC architecture FPSCR[UE] denormalized singleprecision number copied from memory location another means instruction followed stfs instruction, "copies" same.
B.20 Move from FPSCR
POWER architecture defines high-order bits result mffs x'FFFF FFFF'. PowerPC architecture they undefined.
PowerPC RISC Microprocessor User's Manual
B.21 Clearing Bytes Data Cache
dclz instruction POWER architecture dcbz instruction PowerPC architecture have same opcode. However, functions differ following respects: dclz instruction clears line; dcbz clears block sector 601). dclz instruction saves dcbz does not. dclz instruction supervisor-level; dcbz not.
B.22 Segment Register Instructions
definitions four segment register instructions (mtsr, mtsrin, mfsr, mfsrin) differ respects between POWER architecture PowerPC architecture. Instructions similar mtsrin mfsrin called mtsri mfsri POWER architecture. Privilege-mfsr mfsri user-level instructions POWER architecture, while mfsr mfsrin supervisor-level PowerPC architecture. Function-the indirect instructions (mtsri mfsri) POWER architecture register computing segment register number, computed stored into rD); PowerPC architecture mtsrin mfsrin have field stored. mtsr, mtsrin (mtsri), mfsr instructions have same opcodes PowerPC architecture POWER architecture. mfsri instruction POWER architecture mfsrin instruction PowerPC architecture have different opcodes.
B.23 Entry Invalidation
tlbi instruction POWER architecture tlbie instruction PowerPC architecture have same opcode. However, functions differ following respects. tlbi instruction computes (rA|0) (rB), while tlbie lacks field computes (rB). tlbi instruction saves tlbie lacks field does save
B.24 Timing Facilities
This section describes differences between POWER architecture PowerPC architecture timer facilities.
B.24.1 Real-Time Clock
implements POWER-based RTC. Note that POWER supported PowerPC architecture. Instead, PowerPC architecture provides time base (TB).
Appendix POWER Architecture Cross Reference
Both time base 64-bit special purpose registers, they differ following respects. counts seconds nanoseconds, while counts "ticks." frequency implementation-dependent. increments discontinuously-1 added RTCU when value RTCL passes 999_999_999. increments continuously-1 added when value passes x'FFFF FFFF'. written read mtspr mfspr instructions, using numbers that denote RTCU RTCD. written read instructions mtspr mftb. numbers that denote RTCL RTCU invalid PowerPC architecture except 601. guaranteed increment least once time required execute Immediate (addi) instructions. analogous guarantee made bits RTCL need implemented, while bits must implemented.
B.24.2 Decrementer
PowerPC architecture register decrements same rate that increments, while POWER decrementers decrement every nanosecond (which same rate that increments). bits POWER need implemented, while bits PowerPC architecture must implemented.
B.25 Deleted Instructions
Table lists instructions that part POWER architecture have been dropped from PowerPC architecture. POWER instructions that implemented processor identified table
Table B-3. POWER Instructions Deleted from PowerPC Architecture
Mnemonic clcs dclst divs Absolute Cache Line Compute Size Cache Line Flush Cache Line Invalidate Data Cache Line Store Divide Divide Short Instruction Primary Opcode Secondary Opcode PowerPC Microprocessor
PowerPC RISC Microprocessor User's Manual
Table B-3. POWER Instructions Deleted from PowerPC Architecture (Continued)
Mnemonic dozi lscbx maskg maskir mfsrin nabs rlmi rrib sleq sliq slliq sllq sraiq sraq srea sreq sriq srliq srlq svcx Instruction Difference Zero Difference Zero Immediate Load String Compare Byte Indexed Mask Generate Mask Insert from Register Move from Segment Register Indirect Multiply Negative Absolute Real Address Compute Rotate Left then Mask Insert Rotate Right Insert Shift Left Extended Shift Left Extended with Shift Left Immediate with Shift Left Long Immediate with Shift Left Long with Shift Left with Shift Right Algebraic Immediate with Shift Right Algebraic with Shift Right Extended Shift Right Extended Algebraic Shift Right Extended with Shift Right Immediate with Shift Right Long Immediate with Shift Right Long with Shift Right with Supervisor Call, with Primary Opcode Secondary Opcode PowerPC Microprocessor
Note: Many these instructions register. defined PowerPC architecture, implemented processor.
Appendix POWER Architecture Cross Reference
B.26 POWER Instructions Supported PowerPC Architecture
Table lists POWER instructions implemented PowerPC architecture.
Table B-4. POWER Instructions Implemented PowerPC Architecture
POWER Mnemonic amex andil. andiu. azex bccx bcrx caxx cntlzx dclz extsx fmax fmsx fnmax fnmsx lbrx Extended Immediate Immediate Record Minus Extended Immediate Lower Immediate Upper Zero Extended Branch Conditional Count Register Branch Conditional Link Register Compute Address Lower Compute Address Upper Compute Address Count Leading Zeros Data Cache Line Zero Data Cache Synchronize Extend Sign Floating Floating Divide Floating Multiply Floating Multiply-Add Floating Multiply-Subtract Floating Negative Multiply-Add Floating Negative Multiply-Subtract Floating Subtract Instruction Cache Synchronize Load Load Byte-Reverse Indexed Instruction Mnemonic addcx addex addic addic. addmex andi. andis. addzex bcctrx bclrx addi addis addx cntlzwx dcbz sync extshx faddx fdivx fmulx fmaddx fmsubx fnmaddx fnmsubx fsubx isync lwbrx Carrying Extended Immediate Carrying Immediate Carrying Record Minus Extended Immediate Immediate Shifted Zero Extended Branch Conditional Count Register Branch Conditional Link Register Immediate Immediate Shifted Count Leading Zeros Word Data Cache Block Zero Synchronize Extend Sign Half Word Floating-Point Floating-Point Divide Floating-Point Multiply Floating-Point Multiply-Add Floating-Point Multiply-Subtract Floating-Point Negative Multiply-Add Floating-Point Negative Multiply-Subtract Floating-Point Subtract Instruction Synchronize Load Word Zero Load Word Byte-Reverse Indexed PowerPC Instruction
B-10
PowerPC RISC Microprocessor User's Manual
Table B-4. POWER Instructions Implemented PowerPC Architecture (Continued)
POWER Mnemonic mtsri muli mulsx oril oriu rlimix rlinmx rlnmx sfex sfmex sfzex srax sraix stbrx stsi stsx Instruction Load Multiple Load String Immediate Load String Indexed Load with Update Load with Update Indexed Load Indexed Move Segment Register Indirect Multiply Immediate Multiply Short Immediate Lower Immediate Upper Rotate Left Immediate then Mask Insert Rotate Left Immediate then With Mask Rotate Left then with Mask Subtract from Subtract from Extended Subtract from Immediate Subtract from Minus Extended Subtract from Zero Extended Shift Left Shift Right Shift Right Algebraic Shift Right Algebraic Immediate Store Store Byte-Reverse Indexed Store Multiple Store String Immediate Store String Indexed Store with Update Mnemonic lswi lswx lwzu lwzux lwzx mtsrin mulli mullwx oris rlwimix rlwinmx rlwnmx subfcx subfex subfic subfmex subfzex slwx srwx srawx srawix stwbrx stmw stswi stswx stwu PowerPC Instruction Load Multiple Word Load String Word Immediate Load String Word Indexed Load Word Zero with Update Load Word Zero with Update Indexed Load Word Zero Indexed Move Segment Register Indirect Multiply Immediate Multiply Immediate Immediate Shifted Rotate Left Word Immediate then Mask Insert Rotate Left Word Immediate then with Mask Rotate Left Word then with Mask Subtract from Carrying Subtract from Extended Subtract from Immediate Carrying Subtract from Minus Extended Subtract from Zero Extended Shift Left Word Shift Right Word Shift Right Algebraic Word Shift Right Algebraic Word Immediate Store Word Store Word Byte-Reverse Indexed Store Multiple Word Store String Word Immediate Store String Word Indexed Store Word with Update
Appendix POWER Architecture Cross Reference
B-11
Table B-4. POWER Instructions Implemented PowerPC Architecture (Continued)
POWER Mnemonic stux svca tlbi xoril xoriu Instruction Store with Update Indexed Store Indexed Supervisor Call Trap Trap Immediate Invalidate Entry Immediate Lower Immediate Upper Mnemonic stwux stwx tlbie xori xoris PowerPC Instruction Store Word with Update Indexed Store Word Indexed System Call Trap Word Trap Word Immediate Translation Lookaside Buffer Invalidate Entry Immediate Immediate Shifted
Supervisor-level instruction
B-12
PowerPC RISC Microprocessor User's Manual
Appendix PowerPC Instructions Implemented
This appendix describes 32-bit 64-bit PowerPC instructions that implemented PowerPC microprocessor. also provides 32-bit 64-bit encodings that implemented 601. Table provides list 32-bit PowerPC instructions that optional PowerPC architecture implemented 601. Attempting execute these instructions causes illegal instruction exception.
Table C-1. 32-Bit Instructions Implemented PowerPC Microprocessor
Mnemonic fres frsqrte fsel fsqrt fsqrts mfspr mftb mtspr stfiwx tlbia tlbsync Instruction Floating-Point Reciprocal Estimate Single-Precision Floating-Point Reciprocal Square Root Estimate Floating-Point Select Floating-Point Square Root Floating-Point Square Root Single-Precision Move from Special Purpose Register Move from Time Base Move Special Purpose Register Store Floating-Point Integer Word Indexed Translation Lookaside Buffer Invalidate Translation Lookaside Buffer Synchronize
Some encodings supported 601. These encodings listed Table Table C-4.
Table provides list 32-bit encodings that implemented 601.
Appendix PowerPC Instructions Implemented
Table C-2. 32-Bit Encodings Implemented PowerPC Microprocessor
Decimal SPR[5-9] 01000 01000 10000 10000 10000 10000 10000 10000 10000 10000 SPR[0-4] 11100 11101 11000 11001 11010 11011 11100 11101 11110 11111 DBAT0U DBAT0L DBAT1U DBAT1L DBAT2U DBAT2L DBAT3U DBAT3L Register Name Access
Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor
Table provides list 64-bit instructions that implemented 601, that generate illegal instruction exception.
Table C-3. 64-Bit Instructions Implemented PowerPC Microprocessor
Mnemonic cntlzd divd divdu extsw fcfid fctid fctidz ldarx ldux lwaux Instruction Count Leading Zeros Double Word Divide Double Word Divide Double Word Unsigned Extend Sign Word Floating-Point Convert From Integer Double Word Floating-Point Convert Integer Double Word Floating-Point Convert Integer Double Word with Round toward Zero Load Double Word Load Double Word Reserve Indexed Load Double Word with Update Load Double Word with Update Indexed Load Double Word Indexed Load Word Algebraic Load Word Algebraic with Update Indexed
PowerPC RISC Microprocessor User's Manual
Table C-3. 64-Bit Instructions Implemented PowerPC Microprocessor (Continued)
Mnemonic lwax mulld mulhd mulhdu rldcl rldcr rldic rldicl rldicr rldimi slbia slbie srad sradi stdcx. stdu stdux stdx Instruction Load Word Algebraic Indexed Multiply Double Word Multiply High Double Word Multiply High Double Word Unsigned Rotate Left Double Word then Clear Left Rotate Left Double Word then Clear Right Rotate Left Double Word Immediate then Clear Rotate Left Double Word Immediate then Clear Left Rotate Left Double Word Immediate then Clear Right Rotate Left Double Word Immediate then Mask Insert Invalidate Invalidate Entry Shift Left Double Word Shift Right Algebraic Double Word Shift Right Algebraic Double Word Immediate Shift Right Double Word Store Double Word Store Double Word Conditional Indexed Store Double Word with Update Store Double Word Indexed with Update Store Double Word Indexed Trap Double Word Trap Double Word Immediate
Table provides 64-bit encoding that implemented 601.
Table C-4. 64-Bit Encoding Implemented PowerPC Microprocessor
Decimal SPR[5-9] 01000 SPR[0-4] 11000 Register Name Access
Supervisor
Appendix PowerPC Instructions Implemented
cntlzd
cntlzd cntlzd.
Implemented
rA,rS rA,rS (Rc=0) (Rc=1)
cntlzd
Integer Unit
Count Leading Zeros Double Word
Reserved
00000
while n<64 rS[n]=1 then leave nn+1
count number consecutive zero bits starting register placed into This number ranges from inclusive. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: (Rc=1)
divd
Divide Double Word
Implemented
rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE=0 Rc=0) (OE=0 Rc=1) (OE=1 Rc=0) (OE=1 Rc=1)
divd
Integer Unit
divd divd. divdo divdo.
dividend[0-63]rA divisor[0-63]rB rDdividend+divisor
PowerPC RISC Microprocessor User's Manual
64-bit dividend 64-bit divisor 64-bit quotient dividend divisor placed into remainder supplied result. Both dividend divisor interpreted signed integers. quotient unique signed integer that satisfies dividend=(quotientdivisor)+r where |divisor| dividend non-negative, -|divisor| dividend negative. attempt made perform divisions 0x8000_0000_0000_0000 <anything> then contents undefined. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Exception Register: Affected: OE=1) Rc=1)
divdu
divdu divdu. divduo divduo.
Implemented
rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE=0 Rc=0) (OE=0 Rc=1) (OE=1 Rc=0) (OE=1 Rc=1)
divdu
Integer Unit
Divide Double Word Unsigned
dividend[0-63]rA divisor[0-63]rB rDdividend+divisor
64-bit dividend 64-bit divisor 64-bit quotient dividend divisor placed into remainder supplied result.
Appendix PowerPC Instructions Implemented
Both dividend divisor interpreted unsigned integers. quotient unique unsigned integer that satisfies dividend=(quotientdivisor)+r where divisor. attempt made perform division <anything> then contents undefined. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Exception Register: Affected: OE=1) Rc=1)
extsw
Extend Sign Word
Implemented
rA,rS rA,rS (Rc=0) (Rc=1)
extsw
extsw extsw.
Reserved
00000
SrS[32] rA[32-63]rS[32-63] rA[0-31](32)S
Register rS[32-63] placed into rA[32-63]. placed into rA[0-31]. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
PowerPC RISC Microprocessor User's Manual
fcfid
fcfid fcfid.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fcfid
Floating-Point Unit
Floating-Point Convert from Integer Double Word
Reserved
00000
64-bit signed fixed-point operand register converted infinitely precise floating-point integer. result conversion already double-precision range placed into register frD. Otherwise result conversion rounded doubleprecision using rounding mode specified FPSCR[RN] placed into register frD. FPSCR[FPRF] class sign result. FPSCR[FR] result incremented when rounded. FPSCR[FI] result inexact. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR1 Field): Affected: Exception Register: Affected: FPRF, Rc=1)
fctid
fctid fctid.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fctid
Floating-Point Convert Integer Double Word
Reserved
00000
floating-point operand converted 64-bit signed fixed-point integer, using rounding mode specified FPSCR[RN], placed into frD. operand greater than 0x'7FFF_FFFF_FFFF_FFFF'. operand less than -263, then 0x'8000_0000_0000_0000'.
Appendix PowerPC Instructions Implemented
Except enabled invalid operation exceptions, FPSCR[FPRF] undefined. FPSCR[FR] result incremented when rounded. FPSCR[FI] result inexact. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR1 Field): Affected: Exception Register: Affected: FPRF (undefined), VXSNAN VXCVI Rc=1)
fctidz
fctidz fctidz.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fctidz
Floating-Point Convert Integer Double Word with Round toward Zero
Reserved
00000
floating-point operand converted 64-bit signed fixed-point integer, using rounding mode round toward zero, placed into frD. operand greater than 0x'7FFF_FFFF_FFFF_FFFF'. operand less than -263, then 0x'8000_0000_0000_0000'. Except enabled invalid operation exceptions, FPSCR[FPRF] undefined. FPSCR[FR] result incremented when rounded. FPSCR[FI] result inexact. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR1 Field): Affected: Exception Register: Affected: FPRF (undefined), VXSNAN VXCVI Rc=1)
PowerPC RISC Microprocessor User's Manual
fresx
fres fres.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fresx
Floating-Point Unit
Floating-Point Reciprocal Estimate Single-Precision
Reserved
00000 00000
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. single-precision estimate reciprocal floating-point operand register placed into register frD. estimate placed into register correct precision part reciprocal frB. Operation with various special values operand summarized below.
Operand SNaN QNaN Result QNaN** QNaN Exception None None VXSNAN None
result FPSCR[ZE]=1. result FPSCR[VE]=1.
FPSCR[FPRF] class sign result, except invalid operation exceptions when FPSCR[VE]=1 zero divide exceptions when FPSCR[ZE]=1. Other registers altered: Condition Register (CR1 Field): Affected: FEX, Rc=1) Floating-point Status Control Register: Affected: VXSNAN, FPRF, (undefined), (undefined)
Appendix PowerPC Instructions Implemented
frsqrte
frsqrte frsqrte.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
frsqrte
Floating-Point Unit
Floating-Point Reciprocal Square Root Estimate
Reserved
00000 00000
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. double-precision estimate reciprocal square root floating-point operand register placed into register frD. estimate placed into register correct precision part reciprocal square root frB. Operation with various special values operand summarized below.
Operand SNaN QNaN Result QNaN** QNaN** QNaN** QNaN Exception VXSQRT VXSQRT None VXSNAN None
result FPSCR[ZE]=1. result FPSCR[VE]=1.
FPSCR[FPRF] class result, except invalid operation exceptions when FPSCR[VE] zero divide exceptions when FPSCR[ZE] Other registers altered: Condition Register (CR1 Field): Affected: FEX, Rc=1) Floating-point Status Control Register: Affected: VXSNAN, FPRF, (undefined), (undefined)
C-10
PowerPC RISC Microprocessor User's Manual
fselx
Floating-Point Select
Implemented
frD,frA,frC,frB frD,frA,frC,frB (Rc=0) (Rc=1)
fselx
Floating-Point Unit
fsel fsel.
(frA) then else frD(frB)
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. floating-point operand register compared value zero. operand greater than equal zero, register contents register frC. operand less than zero NaN, register contents register frB. comparison ignores sign zero (i.e., regards equal -0). Other registers altered: Condition Register (CR1 Field): Affected: FEX, Rc=1)
Care must taken using fsel IEEE compatibility required, values being tested NaNs infinities.
fsqrtx
fsqrt fsqrt.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fsqrtx
Floating-Point Unit
Floating-Point Square Root
Reserved
00000 00000
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. square root floating-point operand register placed into register frD.
Appendix PowerPC Instructions Implemented
C-11
most significant resultant significand result normalized. result rounded target precision under control floating-point rounding control field FPSCR placed into register frD. Operation with various special values operand summarized below.
Operand SNaN QNaN Result QNaN* QNaN* QNaN* QNaN Exception VXSQRT VXSQRT None None VXSNAN None
result FPSCR[VE]=1.
FPSCR[FPRF] class sign result, except invalid operation exceptions when FPSCR[VE]=1. Other registers altered: Condition Register (CR1 Field): Affected: FEX, Rc=1) Floating-point Status Control Register: Affected: VXSQRT, VXSNAN, FPRF,
fsqrtx
fsqrts fsqrts.
Implemented
frD,frB frD,frB (Rc=0) (Rc=1)
fsqrtx
Floating-Point Unit
Floating-Point Square Root Single-Precision
Reserved
00000 00000
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. square root floating-point operand register placed into register frD. most significant resultant significand result normalized. result rounded target precision under control floating-point rounding control field FPSCR placed into register frD.
C-12
PowerPC RISC Microprocessor User's Manual
Operation with various special values operand summarized below.
Operand SNaN QNaN Result QNaN* QNaN* QNaN* QNaN Exception VXSQRT VXSQRT None None VXSNAN None
result FPSCR[VE]=1.
FPSCR[FPRF] class sign result, except invalid operation exceptions when FPSCR[VE]=1. Other registers altered: Condition Register (CR1 Field): Affected: FEX, Rc=1) Floating-point Status Control Register: Affected: VXSQRT, VXSNAN, FPRF,
Load Double Word
Implemented
rD,ds(rA)
Integer Unit
rA=0 then else EAb+EXTS(ds||0b00) rDMEM(EA,
(rA|0)+(ds||0b00). double word memory addressed loaded into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
Appendix PowerPC Instructions Implemented
C-13
ldarx
ldarx
Implemented
rD,rA,rB
ldarx
Integer Unit
Reserved
Load Double Word Reserve Indexed
rA=0 then else EAb+rB RESERVE1 RESERVE_ADDRfunc(EA) rDMEM(EA,
(rA|0)+(rB). double word memory addressed loaded into This instruction creates reservation store double word conditional instruction. address computed from associated with reservation, replaces address previously associated with reservation. must multiple not, system alignment error handler invoked results boundedly undefined. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
C-14
PowerPC RISC Microprocessor User's Manual
Implemented
rD,ds(rA)
Integer Unit
Load Double Word with Update
EArA+EXTS(ds||0b00) rDMEM(EA, rAEA
(rA)+(ds||0b00). double word memory addressed loaded into placed into rA=0 rA=rD, instruction form invalid. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
ldux
ldux
Implemented
rD,rA,rB
ldux
Integer Unit
Reserved
Load Double Word with Update Indexed
EArA+ rDMEM(EA, rAEA
(rA)+(rB). double word memory addressed loaded into placed into rA=0 rA=rD, instruction form invalid. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction invoked.
Appendix PowerPC Instructions Implemented
C-15
Implemented
rD,rA,rB
Reserved
Load Double Word Indexed
then else EAb+rB rDMEM(EA,
(rA|0)+(rB). double word memory addressed loaded into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
Load Word Algebraic
Implemented
rD,ds(rA)
Integer Unit
rA=0 then else EAb+EXTS(ds||0b00) rDEXTS(MEM(EA,
(rA|0)+(ds||0b00). word memory addressed loaded into rD[32-63]. Register rD[0-31] filled with copy loaded word. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
C-16 PowerPC RISC Microprocessor User's Manual
lwaux
lwaux
Implemented
rD,rA,rB
lwaux
Reserved
Load Word Algebraic with Update Indexed
EArA+rB rDEXTS(MEM(EA, rAEA
(rA)+(rB). word memory addressed loaded into rD[32-63]. Register rD[0-31] filled with copy loaded word. placed into rA=0 rA=rD, instruction form invalid. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
lwax
lwax
Implemented
rD,rA,rB
lwax
Reserved
Load Word Algebraic Indexed
rA=0 then else rDEXTS(MEM(EA,
(rA|0)+(rB). word memory addressed loaded into rD[32-63]. Register rD[0-31] filled with copy loaded word. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
Appendix PowerPC Instructions Implemented
C-17
mftb
Move from Time Base
Implemented
rD,TBR
mftb
Integer Unit
mftb
Reserved
nTBR[5-9] TBR[0-4] n=268 then (64-bit implementation) then rDTB else TB[32-63] else n=269 then (64-bit implementation) then rD(32)0 TB[0-31] else rDTB[0-31]
field denotes either time base time base upper, encoded shown Table C-5. contents designated register copied When reading Time Base Upper 64-bit implementation, high-order bits zero.
Table C-5. Encodings mftb
Decimal TBR* TBR[5-9] TBR[0-4] 01000 01000 01100 01101 Register Name Access User User
*Note that order 5-bit halves number reversed.
field contains value other than values shown Table C-5, instruction form invalid. Other registers altered: None
C-18
PowerPC RISC Microprocessor User's Manual
mulhd
mulhd mulhd.
Implemented
rD,rA,rB rD,rA,rB (Rc=0) (Rc=1)
mulhd
Integer Unit
Multiply High Double Word
prod[0-127]rArB rDprod[0-63]
64-bit multiplicands high-order bits 128-bit product multiplicands placed into Both multiplicands product interpreted signed integers. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
mulhdu
mulhdu mulhdu.
Implemented
rD,rA,rB rD,rA,rB (Rc=0) (Rc=1)
mulhdu
Integer Unit
Multiply High Double Word Unsigned
prod[0-127]rArB rDprod[0-63]
64-bit multiplicands high-order bits 128-bit product multiplicands placed into Both multiplicands product interpreted unsigned integers. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked.
Appendix PowerPC Instructions Implemented C-19
Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
mulld
mulld mulld. mulldo mulldo.
Implemented
rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE=0 Rc=0) (OE=0 Rc=1) (OE=1 Rc=0) (OE=1 Rc=1)
mulld
Integer Unit
Multiply Double Word
prod[0-127]rArB rDprod[64-127]
64-bit operands low-order bits 128-bit product operands placed into OE=1, then product cannot represented bits. Both operands product interpreted signed integers. However, result independent whether operands interpreted signed unsigned integers. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Exception Register: Affected: OE=1) Rc=1)
C-20
PowerPC RISC Microprocessor User's Manual
rldcl
rldcl rldcl.
Implemented
rA,rS,rB,MB rA,rS,rB,MB
rldcl
Integer Unit
Rotate Left Double Word then Clear Left
(Rc=0) (Rc=1)
nrB[58-63] rROTL[64](rS, bMB[5] MB[0-4] mMASK(b,
contents rotated[64] left number bits specified rB[58-63]. mask generated having 1-bits from through 0-bits elsewhere. rotated data ANDed with generated mask result placed into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
rldcr
rldcr rldcr.
Implemented
rA,rS,rB,ME rA,rS,rB,ME
rldcr
Integer Unit
Rotate Left Double Word then Clear Right
(Rc=0) (Rc=1)
nrB[58-63] rROTL[64](rS, eME[5] ME[0-4] mMASK(0,
Appendix PowerPC Instructions Implemented
C-21
contents rotated[64] left number bits specified rB[58-63]. mask generated having 1-bits from through 0-bits elsewhere. rotated data ANDed with generated mask result placed into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
rldic
rldic rldic.
Implemented
rA,rS,SH,MB rA,rS,SH,MB
rldic
Integer Unit
Rotate Left Double Word Immediate then Clear
(Rc=0) (Rc=1)
nSH[5] SH[0-4] rROTL[64](rS, bMB[5] MB[0-4] mMASK(b,
contents rotated[64] left bits. mask generated having 1-bits from through 63-SH 0-bits elsewhere. rotated data ANDed with generated mask result placed into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
C-22
PowerPC RISC Microprocessor User's Manual
rldicl
rldicl rldicl.
Implemented
rA,rS,SH,MB rA,rS,SH,MB
rldicl
Integer Unit
Rotate Left Double Word Immediate then Clear Left
(Rc=0) (Rc=1)
nSH[5] SH[0-4] rROTL[64](rS, bMB[5] MB[0-4] mMASK(b,
contents rotated[64] left bits. mask generated having 1-bits from through 0-bits elsewhere. rotated data ANDed with generated mask result placed into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
rldicr
rldicr rldicr.
Implemented
rA,rS,SH,ME rA,rS,SH,ME
rldicr
Integer Unit
Rotate Left Double Word Immediate then Clear Right
(Rc=0) (Rc=1)
nSH[5] SH[0-4] rROTL[64](rS, eME[5] ME[0-4] mMASK(0,
Appendix PowerPC Instructions Implemented
C-23
contents rotated[64] left bits. mask generated having 1-bits from 0-bits elsewhere. rotated data ANDed with generated mask result placed into This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
rldimi
rldimi rldimi.
Implemented
rA,rS,SH,MB rA,rS,SH,MB
rldimi
Integer Unit
Rotate Left Double Word Immediate then Clear Left
(Rc=0) (Rc=1)
nSH[5] SH[0-4] rROTL[64](rS, bMB[5] MB[0-4] mMASK(b, rA(r
contents rotated[64] left bits. mask generated having 1-bits from through 63-SH 0-bits elsewhere. rotated data inserted into under control generated mask. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
C-24
PowerPC RISC Microprocessor User's Manual
slbia
Invalidate
Implemented
slbia
Reserved
00000
00000
00000
entriesinvalid
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. invalidated regardless settings MSR[IT] MSR[DT]. This instruction supervisor-level. This instruction optional PowerPC architecture. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause illegal instruction type program exception. necessary that point valid segment table when issuing slbia. Other registers altered: None
slbie
Invalidate Entry
Implemented
slbie
slbie
Reserved
00000 00000
EA(rB) entry exists then entryinvalid
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes.
Appendix PowerPC Instructions Implemented
C-25
contents segment lookaside buffer (SLB) contains entry corresponding that entry made invalid (i.e., removed from SLB). search done regardless settings MSR[IT] MSR[DT]. Block address translation any, ignored. This instruction supervisor-level. This instruction optional PowerPC architecture. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause illegal instruction type program exception. Other registers altered: None necessary that point valid segment table when issuing slbie.
Shift Left Double Word
Implemented
rA,rS,rB rA,rS,rB (Rc=0) (Rc=1)
Integer Unit
sld.
nrB[58-63] rROTL[64](rS, rB[57]=0 then mMASK(0, 63-n) else m(64)0
contents shifted left number bits specified rB[57-63]. Bits shifted position lost. Zeros supplied vacated positions right. result placed into Shift amounts from give zero result. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
C-26
PowerPC RISC Microprocessor User's Manual
srad
srad srad.
Implemented
rA,rS,rB rA,rS,rB (Rc=0) (Rc=1)
srad
Integer Unit
Shift Right Algebraic Double Word
nrB[58-63] rROTL[64](rS, 64-n) rB[57]=0 then mMASK(n, else m(64)0 SrS[0] rA(r (((64)S) ((r& m)0)
contents shifted right number bits specified rB[57-63]. Bits shifted position lost. replicated fill vacated positions left. result placed into negative 1-bits shifted position otherwise shift amount zero causes equal Shift amounts from give result sign bits cause receive sign This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked.
Appendix PowerPC Instructions Implemented
C-27
Other registers altered: Condition Register (CR0 Field): Affected: Exception Register: Affected: Rc=1)
sradi
sradi sradi.
Implemented
rA,rS,SH rA,rS,SH (Rc=0) (Rc=1)
sradi
Integer Unit
Shift Right Algebraic Double Word Immediate
nSH[5] SH[0-4] rROTL[64](rS, 64-n) mMASK(n, SrS[0] rA(r (((64)S) ((r& m)0)
contents shifted right bits. Bits shifted position lost. replicated fill vacated positions left. result placed into negative 1-bits shifted position otherwise shift amount zero causes equal This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Exception Register: Affected: Rc=1)
C-28
PowerPC RISC Microprocessor User's Manual
Shift Right Double Word
Implemented
rA,rS,rB rA,rS,rB (Rc=0) (Rc=1)
Integer Unit
srd.
nrB[58-63] rROTL[64](rS, 64-n) rB[57]=0 then mMASK(n, else m(64)0
contents shifted right number bits specified rB[57-63]. Bits shifted position lost. Zeros supplied vacated positions left. result placed into Shift amounts from give zero result. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected: Rc=1)
Store Double Word
Implemented
rS,ds(rA)
Integer Unit
rA=0 then else EXTS(ds||0b00) (MEM(EA, 8))rS
(rA|0)+(ds||0b00). Register stored into double word memory addressed
Appendix PowerPC Instructions Implemented
C-29
This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
stdcx.
stdcx.
Implemented
rS,rA,rB
stdcx.
Integer Unit
Store Double Word Conditional Indexed
rA=0 then else RESERVE then (MEM(EA, 8))rS RESERVE0 CR00b00 XER[SO] else CR00b00 XER[SO]
(rA|0)+(rB). reservation exists, stored into double word memory addressed reservation cleared. reservation does exist, instruction completes without altering memory. Field reflect whether store operation performed (i.e., whether reservation existed when stdcx. instruction commenced execution), follows: CR0[LT 0b00 store_performed XER[SO] must multiple not, system alignment error handler invoked results boundedly undefined. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: Condition Register (CR0 Field): Affected:
C-30
PowerPC RISC Microprocessor User's Manual
stdu
stdu
Implemented
rS,ds(rA)
stdu
Integer Unit
Store Double Word with Update
EArA+EXTS(ds||0b00) (MEM(EA, 8))rS rAEA
(rA)+(ds||0b00). Register stored into double word memory addressed placed into rA=0, instruction form invalid. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
stdux
stdux
Implemented
rS,rA,rB
stdux
Integer Unit
Reserved
Store Double Word with Update Indexed
EArA MEM(EA, 8)rS rAEA
(rA)+(rB). Register stored into double word memory addressed placed into rA=0, instruction form invalid.
Appendix PowerPC Instructions Implemented
C-31
This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
stdx
stdx
Implemented
rS,rA,rB
stdx
Integer Unit
Reserved
Store Double Word Indexed
rA=0 then else EAb+rB (MEM(EA, 8))rS
(rA|0)+(rB). Register stored into double word memory addressed This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
stfiwx
stfiwx
Implemented
frS,rA,rB
stfiwx
Floating-Point Unit
Store Floating-Point Integer Word
Reserved
then else EAb+rB MEM(EA, 4)frS[32-63]
C-32
PowerPC RISC Microprocessor User's Manual
(rA|0)+(rB). contents low-order bits register stored, without conversion, into word memory addressed Other registers altered: None
Trap Double Word
Implemented
TO,rA,rB
Integer Unit
Reserved
TO[0] then TRAP TO[1] then TRAP TO[2] then TRAP TO[3] then TRAP TO[4] then TRAP
contents compared with contents field corresponding condition result comparison, then system trap handler invoked. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
Appendix PowerPC Instructions Implemented
C-33
Implemented
TO,rA,SIMM
SIMM
Integer Unit
Trap Double Word Immediate
EXTS(SIMM)) TO[0] then TRAP EXTS(SIMM)) TO[1] then TRAP EXTS(SIMM)) TO[2] then TRAP EXTS(SIMM)) TO[3] then TRAP EXTS(SIMM)) TO[4] then TRAP
contents compared with sign-extended SIMM field. field corresponding condition result comparison, then system trap handler invoked. This instruction defined only 64-bit implementations. Using 32-bit implementation will cause system illegal instruction error handler invoked. Other registers altered: None
tlbia
Implemented
tlbia
Integer Unit
Reserved
Translation Lookaside Buffer Invalidate
00000
00000
00000
entries invalid
This PowerPC instruction implemented 601. Execution this instruction will invoke illegal instruction handler. description operation this instruction provided emulation purposes. entire invalidated (that entries removed). invalidated regardless settings MSR[IT] MSR[DT]. This supervisor-level instruction. This instruction optional PowerPC architecture.
C-34 PowerPC RISC Microprocessor User's Manual
Other registers altered: None necessary that point valid segment table when issuing tlbia.
tlbsync
Synchronize
Implemented
tlbsync
Reserved
00000
00000
00000
tlbsync instruction waits until previous tlbie, tlbiex, tlbia instructions executed processor executing this instruction have been received completed other processors. This instruction supervisor-level. This instruction optional PowerPC architecture, must implemented following true: invalidation instruction that broadcasts implemented. eciwx ecowx instructions implemented.
Other registers altered: None
Appendix PowerPC Instructions Implemented
C-35
C-36
PowerPC RISC Microprocessor User's Manual
Appendix Classes Instructions
This appendix describes classes PowerPC instructions defined. three classifications follows: Defined Illegal Reserved
Note that while definitions these terms consistent among PowerPC processors, assignment these classifications not. example, instruction that specific 64-bit implementations considered defined 64-bit implementations, illegal 32-bit implementations such PowerPC microprocessor.
Classes Instructions
32-bit implementation PowerPC architecture with differences redefinitions noted throughout this document. Differences stem largely from different address sizes compliance with POWER architecture. instructions belong following three classes: Defined Illegal Reserved
class determined examining opcode extended opcode, any. opcode, combination opcode extended opcode, that defined instruction reserved instruction, instruction illegal. future versions PowerPC architecture, instructions that illegal become defined being added architecture) reserved being assigned special purposes). Likewise, reserved instructions become defined.
D.1.1 Defined Instruction Class
Defined instructions guaranteed supported PowerPC implementations, except stated instruction descriptions Chapter "Instruction Set."
Appendix Classes Instructions
provides hardware support most instructions defined 32-bit implementations; does provide direct hardware support instructions listed Appendix "PowerPC Instructions Implemented." invokes system illegal instruction error handler (part program exception) when unimplemented PowerPC instructions encountered they emulated software, required. defined instruction have invalid forms, described Section D.1.1.1, "Invalid Instruction Forms."
D.1.1.1 Invalid Instruction Forms
instruction form invalid more operands, excluding opcodes, coded incorrectly. Attempting execute invalid form instruction either invokes system illegal instruction error handler program exception) yields undefined results. Chapter "Instruction Set," individual instruction descriptions. Invalid forms result when operand coded incorrectly, example, when reserved shown coded "1". following instructions have invalid forms identified their individual instruction descriptions: Branch conditional instructions Load/store with update instructions Load multiple instructions Load string instructions Move to/from special purpose register (mtspr, mfspr) Load/store floating-point with update instructions
some cases, invalid form PowerPC instruction invalid form corresponding POWER instruction. result, maintain compatibility with POWER applications, often handles PowerPC invalid forms described POWER architecture. other cases, handles invalid form manner that most convenient that particular case. Each PowerPC invalid forms addressed this document, description handles each case provided.
D.1.2 Illegal Instruction Class
Illegal instructions grouped into following categories: Instructions that implemented PowerPC architecture. These opcodes available future extensions PowerPC architecture; that future versions PowerPC architecture define these instructions perform functions. following primary opcodes illegal:
PowerPC RISC Microprocessor User's Manual
Instructions that implemented PowerPC architecture implemented specific PowerPC implementation (for example, instructions that executed 64-bit PowerPC processors considered illegal 32-bit processors. following opcodes defined 64-bit implementations only illegal 601:
following primary opcodes have unused extended opcodes. Their unused extended opcodes determined from information Section A.2, "Complete Instruction List Sorted Opcode," Section D.1.3, "Reserved Instructions." Notice that extended opcodes instructions that defined only 64-bit implementations illegal 32-bit implementations. unused extended opcodes illegal. (opcodes illegal 32-bit implementations, 64-bit opcodes they have some unused extended opcodes).
attempt execute illegal instruction invokes illegal instruction error handler program exception) other effect. Section 5.4.7, "Program Exception (x'00700')," additional information about illegal invalid instruction exceptions. Note that instruction consisting entirely binary zeros guaranteed illegal instruction. This increases probability that attempt execute data uninitialized memory invokes system illegal instruction error handler program exception). Note that only primary opcode consists zeros, instruction considered reserved instruction, described Section D.1.3, "Reserved Instructions." With exception instruction consisting entirely binary zeros, illegal instructions available further additions PowerPC architecture.
D.1.3 Reserved Instructions
Reserved instructions allocated specific purposes outside scope PowerPC architecture. attempt execute reserved instruction either causes program exception yields undefined results. attempt execute reserved instruction invokes illegal instruction error handler program exception); however, executes many POWER architecture instructions that otherwise part PowerPC architecture. Section 5.4.7, "Program Exception (x'00700')," additional information about illegal invalid instruction exceptions. instructions this class allocated specific purposes that outside scope PowerPC user instruction architecture, PowerPC virtual environment architecture, PowerPC operating environment architecture.
Appendix Classes Instructions
following types instructions included this class: Instructions POWER architecture that have been included PowerPC user instruction architecture Implementation-specific instructions used conform PowerPC architecture specifications instruction with primary opcode when instruction does consist entirely binary zeros other implementation-specific instructions that defined PowerPC user instruction architecture, PowerPC virtual environment architecture, PowerPC operating environment architecture
PowerPC RISC Microprocessor User's Manual
Appendix Multiple-Precision Shifts
This appendix gives examples multiple precision shifts
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