MC92604 Dual Design Verification Board User's Guide Device Suppor

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

MC92604 Dual Design Verification Board User's Guide Device Suppor

Datasheet Thumbnail

Top Searches for this datasheet

MC92604DVBUG 3/2004 Rev.
MC92604 Dual Design Verification Board User's Guide
Device Supported: MC92604
More Information This Product, www.freescale.com
Contents
Paragraph Section Number Title Chapter General Information
Contents
Page Number
Introduction. Design Verification Board Features Specifications. Abbreviation List Related Documentation. Block Diagram Board Components Contact Information Chapter Hardware Preparation Installation
2.3.1 2.3.2 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5.1 2.5.1.1 2.5.1.2 2.5.2 2.5.3
Unpacking Instructions MC92604DVB Package Contents Hardware Preparation Setting Power Supply Voltage Regulators Setting Voltage Regulators. Reference Clock Source. Using Onboard Oscillators. External Reference Clock Source Supplying Clock MC92604 3.3V_CLK_OUTn Connectors Clock Frequency Selection Interface Components Parallel Inputs Outputs. Parallel Inputs Parallel Outputs +VDDQ Ground (GND) Access Connections. Serial Inputs Outputs. Special Application Connections. Special Test Connection. Test Traces
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Contents
Paragraph Number Title Chapter Laboratory Equipment Quick Setup Evaluation 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.2 3.2.2.1 3.2.2.2 3.2.2.3 Recommended Laboratory Equipment Quick Setup Data-Eye Diagram Quick Setup Data-Eye Generation Observation Equipment Setup. Parallel Input Connections. Basic Observation-Test Procedure. Quick Setup Error Rate Checking. Equipment Setup. Parallel Connections. Quick Setup BERC Test Procedure Chapter Test Setups 4.1.1 4.1.2 4.2.1 4.2.2 4.2.3 4.2.4 Serial Link Verification Using Serial Error Rate Tester (BERT) Test Setup Full-Speed Mode Test Setup Half-Speed Modes Jitter Testing. Jitter Test System Calibration Reference Clock Jitter Transfer Test. Reference Clock Jitter Tolerance Test Data Jitter Tolerance Test. Appendix Connector Signals A.1.1 A.1.2 Input: (0.100") Connectors. Control Signal Input Connectors Transmitter Parallel Data Input Connectors Output: (0.100") Connectors JTAG Connector MDIO Connector SFP_CTRL Connector Page Number
MOTOROLA
Contents
More Information This Product, www.freescale.com
Contents
Paragraph Number Title Appendix Parts List Design Verification Board Parts List .B-1 Appendix Prescaler Jitter Measurement Page Number
Divide-by-xx Prescaler Description .C-1 Prescaler Components.C-2 Appendix Revision History
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Chapter General Information
Introduction
This user's guide describes MC92604DVB design verification board MC92604 integrated circuit. design verification board (DVB) facilitates full evaluation MC92604 Dual Gigabit Ethernet transceiver (GEt). should read conjunction with MC92604 Dual Gigabit Ethernet Transceiver Reference Manual. This design verification board intended evaluation testing purposes only. Motorola does guarantee performance production environment. This board designed used with laboratory equipment (pattern generators, data analyzers, BERT, scopes, etc.) connected other evaluation boards. Access MC92604 device (verification chip) through connectors each pin, allow complete in-depth `design verification' testing chip design. This allows user check features/functions MC92604 device. parallel data input ports configuration/control signal pins, accessed through common 0.100" male connectors (headers). parallel data output ports accessed through 0.100" connectors. Device JTAG MDIO port signals also accessed with separate connectors. MC92604 high-speed serial receivers transmitters accessed coaxial connectors signal integrity measurements. Gigabit Ethernet fiber media evaluations made with provided small form-factor pluggable (SFP) socket DVB, (multi-source agreement) compliant transceiver. this socket, four short coax cables required connect socket device's transmitter receiver connectors. single 5.0-V power source required operation. necessary voltages generated regulators onboard. reference clock MC92604 chip provided using either external clock onboard crystal oscillator. Clock drivers provide additional clock signals triggering analyzer instrumentation scopes.
MOTOROLA
Chapter General Information
More Information This Product, www.freescale.com
Design Verification Board Features
Design Verification Board Features
single external 5.0-V onboard regulators supply power onboard circuitry. Reference clock source 250-MHz crystal oscillator external clock source. IEEE 802.3-2002® compliant GMII interfaces accessible through standard 0.100", connectors data generators analyzers. full-duplex differential data links accessible through connectors. pairs test traces with connections facilitate measurements characteristic impedance representative board traces. Connectors provided JTAG MDIO ports socket provided MSA-compliant fiber modules IEEE 1394b (bilingual) socket provided standard cable links
functional, physical, performance features MC92604DVB follows:
Specifications
Table 1-1. MC92604DVB Design Verification Board Specifications
Characteristics Specifications typical 0.15 MAPBGA 0°-30°C FR-4 Height Width Thickness 11.2", 9.35", 0.062", Four ground planes, split power plane, three signal routing layers, bottom component layers with some additional signal routing.
MC92604DVB design verification board specifications provided Table 1-1.
Board revision External power supply Support circuit regulator MC92604 core link regulator Interface (VDDQ) regulator MC92604 package Operating temperature Material Dimensions
Conducting layers
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Abbreviation List
Abbreviation List
Table 1-2. Acronyms Abbreviated Terms
Term BIST Meaning High logic level (nominally logic level (nominally Built-in self-test Design verification board Interface Management data input/output port Multi-source agreement connection Pseudo-noise Pseudo random sequence Small form-factor pluggable (fiber optics module) Test access port Time delay reflectometry Peak-to-peak unit interval
Table contains abbreviations used this document.
MDIO PRBS UIp-p
Related Documentation
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual (MC92604RM) MC92604DVB schematics MC100ES6222 data sheet MPC9456 data sheet IEEE 802.3-2002, Part Carrier sense multiple access with collision detection (CSMA/CD) access method physical layer specifications
Related documentation includes following:
MOTOROLA
Chapter General Information
More Information This Product, www.freescale.com
Block Diagram
Block Diagram
3.3V_CLK_OUT1 CLK_IN +VDDQ/GND PG14 0.100" Connector X-TAL X-TAL MC100 ES6222 TST1 TST2 DIFF_CLK_OUT5 DIFF_CLK_OUT6 +3.3 R22V1 TST5 TST6 +VDDQ RECV_B Status LEDs RECV_A Status LEDs REF_CLK +2.5- 3.5-V Regulator +3.3-V Regulator 3.3V_CLK_OUT2 3.3V_CLK_OUT3 3.3V_CLK_OUT4 MPC9456 R12V
T3,4
Vertical Test Traces
R22V +1.8-V Regulator +1.8
0.100" Connectors
RECV_A RECV_B MC92604
RLINK_A XLINK_A RLINK_B XLINK_B 1394b
0.100" Connectors PG10 PG11 CLK_A_PG CLK_B_PG
XMIT_A A_XCLK XMIT_B B_XCLK Control JTAG MDIO
PG12 PG13 0.100" Connector
TST3 TST4
Horizontal Test Traces
TST7 TST8
0.100" Connectors
Figure 1-1. MC92604DVB Design Verification Board Block Diagram
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Board Components
Board Components
Table list major components MC92604DVB design verification board. complete parts listing found Appendix "Parts List."
Table 1-3. Major Board Components
Component MC92604ZT 0.100" connectors 0.100" connectors Description Motorola dual gigabit ethernet transceiver SERDES PG1-PG4, PG8-PG11, PG13 provide access parallel inputs control signals. LA1-LA2 provide access parallel outputs. PG12 PG14 provide access connector +VDD/ground planes, respectively. SMA1-SMA8: Serial transmit receive connections TST1-TST8: Impedance test trace connections CLK_OUT1-CLK_OUT6: Reference clock outputs CLK_IN: External reference clock input CLK_A_PG, CLK_B_PG: Input clock connectors Provide connections optical modules Provide serial interface `Firewire' type cable VR33, VR18, VR1: +3.3 +1.8 +VDD voltage regulators R12V, R22V, R22V1: Potentiometers setting +3.3 +1.8 +VDD voltage levels Onboard 250-MHz crystal oscillator Divide-by-1 divide-by-2 clock buffer +3.3-V LVCMOS clock buffer
0.100" connectors connectors
connector IEEE 1394b bilingual connector LT1587 voltage regulators Potentiometers XTAL oscillator MC100ES6222 clock buffer MPC9456 clock buffer
Contact Information
questions concerning MC92604 design verification place order kit, contact your local Motorola field applications engineer.
MOTOROLA
Chapter General Information
More Information This Product, www.freescale.com
Chapter Hardware Preparation Installation
This chapter provides unpacking, hardware preparation, configuration-installation instructions, description interface components MC92604DVB.
Unpacking Instructions
Unpack board from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
MC92604DVB Package Contents
Table 2-1. MC92604DVB Contents
Qty. Item MC92604DVB design verification board MC92604DVBUG Dual Design Verification Board User's Guide MC92604 Dual Gigabit Ethernet Transceiver Reference Manual Complete MC92604DVB design verification board schematics 0.100" shunts Square receptacle patch cords
Table describes contents MC92604DVB kit.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Hardware Preparation
Hardware Preparation
Operation MC92604DVB requires proper setup power supply voltage regulators well reference clock. Figure depicts location major components board. following sections describe proper setup MC92604DVB.
+3.3-V Power Connection Clock Buffers Buffered Clock Outputs External Clock Inputs Switch VDDQ Power Connection Diff Clock Buffered Outputs Crystal Oscillator
+5-V Power Connectors
+1.8-V Power Connectors
Voltage Regulators
Connectors Connector Vertical Test Traces Connectors Serial Differential Connectors
MC92604
Receiver Status LEDs
Connector Connectors
Module Socket
1394 Socket
Connectors Module
Horizontal Test Traces
Connectors 1394 Socket
Figure 2-1. Side Part Location Diagram
MOTOROLA
Chapter Hardware Preparation Installation
More Information This Product, www.freescale.com
Hardware Preparation
2.3.1
Setting Power Supply Voltage Regulators
MC92604DVB requires single +5.0-V supply. Fully operational, board will draw maximum current less than amps from +5.0-V supply. Actual current consumption depends user voltage levels, clock frequencies, module, MC92604 operating mode. board contains +5.0-V connection posts ground connection posts. These duplicate connections simplify using four-wire supply: supply ground, force sense.
2.3.2
Setting Voltage Regulators
+5.0-V supply used power on-board voltage regulators, VR33, VR18, VR1. These regulators generate +3.3, +1.8, +2.5/3.3 (VDDQ), respectively. +3.3-V supply provides power oscillator, clock buffer chips, drivers, power source socket. This supply varied over range +3.3 using R12V potentiometer. +1.8-V supply used power MC92604 core logic, transceivers, on-chip phase-locked loop (PLL). This regulator adjusted over range +1.8 0.15 using R22V. VDDQ supply powers MC92604 control signal, parallel input, output interface circuitry. This voltage level determined desired logic interface. supply adjusted using R22V1 potentiometer from nominal +2.5 +3.3 +3.3-V, +1.8-V, +VDDQ supplies accessible connection posts. Note that these regulators should voltage limits within operating ranges described MC92604 Dual Gigabit Ethernet Transceiver Reference Manual. Failure operate within these ranges could cause damage MC92604. Motorola will guarantee MC92604 operation beyond ranges specified. R12V, R22V, R22V1 potentiometers will factory +3.3, +1.8, +3.3 respectively.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Reference Clock Source
Reference Clock Source
Through combination clock buffers, reference clock supplied MC92604 several output connectors. input reference clock MC92604 supplied using either onboard crystal oscillator, directly driving external reference clock into board's clock buffer circuit connector, CLK_IN. When selecting reference oscillators external reference frequencies, only those frequencies listed MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, considered valid. Motorola does guarantee operation MC92604 frequencies other than those listed reference manual. switch settings select either onboard oscillator external reference, well enable clock buffer chips.
clock circuitry MC92604DVB shown Figure 2-2.
250-MHz Oscillator CLK_IN CLK_0 CLK_1 CSEL MPC9456 3.3V_CLK_OUT3 3.3V_CLK_OUT4 TTL_REF_CLK 3.3V_CLK_OUT1 3.3V_CLK_OUT2 MC100ES6222 REF_CLK_P REF_CLK_N
DIFF_CLK_OUT5 DIFF_CLK_OUT6
Figure 2-2. Clock Circuitry
2.4.1
Using Onboard Oscillators
There available positions using onboard oscillators. standard 14-pin socket available board allow user easily change frequencies swapping crystal oscillators with other values. onboard oscillators must times desired MC92604 reference clock frequency. default reference clock frequency oscillator supplied with board MHz.
MOTOROLA
Chapter Hardware Preparation Installation
More Information This Product, www.freescale.com
Reference Clock Source
Crystal oscillators used with this board should have +3.3-V complementary PECL outputs capable driving line terminated with Oscillators conforming these specifications available surface mount packages soldered onto underside MC92604DVB location This oscillator, then enabled placing switch `on' position. Both types crystal oscillators available from external vendors variety frequencies. shipped with either oscillator installed. When using oscillator, oscillator must removed from socket. Once either type oscillator installed, switch must placed `on' position select onboard oscillator.
2.4.2
External Reference Clock Source
input reference clock also supplied using external reference clock into clock buffer circuit board CLK_IN connector. supply external reference clock, switch number must `off' position. user must then supply 1.0-Vp-p input clock connector. CLK_IN input coupled board and, therefore, does require biasing input signal. This external clock input also terminated with impedance.
2.4.3
Supplying Clock MC92604
input reference clock, from either onboard oscillator external source, applied MC100ES6222 clock buffer. This buffer input clock select multiplexer, programmable divide-by-one/divide-by-two function. buffer also contains master reset (Enable). recommended that this reset, found switch activated, then deactivated after changing divide-by-xx switch. This will ensure proper frequency generation. MC100ES6222 PECL outputs provide differential reference clock MC92604 (REF_CLK_P REF_CLK_N) also MC9456 fanout buffer. When using default 250-MHz clock, switch position must `off' divide-by-2 provide MC92604. differential output pair, DIFF_CLK_OUT5 DIFF_CLK_OUT6, also provided with external equipment.
2.4.4
3.3V_CLK_OUTn Connectors
Four single-ended, 3.3-V level, clock signals available connectors drive other instruments. Between MC100ES6222 output SMAs, MPC9456 which performs differential PECL single-ended +3.3-V LVTTL/CMOS level shift. These CMOS outputs series terminated board, then connect connectors labeled 3.3V_CLK_OUT1, 3.3V_CLK_OUT2, 3.3V_CLK_OUT3, 3.3V_CLK_OUT4. outputs MPC9456 disabled setting switch SW1, switch `off.'
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Reference Clock Source
2.4.5
Clock Frequency Selection
accommodate fact that MC92604 receive data both edges reference clock (DDR), many pieces test equipment single-edge triggered (SDR), MC92604DVB clock outputs programmed either same supplied frequency half supplied frequency setting SW1, switches either `on' (divide-by-one) `off' (divide-by-2). This allows interface between board bench either with double speed clock, double data rate (DDR) with single speed clock. outputs 3.3V_CLK_OUT1 3.3V_CLK_OUT2 programmed setting SW1, switch 3.3V_CLK_OUT3 3.3V_CLK_OUT4 outputs programmed setting SW1, switch Table lists switch positions output frequencies. input frequency, CLK_IN refers either onboard oscillator frequency externally applied clock source frequency. NOTE Only those frequencies listed MC92604 Dual Gigabit Ethernet Transceiver Reference Manual considered valid. Motorola does guarantee operation MC92604 frequencies other than those listed reference manual.
Table 2-2. Settings Output Frequencies
Switch Switch Position REF_CLK_P, REF_CLK_N, DIFF_CLK_OUT5, DIFF_CLK_OUT6 CLK_IN CLK_IN/2 3.3V_CLK_OUT1, 3.3V_CLK_OUT2 CLK_IN CLK_IN/2 3.3V_CLK_OUT3, 3.3V_CLK_OUT4 CLK_IN CLK_IN/2
Table depicts settings using onboard oscillator with divide-by-two function MC92604 3.3V_CLK_OUTn outputs. 3.3V_CLK_OUT1 3.3V_CLK_OUT2 outputs enabled divide-by-one function. 3.3V_CLK_OUT3 3.3V_CLK_OUT4 outputs also enabled divide-by-two function.
MOTOROLA
Chapter Hardware Preparation Installation
More Information This Product, www.freescale.com
Interface Components
Enabled Clk_In Clk_In Enabled Clk_In Onboard Reset MPC9456 Output ENABLE_B
Clk_In/2 3.3V_CLK_OUT3, _OUT4 Frequency Select Clk_In/2 3.3V_CLK_OUT1, _OUT2 Frequency Select Reset MC100ES6222 Reset
Clk_In/2 MC92604 REF_CLK, Frequency select External Onboard/External CLK_IN Select Alternate Oscillator ENABLE
Figure 2-3. Reference Clock Selection Example Switch Settings
Interface Components
following sections list descriptions MC92604DVB interface connector components.
2.5.1
Parallel Inputs Outputs
MC92604 parallel supplied VDDQ voltage regulator (set rail-to-rail signal swing. MC92604DVB shipped with VDDQ
2.5.1.1
Parallel Inputs
parallel inputs, both data control, accessible 0.100" connectors. Figure depicts 0.100" connector numbering scheme, with being labeled board. complete mapping MC92604 inputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-4. 0.100" Input Connector Numbering Scheme (Top View)
description input functionality MC92604, refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
2.5.1.2 Parallel Outputs
Special Application Connections
parallel outputs, both data status bits, present 0.100" connectors. Figure depicts 0.100" output connector numbering scheme, with labeled board. parallel output signals MC92604 2.5- 3.3-V logic compatible depending setting VDDQ regulator. complete mapping MC92604 outputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-5. 0.100" Output Connector Number Scheme (Top View)
information regarding MC92604 outputs, refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual.
2.5.2
+VDDQ Ground (GND) Access Connections
MC92604DVB also 0.100" connector, PG14, with dedicated connections +VDDQ ground planes. These useful biasing parallel input signals using jumper cables. number pins connected VDDQ plane. even number pins connected ground (0.0 plane.
2.5.3
Serial Inputs Outputs
MC92604 high-speed serial differential inputs outputs connected appropriately labeled pairs connectors through board traces with characteristic impedance (100- differential). output driver requires parallel termination mid-rail (+0.9 nominal +1.8-V supply). termination voltage +0.9 signal must coupled. There coupling blocking) serial outputs board. needed, coupling must done in-line before termination. During testing, serial transmitter outputs should terminated with This done connecting serial transmitter outputs serial receiver inputs, laboratory equipment with input impedance through in-line coupling, terminating outputs with terminations.
Special Application Connections
There sets special connectors provided application interface evaluation. Gigabit Ethernet socket provided with connections connect
MOTOROLA
Chapter Hardware Preparation Installation
More Information This Product, www.freescale.com
Special Test Connection
MC92604DVB serial links then perform evaluation testing with fiber optic interface. user must supply module. provided with MC92604DVB. socket it's control interface connector, SFP_CTRL. mapping this 0.100" connector listed Appendix "Connector Signals." Likewise, IEEE 1394B socket (bilingual version) provided with connections connect MC92604 serial links perform testing with standard patch cords. (Note that there slight impedance mismatch, 1394 cables 110- differential.)
Special Test Connection
MC92604DVB also contains oscilloscope test socket, labeled TPA. When MC92604 configured factory test mode, this test socket enables special access PLL. NOTE This test mode factory testing purposes only. There system applications this mode test socket should remain unconnected times.
Test Traces
MCS92610DVB design verification board both vertical horizontal test traces: Vertical: TST1-TST5 TST2-TST6 11.82 inches long. Horizontal: TST3-TST7 TST4-TST8 9.86 inches long.
These traces used determine impedance board using measurement techniques. NOTE These test traces cannot used differential pairs. When doing measurements, observe difference propagation delays. This trace being surface (top bottom) layer other being embedded signal layer. verticle pair, TST1-TST5 trace bottom surface layer (10) TST2-TST6 embedded signal layer (6). horizontal test traces have TST3-TST7 located embedded signal layer TST4-TST8 surface layer (1).
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Chapter Laboratory Equipment Quick Setup Evaluation
This chapter begins with listing recommended test equipment needed perform complete evaluations MC92604. Chapter "Test Setups," will cover specific setup configurations this equipment depending desired feature under test. Appendix "Parts List," offers various suggested data test patterns that used with these test setups. quick setup evaluation procedures outlined below describe MC92604DVB used evaluate data `eye diagram' simple error rate test using internal test features MC92604 with minimal amount test equipment. Only power supply sampling oscilloscope required. Details testing specific systems left user. more information regarding MC92604 feature set, refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual.
Recommended Laboratory Equipment
Evaluation MC92604 feature possible using MC92604DVB evaluation conjunction with several pieces test equipment. quick setup evaluations other tests listed this guide utilize basic test equipment listed Table 3-1. Equivalent instrumentation substituted. pieces test equipment necessary tests.
Table 3-1. Recommended Test Equipment
Quantity Equipment MC92604DVB evaluation Tektronix 8000 digital sampling oscilloscope Tektronix 80E04 TDR/sampling head GHz) Tektronix 80E03 sampling heads GHz) Hewlett-Packard HP16700 logic analysis system Hewlett-Packard HP16522A pattern generators Hewlett-Packard HP16557D logic analyzers Hewlett-Packard HP6624A system power supply
MOTOROLA
Chapter Laboratory Equipment Quick Setup Evaluation
More Information This Product, www.freescale.com
Recommended Laboratory Equipment
Table lists laboratory accessories.
Table 3-2. Accessories
male each coax patch cords, lengths: various 3-dB attenuators 6-db attenuators blockers couplers) terminations ground) feed through terminations 5/16" torque wrench (fits SMA, 2.9- 3.5-mm connectors) Bias-T networks
Power splitters adapters female female adapters male male adapters optical module (Agilent: HFBR5710L)
In-depth testing MC92604 performed using error rate tester jitter analysis system. Table provides list test equipment that used these types tests.
Table 3-3. Jitter Analysis Test Equipment
Quantity each Equipment Agilent 71500C jitter analysis system 70820A microwave transition analyzer 70004A display 3325B synthesizer/function generator 83752A synthesized sweeper 86130A BitAlyzer (serial error rate tester) 70874C jitter personality card Assorted bandpass filters Rohde Schwarz SMIQ-04B signal generator Agilent 6624A system power supply Agilent 11636B power splitter Divide-by-xx prescalers
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
Quick Setup Data-Eye Diagram
MC92604DVB design evaluation comes equipped immediately demonstrate MC92604 functions: Data-eye signal generation observation error rate checking using internal built-in self-test (BIST) features
3.2.1
Quick Setup Data-Eye Generation Observation
transmitted data-eye observed either serial outputs MC92604 using integrated, 23rd order, pseudo-noise (PN) pattern generator. implementation 23-bit generator uses following polynomial:
Stimulus from this generator also used further system testing. Refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, more information.
3.2.1.1
Equipment Setup
Generation observation data-eye produced on-chip generator requires only MC92604DVB, power supply, high-speed digital sampling scope, 0.100" shunts single receptacle patch cords. MC92604DVB test equipment should connected depicted Figure 3-1. Configure clock circuits with SW1, shown Figure 2-3. NOTE unconnected serial transmitter outputs should terminated This done connecting serial transmitter outputs serial receiver inputs terminations through in-line coupling blocking).
MOTOROLA
Chapter Laboratory Equipment Quick Setup Evaluation
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
+5-V Supply
1357
CLK_OUT1
XMIT_P XMIT_N MC92604DVB
Blockers
TRIG Blocker
Figure 3-1. Data-Eye Observation Setup
3.2.1.2
Parallel Input Connections
basic diagram will generated biasing parallel inputs according Table 3-4. Ground connections made using 0.100" shunts. Connections VDDQ made using square receptacle patch cords jumpering numbered pins header PG14. shunts patch cords provided with MC92604DVB kit. even number pins connector headers connected board's ground plane. unlisted pins connected. signal pins five connectors: CNTRL_SIG_0, CNTRL_SIG_1, CNTRL_SIG_2, JTAG, MDIO have pullup resistors VDDQ. making connection (N/C) these pins, they effectively biased high logic `1.' Using shorting shunt will bias them logic `0.' signal pins channel _XMIT _XCLK connectors have pullup resistors and, therefore, will need biased high with jumper connections VDDQ biased with shorting shunts. Using jumper wire RESET (connector CTRL_SIG_0, connecting access connector PG14, will allow MC92604 held reset mode (connected ground) released (connected VDDQ).
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
Table 3-4. Parallel Input Biasing Quick Setup Evaluations
Signal CTRL_SIG_0 REPE RCCE RECV_CLK_CENT ADIE RESET STNDBY A_XMIT XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_4 XMIT_A_5 XMIT_A_6 XMIT_A_7 B_XMIT XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_4 XMIT_B_5 XMIT_B_6 XMIT_B_7 SFP_CTRL MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 RATE_SELECT TX_DISABLE Jumper Bias Level Signal CTRL_SIG_1 LBOE USE_DIFF_CLK MEDIA TBIE COMPAT JPAK RECV_REF_A XMIT_REF_A ENABLE_AN A_XCLK GTX_CLK_0 XCVR_A_DISABLE XMIT_A_CLK XMIT_A_K XCVR_A_LBE XMIT_A_ENABLE (bit XMIT_A_ERR (bit B_XCLK GTX_CLK_1 XCVR_B_DISABLE XMIT_B_CLK XMIT_B_K XCVR_B_LBE XMIT_B_ENABLE (bit XMIT_B_ERR (bit TRST MDIO MD_CLK MD_ENABLE MD_DATA MD_ADR_1 MD_ADR_2 MD_ADR_3 MD_ADR_4 Bias Level Signal CTRL_SIG_2 BSYNC DROP_SYNC TST_1 TST_0 WSYNC1 WSYNC0 ENABLE_RED BROADCAST XCVR_RSEC JTAG Bias Level
MOTOROLA
Chapter Laboratory Equipment Quick Setup Evaluation
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
3.2.1.3
Basic Observation-Test Procedure
Connect MC92604DVB test equipment described Figure Table 3-4. This will place MC92604 generation mode with MC92604 reset. Steps skipped previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (3.3 regulators connectors respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT1 (period ns). Observe XMIT_x_P XMIT_x_N output. Since chip reset, transmitter should show constant output level ground. Connect RESET (connector CTRL_SIG_0, VDDQ access connection connector PG14. This releases RESET signal. Observe XMIT_x_P XMIT_x_N. transmitter should outputting random data. Setting digital sampling oscilloscope infinite persistence mode will display data-eye. example data-eye shown Figure 3-2.
Figure 3-2. MC92604 Data-Eye Using Recommended Test Setup
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
3.2.2
Quick Setup Error Rate Checking
addition having integrated generator, MC92604 also error rate checker (BERC). integrated 23rd order signature analyzer, that synchronized incoming stream used count code group mismatch errors relative internal reference pattern. following test procedure will describe this BIST feature. more information concerning MC92604 BIST, refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual.
3.2.2.1
Equipment Setup
Connect MC92604DVB shown Figure 3-3, connecting transmitter outputs link under test (XLINK_x_P/N) receiver under test (RLINK_x_P/N).
+5-V Supply
Logic Analyzer
CLK_OUT1 B_RECV
A_RECV
XLINK_B_N XLINK_B_P RLINK_B_N RLINK_B_P XLINK_A_P XLINK_A_N RLINK_A_P RLINK_A_N
LEDs COMMA
MC92604DVB
Figure 3-3. Error Rate Check Test Setup
3.2.2.2
Parallel Connections
bias connections parallel inputs perform quick setup BERC test same those quick setup diagram shown Table 3-4. parallel outputs connected data analysis system. simple quick test, logic analyzer required, since errors reported observed channel status LEDs.
MOTOROLA
Chapter Laboratory Equipment Quick Setup Evaluation
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
3.2.2.3
Quick Setup BERC Test Procedure
Connect MC92604DVB test equipment described Section 3.2.2.1, "Equipment Setup." This will place MC92604 generation mode with MC92604 reset, receivers BERC mode using recovered clock. Step skipped previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (3.3 regulators connectors respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT1 (period ns). Connect RESET (connector CTRL_SIG_0, VDDQ access connection connector PG14. This releases RESET signal. Observe parallel outputs data analyzer status LEDs. described MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, MC92604 will start lock PLL, initialize receivers, perform byte alignment, reset error counter. When receivers locked BIST running, recovered clock observable RECV_x_RCLK. Figure example receiver startup error detection sequence. Once receiver initially locked receiver data bits, RECV_x_[7:0], zero (logic low). Should error occur, RECV_x_[7:0] will increment RECV_x_ERR will flag error during that byte time. value RECV_x_[7:0] remains constant until another error detected system reset. receiver counter fills with errors, bits RECV_x_[7:0] stay logic high (11111111) until receiver reset. Refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, more detail.
Table 3-5. BIST Error Codes
RECV_x_DV High High High RECV_x_ERR RECV_x_COMMA High High Don't care High Don't care Don't care Status Description byte/word sync: receiver startup lost byte alignment searching alignment. BIST running, mismatch this code group. BIST running, this code group COMMA code group. Receiver byte/word synchronized, analyzer locked. BIST running, mismatch error this code group.
error count status observed channel LEDs. Simple error rate calculated. example: error count LEDs test been running minutes, would errors divided seconds bits second)] 2.515-13.
MC92604 Design Verification Board User's Guide MOTOROLA
More Information This Product, www.freescale.com
Quick Setup Data-Eye Diagram
RESET RECV_x_RCLK RECVx_ERR RECV_x_DV RECV_x_COMMA RECV_x_7 Don't Care Don't Care Don't Care Valid Comma Detected
RECV_x_1 RECV_x_0 MC92604 Reset Byte Sync RCVR Startup RCVR Synced Analyzer Locked BIST Running Mismatch These Characters BIST Running Mismatches Counted
Figure 3-4. Receiver Startup Error Detection Sequence
MOTOROLA
Chapter Laboratory Equipment Quick Setup Evaluation
More Information This Product, www.freescale.com
Chapter Test Setups
This chapter outlines laboratory test equipment setup procedure evaluate features MC92604 more depth than those outlined previous chapter. These setups meant guidelines only implied complete. Details testing specific system applications left user.
Serial Link Verification Using Serial Error Rate Tester (BERT)
This test setup used observe rate which MC92604 produces errors given either pseudo-random (PRBS) patterns user-defined pattern sets generated serial error rate tester (BERT). MC92604 placed repeater mode, REPE high, thereby disabling parallel receiver transmitter buses. Testing performed using ten-bit interface mode does require insertion idle characters word recognition byte alignment. verification using 8B/10B encoder other MC92604 features required, then appropriate idle insertion timing requirements outlined MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, must followed.
4.1.1
Test Setup Full-Speed Mode
Figure depicts test setup MC92604 full-speed mode (HSE `0'). control bits follows: REPE TBIE
other control bits `0,' except RESET, which initially `0,' then transitioned start MC92604.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Serial Link Verification Using Serial Error Rate Tester (BERT)
Source
Power Splitter
Clean Clock 1.25
Error Rate Tester Pattern Generator CK_OUT Error Detector Serial Data Serial Data Prescaler Divide-by-10 Reference Clock 62.5 MC92604DVB (Repeater Mode)
Blocker
Prescaler Divide-by-10
Reference Clock
MC92604DVB (Repeater Mode)
Figure 4-1. Full-Speed Serial Link Test Setup
4.1.2
Test Setup Half-Speed Modes
Serial link testing also performed using half-speed mode (HSE `1'). This reduces frequencies setup factor two. Figure depicts serial link test setup using divide-by-10 prescaler. control bits follows: REPE TBIE
other control bits `0,' except RESET, which initially `0,' then transitioned start MC92604.
Clean Clock Source Power Splitter Error Rate Tester Pattern Generator Error Detector
Blocker
Figure 4-2. Half-Speed Serial Link Test Setup
MOTOROLA
Chapter Test Setups
More Information This Product, www.freescale.com
Jitter Testing
Jitter Testing
following tests guidelines verifying performance MC92604 `noisy' conditions. Results will vary depending input reference frequencies, MC92604 mode operation, test setup equipment, test environment.
4.2.1
Jitter Test System Calibration
Before beginning type jitter measurements, system must first calibrated, shown configuration Figure 4-3, produce desired frequency amplitude modulation jittered source. amplitude modulation then translated into jitter units peak-to-peak unit intervals (UIp-p). Different synthesized sweepers have different characteristics different frequencies. possible that certain frequencies will produce spurious side lobes which will affect jitter characterization. strongly advised that bandpass filter centered carrier frequency used input microwave transition analyzer. Refer synthesized sweeper reference manual more details.
Function Generator 10-MHz Reference Clock
Modulation Signal
HPIB
70000 Mainframe with Microwave Transition Analyzer
Filter
Synthesized Sweeper (Carrier Frequency)
Jittered Clock
Power Splitter
Figure 4-3. Jitter Measurement System Calibration
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Jitter Testing
4.2.2
Reference Clock Jitter Transfer Test
test setup shown Figure used observe amount jitter placed reference clock that transferred data outputs. Example frequencies were chosen match narrow bandpass filters available with Agilent 71500C jitter analysis system. control bits `0,' except RESET, which initially `0,' then transitioned start MC92604. XMIT data bits follows: XMIT_x_ENABLE XMIT_x_[7:0] 0xB5 XMIT_x_CLK jumpered GTX_CLK
This data pattern appears 625-MHz clock signal serial outputs.
Function Generator 10-MHz Reference Clock
Modulation Signal
Blocker 70000 Mainframe with Microwave Transition Analyzer Filter Filter Blocker Prescaler Divide-by-2 Synthesized Sweeper (Carrier Frequency) 1.25 Jittered Clock
Serial Data
HPIB
Power Splitter
Jittered Reference Prescaler Clock MC92604DVB Divide-by-10 XMIT Data D21.5
Figure 4-4. Reference Clock Jitter Transfer Test Setup
MOTOROLA
Chapter Test Setups
More Information This Product, www.freescale.com
Jitter Testing
4.2.3
Reference Clock Jitter Tolerance Test
test setup Figure used observe amount jitter placed reference clock that does produce errors serial data outputs compared input serial data stream. MC92604 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: REPE TBIE
other control inputs `0.'
Error Rate Data over HPIB
Function Generator 10-MHz Reference Clock
Source
Clean Clock 1.25
Error Rate Tester Pattern Generator Error Detector
Modulation Signal
HPIB
Synthesized Sweeper (Carrier Frequency)
Jittered Clock 1.25
Power Splitter
Prescaler Divide-by-10
Jittered Reference Clock
MC92604DVB
Figure 4-5. Reference Clock Jitter Tolerance Test Setup
MC92604 Design Verification Board User's Guide
More Information This Product, www.freescale.com
Serial Data
70000 Mainframe with Microwave Transition Analyzer
Blocker
MOTOROLA
Jitter Testing
4.2.4
Data Jitter Tolerance Test
test setup shown Figure used observe amount jitter placed serial data inputs that does produce errors serial data outputs. MC92604 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: REPE TBIE
other control inputs `0.'
Error Rate Data Over HPIB
Function Generator 10-MHz Reference Clock
Clean Clock Source 1.25
Error Rate Tester Pattern Generator Power Splitter Error Detector
Modulation Signal
Blocker Serial Data Prescaler Divide-by-10 Reference Clock MC92604DVB (Repeater Mode)
HPIB
70000 Mainframe with Microwave Transition Analyzer
Synthesized Sweeper (Carrier Frequency)
Jittered Clock 1.25
Figure 4-6. Data Jitter Tolerance Test Setup
MOTOROLA
Chapter Test Setups
More Information This Product, www.freescale.com
Appendix Connector Signals
parallel data input output signals MC92604DVB design verification board listed following tables. connection test points common 0.100" spaced type connectors.
Input: (0.100") Connectors
configuration control inputs MC92604 connectors. There total nine input connectors DVB. each connector, even numbers connected ground plane. config/control signal inputs numbers) have pullup resistors board. Therefore, configuration requires `high' logic left open. data inputs, however, have pullups will need jumpered VDDQ logic signal input required `low,' shorting jumper installed. signal name, description, MC92604 device `ball' (pin) number listed following tables each input connectors.
A.1.1
Control Signal Input Connectors
signals connectors CTRL_SIG_0, CTRL_SIG_1, CTRL-SIG_2 (PG1-PG3, respectively) control input signals that basic configuration MC92604. These signals corresponding connector pins listed Table A-1, Table A-2, Table A-3, respectively.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Table A-1. CTRL_SIG_0 Connector
Connector MC92604 Input Signal Name REPE RCCE RECV_CLK_CENT ADIE RESET STNDBY Repeater mode enable Recovered clock enable
Input: (0.100") Connectors
Description
Center recovered clock relative data Half-speed mode enable Add/drop idle enable System reset Enable double data rate Standby mode enable Ground connection
Table A-2. CTRL_SIG_1 Connector
Connector MC92604 Input Signal Name LBOE USE_DIF_CLK MEDIA TBIE COMPAT JPACK RECV_REF_A XMIT_REF_A ENABLE_AN Loopback output enable differential reference clock inputs Media impedance select Ten-bit interface enable IEEE 802.3 compatibility mode enable Enable FIFO jumbo packets receiver primary clock output transmit primary clock input Enable auto-negotiate GMII mode Ground connection Description
MOTOROLA
Appendix Connector Signals
More Information This Product, www.freescale.com
Input: (0.100") Connectors
Table A-3. CTRL_SIG_2 Connector
Connector
MC92604
Input Signal Name BSYNC DROP_SYNC TST_1 TST_0 WSYNC1 WSYNC0 ENAB_RED BROADCAST XCVR_RSEL
Description Byte synchronization mode Drop synchronization Test mode-select Test mode-select Word sync. mode definer Word sync. mode definer Enable redundant link operation Transmit over both links XLINK_B RLINK_B Ground connection
A.1.2
Transmitter Parallel Data Input Connectors
MC92604 transmitter parallel data input signals channels mapped connectors listed tables below. Table shows 8-bit data byte input transmitter channels respectively, A_XMIT B_XMIT (PG8, PG10) connectors.
Table A-4. A_XMIT B_XMIT Connectors
MC92604 Ball Connector A_XMIT B_XMIT (Channel (Channel Input Signal Name Description
XMIT_x_0 XMIT_x_1 XMIT_x_2 XMIT_x_3 XMIT_x_4 XMIT_x_5 XMIT_x_6 XMIT_x_7
Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Ground connection
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Input: (0.100") Connectors
Table lists remaining transmitter input signals channels A_XCLK B_XCLK (PG9 PG11) connectors, respectively. x_XCLK connector buffered reference clock output from MC92604 that used input clock pattern generator. These signals supply GTX_CLK reference when interfacing Ethernet MACs. Alternatively, external pattern generator clock reference supplied CLK_x_PG, connectors. these external sources used, resistors must installed resistors removed, respectively. NOTE external clock source used must same frequency that REF_ MC92604 chip. user utilize 3.3_CLK_OUTn clocks provided source clock pattern generator.
Table A-5. A_XCLK B_XCLK Connectors
MC92604 Ball Connector A_XCLK B_XCLK (Channel (Channel Input Signal Name Description
Buffered reference clock: GTX_CLK0 channel GTX_CLK1 channel XCVR_x_DISABLE XMIT_x_CLK XMIT_x_K XCVR_x_LBE XMIT_x_ENABLE (XMIT_x_8) XMIT_x_ERR (XMIT_x_9) Transceiver disable Transmitter interface clock Transmitter special character Transmitter loopback enable Transmitter enable data (data ten-bit mode) Transmitter force code error (data ten-bit mode) Ground connection
MOTOROLA
Appendix Connector Signals
More Information This Product, www.freescale.com
Output: (0.100") Connectors
Output: (0.100") Connectors
MC92604 receiver parallel data outputs connected 0.100" connectors. mapping these signals contained Table A-6. Table lists signals A_RECV (LA1) B_RECV (LA2) connectors. Note that receive data clock, RECV_x_RCLK, brought connector pins. Care should exercised when connecting both these pins exceed drive capacity chip output. Refer MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, more details.
Table A-6. A_RECV B_RECV Connectors
MC92604 Ball Connector A_RECV, B_RECV, (Channel (Channel RECV_x_RCLK RECV_x_RCLK RECV_x_RCLK Output Signal Name Description
XCVR_ receive data clock XCVR_ receive data clock XCVR_ receive data clock_complement Ground connection
channel channel this (JTAG, test data out) RECV_x_K RECV_x_COMMA RECV_x_ERR (bit RECV_x_DV (bit RECV_x_7 RECV_x_6 RECV_x_5 RECV_x_4 RECV_x_3 RECV_x_2 RECV_x_1 RECV_x_0 Receiver detect status Receiver COMMA detect status Receiver error detect (bit 10-bit mode) Receiver data valid status (bit 10-bit mode) Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
JTAG Connector
JTAG Connector
Table lists signals JTAG (PG13) connector. This MC92604 test access port, TAP, interface IEEE 1149 JTAG testing. NOTE There 100-K internal pullups TMS, TDI, TRST. TRST held during power does receive active preset after power test logic assume indeterminate state disabling some normal transceiver functions. recommended that TRST terminated following ways:
TRST driven controller that provides reset after power Connect TRST RESET. Terminate TRST with resistor hardwire) ground.
10K-pullup TCLK provide input termination clock input used. important shorting jumper TRST input comply with above note. more information test access port, Section MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, more details.
Table A-7. JTAG Connector
Connector MC92604 TRST Input Signal Name JTAG test data JTAG test clock JTAG test mode select JTAG test reset Ground connection Description
MOTOROLA
Appendix Connector Signals
More Information This Product, www.freescale.com
MDIO Connector
MDIO Connector
Table lists signals MDIO (PG4) connector. These connections MDIO device address configuration interface MC92604. MDIO being used, MD_ENABLE must terminated low. Chapter MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, details. There other connection requirements MDIO connector.
Table A-8. MDIO Connector
Connector MC92604 Input Signal Name MD_CLK MD_ENABLE MD_DATA MD_ADR_1 MD_ADR_2 MD_ADR_3 MD_ADR_4 MDIO clock MDIO enable MDIO data (bidirectional data) MDIO address MDIO address MDIO address MDIO address Ground connection Description
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
SFP_CTRL Connector
SFP_CTRL Connector
control signals small form-factor pluggable (SFP) socket available SFP_CTRL (PG12) connector listed Table A-9. These standard signals multiple source agreement (MSA) fiber optic modules. TX_DISABLE must module operate.
Table A-9. SFP_CTRL Connector
Connector Module MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 RATE_SELECT TX_DISABLE Input Signal Name Module definition Module definition Module definition Rate select. connected most SFPs. transmitter disable Description
MOTOROLA
Appendix Connector Signals
More Information This Product, www.freescale.com
Appendix Parts List
Design Verification Board Parts List
Table shows parts used constructing MC92604DVB design verification board.
Table B-1. MC92604DVB Design Verification Board Parts List
Item Qty. U4-5 C11-12 C2-6 C25-26 C28-29 C36-40 C42-43 C45-47 C49-53 C58-63 C301-302 C73-79 Reference Value 0.01 Manufacturer Molex Inc. Fairchild Semiconductor Part 45241-0001 74VCX16244 CAP0603, Description IEEE 1394B bilingual socket Buffer 1.2-3.6 0603 ceramic chip capacitor
CAP0805, 0.01 0805 chip capacitor
0.05
CAP0805,0.05 0805 chip capacitor CAP0805, CAP1812, 0805 chip capacitor 1812 chip capacitor
C9-10 C71-72 C18-19 C30-33 C54-57 C303-304 C22-23 C67-68 socket Electronics Raltron Omron
CAP7343, 7343 solid tantalum chip capacitor, ESR, CAP7343, M2988-250M CE8950A-LZ250.000 504-AG11D A6S-7104 7343H solid tantalum chip capacitor, ESR, 250-MHz PECL oscillator 250-MHz surface mount PECL oscillator Socket oscillator; DIP4(14) 7-pole slide switches, (open/closed)
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Design Verification Board Parts List
Table B-1. MC92604DVB Design Verification Board Parts List (continued)
Item Qty. Reference PG12 PG14 PG1-4 PG8-11 PG13 LA1-2 L1-2 VR18 VR33 Value Linear Technology/ International Rectifier Motorola Motorola Molex Inc. Motorola Manufacturer Part 2516-6002UB 3428-6002UB 2540-6002UB IND-MOLDED, LT1587 Description keyed header with shroud, 0.1" spacing, profile keyed header with shroud, 0.1" spacing, profile keyed header with shroud, 0.1" spacing, profile Inductor-molded, Linear voltage regulator, amps, 3-lead
T1-9
MC92604ZT MC100ES6222 74441-0010 MPC9456
Dual SerDes Gigabit Ethernet transceiver 1:15 differential ECL/PECL clock divider fanout buffer 20-pin connector 2.5-3.3 LVCMOS clock fanout buffer 4-mm screw terminal binding post, 2-red, 4-black, 1-yellow, 1-blue, 1-green 0603 chip resistor 0805 chip resistor 0805 chip resistor 0805 chip resistor
Technology 2303/2304/9648/ 9649/9650 RES0603, RES0805, RES0805, RES0805,
R5-6 R62-63 R70-71 R74-75 R25-26 R36-39 R7-9 R14-18 R28-32 R34-35 R48-49 R52-59 R78-84 R88-91 R96-104 R117-128
R3-4 R50-51 R60-61 R68-69 R72-73 R92-95 R105-112 R130-141 1650
RES0805,
0805 chip resistor
RES0805, 1650 0805 chip resistor RES0805, RES0805, 0805 chip resistor 0805 chip resistor
MOTOROLA
Appendix Parts List
More Information This Product, www.freescale.com
Design Verification Board Parts List
Table B-1. MC92604DVB Design Verification Board Parts List (continued)
Item Qty. Reference R45-47 R85-87 R43-44 R76-77 RR40-41 R113 Value Johnson Johnson Manufacturer Part RES0805, RES0805, RES1206, RES1206, 129-0701-202 Description 0805 chip resistor 0805 chip resistor 1206 chip resistor 1206 chip resistor Scope test socket jack socket
1394B_A_N 1394B_A_P 1394B_B_N 1394B_B_P CLK_A_PG CLK_B_PG CLK_IN CLK_OUT1-4 DIFF_CLK_OUT5-6 RX_A_N RX_A_P RX_B_N RX_B_P SFP_RX_N SFP_RX_P SFP_TD_N SFP_TD_P TST1-8 TX_A_N TX_A_P TX_B_N TX_B_P D1-3 D6-14 D22-30 D1-3 D6-14 D22-30
Dialight Dialight Dialight
597-5311-402 597-5111-402 597-5411-402 3214W-1-502E
Green Yellow Surface mount trimming resistor, cage assembly press-fit legs clips 0.100" shunts Square receptacle patch cord
R12V R22V R22V1 Molex Inc. Pomona
73927-0009 929950-00 4741-12-0/ 4741-12-2
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Appendix Prescaler Jitter Measurement
Divide-by-xx Prescaler Description
Evaluating jitter system requires that clocks within system based common source. this reason, often necessary prescalers derive needed reference clock. Motorola developed small programmable prescaler with maximum input frequency which assembled using commercially available parts. Figure depicts block diagram this prescaler.
Clock Divide Clock In_alt 5-Bit Programmable Counter Divide Prescaler Level Shift Clock
Bank Switch
Bank Switch
Figure C-1. Divide-by-xx Prescaler Block Diagram
input prescaler either through divide-by-2 directly into 5-bit programmable counter. bank bank switches used select variety prescaler values based following formula:
Modulus
where
MOTOROLA
Appendix Prescaler Jitter Measurement
More Information This Product, www.freescale.com
Prescaler Components
values commonly used 1.0-Gbit systems refer Table C-1.
Table C-1. Switch Settings 1.0-Gbit SERDES Prescalers
Bank Input Clock In_alt Clock Clock Clock Bank Modulus
Schematics this prescaler available from your Motorola field applications engineer.
Prescaler Components
Table C-2. Major Components Divide-by-xx Prescaler
Table lists major integrated circuit components needed prescaler.
Part MC12093 MC100ELT23 MC100ELT21 MC100ELT26 HMMC-3122 HMC364S8G HMC394LP4
Manufacturer Motorola Semiconductor Semiconductor Semiconductor Agilent Hittite Microwave Hittite Microwave
Supplier Newark Newark Newark Newark Arrow Hittite Hittite
Comments 1.1-GHz prescaler (divide Dual differential PECL translator, with separate inputs. Single differential PECL translator. Alternative above part. Dual differential PECL translator, with common inputs. Alternative above part. 12-GHz divide-by-2 prescaler, GaAs MMIC. 12-GHz divide-by-2 prescaler, GaAs MMIC. Pin-for-pin alternative above part. 2.2-GHz programmable 5-bit counter, GaAs MMIC.
MC92604 Design Verification Board User's Guide
MOTOROLA
More Information This Product, www.freescale.com
Appendix Revision History
This appendix provides list major differences between revisions MC92604 Dual Design Verification Board User's Guide (MC92604DVBUG). This initial version user's guide, there currently changes document.
MOTOROLA
Appendix Revision History
More Information This Product, www.freescale.com
REACH USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution P.O. 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, King Street Industrial Estate, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors
limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
Motorola Stylized Logo registered U.S. Patent Trademark Office. digital trademark Motorola, Inc. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2004 MC92604DVBUG
More Information This Product, www.freescale.com

MC92604 Dual Design Verification Board User's Guide Device Suppor

Top Searches for this datasheet

Other recent searches