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Freescale Semiconductor, Inc. M68EM05JP7UM / D

M68EM05JP7

Freescale Semiconductor, Inc. M68EM05JP7UM / D
M68EM05JP7
Freescale Semiconductor, Inc..
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Freescale Semiconductor, Inc.
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M68EM05JP7
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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity / Affirmative Action Employer.
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Revision History
Previous Revision Current Revision
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Date Changes Location
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Table of Contents
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MMDS / MMEVS Configuration and Operation
Schematics
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General Description
Contents
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Introduction
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Emulation Components
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General Description Emulation Module Layout
Emulation Module Layout
Figure 1 shows the layout of the M68EM05JP7. Jumper header W1 controls the low-power oscillator (LPO) source. Jumper header W2 lets you select the external pin oscillator (EPO) source. Jumper header W3 selects the software pulldown inhibit mask option for port A. Jumper header W4 controls the voltage applied to the IRQ / VPP pin. Jumper header W5 determines the source voltage for the IRQ / VPP pin.
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Target connector J2 is the interface to a target system this connector uses a separately purchased target cable assembly. When you install the M68EM05JP7 on the MMDS, the target cable passes through the slit in the station module enclosure. Connector J1 connects to a logic analyzer. Variable resistor VR1 controls the MCU operating voltage between 3.0 V and 5.0 V. Test point header TP1 is the monitor point for MCU operating voltage adjustment. The MC68HC705JP7 MCU is at location XU22. DIN connectors P1 and P2 connect the EM and a development system platform board. Lever terminal connector P3 is for inputting the personality EPROM (PEPROM) programming voltage.
J1 VR1 TP1
XU22 P3
Figure 1. M68EM05JP7 Emulation Module
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Target Cable Assemblies
To connect your M68EM05JP7 to a target system, you need a separately purchased target cable assembly. Cable assemblies are available for four MCU packages: 20- and 28-pin DIP and 20- and 28-pin SOIC packages. The target cable connects to the emulator via connector J2 on the M68EM05JP7 emulation module. Pin assignments and signal descriptions for connector J2 can be found in Target Cable Connector Pin Assignments on page 14. Figure 2 represents a target cable assembly. An assembly for DIP packages consists of a flex cable and a target head adapter. The assembly for SOIC packages requires an additional SOIC adapter. One end of the flex cable plugs onto M68EM05JP7 connector J2 with orientation shown in Figure 2. The other end of the flex cable plugs into the target head adapter. The target head adapter then inserts into either a DIP footprint in a target system or into the SOIC adapter. The MCU package in your target system determines the target cable assembly components required: · · · For a 20-pin DIP package (MC68HC(7)05JJx MCUs), use flex cable M68CBL05A and target head adapter M68TA05JJ7P20. For a 28-pin DIP package (MC68HC(7)05JPx MCUs), use flex cable M68CBL05A and target head adapter M68TA05JP7P28. For a 20-pin SOIC package (MC68HC(7)05JJx MCUs), use the flex cable assembly for the 20-pin DIP in conjunction with SOIC adapter M68DIP20SOIC. For a 28-pin SOIC package (MC68HC(7)05JPx MCUs), use the flex cable assembly for the 28-pin DIP in conjunction with SOIC adapter M68DIP28SOIC.
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General Description Target Cable Assemblies
TO EMULATION MODULE
FLEX CABLE
TO TARGET HEAD ADAPTER
TARGET HEAD ADAPTER EMULATION MODULE TO TARGET SYSTEM MCU SOCKET
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20-PIN DIP
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20
28-PIN DIP
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28
20-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20 DIP TO SOIC ADAPTER: M68DIP20SOIC
28-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28 DIP TO SOIC ADAPTER: M68DIP28SOIC
Figure 2. Target Cable Assembly
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Connector Information
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Target Cable Connector Pin Assignments
Figure 3 shows the pin assignments for connector J2. Table 1 lists signal descriptions for connector J2.
PB0 / AN0 EVDD GND OSC1 OSC2 PC3 PC2 PC1 PC0 RESET IRQ PA0 PA1 PA2 GND GND GND GND GND GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB1 / AN1 PB2 / AN2 PB3 / AN3 / TCAP PB4 / AN4 / TCMP PB5 / SDO PC4 PC5 PC6 PC7 PB6 / SDI PB7 / SCK PA5 PA4 PA3 GND GND GND GND GND GND
Figure 3. Target Connector Pin Assignments
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General Description Connector Information
Table 1. Connector J2 Signal Descriptions
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NOTE: Port C is bonded out only on the MC68HC705JP7 MCU.
TARGET INTERRUPT REQUEST - Active-low input signal from the target that asynchronously applies an MCU interrupt
NOTE: The VPP programming voltage should not be applied to this
pin. Doing so will damage the development system. Connector P3 is available for programming voltage input.
RESET PA0, PA5, PA1, PA4, PA2, PA3
Active-low bidirectional signal to / from the target system is driven low to pull the MCU into reset. PORT A (bits 0, 5, 1, 4, 2, 3) - General-purpose I / O lines are controlled by software via data direction and data registers. Port A has high-current sink capability on all pins and external interrupt capability on bits 0-3.
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Logic Analyzer Connector Pin Assignments Figure 4 shows the pin assignments for logic analyzer connector J1. This connector provides easy access to many of the signals used internally. Table 2 lists signal descriptions for this connector.
- - LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LR / W - - - VCC RESET 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND - GND LA12 - - - AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR - - ACLK -
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Figure 4. Connector J1 Pin Assignments
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General Description Connector Information
Table 2. Logic Analyzer Connector J1 Signal Descriptions
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AD7-AD0 LR / W LIR VCC ACLK
RESET
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MMDS / MMEVS Configuration and Operation
Contents
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Introduction
The following paragraphs explain how to configure and use your M68EM05JP7 as part of an MMDS or MMEVS system. For other parts of system installation and configuration, see either the MMDS0508 Operations Manual (MMDS0508OM / D) or MMEVS05 / MMEVS08 Operations Manual (MMEVS0508OM / D). The topics covered in this chapter are:
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Setting M68EM05JP7 Jumper Headers on page 21 explains how to set the M68EM05JP7 jumper headers. Remaining System Installation on page 25 covers the final steps to system installation. Setting Emulation Voltage on page 26 explains how to adjust the MC68HC705JP7 MCU operating voltage. Personality Files Usage on page 27 discusses the personality file used on the M68EM05JP7 board. Personality EPROM Programming on page 27 covers programming procedures for the 64-bit personality EPROM. Emulation Specifics on page 29 explains special considerations for emulating with this module.
NOTE:
You can configure an M68EM05JP7 already installed in the system platform board. To do so, remove system power and then follow the guidance of this chapter. Be sure to switch off power before you reconfigure an installed EM. Reconfigure EM jumper headers with the power on can damage emulation circuits.
CAUTION:
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MMDS / MMEVS Configuration and Operation Setting M68EM05JP7 Jumper Headers
Setting M68EM05JP7 Jumper Headers
Your M68EM05JP7 has five jumper headers - W1 through W5. The following explains how to configure these components.
Internal Clock Control Header, W1
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The internal clock control header provides access to the emulated internal low-power oscillator (LPO) frequency generated by the Y1 crystal circuit. The LPO on the M68EM05JP7 module operates at 500 kHz, the nominal LPO frequency. The LPO frequency passes through jumper header W1 and gives the user the ability to supply an alternate LPO frequency. To use an alternate internal clock source, remove the fabricated jumper from W1 and connect the source to the OUT pin of header W1. A digital ground connection is available at the GND pin.
NOTE:
The user-supplied LPO source should be a CMOS level square wave.
W1 LPO IN OUT GND
FABRICATED JUMPER
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NOTE:
The user-supplied source through the target cable should be a CMOS level square wave.
The fourth possible external clock source is a user-supplied crystal oscillator circuit. The M68EM05JP7 has been designed with an unpopulated crystal circuit. For this source, reposition the W2 jumper between pins Y2 and C and supply the components for the Y2 crystal circuit. The IC device at location U1 is an 74HCU04 inverter and provides the inverter for a standard single inverter oscillator. The user supplies the appropriate crystal, resistors, and capacitors for operating the external clock at a particular frequency. See M68EM05JP7 Schematics (Sheet 4 of 7) on page 39 for schematic details of the crystal circuit.
W2 CLK SRC Y2 CAN MMDS TGT-OSC C C C C FABRICATED JUMPER
NOTE:
To use any of the external clock sources, the external pin oscillator must be selected as the MCU clock source through manipulation of the OM2:OM1 bits in the IRQ status and control register (ISCR)
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MMDS / MMEVS Configuration and Operation Setting M68EM05JP7 Jumper Headers
SWPDI Mask Option Control Header, W3
Jumper header W3 controls the software pulldown inhibit mask option for port A. With the jumper in the ENABL position, the mask option bit is clear and the port A pulldowns can be controlled via software. With the jumper in the INHIB position, the mask option is set and the port A pulldowns are inhibited.
NOTE:
The port B pulldowns are not controlled by this jumper. They are controlled by what is programmed in the SWPDI bit of the mask option register in the resident MC68HC705JP7 MCU.
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W3 SWPDI
FABRICATED JUMPER ENABL
INHIB
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IRQ / VPP Level Control Header, W4 When the resident MC68HC705JP7 is in reset, the IRQ / VPP voltage level is at the voltage determined by IRQ / VPP source control header W5. The IRQ / VPP level control header W4 controls the voltage level the IRQ / VPP pin will be at during routine operation when the external IRQ is not asserted and the part is not in reset. If jumper header W4 is in the NORMAL position, the IRQ / VPP level will drop to the MCU operating voltage once the part comes out of reset. If jumper header is in the 2XHOLD position, the IRQ / VPP level will be held at the voltage determined by IRQ / VPP source control header W5.
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NOTE:
The W4 jumper header should be in the 2XHOLD position for personality EPROM programming only.
W4 IRQ LVL
NORMAL
2XHOLD
FABRICATED JUMPER
IRQ / VPP Source Control Header, W5
Jumper header W5 determines the source for high voltage applied to the IRQ / VPP pin. In the NORMAL position, the voltage is supplied from the development systems charge pump (~12 V). In the VPP position, the voltage is supplied from the user through lever terminal connector P3.
NOTE:
The W5 jumper header should be in the VPP position for personality EPROM programming only.
W5 IRQ VPP
FABRICATED JUMPER
NORMAL
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MMDS / MMEVS Configuration and Operation Remaining System Installation
Remaining System Installation
When you have configured headers W1-W5, M68EM05JP7 configuration is completed. At that time, make sure of these points: · · · Ensure that the power to the development tool is off. Remove the panel from the station module top, if installing the M68EM05JP7 in an MMDS station module. Fit together EM connectors P1 and P2 on the bottom of the board and platform board DIN connectors. Snap the corners of the EM onto the plastic standoffs. Connect the target cable, if appropriate. Replace the panel, if installing in an MMDS.
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At this point, you are ready to make remaining cable connections, as necessary, and restore power. For instructions, consult either the MMEVS05 / MMEVS08 Operations Manual (MMEVS0508OM / D) or MMDS0508 Operations Manual (MMDS0508OM / D).
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Setting Emulation Voltage
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VR1 TP1 GND
ADJUST
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MMDS / MMEVS Configuration and Operation Personality Files Usage
Personality Files Usage
The development system uses a specific personality file to emulate MC68HC(7)05JJx and MC68HC(7)05JPx MCU devices: file 0002BVxx.MEM. The debugger software loads this personality file upon power up. The file is on an individual disk shipped with the M68EM05JP7.
NOTE:
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Note that personality file names follow the pattern 00ZZZVxx.MEM, where ZZZ is the EM identifier or MCU name and xx is the version of the file.
Personality EPROM Programming
The MC68HC705JP7 and MC68HC705JJ7 MCUs have a 64-bit personality EPROM (PEPROM) that is controlled through MCU registers and the IRQ / VPP voltage. To program this array on the resident MCU, the user must write or obtain code that will modify the array correctly.
NOTE:
The MC68HC05JJ6 MCU does not have the personality EPROM. When emulating the MC68HC05JJ6 MCU, user code should not manipulate the PEPROM status and control register (PEBSR) or the PEPROM bit select register (PEBSR).
Refer to the general release specification for proper programming sequence. The required programming voltage must be supplied by the user through lever terminal connector P3. Proper configuration of jumper headers W4 and W5 is also required.
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Freescale Semiconductor, Inc. MMDS / MMEVS Configuration and Operation
The following sequence shows how to program the PEPROM: 1. Ensure that power to the development system is off.
2. On the M68EM05JP7 emulation module, set jumper header W4 to the 2XHOLD position and the W5 jumper header to the VPP position. 3. On the M68EM05JP7 emulation module, make connections to P3 to supply the required programming voltage. Do not turn the VPP supply voltage on.
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4. Turn on power to the development system. 5. Turn on the VPP supply voltage. At this point, the proper programming voltage is applied to the resident MCU. 6. Start running debugger software. 7. Load and execute the necessary code to program the PEPROM. 8. Once the PEPROM programming is complete, exit the debugger software. 9. Remove VPP source voltage from connector P3. 10. Turn off development system power. 11. Reposition jumper headers W4 and W5 to the normal position.
NOTE:
To program the PEPROM, VDD must be greater than 4.5 Vdc. To avoid damaging emulator circuits, the development system voltage must be turned on before you supply the VPP source voltage through the P3 connector. Also, the source voltage should be removed from P3 before turning off the development system voltage.
CAUTION:
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MMDS / MMEVS Configuration and Operation Emulation Specifics
Emulation Specifics
The following paragraphs detail differences between the performance of MC68HC(7)05JPx and MC68HC(7)05JJx MCUs run in single-chip operation and how certain features will perform during emulation.
IRQ / VPP Input Pin
In single-chip mode operation: The IRQ / VPP pin drives the asynchronous IRQ interrupt function of the CPU. The pin is also used for programming voltage when programming the personality EPROM, the user EPROM, or the MOR. In emulation: The IRQ / VPP signal supplied to connector J2 through a target cable drives only the asynchronous IRQ interrupt function. A VPP voltage should not be supplied to the IRQ / VPP pin in a target application while the emulator is connected. Connector P3 is available for VPP programming voltage input.
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Pullup on IRQ
In single-chip mode operation: There is no pullup on the IRQ pin. Your application must pull the IRQ pin to VDD level to prevent interrupts. In emulation: The IRQ pin is pulled up on the module. Be aware that an application without the IRQ pin pulled high will emulate correctly but will fail in the application because of a floating IRQ line. The IRQ pin pulled high on the module causes these results.
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Personality EPROM In single-chip mode operation: The MC68HC05JJ6 does not have a personality EPROM and accesses to the PEPROM registers are undefined. In emulation: The MC68HC05JJ6 device is emulated with a MC68HC705JP7 device resident on the M68EM05JP7 module. For accurate emulation, the PEPROM registers should not be accessed when emulating the MC68HC05JJ6 MCU.
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Mask Option Register (MOR) Control
In single-chip mode operation: The MCU mask options will be determined by which options have been programmed in the MOR EPROM location of the resident MC68HC705JP7 MCU. This register must be programmed using a dedicated programmer. In emulation: Like single-chip, the mask option register should be programmed to the desired value using a dedicated programmer prior to insertion in the M68EM05JP7 module. The exception is the SWPDI mask option, which is detailed in SWPDI Mask Option Bit.
SWPDI Mask Option Bit
In single-chip mode operation: The software programmable pulldown inhibit option is determined by what has been programmed in the mask option register (MOR). If the bit is set, all I / O pulldowns are inhibited. In emulation: The programmed software programmable pulldown inhibit option only controls the pulldowns for port B. The port A and port C pulldown inhibit option is emulated with jumper header W3.
NOTE:
Port C is bonded out only on the MC68HC705JP7 MCU.
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Schematics
Contents
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M68EM05JP7 Schematics
Refer to the following pages for the seven sheets of schematics for the M68EM05JP7 emulation module.
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M68EM05JP7 Schematics (Sheet 1 of 7)
NOTES, 110 O 2 Make LIR to PFB be low true.
UNLESS OTHERWISE SPECIFIED
PCB REV
SCH REV
VCC PIN LOCATIONS :
M68EM05JP7 EMULATION MODULE
Decouple Caps for ICs as labeled. All caps are 0.1 uF @ 50 V
VCC C3 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 GND VCC
GROUND PIN LOCATIONS :
DEVICE TYPE, PIN NUMBERS, AND REFERENCE DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS :
C34 GND
4. TP1 3 2 1 HDR103 GND C19 C23 C33 TEST POINT FOR LVDD ADJUST LVDD
RESISTANCE VALUES ARE IN OHMS.
CAPACITANCE VALUES ARE IN MICROFARADS.
CHRGPMP 3 U18 VIN VOUT C30 0.1UF GND 1 ADJUST LM317T 2 R8 240
Spare Gates
VCC-1 VCC-1 VCC-1 U1E 9 11 10 9 74HCU04 74ACT00 U27C 74HC4066 12 11 1 2 11 13 74HCU04 74ACT00 U27D 74HC4066 10 11 GND-1 13 74HC32 U1F U28D 13 12 12 U16D 8 10 8 6 U28C
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Title
ORCAD IV FLAT FILES CSIC DEVELOPMENT TOOLS
Schematics M68EM05JP7 Schematics
COMPUTER GENERATED DRAWING : DO NOT REVISE MANUALLY
M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 1 of
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M68EM05JP7 Schematics (Sheet 2 of 7)
Direct Target Connector Bus MCU1.28 MCUAD0.7 LA0.14 LSByte Address / Data Bus LVDD LA0.14 MCUAD0.7
MCU1.28
LVDD LOGIC ANALYZER CONNECTOR 27 GND 11 1 GND LA12 C OC 74HCT573 26 VSS J1 XU22 VDD
R10 10K
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 2 3 4 5 6 7 8 9 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 19 18 17 16 15 14 13 12 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0
U11 D1 D2 D3 D4 D5 D6 D7 D8
PC7 PC6 PA5 PA4 PA3 PA2 PA1 PA0 R11 GND 10K GND
9 8 12 13 14 15 16 17 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LR / W
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
AD0.7
MCU-RESET IRQ
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR ACLK
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 VCC 35 37 COP-RESET 39 HDR220
TST-RNG LR / W U6A 1 2
PC7 PC6 PA5 PA4 PA3 PA2 PA1 PA0 VCC-1 VCC-1
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
COP-RESET U6E PH2 4 2 D Q 12 D Q 11 Q 74HCT74 6 E-EM 5 3 1 0 9 U7A U7B U15D 12 11 13 U16C Q 8 1 74HCT74 3 VCC-1 GND 74HCT32 74HC04 9 8 10 74HC32 SCLK 3 4 U6B 74HC04 11 10 SCLK
MCU11 MCU10 MCU5 MCU4 MCU3 MCU2 MCU1 MCU28 PB7 / SCK PB6 / SDI PB5 / SDO PB4 / AN4 / TCMP PB3 / AN3 / TCAP PB2 / AN2 PB1 / AN1 PC5 PB0 / AN0 PC4 PC3 PC2 7 6 23 22 A8 / A9 A10 / A11 A12 LIR / RW E LV-OSC1 R7 10K 1 VCC-1 LV-PA-IRQ GND P R CLK C L P R CLK C L 21 20 25 24 RESET IRQ / VPP OSC1 OSC2 MC68HC705JP7EDW PC1 PC0
MCU-RESET IRQ
LV-PA-IRQ LV-OSC1
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PH2 E-EM LV-OSC2 Title
LV-OSC2
CSIC DEVELOPMENT TOOLS M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 2 of
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M68EM05JP7 Schematics (Sheet 3 of 7)
PA0.5 DAUGHTER BOARD CONNECTOR #2 TGT-PC0.7 U6F GND VCC P2C 13 74HC04 LOCKOUT P2A P2B 12 VCC GND
PA0.5 TGT-PC0.7 LOCKOUT LOCKOUT T-IRQ TOSC2 TGT-OSC
1 MCU1.28
TARGETJ2 CONNECTOR
(PB0) MCU28 EVDD GND
GND MMDS-RESET COP-RESET (PRU-D)
TGT-PC0 TGT-PC1 TGT-PC2 TGT-PC3 TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 LOCKOUT T-RST (RESET-IN) PORTS
PRU NOT
MCU1 (PB1) MCU2 (PB2) MCU3 (PB3) MCU4 (PB4) MCU5 (PB5) TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 MCU10 (PB6) MCU11 (PB7) TGT-PA5 TGT-PA4 TGT-PA3
MCU1.28
VPRU EVDD VCC GND GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
TGT-PA0.5
LA0.14 P1B P1C P1A GND-1 (LA14) (LA13) LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0
LA0.14
LIR LR / W SCLK SCLK
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR LR / W SCLK SCLK
SH 4 SWITCH SWITCH
INTERNAL
INTERNAL SWITCH (WE) (U / M) (OE)
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MMDSIRQ CHRGPMP MMDSOSC
CSIC DEVELOPMENT TOOLS M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 3 of
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M68EM05JP7 Schematics (Sheet 4 of 7)
VPP FOR PEP
IRQ VPP
IRQ W4 LEVEL LPO HEADER
LA0.14 VCC VCC R5 10K R4 10K LOCKOUT
DECODE AND OSC SWITCH
PH2 DATAOUT-EN DATAIN-EN TST-RNG
DECODE TABLE
INTERNAL
INTERNAL WR-DDRA WR-DDRC WR-PDRA PORTS LR / W SWITCH OSCBUF U1C 5
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INTERNAL WR-DDRA WR-DDRC WR-PDRA PORTS WR-ISCR 2 3 4 5 6 7 8 9 10 LA0 11 LA1 LPO-FREQ 13 14 PH2 DATAOUT-EN15 DATAIN-EN 16 17 TST-RNG 18 LR / W WR-ISCRIN 19 20 SWITCH 21 OSCBUF IO31 IO0 IO1 IO30 IO2 IO29 IO3 IO28 IO4 IO27 IO5 IO26 IO6 IO25 IO7 IO24 I0 CLK1 / I5 I1 I4 CLK0 / I2 I3 IO8 IO23 IO9 IO22 IO10 IO21 IO11 IO20 IO12 IO19 IO13 IO18 IO14 IO17 IO15 IO16 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 27 26 25 24 23 34 VSS VSS VSS VSS MACH215-12JC GND CLK-E EPO-FREQ LOCKOUT LV-OSC1 E-EM LA12 LA11 LA10 LA4 LA3 LA2 LA5 LA6 LA7 LA8 LA9 AD6 AD5 CLK-L
SWITCH PORTS WR-ISCR WR-PDRA WR-DDRA WR-DDRC TST-RNG
LV-OSC1 E-EM AD0.7
CLK SRC
W2 2 4 6 8 Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 4 of REV 2 7 CSIC DEVELOPMENT TOOLS
Schematics M68EM05JP7 Schematics
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M68EM05JP7 Schematics (Sheet 5 of 7)
PA0.5
TO / FROM PRU
TGT-PA4
PA3 PA4 PA5 Z0 Z1 6 11 10 9 INH A B 7 C VEE 74HC4053 5 3 DDRA3 DDRA4 DDRA5 2 1
INH A B 7 C VEE 74HC4053 U25 14 X0 X X1 Y 15 Y0 4 Y1 Z
TGT-PA3
TGT-PA2
PORT A HIGH CURRENT
PDICH PDICL
WR-PDRA LOCKOUT WR-DDRA
DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 WR-PDRA LOCKOUT WR-DDRA PA5 PA4 PA0 PA3 TGT-PA3 TGT-PA0 PAPULL3 PAPULL0 1 12 VSS VSS VSS VSS MACH215-12JC GND PAPULL0.5 TGT-PA0.5 PA0.5 U15A PA0 1 3 PA1 2 U15B 74HCT32 U15C PA2 9 8 PA3 10 74HCT32 AD7.0 74HCT32 5 4 6 PA-IRQ GND 23 34
2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 IO0 IO31 IO1 IO30 IO2 IO29 IO3 IO28 IO4 IO27 IO5 IO26 IO6 IO25 IO7 IO24 I0 CLK1 / I5 I1 I4 CLK0 / I2 I3 IO8 IO23 IO9 IO22 IO10 IO21 IO11 IO20 IO12 IO19 IO13 IO18 IO14 IO17 IO15 IO16 2 PAPULL2 PAPULL5 TGT-PA2 TGT-PA5 AD5 AD4 AD3 AD2 AD1 AD0 SWPDI PA1 PA2 AD6 AD7 TGT-PA4 TGT-PA1 PAPULL4 PAPULL1
TGT-PA0
SWPDI MASK OPTION W3
3 1 HDR103 GND 1-2 ENABLE 2-3 INHIBIT VCC
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SWPDI Title
PAPULL1
SWPDI
PA-IRQ
CSIC DEVELOPMENT TOOLS
Schematics M68EM05JP7 Schematics
AD0.7
M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 5 of
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M68EM05JP7 Schematics (Sheet 6 of 7)
TGT-PC0.7
PORT C PULLDOWN
TGT-PC0 TGT-PC1 TGT-PC2
AD0.7
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 1 19 1G 2G 74HC244 GND 2 5 4 U3A 74HC125 3 74HC32 U16B 4 6 PDICH 5 74HC32 5 3 1 RN1A 2 RN1B 4 RN1C 6 7 6 10 U3B 74HC125 8 1 SWPDI 1 3 PDICL 2 U16A 11 1 CLK CLR 74HCT273 2 5 6 9 12 15 16 19 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRC7 2 4 6 8 11 13 15 17 WR-DDRC LOCKOUT
U9 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
WR-DDRC LOCKOUT
9 13 U3C 74HC125
SWPDI
U3D 74HC125 1 1
PDICL
PDICH
RN1D 8
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Title
CSIC DEVELOPMENT TOOLS M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 6 of
Schematics M68EM05JP7 Schematics
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M68EM05JP7 Schematics (Sheet 7 of 7)
ADDRESS / DATA BUS CONVERSION
EM RESET CIRCUIT
SH 3 Q3 2N4401
MMDS-RESET
SH 2 CR2 1N5817
MCU-RESET
LVDD AD1 AD0 OSC1 3 5 7 9 11 14 PA-IRQ LVDD-1 U6D 8 9 74HC04 OSCBUF SH 4 PA-IRQ SH 5
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 2 4 6 10 12 15 Y0 Y1 Y2 Y3 Y4 Y5 A0 A1 A2 A3 A4 A5 LVDD 20
COP-RESET
LV-PA-IRQ LV-OSC2 LV-OSC1 R6
TO / FROM TARGET T-RESET
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TGT-RESET LEVEL CONVERSION
GND-1 GND Title
CSIC DEVELOPMENT TOOLS M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 7 of
Schematics M68EM05JP7 Schematics
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M68EM05JP7UM / D
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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution P.O. Box 20912 Phoenix, Arizona 85036.1-800-441-2447 or 602-303-5454
JAPAN: Nippon Motorola Ltd. Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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M68EM05JP7UM / D