56F826 Evaluation Module Hardware User's Manual Motorola, Inc., 2

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Order this document DSP56F826EVMUM/D Rev. 06/06/2003
56F826 Evaluation Module Hardware User's Manual
Motorola, Inc., 2003. rights reserved.
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Table Contents
Preface Audience Organization. Suggested Reading Notation Conventions Definitions, Acronyms, Abbreviations References Chapter Introduction 56F826EVM Architecture 56F826EVM Configuration Jumpers. 56F826EVM Connections Chapter Technical Summary 56F826 Program Data Memory EEPROM Memory RS-232 Serial Communications. Clock Source Operating Mode Debug LEDs. Debug Support 2.8.1 JTAG Connector. 2.8.2 Parallel JTAG Interface Connector External Interrupts 2-10 2.10 Reset. 2-11 2.11 Power Supply 2-12 2.12 Stereo Codec 2-13 2.12.1 Analog Input/Output. 2-13 2.12.2 Digital Interface 2-14
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2.13 Daughter Card Connectors 2.13.1 Memory Daughter Card Expansion Connector 2.13.2 Peripheral Daughter Card Expansion Connector 2.14 Test Points Appendix 56F826EVM Schematics Appendix 56F826EVM Bill Material
2-15 2-16 2-17 2-18
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List Figures
Block Diagram 56F826EVM 56F826EVM Jumper Reference Connecting 56F826EVM Cables Schematic Diagram External Memory Interface EEPROM Memory Block Diagram Schematic Diagram RS-232 Interface Schematic Diagram Clock Interface Schematic Diagram Debug Interface Block Diagram Parallel JTAG Interface. Schematic Diagram User Interrupt Interface 2-10 Schematic Diagram RESET Interface 2-11 Schematic Diagram Power Supply 2-12 Codec Analog Connections. 2-14 CS4218 Stereo Audio Codec 2-15 56F826 Processor RESET, MODE, CLOCK IRQS. PROGRAM DATA SRAM MEMORY Serial 1M-bit Serial EEPROM Memory PORT, RS-232 Connector 16-bit Stereo Codec Parallel JTAG Host Target Interface JTAG Connector Daughter Card Expansion Connectors Power Supplies A-10 Bypass Caps A-11
2-10 2-11 A-10
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List Tables
56F826EVM Default Jumper Options Port Connector Description RS-232 Serial Connector Description. Operating Mode Selection JTAG Connector Description Parallel JTAG Interface Disable Jumper Selection. Parallel JTAG Interface Connector Description Codec Sample Rate Selector 2-13 Memory Daughter Card Connector Description. 2-16 Peripheral Daughter Card Connector Description 2-17
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viii
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Preface
This reference manual describes detail hardware 56F826 Evaluation Module.
Audience
This document intended application developers creating software devices using Motorola 56F826 part.
Organization
This manual organized into chapters appendixes. Chapter Introduction provides overview 56F826EVM features. Chapter Technical Summary describes 56F826EVM hardware detail. Appendix 56F826EVM Schematics contains schematics 56F826EVM.
Appendix 56F826EVM Bill Material provides list materials used 56F826EVM board.
Suggested Reading
More documentation 56F826 56F826EVM found URL:
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Preface More Information This Product, www.freescale.com
Notation Conventions
This manual uses following notational conventions:
Term Value Active High Signals (Logic One) Active Signals (Logic Zero) Symbol special symbol attached signal name Noted with overbar text most figures Begin with symbol special symbol attached number Begin with letter attached number Considered positive unless specifically noted negative value Linkable on-line Reference sources, paths, emphasis Examples CLKO schematic drawings, Active Signals noted backslash: Exceptions
Hexadecimal Values Decimal Values
$0FF0 b1010 b0011 Voltage often shown positive: +3.3V
Binary Values
Numbers
Blue Text Bold
.refer Figure .see:
http://www.motorola.com/.
Definitions, Acronyms, Abbreviations
Definitions, acronyms abbreviations terms used this document defined below reference codec EEPROM GPIO COder/DECoder, part used convert analog signals digital (Coder) digital signals analog (Decoder) Electrically Erasable Programmable Read-Only Memory Evaluation Module, hardware platform which allows customer evaluate silicon develop their application General Purpose Input Output Port; does share functionality with other peripheral chip only input, output level-sensitive interrupt input Integrated Circuit
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JTAG LQFP MPIO OnCE
SRAM
Joint Test Action Group, protocol/interface used test debug Low-profile Quad Flat Pack Multi-Purpose Input Output Port; shares package pins with other peripherals chip function GPIO On-Chip Emulation, debug port created Motorola enable designers create low-cost hardware interface professional-quality debug environment Printed Circuit Board Phase Locked Loop Random Access Memory Read-Only Memory Serial Communications Interface Port Serial Peripheral Interface Port Static Random Access Memory Synchronous Serial Interface Port Wait State
References
following sources were used produce this manual: DSP56800 Family Manual, Motorola, DSP56800FM/D 56F826/827 User's Manual, Motorola, DSP56F826-827UM/D 56F826 Technical Data, Motorola, DSP56F826/D
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Chapter Introduction
56F826EVM used demonstrate abilities 56F826 provide hardware tool allowing development applications that 56F826.
56F826EVM evaluation module board that includes 56F826 part, 16-bit stereo codec, external memory daughter card expansion interface. daughter card expansion connectors signal monitoring user feature expandability. 56F826EVM designed following purposes: Allowing users become familiar with features 56800 architecture. tools examples provided with 56F826EVM facilitate evaluation feature benefits family. Serving platform real-time software development. tool suite enables user develop simulate routines, download software on-chip on-board RAM, debug using debugger JTAG/OnCEport. breakpoint features OnCE port enable user easily specify complex break conditions execute user-developed software full-speed, until break conditions satisfied. ability examine modify user accessible registers, memory peripherals through OnCE port greatly facilitates task developer. Serving platform hardware development. hardware platform enables user connect external hardware peripherals. on-board peripherals disabled, allowing user reassign hybrid controller's peripherals. OnCE port's unobtrusive design means that memory board chip available user.
56F826EVM Architecture
56F826EVM facilitates evaluation various features present 56F826 part. 56F826EVM used develop real-time software hardware products based 56F826. 56F826EVM provides features necessary user write debug software, demonstrate functionality that software interface with
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Introduction More Information This Product, www.freescale.com
customer's application-specific device(s). 56F826EVM flexible enough allow user fully exploit 56F826's features optimize performance product, shown Figure 1-1.
56F826
RESET LOGIC RESET EEPROM 1M-bit Interface RS-232 Interface DSub 9-Pin
MODE LOGIC
MODE
Program Memory 64Kx16-bit SRAM Data Memory 64Kx16-bit SRAM Memory Daughter Card Connector JTAG Connector
Address, Data Control Peripheral Daughter Card Connector
JTAG/OnCE
Stereo 16-bit Codec
Stereo Line Stereo Line Headphone Jack
DSub 25-Pin
Parallel JTAG Interface
GPIO
Debug LEDs
4.00MHz Crystal
XTAL/EXTAL
+2.5V, +3.3V
Power Supply +2.5V, +3.3V +5.0V
Figure 1-1. Block Diagram 56F826EVM
56F826EVM Configuration Jumpers
Seven jumper groups, (JG1-JG7), shown Figure 1-2, used configure various features 56F826EVM board. Table describes default jumper group settings.
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56F826EVM Configuration Jumpers
RESET
JTAG
HEADPHONE
DSP56F826EVM
LEDS
IRQA IRQB LINE LINE
Figure 1-2. 56F826EVM Jumper Reference Table 1-1. 56F826EVM Default Jumper Options
Jumper Group Comment Enable on-board Parallel JTAG Host/Target Interface Enable RS-232 output Enable on-board SRAM on-board EXTAL crystal input oscillator on-board XTAL crystal input oscillator Selects device's Mode operation upon exit from reset Enable EEPROM Jumpers Connections 1-2, 3-4,
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56F826EVM Connections
interconnection diagram shown Figure connecting external +12.0V power supply external +5.0V power supply 56F826EVM board.
Parallel Extension Cable 56F826EVM PC-compatible Computer
Connect cable Parallel/Printer port External with 2.1mm, +12.0V receptacle Power connector +5.0V Supply
Figure 1-3. Connecting 56F826EVM Cables
Perform following steps connect 56F826EVM cables: Connect parallel extension cable parallel port host computer Connect other parallel extension cable 56F826EVM board shown Figure 1-3. This provides connection which allows host computer control board. Make sure that external +12.0V 2.1A switching power supply external +5.0V power supply plugged into +120V power source Connect 2.1mm output power plug from external switching power supply into 56F826EVM board, shown Figure 1-3. Optionally, attach external +5.0V power supply 2-pin terminal block, TB1. Apply power external power supply. green Power-On LED, LED7, will illuminate when power applied correctly.
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Chapter Technical Summary
56F826EVM designed versatile hybrid controller development card developing real-time software hardware products support generation applications digital wireless messaging, digital answering machines, feature phones, modems, digital cameras. power 16-bit 56F826 device, combined with on-board 16-bit external program static (SRAM), 16-bit external data SRAM, RS-232 interface, stereo 16-bit codec interface, Daughter Card Expansion interface parallel JTAG interface, makes 56F826EVM ideal developing implementing many audio voice algorithms, well learning architecture instruction 56F826 processor. main features 56F826EVM, with board schematic reference designators, include: 56F826EVM 16-bit +2.5V/+3.3V hybrid controller operating 80MHz [U1] External fast static (FSRAM) memory [U2], configured bits Program memory with wait states 70MHz bits Data memory with wait states 70MHz 1Mbit Serial EEPROM [U4] 4.00MHz crystal oscillator device frequency generation [Y1] Optional external oscillator frequency input connector [JG4 JG5] Joint Test Action Group (JTAG) port interface connector external debug Host Target Interface [J3] On-board Parallel JTAG Host Target Interface, with connector printer port cable [P2] RS-232 interface easy connection host processor 16-bit stereo codec interface [U5, Stereo headphone interface Codec sample rate selector [S4]
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Peripheral Daughter Card Expansion Connector, allow user connect SCI, SSI, GPIO-compatible peripheral hybrid controller[J2] Memory Daughter Card Expansion Connector, allow user connect memory memory device hybrid controller[J1] On-board power regulation from external +12V DC-supplied power input [P1] On-board power regulation from optional DC-supplied power input [TB1] Light Emitting Diode (LED) power indicator [LED7] on-board real-time user debugging LEDs [LED1-6] Manual RESET push-button [S1] Manual interrupt push-button IRQA [S2] Manual interrupt push-button IRQB [S3]
56F826
56F826EVM uses Motorola DSP56F826BU80 part, designated board schematics. This part will operate maximum speed 80MHz. full description 56F826, including functionality user information, provided these documents: 56F826 Preliminary Technical Data Sheet, (DSP56F826-827 UM/D): Provides features list specifications including signal descriptions, power requirements, timing requirements available packaging. 56F826/827 16-Bit Digital Signal Processor User's Manual, (56F826UM/AD): Provides overview description detailed information about on-chip components including memory maps, peripheral functionality, control/status register descriptions each subsystem. DSP56F800Family Manual, (DSP56F800FM/D): Provides detailed description core processor, including internal status control registers detailed description family instruction set.
Refer these documents detailed information about chip functionality operation. They found this URL:
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Program Data Memory
Program Data Memory
56F826EVM uses bank Fast Static (GSI GS72116, labeled external memory expansion; FSRAM schematic diagram Figure 2-1. This physical memory bank split into logical memory banks 64Kx16-bits: program memory other data memory. using hybrid controller's program strobe, signal line along with memory chip's signal line, half memory chip selected when program memory accesses requested other half memory chip selected when data memory access requested. This memory bank will operate with zero wait state accesses while 56F826 running 70MHz. However, when running 80MHz, memory bank operates with four wait state accesses. This memory bank disabled removing jumper JG3.
56F826 A0-A15 D0-D15
+3.3V
GS72116 A1-A16 DQ0-DQ15
Jumper 1-2: Enable SRAM Jumper Removed: Disable SRAM
Figure 2-1. Schematic Diagram External Memory Interface
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EEPROM Memory
1Mbit, +3.3V, SPI, serial EEPROM Memory, Atmel AT45DB011-SC, provided 56F826EVM; reference Figure 2-2. This memory connects directly Port through header 56F826. used load program code data into 56F826's internal external memory spaces. jumper block, JG7, provided, which allows user disconnect on-board EEPROM from port connect port peripheral. header details shown Table 2-1.
EEPROM Enable 56F826 MOSI MISO
Serial EEPROM
SCLK GPIOF7
(SPI Port Connector)
Figure 2-2. EEPROM Memory Block Diagram
Table 2-1. Port Connector Description
Signal SS/GPIO7 MISO MOSI SCLK Signal
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RS-232 Serial Communications
RS-232 Serial Communications
56F826EVM provides RS-232 interface RS-232 level converter, (Maxim MAX3245EEAI, designated U3). Refer RS-232 schematic diagram Figure 2-3. RS-232 level converter transitions UART's +3.3V signal levels RS-232 compatible signal levels connects host's serial port connector Flow control provided, could implemented using uncommitted GPIO signals. pinout connector listed Table 2-2. RS-232 level converter/transceiver disabled placing jumper JG2.
56F826
RS-232 Level Converter Interface
TXDO RXDO
+3.3V
T1in R1out
T1out R1in
FORCEOFF
Jumper Removed: Enable RS-232 Jumper 1-2: Disable RS-232
Figure 2-3. Schematic Diagram RS-232 Interface
Table 2-2. RS-232 Serial Connector Description
Signal Jumper Jumper Signal Jumper Jumper Jumper
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Clock Source
56F826EVM uses 4.00MHz crystal, connected External Crystal Inputs, EXTAL XTAL. achieve 80MHz maximum operating frequency, 56F826 uses internal multiply input frequency external oscillator source connected hybrid controller using oscillator bypass connectors, JG5; Figure 2-4. input frequency above 4MHz, then EXTAL input should jumpered ground adding jumper between pins input frequency would then injected JG5's hybrid controller needs synchronized codec's sample frequency, then controller's input frequency should jumpered using 12.2280MHz codec frequency. input frequency below 4MHz, then input frequency injected JG4's
EXTERNAL OSCILLATOR HEADERS
4.00MHz
56F826
EXTAL
12.2880MHz
XTAL
Figure 2-4. Schematic Diagram Clock Interface
Operating Mode
56F826EVM provides boot-up MODE selection jumper, JG6. This jumper used select operating mode hybrid controleer exits RESET. Refer DSP56F826 User's Manual complete description chip's operating modes. Table shows operating modes available 56F826.
Table 2-3. Operating Mode Selection
Operating Mode Jumper Comment Bootstrap from internal memory Bootstrap from external memory
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Debug Support
Debug LEDs
on-board Light-Emitting Diodes (LEDs) provided allow real-time debugging user programs. These LEDs will allow programmer monitor program execution without having stop program during debugging; refer Figure 2-5. User LED1 controlled Port signal. User LED2 controlled PB1. User LED3 controlled PB2. User LED4 controlled PB3. User LED5 controlled PB4. User LED6 controlled PB5. Setting PB0, PB1, PB2, PB3, Logic value will turn associated LED.
56F826
INVERTING BUFFER
+3.3V
YELLOW
GREEN
YELLOW
GREEN
Figure 2-5. Schematic Diagram Debug Interface
Debug Support
56F826EVM provides on-board Parallel JTAG Host Target Interface JTAG interface connector external Target Interface support. interface connectors provided support each these debugging approaches. These connectors designated JTAG connector Host Parallel Interface Connector.
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2.8.1 JTAG Connector
JTAG connector 56F826EVM allows connection external Host Target Interface downloading programs working with 56F826's registers. This connector used communicate with external Host Target Interface which passes information data back forth with host processor running debugger program. Table shows pin-out this connector.
Table 2-4. JTAG Connector Description
Signal RESET +3.3V Signal TRST
When this connector used with external Host Target Interface, parallel JTAG interface should disabled placing jumper jumper block JG1. Reference Table this jumper's selection options.
Table 2-5. Parallel JTAG Interface Disable Jumper Selection
jumpers Comment On-board Parallel JTAG Interface Enabled Disable on-board Parallel JTAG Interface
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Debug Support
2.8.2 Parallel JTAG Interface Connector
Parallel JTAG Interface Connector, allows 56F826 communicate with Parallel Printer Port Windows reference Figure 2-6. using this connector, user download programs work with 56F826's registers. Table shows pin-out this connector. When using parallel JTAG interface, jumper should removed, shown Table 2-5.
Parallel JTAG Interface
+3.3V
56F826 TRST RESET
P_TRST P_RESET
DB-25 Connector
Jumper Removed: Enable JTAG Jumper 1-2: Disable JTAG
Figure 2-6. Block Diagram Parallel JTAG Interface
Table 2-6. Parallel JTAG Interface Connector Description
Signal PORT_RESET PORT_TMS PORT_TCK PORT_TDI PORT_TRST PORT_IDENT Signal PORT_IDENT
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Table 2-6. Parallel JTAG Interface Connector Description
Signal PORT_VCC PORT_TDO PORT_CONNECT Signal
External Interrupts
on-board push-button switches provided external interrupt generation, shown Figure 2-7. allows user generate hardware interrupt signal line IRQA. allows user generate hardware interrupt signal line IRQB. These switches allow user generate interrupts user-specific programs.
+3.3V
56F826
0.1µF +3.3V
IRQA
0.1µF
IRQB
Figure 2-7. Schematic Diagram User Interrupt Interface
2-10
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Reset
2.10 Reset
Logic provided 56F826 generate internal Power-On RESET. Additional reset logic provided support RESET signals from JTAG connector, Parallel JTAG Interface user RESET push-button; refer Figure 2-8.
JTAG_RESET
RESET
RESET PUSHBUTTON MANUAL RESET
TRST JTAG_TAP_RESET
Figure 2-8. Schematic Diagram RESET Interface
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2-11
2.11 Power Supply
main power input, +12.0V 56F826EVM through 2.1mm coax power jack. optional +5.0V power supply input available through 2-pin terminal block, TB1. 1.2A power supply provided with 56F826EVM; however, less than 500mA required EVM. remaining current available user's custom daughter card application, when connected daughter card interface. power regulation 56F826EVM provides +5.0V voltage regulation codec's analog circuits additonal voltage regulation logic EVM. additional voltage regulation logic provides +2.5V voltage regulation hybrid controller's core +3.3V voltage regulation controller's I/O, memory, parallel JTAG interface supporting logic; refer Figure 2-9. Power applied 56F826EVM indicated with Power-On LED, referenced LED7.
+12.0V
+5.0V Regulator
Power Condition
+5.0V Analog
CODEC
+5.0V
+3.3V Regulator
+3.3
56F826
56F826EVM PARTS
+2.5V Regulator
+2.5V
56F826 CORE
Figure 2-9. Schematic Diagram Power Supply
2-12
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Stereo Codec
2.12 Stereo Codec
16-bit audio quality stereo codec, Crystal Semiconductor CS4218, connected 56F826's port support audio, voice signal analysis applications. codec clocked with 12.288MHz oscillator allowing codec operate between sample frequency 8kHz 48kHz. sample rate manually using appropriate switch positions switch This three position switch makes sample rate selections detailed Table possible. codec supports +3.3V digital levels, eliminating need voltage level translation circuitry. Additionally, zero resistors provided allow user disconnect on-board codec from port connect codec port; Figure 2-11. on-board codec analog signal-conditioning logic, allowing direct connection line level input line level output signals through 1/8" stereo jacks; reference Figure 2-10.
Table 2-7. Codec Sample Rate Selector
Position (MF6) Position (MF7) Position (MF8) Sample Rate
48.00kHz 32.00kHz 24.00kHz 19.20kHz 16.00kHz 12.00kHz 9.60kHz 8.00kHz
2.12.1 Analog Input/Output
56F826EVM uses jacks line level stereo input, line level stereo output stereo headphone output. National Semiconductor LM4880 provides drive required headphones. This device offers THD, which superior CS4218's on-chip headphone drive circuitry factor two. basic analog codec connections shown Figure 2-10.
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2-13
CS4218 Line Level Input RIN1 LIN1
LOUTL LOUTR
Line Level Output
LM4880
Headphone Output
Figure 2-10. Codec Analog Connections
2.12.2 Digital Interface
serial interface codec transfers digital audio data control data into device. port, which consists independent transmitter receiver sections, used serial communication with codec. hybrid controller side, Serial Transmit Data, STD, output when data being transmitted codec. Serial Receive Data, SRD, input when data being received from codec. These pins connected codec Serial Data Input, SDIN, Serial Data Output, SDOUT, pins. hybrid controller's Transmit Serial Clock, STCK, provides serial rate clock interface. connected codec Serial Port Clock, SCLK, pin. Data transmitted rising edge SCLK received falling edge SCLK. hybrid controller's GPIO PORT pin, PD0, programmed control codec's Active Reset, RESET, signal. Serial Transmit Frame Sync pin, STFS, programmed control codec's Frame Sync, FSYNC, signal. FSYNC sampled SCLK, with rising edge indicating that frame about start. FSYNC frequency always system's sample rate. input codec, output from codec data mode. basic codec digital connections shown Figure 2-11. codec's MODE three MODE selection resistors, R96-R98. factory default setting MODE codec Master with data word bits frame; i.e., bits, Left channel bits, Right channel. sample rate selected Sample Rate Selector switch reference Table selection options. Codec control information sent over separate serial port using:
2-14 56F826 Evaluation Module Hardware User's Manual More Information This Product, www.freescale.com MOTOROLA
Daughter Card Connectors
Control Chip Select, CCS, signal; Control Data Input, CDIN, signal; Control Clock, CCLK, signal.
56F826 STCK STFS
CODEC Enable Logic
CS4218 SDIN SDOUT SCLK FSYNC RESET
CDIN CCLK
Figure 2-11. CS4218 Stereo Audio Codec
2.13 Daughter Card Connectors
board contains daughter card expansion connectors. connector, contains hybrid controller's external memory signals. other connector, contains controller's peripheral port signals.
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2-15
2.13.1 Memory Daughter Card Expansion Connector
hybrid controller's external memory signals connected Memory Daughter Card Expansion connector, Table shows port signal assignments.
Table 2-8. Memory Daughter Card Connector Description
Signal +3.3V Signal +3.3V
2-16
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Daughter Card Connectors
Signal Signal
2.13.2 Peripheral Daughter Card Expansion Connector
hybrid controller's peripheral port signals connected Peripheral Daughter Card Expansion connector, Table shows port signal assignments.
Table 2-9. Peripheral Daughter Card Connector Description
Signal CLKO SRFS SCLK MOSI MISO SRCK STFS RESET Signal
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2-17
Table 2-9. Peripheral Daughter Card Connector Description (Continued)
Signal STCK IRQB IRQA +3.3V Signal RXD1 TXD1 RXD0 TXD0 +3.3V
2.14 Test Points
56F826EVM board total seven test points. Three digital test points located corners board. +5.0VA AGND test points located analog corner board. +2.5V +3.3V test points located power supply section board.
2-18
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Appendix 56F826EVM Schematics
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56F826EVM Schematics More Information This Product, www.freescale.com
D[0.15] A[0.15] +3.3V U11A LED1 U11B LED2 U11C LED3 U11D LED4 U11E LED5 EXTAL XTAL MC74AC04AD U11F LED6 +2.5V MC74AC04AD +3.3V +2.5V CLKO /IRQA /IRQB
+3.3V
MC74AC04AD
A0/PE0 A1/PE1 A2/PE2 A3/PE3 A4/PE4 A5/PE5 A6/PE6 A7/PE7 A8/PA0 A9/PA1 A10/PA2 A11/PA3 A12/PA4 A13/PA5 A14/PA6 A15/PA7
YELLOW
MC74AC04AD
MISO MOSI SCLK MISO/PF6 MOSI/PF5 SCLK/PF4 SS/PF7 TXD0/SCLK0 RXD0/MOSI0
TXD0 RXD0
GREEN
MC74AC04AD
TXD1 RXD1 TXD1/MISO0 RXD1/SS0 SRD/PC0 STD/PC3 STFS/PC4 SRFS/PC1 STCK/PC5 SRCK/PC2
STFS SRFS STCK SRCK
MC74AC04AD
/RESET RESET XBOOT EXTAL XTAL CLKO IRQA IRQB VDDA VSSA VDD1 VDD2 VDD3 VDD4 VDDC1 VDDC2 VDDC3
XBOOT
TA0/PF0 TA1/PF1 TA2/PF2 TA3/PF3
YELLOW
/TRST TRST GND1 GND2 GND3 GND4 GND5 GND6 GND7
GREEN
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DSP56F826BU80 Title Size
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
DSP56F826 Processor DEBUG LEDS Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer: DSPD Design Sheet
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Figure A-1. 56F826 Processor
+3.3V EXTAL
MOTOROLA
IRQA PUSHBUTTON
/IRQA 0.1uF XTAL +3.3V
BYPASS
4.00MHz 12.288MHZ
>8MHZ IRQB PUSHBUTTON
/IRQB /POR 0.1uF +2.5V 0.1uF
RESET PUSHBUTTON
+3.3V DS1818 /POR XBOOT
BOOT MODE JUMPER BOOT BOOT
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DS1818
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
Title Size
RESET, CLOCK, BOOT MODE IRQS Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
Figure A-2. RESET, MODE, CLOCK IRQS
64Kx16-bit Program 64Kx16-bit Data Memory
D[0.15] A[0.15]
+3.3V
SRAM ENABLE JUMPER OPTION
TP-12 +3.3V
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16
SRAM ENABLE
SRAM DISABLE
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Title Size
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
DATA SRAM MEMORY Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
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Figure A-3. PROGRAM DATA SRAM MEMORY
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+3.3V AT45DB011-SC
RESET /RES EE_SCK EE_SI EE_SO
/EE_CS
MISO MOSI SCLK
EEPROM Enable
+3.3V /RES
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Title Size
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
Serial 1M-Bit EEPROM MEMO Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
Figure A-4. Serial 1M-bit Serial EEPROM Memory
+3.3V VC1C2+ C2GND 1.0uF 1.0uF 1.0uF 1.0uF TXD0 T2IN T3IN RXD0 R2IN R3IN R4IN R5IN T1IN T2IN T3IN T1OUT T2OUT T3OUT
+3.3V T2IN T3IN R2IN R3IN R4IN R5IN
+3.3V FORCEON INVALID FORCEOFF 5EEAI
R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT R1IN R2IN R3IN R4IN R5IN
RS-232 ENABLE
RS-232 CONNECTOR
RS-232 ENABLE
RS-232 DISABLE
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Title Size
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
PORT, RS-232 CONNECTOR Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
MOTOROLA
Figure A-5. PORT, RS-232 Connector
RING_OUT TIP_OUT MODE2 RIN1 LOUT LIN1 0.0022uF 1/8" 0.0022uF 39.2K 39.2K 0.47uF RIN2 0.47uF LIN2 REFBUF 0.47uF 0.1uF REFGND 20.0K
0.33uF +3.3V /PDN 470pF MODE1 ROUT LOUT ROUT
5.62K 5.62K
LOUT 20.0K BYPASS SHUTDN
STFS
CODEC_FSYNC
16.00 12.00 9.60 8.00 19.20 24.00
IN_A BYPASS SHUTDN
OUT_A LM4880M
MOTOROLA
RING_IN
5.62K 470pF 0.33uF
TIP_IN
1/8"
Line-Input Stereo Jack Line Stereo Jack
5.62K /CCS CCLK CDIN
MODE3
/CCS
+3.3V 12.288MHZ REFBY 47uF 10VDC SWODE3 SWODE2 SWODE1 MODE3 MODE2 MODE1
12.288MHZ +3.3V
+3.3V
12.288MHZ /CODEC_RESET /PDN CODEC_FSYNC CODEC_SCLK CODEC_SDOUT CODEC_SDIN CLKIN RESET SSYNC SCLK SDOUT SDIN VDDA GNDA CS4218-KQ +5.0VA
SHUTDN
CODEC_SDIN
20.0K 20.0K IN_B OUT_B RING_PHN TIP_PHN
ROUT
CODEC_SDOUT
Sample Select
48.00 32.00
(KHZ)
STCK
CODEC_SCLK
47uF 10VDC
Headphone Stereo Jack
1/8" +5.0VA 47uF 10VDC
/CODEC_RESET
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SERIAL MODE SELECTED MASTER, 32BITS FRAME MODE1 MODE2
/CCS
CDIN
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
CCLK
Title
MODE3
16-BIT STEREO CODEC Size Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer: DSPD Design Sheet
Figure A-6. 16-bit Stereo Codec
DB25M
Parallel JTAG Interface
PORT_IDENT +3.3V 5.1K
PORT_RESET /J_TRST +3.3V PORT_TDO PORT_CONNECT 5.1K MC74LCX244DW PORT_VCC PORT_TMS PORT_TCK PORT_TDI /PORT_TRST PORT_DE P_RESET
On-Board Host Target Interface Disable
+3.3V /J_RESET /POR 74AC00 2N2222A /J_TRST 74AC00 +3.3V 74AC00 5.1K /TRST 74AC00 /RESET /J_RESET 5.1K /J_RESET +3.3V /J_TRST
P_RESET
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/POR /J_TRST
JTAG Connector
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
Title Size
PARALLEL JTAG HOST TARGET INTERFACE JTAG CONNECTOR Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer: DSPD Design Sheet
MOTOROLA
Figure A-7. Parallel JTAG Host Target Interface JTAG Connector
MOTOROLA
/CS1 SRFS SCLK MOSI MISO SRCK STFS /RESET
CLKO
/CS0 /CS2 +3.3V +3.3V STCK /IRQB /IRQA
RXD1 TXD1 RXD0 TXD0 +3.3V
/CS3 +3.3V
Daughter Address/Data Connector
Daughter Peripheral Port Connector
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Title Size
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
DAUGHTER CARD EXPANSION CONNECTORS Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
Figure A-8. Daughter Card Expansion Connectors
A-10
EXTERNAL POWER INPUT 7-12VDC/AC
FM4001 FERRITE BEAD MC33269DT-3.3 VOUT VOUT 0.1uF 47uF 10VDC VOUT VOUT 470uF 16VDC +5.0V FM4001
+3.3V
FM4001 MC33269DT-ADJ +5.0VA 0.1uF VOUT VOUT 0.1uF
+5VDC INPUT
+5.0V
+2.5V FERRITE BEAD 47uF 10VDC
+5.0V
Rlow
FERRITE BEAD
Vout 1.25( (Rhigh/Rlow))
47uF 10VDC
Rhigh
FERRITE BEAD
Rhigh 1.8V Rhigh 2.5V
+3.3V
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5.0V, 3.3V REGULATOR
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
LED7
Title Size
UPPLIES Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
Rev. Designer:
POWER GOOD
MC33269
MOTOROLA
Figure A-9. Power Supplies
DSP56F826
+2.5V 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF +2.5V +2.5V +2.5V +3.3V +3.3V +3.3V +3.3V
0.01uF
0.1uF
0.01uF
+5.0VA TEST POINT
+3.3V TEST POINT
+2.5V TEST POINT
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+3.3V 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF 0.1uF +3.3V +3.3V +3.3V +3.3V +3.3V
Standard Products Division
2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510
Title Size
BYPASS CAPS Document Number DSP56F826EVM.DSN Date: Sunday, April 2001
MOTOROLA
AT45DB011 74AC04 74AC00 DS1818 MAX3245 74LCX244 LM4880
+5.0VA
+2.5V
+3.3V
0.01uF
0.1uF
GS72116
+3.3V
+3.3V
0.01uF
0.1uF
0.1uF
CS4218
+5.0VA +3.3V
ANALOG GROUND TEST POINT
GROUND TEST POINTS
+3.3V +2.5V
+3.3V
+3.3V
Rev. Designer:
A-11
Figure A-10. Bypass Caps
A-12
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MOTOROLA
Appendix 56F826EVM Bill Material
Description Ref. Designators Integrated Circuits DSP56F826BU80 GS72116 MAX3245 AT45DB011 CS4218 LM4880 12.288MHZ 74LCX244 74AC00 +3.3V Voltage Regulator 74AC04 +2.5V Voltage Regulator +5.0V Voltage Regulator Resistors 5.1K 5.62K R11, R10, R12, R20, R23, R24, R21, SMEC, RC73L2A10MOHMJT SMEC, RC73L2A470OHMJT SMEC, RC73L2A270OHMJT SMEC, RC73L2A47KOHMJT Motorola, DSP56F826BU80 GSI, GS72116TP-12 Maxim, MAX3245EEAI Atmel, AT45DB011-SC Crystal Semiconductor, CS4218-KQ National Semiconductor, LM4880M Epson, SG-531P-12.288MC Semiconductor, MC74LCX244ADW Fairchild, 74AC00SC Semiconductor, MC33269DT-3.3 Semiconductor, MC74AC04AD Semiconductor, MC33269DT-ADJ Semiconductor, MC33269DT-5 Vendor Part
SMEC, RC73L2A5.1KOHMJT SMEC, RC73L2A51OHMJT SMEC, RC73L2A5.62KOHMFT
MOTOROLA
56F826EVM Bill Material More Information This Product, www.freescale.com
Description
Ref. Designators Resistors (Continued)
Vendor Part
39.2K
R34, R36, R37, R45, R67, R72, R85, R87, R40, R41, R62, R68, R69, R54, R88, R89, R96, R94, Inductors
SMEC, RC73L2A39.2KOHMFT SMEC, RC73L2A10KOHMJT
20.0K
SMEC, RC73L20.0KOHMFT SMEC, RC73L2A1KOHMJT
SMEC, RC73JP2A
SMEC, RC73L243OHMFT
1.0mH FERRITE BEAD
LEDs
Panasonic, EXC-ELSA35V
Yellow Green
LED1, LED4 LED2, LED5 LED3, LED6, LED7 Diode
Hewlett-Packard, HSMS-C650 Hewlett-Packard, HSMY-C650 Hewlett-Packard, HSMG-C650
S2B-FM401 Bridge Rectifier
Vishay, DL4001DICT General Semiconductor, DF02S
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MOTOROLA
Description
Ref. Designators Capacitors
Vendor Part
470µF, 0.1µF
C22, C32, C34, C36, C38, C40, C42, C44, C46, C48, C50, C51, C53, C23, C24, C56, C10, C11, C13, C19, C20, C15, C17, C18, C33, C35, C37, C39, C41, C43, C45, C52,
ELMA, RV-16V471MH10R SMEC, MCCE104K2NR-T1
47µF, 0.33µF 470pF 1.0µF,
ELMA, RV2-16V470M-R SMEC, MCCE334K3NR-T1 SMEC, MCCE471J2NO-T1 SMEC, MCCE105K3NR-T1
0.0022µF 0.47µF 0.01µF
SMEC, MCCE222K2NR-T1 SMEC, MCCE474K3NR-T1 SMEC, MCCE103K2NR-T1
Description
Ref. Designator Jumpers
Vendor Part
Bergstick Bergstick Bergstick
JG1, JG2, JG3, JG4, Test Points
SAMTEC, TSW-102-07-S-S SAMTEC, TSW-103-07-S-S SAMTEC, TSW-104-07-S-D
Bergstick
Crystals
Samtec, TSW-101-07-S-S
4.00MHz Crystal
Connectors
CTS, ATS04ASM-T
2.1mm coax Power Connector DB25M Connector
Switchcraft, RAPC-722 AMPHENOL, 617-C025P-AJ121
MOTOROLA
56F826EVM Bill Material More Information This Product, www.freescale.com
Description DE9S Connector 1/8" Stereo Jack 51-Pin Connector Bergstick 2-Pin Terminal Block
Ref. Designator Switches
Vendor Part AMPHENOL, 617-C009S-AJ120 Switchcraft, 35RAPC4BHN2 BERG, 91930-21151 SAMTEC, TSW-107-07-S-D On-Shore Technology, ED500/2DS
SPST Pushbutton 3-Position
Transistors
Panasonic, EVQ-PAD05R CTS, 209-3LPST
2N2222A
Miscellaneous
ZETEX, FMMT2222ACT
Shunt Rubber Feet
SH1-SH8 RF1-RF4
Samtec, SNT-100-BL-T SJ5018BLKC
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MOTOROLA
Index
Numerics
1.2A Power Supply 2-12 16-bit +2.5V/+3.3V hybrid processor 16-bit Stereo Codec Interface 1Mbit Serial EEPROM 4.00MHz Crystal Oscillator 56F826 Technical Data 56F826/827 User's Manual 64Kx16 bits Data Memory 64Kx16 bits Program Memory
Host Parallel Interface Connector Host Target Interface
Integrated Circuit
codec Coder/Decoder codec Connectors Peripheral Expansion 2-16
Joint Test Action Group JTAG 1-1, Connector JTAG JTAG Port Interface Jumper Group
Data Memory Daughter Card Expansion Interface Debugging DSP56800 Family Manual
EEPROM EEPROM Electrically Erasable Programmable Read-Only Memory Evaluation Module
Low-Profile Quad Flat Pack LQFP LQFP
MPIO MPIO Multi-Purpose Input Output port
FSRAM 2-1,
On-Board Power Regulation OnCE OnCE OnCE(TM)
General Purpose Input Output GPIO GPIO
MOTOROLA
Index More Information This Product, www.freescale.com
On-Chip Emulation Operating Mode Optional External Oscillator Frequency Input
Parallel JTAG Host Target Interface Peripheral Connectors 2-15 Phase Locked Loop Printed Circuit Board Program Memory
Random Access Memory Read-Only Memory Real-Time Debugging RS-232 Interface Level Converter Schematic Diagram RS-232 Interface RS-232 Serial Communications
Serial Communications Interface Serial Peripheral Interface SRAM External Data External Program SRAM Static Random Access Memory Stereo 16-bit Codec Interface Stereo Headphone Interface Synchronous Serial Interface
Wait State 56F826 Evaluation Module User's Manual More Information This Product, www.freescale.com MOTOROLA
MOTOROLA
Index More Information This Product, www.freescale.com
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MOTOROLA
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Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. 2003. reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
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DSP56826EVMUM/D

56F826 Evaluation Module Hardware User's Manual Motorola, Inc., 2

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