Major Difference FLASH BYTES) (BYTES) (CPU BUS) Pa
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MX10EXA
Major Difference
FLASH BYTES)
(BYTES)
(CPU BUS)
Package
MX10EXAQC MX10EXAUC MX10EXAQCG MX10EXAUCG 2048 PLCC LQFP
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MX10EXA
16-bit Microcontroller Family Flash/2K RAM, Watchdog, 2UARTs
FEATURE
4.5V 5.5V bytes on-chip Flash program memory with InSystem Programming capability Five Flash blocks byte blocks three byte blocks Single supply voltage In-System Programming Flash memory, (VPP=VDD VPP=12V desired) Boot contains level Flash programming routines In-Application Programming default serial loader using UART 2048 bytes on-chip data Supports off-chip program data addressing megabyte address lines) Three standard counter/timers with enhanced features timers have toggle output capability Watchdog timer enhanced UARTs with independent baud rates Seven software interrupts Four 8-bit ports, with programmable output configurations each operating frequency Power saving operating modes: Idle PowerDown.Wake-Up from power-down external interrupt supported. 44-pin PLCC (MX10EXAQC) Commercial grade 44-pin LQFP (MX10EXAUC) Commercial grade 44-pin PLCC (MX10EXAQI) Industrial grade 44-pin LQFP (MX10EXAUI) Industrial grade
GENERAL DESCRIPTION
MX10EXA member Philips' 80C51 (eXtended Architecture) family high performance 16bit single-chip microcontrollers. MX10EXA contains bytes Flash program memory, provides three general purpose timers/ counters, watchdog timer, dual UARTs, four general purpose ports with programmable output configurations.
default serial loader program Boot allows In-System Programming (ISP) Flash memory without need loader Flash code. User programs erase reprogram Flash memory will through standard routines contained Boot (In-Application Programming).
CONFIGURATIONS
P1.0/A0/WRH P1.0/A0/WRH P0.0/A4D0 P0.1/A5D1 P0.2/A6D2 P0.3/A7D3 P0.0/A4D0 P0.1/A5D1 P0.2/A6D2 P0.3/A7D3 P1.4/RxD1 P1.4/RxD1
PLCC
LQFP
P1.3/A3
P1.2/A2
P1.1/A1
P1.3/A3
P1.2/A2
P1.1/A1
P1.5/TxD1 P1.6/T2 P1.7/T2EX P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/BUSW
P0.4/A8D4 P0.5/A9D5 P0.6/A10D6 P0.7/A11D7 EA/VPP/WAIT
P1.5/TxD1 P1.6/T2 P1.7/T2EX P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/BUSW
P0.4/A8D4 P0.5/A9D5 P0.6/A10D6 P0.7/A11D7 EA/VPP/WAIT
MX10EXAQC
PSEN P2.7/A19D15 P2.6/A18D14
MX10EXAUC
PSEN P2.7/A19D15 P2.6/A18D14
P3.6/WRL P3.7/RD XTAL2 XTAL1
P2.0/A12D8 P2.1/A13D9 P2.2/A14D10 P2.3/A15D11
P2.4/A16D12
P2.5/A17D13
P2.0/A12D8 P2.1/A13D9 P2.2/A14D10 P2.3/A15D11 P3.6/WRL P3.7/RD XTAL2 XTAL1
P2.4/A16D12
P2.5/A17D13
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MX10EXA
BLOCK DIAGRAM
Core
Program Memory Bytes FLASH 2048 Bytes Static Port Data
UART0
UART1
Timer
Port Timer Port Port Watchdog Timer
LOGIC SYMBOL
XTAL1 T2EX* TxD1 RxD1 A0/WRH
PORT
XTAL2
PORT
ALTERNATE FUNCTIONS
RxD0 TxD0 INT0 INT1 T1/BUSW
AVAILABLE 40-PIN PACKAGE
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PORT
ADDRESS DATA
EA/WAIT PSEN
PORT
ADDRESS
MX10EXA
DESCRIPTIONS
MNEMONIC P0.0-P0.7 PIN. PLCC LQFP 16,39 17,38 43-36 37-30 TYPE NAME FUNCTION Ground: reference. Power Supply: This power supply voltage normal, idle, power down operation. Port Port 8-bit port with user-configurable output type. Port latches have written them configured quasibidirectional mode during reset. operation port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer section port configuration Electrical Characteristics details. When external program/data used, Port becomes multiplexed data/instruction byte address lines through Port Port 8-bit port with user-configurable output type. Port latches have written them configured quasibidirectional mode during reset. operation port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer section port configuration Electrical Characteristics details. Port also provides special functions described below. A0/WRH: Address external address when external data configured width. When external data configured width, this becomes high byte write strobe. Address external address bus. Address external address bus. Address external address bus. RxD1 (P1.4): Receiver input serial port TxD1 (P1.5): Transmitter output serial port (P1.6): Timer/counter external count input/clockout. T2EX (P1.7): Timer/counter reload/capture/direction control Port Port 8-bit port with user-configurable output type. Port latches have written them configured quasibidirectional mode during reset. operation port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer section port configuration Electrical Characteristics details. When external program/data used 16-bit mode, Port becomes multiplexed high data/instruction byte address lines through When external program/data used 8-bit mode, number address lines that appear port user programmable.
P1.0-P1.7
40-44,
P2.0-P2.7
24-31
18-25
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MX10EXA
MNEMONIC P3.0-P3.7 PIN. PLCC LQFP 11,13-19 5,7-13 TYPE NAME FUNCTION Port Port 8-bit port with user configurable output type. Port latches have written them configured quasibidirectional mode during reset. operation port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer section port configuration Electrical Characteristics details. Port also provides various special functions described below. RxD0 (P3.0): Receiver input serial port TxD0 (P3.1): Transmitter output serial port INT0 (P3.2): External interrupt input. INT1 (P3.3): External interrupt input. (P3.4): Timer external input, timer overflow output. T1/BUSW (P3.5): Timer external input, timer overflow output. value this latched external reset input released defines default external data width (BUSW). 8-bit 16-bit bus. (P3.6): External data memory byte write strobe. (P3.7): External data memory read strobe. Reset: this resets microcontroller, causing ports peripherals take their default states, processor begin execution address contained reset vector. Refer section Reset details. Address Latch Enable: high output signals external circuitry latch address portion multiplexed address/data bus. pulse occurs only when needed order process cycle. Program Store Enable: read strobe external program memory. When microcontroller accesses external program memory, PSEN driven order enable memory devices. PSEN only active when external code accesses performed. External Access/Wait/Programming Supply Voltage: input determines whether internal program memory microcontroller used code execution. value latched external reset input released applies during later execution. When latched external program memory used exclusively, when latched internal program memory will used limit, external program memory used above that point. After reset released, this takes function Wait input. Wait asserted high during external access, that cycle will extended until Wait released. During EPROM programming, this also programming supply voltage input. Crystal Input inverting amplifier used oscillator circuit input internal clock generator circuits. Crystal Output from oscillator amplifier.
PSEN
EA/WAIT /VPP
XTAL1 XTAL2
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MX10EXA
SPECIAL FUNCTION REGISTERS
NAME DESCRIPTION
ADDRESS
FUNCTIONS ADDRESSES
ENBOOT FMIDLE PWR_VLD
Reset
VALUE
AUXR BTRH BTRL
Auxiliary function register configuration register
-DW1
-DW0
WAITD BUSD
Note
timing register high byte timing register byte Code segment Data segment Extra segment
DWA1 DWA0 ALEW -CR1
DRA1 DRA0 CRA1 CRA0
IEH* Interrupt enable high byte -337 IEL* IPA0 IPA1 IPA2 IPA4 IPA5 Interrupt enable byte Interrupt priority Interrupt priority Interrupt priority Interrupt priority Interrupt priority -387 Port Port T2EX Port P2.7 Port
-336
-335 -PT0 -PTI0 PTI1
-334
ETI1
ERI1
ETI0 PRI0 PRI1
ERI0 P2.0 RxD0
P2.6
TxD1 P2.5
RxD1 P2.4
P2.3 INT1
P2.2 INT0
P2.1 TxD0
P0CFGA Port configuration P1CFGA Port configuration P2CFGA Port configuration P3CFGA Port configuration P0CFGB Port configuration P1CFGB Port configuration P2CFGB Port configuration P3CFGB Port configuration
Note Note Note Note Note Note Note Note
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MX10EXA
NAME DESCRIPTION FUNCTIONS ADDRESSES -20E -20D -20C -20B -20A Note Reset VALUE
address
PCON* Power control register -20F PSWH* Program status word (high byte) PSWL* Program status word (low byte) PSW51* 80C51 compatible RTH0 RTH1 RTL0 RTL1 Timer extended reload, high byte Timer extended reload, high byte Timer extended reload, byte Timer extended reload, byte S0CON* Serial port control register
Note
Note
RI_0
STINT0
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 -30D -30C -30B
S0STAT* Serial port extended status S0BUF Serial port buffer register
S0ADDR Serial port address register S0ADEN Serial port address enable register S1CON* Serial port control register RI_1
SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 -32D -32C -32B
S1STAT* Serial port extended status S1BUF Serial port buffer register
STINT1
S1ADDR Serial port address register S1ADEN Serial port address enabler register
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MX10EXA
NAME DESCRIPTION FUNCTIONS ADDRESSES -21E -21D -21C Reset VALUE
address
System configuration register
-21F
SSEL*
Segment selection register Software Interrupt Enable
ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG
-357
SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1
SWR*
Software Interrupt Request
-2C7
SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 C/T2
CP/RL2
T2CON* Timer control register
EXF2 RCLK0 TCLK0 EXEN2 -2CD
T2MOD* Timer mode control Timer high byte Timer byte
RCLK1 TCLK1
T2OE DCEN
T2CAPH Timer capture register, high byte T2CAPL Timer capture register, byte
TCON* TMOD Timer control register Timer high byte Timer high byte Timer byte Timer byte Timer mode control GATE TSTAT*
Timer extended status
-2FE
-2FD
-2FC
GATE -2FB -28A T1OE
WDRUN
-2F9
WDTOF
-2FF
T0OE
WDCON* Watchdog control register Watchdog timer reload
PRE2
PRE1 PRE0
Note
WFEED1 Watchdog feed WFEED2 Watchdog feed
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MX10EXA
NOTES: SFRs addressable. reset, register loaded with binary value 0000 0a11, where value BUSW pin. This defaults address size bits, Since MX10EXA only address lines. loaded from reset vector. bits except loaded from reset vector. Those bits Unimplemented bits SFRs (unknown) times. Ones should written these bits since they used other purposes future derivatives. reset value shown these bits Port configurations default quasi-bidirectional when begins execution from internal code memory after reset, based condition found pin. Thus PnCFGA registers will contain PnCFGB registers will contain When begins execution using external code memory, default configuration pins that associated with external will push-pull. PnCFGA PnCFGB register contents will reflect this difference. WDCON reset value Watchdog reset, other reset causes. MX10EXA implements 8-bit bus. accesses must 8-bit operations. Attempts write bits will actually write only lower bits. Sixteen reads will return undefined data upper byte. AUXR reset value typically 00h. Boot Loader activated reset because Flash status byte nonzero because Boot Vector been forced PSEN reset), AUXR reset value will 1x00 0000b. will on-chip generator running ready, otherwise will
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MX10EXA
FFFFFh
BYTES TOTAL CODE MEMORY
10000h FFFFh BYTEs ON-CHIP CODE MEMORY 0000h
FFFFh BYTE BOOT F800h
Note:The Boot replaces bytes Flash memory when enable xxx.
Figure Program Memory
Data Segment FFFFFh FFFFFh
Other Data Segments
DATA MEMORY (INDIRECTLY ADDRESSED, OFF-CHIP) DATA MEMORY (INDIRECTLY ADDRESSED, OFF-CHIP) 0800h 07FFh DATA MEMORY (INDIRECTLY ADDRESSED, CHIP) 0400H 03FFh BYTES ON-CHIP DATA MEMORY (RAM) DATA MEMORY (DIRECTLY INDIRECTLY ADDRESSABLE, CHIP) 0040h 003Fh DIRECTLY ADDRESSED DATA SEGMENT) 0040h 003Fh 0400H 03FFh DATA MEMORY (DIRECTLY INDIRECTLY ADDRESSABLE, OFF-CHIP)
BIT-ADDRESSABLE DATA AREA DATA MEMORY (DIRECTLY INDIRECTLY ADDRESSABLE, CHIP)
BIT-ADDRESSABLE DATA AREA DATA MEMORY (DIRECTLY INDIRECTLY ADDRESSABLE, OFF-CHIP)
0020h 001Fh
0020h 001Fh
0000h
0000h
Figure Data Memory
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MX10EXA
FLASH EPROM MEMORY GENERAL DESCRIPTION
Flash memory augments EPROM functionality with in-circuit electrical erasure programming. Flash read written bytes. Chip Erase operation will erase entire program memory. Block Erase function erase single Flash block. In-circuit programming standard parallel programming both available. On-chip erase write timing generation contribute user friendly programming interface. Flash reliably stores memory contents even after 10,000 erase program cycles. cell designed optimize erase programming mechanisms. addition, combination advanced tunnel oxide processing internal electric fields erase programming operations produces reliable cycling. InSystem Programming, single power supply. Faster In-system Programming obtained, required, through a+12V supply. Parallel programming (using separate programming hardware) uses a+12V supply.
FEATURES
Flash EPROM internal program memory with Block Erase. Internal byte fixed boot ROM, containing low-level programming routines default loader. Boot turned provide access full byte Flash memory. Boot vector allows user provided Flash loader code reside anywhere Flash memory space. This configuration provides flexibility user. Default loader Boot allows programming serial port without need user provided loader. 1Mbyte external program memory internal program memory disabled(EA=0). Programming erase voltage ISP, parallel programming.Using improve programming erase time. Read/Programming/Erase: Byte-wise read access time Byte Programming (1-2 minutes flash, depending clock frequency). In-circuit programming user selected method, typically RS232 parallel port interface. Programmable security code Flash 10,000 minimum erase/program cycles year minimum data retention.
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MX10EXA
Flash organization contains bytes Flash program memory. This memory organized separate blocks. first blocks bytes size, filling program memory space from address through 3FFF hex. final three blocks bytes size occupy addresses from 4000 through FFFF hex. Figure depicts Flash memory configuration. ENBOOT PWR_VLD Setting ENBOOT AUXR register enables Boot activates on-chip generator connected rather than externally. PWR_VLD flag indicates that available programming erase operations. This flag should checked prior calling Boot programming erase services. When ENBOOT set, typically takes microseconds internal programming voltage ready. ENBOOT will automatically status byte non-zero during reset, when PSEN low, high, high falling edge reset. Otherwise, ENBOOT will cleared during reset. When programming functions needed, ENBOOT cleared. This enables access bytes Flash code memory that overlaid Boot ROM, allowing full bytes Flash cede memory.
Flash Programming Erasure Flash microcontroller supports number programming possibilities on-chip Flash memory. Flash memory programmed parallel fashion standard programming equipment manner similar EPROM microcontroller. microcontroller able program Flash memory while application code running. Also, default loader built into Boot allows programming blank devices serially through UART. Using these types programming, individual blocks erased separately, entire chip erased. Programming Flash memory accomplished byte time.
FFFF BOOT BLOCK BYTES
FFFF F800
C000
Boot When microcontroller programs Flash memory, level details handled code that permanently contained byte "Boot ROM" that separate from Flash memory. user program simply calls entry point with appropriate parameters accomplish desired operation. Boot operations include things like: erase block, program byte, verity byte, program security lock bit, etc. Boot overlays program memory space address space from F800 FFFF hex, when enabled setting ENBOOT AUXR1.7. Boot turned that upper bytes Flash program memory accessible execution.
BLOCK BYTES
PROGRAM ADDRESS
8000
BLOCK BYTES
4000
BLOCK BYTES
2000 BLOCK BYTES 0000
Figure Flash Memory Configuration
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MX10EXA
FMIDLE
FMIDLE AUXR register allows saving additional power turning Flash memory when Idle mode. This must done just prior initiating Idle mode, shown below. AUXR, #$40 ;Set Flash memory idle mode. PCON, #$0l ;Turn Idle mode. ;Execution resumes here when Idle mode terminates. When Flash memory into Idle mode setting FMIDLE, restarting upon exiting Idle mode takes slightly longer, about microseconds. However, standby current consumed Flash memory reduced from about about 1mA. NOTE: When erasing Status Byte Boot Vector, these bytes erased same time. necessary reprogram Boot Vector after erasing updating Status Byte.
Hardware Activation Boot Vector Program execution Boot Vector also forced from outside microcontroller setting correct state pins. While Reset asserted, PSEN must pulled low, allowed float high (need pulled externally), driven logic high VPP). Then reset released. This same effect having non-zero status byte. This allows building application that will normally execute user's code manually forced into operation. Boot enabled when Boot Vector forced described above, branch default loader. Conversely, user code bytes Flash memory executed when Boot Vector used. factory defauolt setting (F800h) changed, will longer point masked-ROM boot loader code. this happens, only possible change contents Boot Vector through parallel programming method, provided that user application does contain customized loader that provides erasing reprogramming Boot Vector Status Byte. After programming FLASH, status byte should erased zero order allow execution user's application code beginning address 0000H.
Default Loader
default loader that accepts programming commands predetermined format contained permanently Boot ROM. factory fresh device will enter this loader automatically powered without first being programmed user. Loader commands include functions such erase block; program Flash memory; read Flash memory; blank check.
Boot Vector
contains special FLASH registers: BOOT VECTOR STATUS BYTE. "Boot Vector" allows forcing execution user supplied Flash loader upon reset, under specific sets conditions. falling edge reset, examines contents Status Byte. Status Byte zero, power-up execution starts location 0000H, which normal start address user's application code. When Status Byte value other than zero, Boot Vector used reset vector bytes), including Boot Program Counter (BPC) Boot (BPSW). factory default settings 8000h BPSW F800h BPC, which corresponds address F900h factory masked-ROM boot loader. Status Byte automatically non-zero value when programming error occurs. custom boot loader written with Boot Vector custom boot loader.
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MX10EXA
WITH WINISP XTAL2
TRANSCEIVER MC145406, MAX232, EQUIVALENT +12V±5% SUPPLY
XTAL1
FEMALE
Figure In-System Programming with Minimum Pins
In-System Programming (ISP)
In-System Programming (ISP) performed without removing microcontroller from system. In-System Programming (ISP) facility consists series internal hardware resources coupled with internal firmware facilitate remote programming through serial port. In-System Programming (ISP) facility made incircuit programming embedded application possible with minimum additional expense components circuit board area. function uses five pins: TxD, RxD, VSS, (see Figure Only small connector needs available interface your application external circuit order this feature. supply should adequately decoupled allowed exceed data sheet limits. feature allows wide range baud rates used application, independent oscillator frequency. also adaptable wide range oscillator frequencies. This accomplished measuring bit-time single received character. This information then used program baud rate terms timer counts based oscillator frequency. feature requires that initial character lowercase sent establish baud rate. firmware provides auto-echo received characters. Once baud rate initialization been performed, firmware will only accept specific Intel Hex-type records. Intel records consist ASCII characters used represent hexadecimal values summarized below: :NNAAAARRDD.DDCC<crlf> Intel record, "NN" represents number data bytes record. will accept (10H) data bytes. "AAAA"" string represents address first byte record. there zero bytes record, this field often 0000. "RR" string indicates record type. record type "00" data record. record type "01" indicates
Using In-System Programming (ISP)
mode entered holding PSEN low, asserting, un-asserting RESET, then releasing PSEN. When mode entered, default loader first disables watchdog timer prevent watchdog reset from occurring during programming.
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MX10EXA
end-of-file mark. this application, additional record types will added indicate either commands data facility. maximum number data bytes record limited (decimal). commands summarized Table record received information record stored internally checksum calculation performed. operation indicated record type performed until entire record been received. Should error occur checksum, will send serial port indicating checksum error. checksum calculation found match checksum record, then command will executed. most cases, successful reception record will indicated transmitting character serial port (displaying contents internal program memory exception). case Data Record (record type 00), additional check made. character will sent unless record checksum matched calculated checksum bytes record were successfully programmed. data record, indicates that checksum failed match, character indicates that bytes property program. facility designed that specific crystal frequencies were required order generate baud rates time programming pulses. actual loader code would typically programmed user into microcontroller parallel fashion default loader during their manufacturing process. entire initial Flash contents programmed that time, rest application programmed into Flash memory later time, possibly using loader code programming. This application controlled programming capability allows possibility changing application code field. application circuit embedded establish telephone data link user's manufacturer's computer, code could downloaded from diskette manufacturer's support system. There even possibility conducting very specialized remote testing failing circuit board manufacturer remotely programming series detailed test programs into application board checking results. user supplied loader should take watchdog timer into account. Typically, watchdog timer would disabled upon entry loader might running, order prevent watchdog reset from occurring during programming.
User Supplied Loader
user program simply decide time, reason, begin Flash programming operations. advance instruct external circuitry apply +12V pin, make certain that Boot enabled. User code contain loader designed replace application code contained Flash memory loading code through communication medium available application. This completely flexible defined designer system. could done serially using RS-232, serially using some other method, even parallel over user defined port. user freedom choose method that does interfere with application circuit. added feature, application program also Flash memory long term data storage, saving configuration information, sensor readings, other desired data.
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MX10EXA
Table Intel-Hex Records Used In-System Programming RECORD TYPE COMMANDIDATA FUNCTION Data Record :nnaaaa00dd.ddcc Where: number bytes (hex) record Aaaa memory address first byte record dd.dd= data bytes checksum File (EOF), operation :xxxxxx0lcc Where: xxxxxx required field, value "don't care" checksum Example:00000001FF Miscellaneous Write Functions :nnxxxx83 ffssddcc Where: number bytes (hex) record xxxx required field, value "don't care" Write Function subfunction code selection code data input needed) checksum Subfunction Code (Erase Blocks) block number bits 7:5, Bits zeros block block block block block Example:0200008301203C erase block Subfunction Code (Erase Boot Vector Status Byte) don't care don't care Example:010000830478 erase boot vector status byte Subtunction Code (Program Security Bits) program security (inhibit writing FLASH) program security (inhibit FLASH verify) program security (disable external memory) Example:02000083050175 program security Subtunction Code (Program Status Byte Boot Vector) program status byte program boot vector Note only bits these special cells programmed time. Example:020000830601FC78 program boot vector FC00h
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MX10EXA
RECORD TYPE COMMANDIDATA FUNCTION Display Device Data Blank Check Record type causes contents entire FLASH array sent serial port formatted display. This display consists address contents bytes starting with that address. display device contents will occur security been programmed. dumping device data serial port terminated reception character. General Format Function :05xxxx84sssseeeeffcc Where: number bytes (hex) record xxxx required field, value "don't care" "Display Device Data blank Check" function code ssss starting address eeee ending address subfunction display data blank check checksum Example:0500008440004FFF00E9 display 4000-4FFF Miscellaneous Read Functions General Format Function :02xxxx85ffsscc Where: number bytes (hex) record xxxx required field, value "don't care" "Miscellaneous Read" function code ffss subfunction selection code 0000 read signature byte manufacturer id(15H) 0001 read signature byte device 1(EAH) 0002 read signature byte device 2(XA= 54H)) 0700 read security bits (returned value bits sb3,sb2,sbl) 0701 read status byte 0702 read boot vector checksum Example:02000085000178 read signature byte device
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MX10EXA
In-Application Programming Method Several Application Program Interface (API) calls available application program permit selective erasing programming FLASH sectors. calls made through common interface, PGM_MTP. programming functions selected setting microcontroller's registers before making call PGM_MTP FFFOH. Results returned registers. calls shown Table Table calls CALL PROGRAM DATA BYTE PARAMETER Input Parameters: address byte program byte program Return Parameter pass, non-zero fail Input Parameters: block number bits 7:5, bits block block block block block Return Parameter pass, non-zero fail Input Parameters: =04h Return Parameter pass, non-zero fail Input Parameters: security (inhibit writing FLASH) security (inhibit FLASH verify) security (disable external memory) Return Parameter:none Input Parameters: 00H- program status byte status byte Return Parameter pass, non-zero fail Note only bits status byte programmed time Input Parameters: program BPC[15:8] (BPC[7:0] unchanged) Return Parameter pass, non-zero fail Note only bits [15:8] programmed time
ERASE BLOCK
ERASE STATUS BYTE
PROGRAM SECURITY
PROGRAM STATUS BYTE
PROGRAM HIGH BYTE
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MX10EXA
CALL READ DEVICE DATA PARAMETER Input Parameters: address byte read Return Parameter value byte read READ MANUFACTURER Input Parameters: (manufacturer Return Parameter value byte read READ DEVICE Input Parameters: (device Return Parameter =value byte read READ DEVICE Input Parameters: =00h (device Return Parameter value byte read READ SECURITY BITS Input Parameters: (security bits) Return Parameter value byte read R4L[3:l] sb3, sb2, READ STATUS BYTE Input Parameters: (status byte) Return Parameter value BPC[l5:8] READ Input Parameters: (boot vector) Return Parameter value byte read
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MX10EXA
CALL PROGRAM ZERO PARAMETER Input Parameters: block number bits 7:5, bits block block block block block Return Parameters: pass, non-zero fail Input Parameters: (after chip erase, return caller) (after chip erase, reset chip) others: error Return Parameters:
pass, non-zero fail
ERASE CHIP
PROGRAM SPECIAL CELL
ERASE SPECIAL CELL
Input Parameters: special cell address 0000h:program BPSW[7:0] 0001h:program BPSW[15:8] 0002h:program BPC[7:0] 0003h:program BPC[15:8] 0004b:program status byte 000Ah:program security 000Ch:program security 000Eh:program security =byte value program Return Parameters: pass, non-zero fail Note only bits these special cells programmed time Input Parameters: special cell address 0000h: erase DPSW[7:0] 000lh: erase DPSW[15:8] 0002h: erase BPC(7:0) 0003h: erase BPC[15:8] 0004h: erase status byte Return Parameters: pass, non-zero fail
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MX10EXA
CALL READ SPECIAL CELL PARAMETER Input Parameters: special cell address 0000h: read BPSW[7:0] 000lh: read BPSW[15:8] 0002h: read BPC[7:0] 0003h: read BPC[15:8] 0004h: read status byte 0006h: read manufacturer 0007h: read device 0008h: read device 000Ah: read security 000Ch: read security 000Eh: read security Return Parameters: value byte read
Security security feature protects against software piracy prevents contents Flash from being read. Security Lock bits located Flash. programmable security lock bits that will provide different levels protection on-chip code data (see Table Table SECURITY LOCK BITS1 Level NOTE: other combination Lock bits defined. Security bits independent each other. Full-chip erase performed regardless states security bits. Setting doesn't prevent programming unprogrammed bits. PROTECTION DESCRIPTION program security features enabled Same level plus block erase disabled. Erase programming status byte boot vector disabled. Same level plus program verification disabled Same level plus external execution disabled.
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MX10EXA
TIMER/COUNTERS standard 16-bit enhanced Timer/Counters: Timer Timer 1.Additionally, third 16-bit Down timer/counter, central timing generator core provides time-base Timers Counters. timer/event counters perform following functions: Measure time intervals pulse duration Count external events Generate interrupt requests Generate timed output waveforms timer/counters (Timer Timer Timer independently programmed operate either timers event counters TnCON register. timers count unless otherwise stated. These timers dynamically read during program execution. base clock rate timers user programmable. This applies timers when running timer mode opposed counter mode), watchdog timer. clock driving timers called TCLK determined setting bits (PT1, PT0) System Configuration Register (SCR). frequency TCLK selected oscillator input divided (Osc/4), oscillator input divided (Osc/16), oscillator input divided (Osc/ 64). This gives range possibilities timer functions, including baud rate generation, Timer capture. Note that this single rate setting applies timers. When timers used counter mode, register will increment whenever falling edge (high transition) detected external input corresponding timer clock. These inputs sampled once every oscillator cycles, take many oscillator cycles detect transition. Thus maximum count rate that supported Osc/4. duty cycle timer clock inputs important, high state timer clock input pins must present oscillator cycles before guaranteed "seen" timer logic. Timer modes kept identical 80C51 timer modes code compatibility. Only mode replaced more powerful 16-bit autoreload mode. This will give timers much larger range when used time bases. recommended settings different modes shown Figure
Timer Timer "Timer" "Counter" function selected control bits special function register TMOD. These Timer/Counters have four operating modes, which selected bit-pairs (Ml, TMOD register.
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MX10EXA
Address:440 Addressable Reset Value:00H
OPERATING Prescaler selection. Osc/4 Osc/16 Osc/64 Reserved Compatibility Mode allows execute most translated 80C51 code register file must copy 80C51 mapping data memory mimic 80C51 indirect addressing scheme. Page Zero mode forces program data addresses 16-bits only. This saves stack space speeds execution limits memory access 64k.
Figure System Configuration Register (SCR)
TMOD Address:45C Addressable Reset Value:00H
GATE GATE TIMER
TIMER
GATE
Gating control when set. Timer/Counter enabled only while "INTn" high "TRn" control set. When cleared Timer enabled whenever "TRn" control set. Timer Counter Selector cleared Timer operation (input from internal system clock.) Counter operation (input from "Tn" input pin). OPERATING 16-bit auto-reload timer/counter 16-bit non-auto-reload timer/counter 8-bit auto-reload timer/counter Dual 8-bit timer mode (timer only) Figure Timer/Counter Mode Control (TMOD) Register
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Enhanced Mode timers 13-bit count mode 80C51 (current Mode been replaced with 16bit auto-reload mode. Four additional 8-bit data registers (two timer: RTHn RTLn) created hold auto-reload values. this mode, overflow will flag TCON register cause both counters loaded from registers respectively. These SFRs will also used hold reload data 8-bit auto-reload mode (Mode instead overflow rate Timer Timer Mode calculated follows: Timer_Rate Osc/(N*(65536 Timer_Reload_Value)) where TCLK prescaler value: (default), Mode Mode 16-bit non-auto reload mode. Mode Mode configures Timer register 8-bit Counter (TLn) with automatic reload. Overflow from only TCON Address:410 Addressable Reset Value:00H TCON.7 sets TFn, also reloads with contents RTLn, which preset software. reload leaves unchanged. Mode operation same Timer/Counter overflow rate Timer Timer Mode calculated follows: Timer_Rate Osc/(N (256 Timer_Reload_Value)) where TCLK prescaler value: Mode Timer Mode simply holds count. effect same setting Timer Mode establishes separate counters. uses Timer control bits: CIT; GATE, TR0, INT0, TF0. locked into timer function takes over from Timer Thus, controls "Timer interrupt. Mode provided applications requiring extra 8bit timer. When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, fact, application requiring interrupt.
TCON.6 TCON.5
TCON.4 TCON.3 TCON.2 TCON.2 TCON.0
SYMBOL FUNCTION Timer overflow flag. hardware Timer/Counter overflow. This flag will T1OE(TSTAT.2) set. Cleared hardware when processor vectors interrupt routine, clearing software. Timer control bit. Set/cleared software turn Timer/Counter on/off. Timer overflow flag. hardware Timer/Counter overflow. This flag will T0OE (TSTAT.0) set. Cleared hardware when processor vectors interrupt routine, clearing software. Timer control bit. Set/cleared software turn Timer/Counter on/off. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt type control bit. Set/cleared software specify falling edge/low level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt Type control bit. Set/cleared software specify falling edge/tow level triggered external interrupts. Figure Timer/Counter(TCON) Register
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T2CON Address:418 Addressable Reset Value:00H EXF2 RCLK0 TCLK0 EXEN2 C/T2 CP/RL2
T2CON.7 T2CON.6
SYMBOL EXF2
T2CON.5 T2CON.4 T2CON.3 T2CON.2 T2CON.1
RCLK0 TCLK0 EXEN2 C/T2
T2CON.0
CP/RL2
FUNCTION Timer overflow flag. hardware Timer/Counter overflow. Must cleared software. will when RCLK0, RCLK1, TCLK0, TCLK1 T2OE=1. Timer external flag when capture reload occurs negative transition T2EX (and EXEN2 set). This flag will cause Timer interrupt when this interrupt enabled. EXF2 cleared software. Receive Clock Flag. Transmit Clock Flag. RCLK0 TCLK0 used select Timer overflow rate clock source UART0 instead Timer Timer external enable allows capture reload occur negative transition T2EX. Start 1/Stop=0 control Timer Timer counter select. Internal timer External event counter (falling edge triggered) Capture/Reload flag. CP/RL2 EXEN2 captures will occur negative transitions T2EX. CP/RL2 EXEN2 auto reloads occur with either Timer overflows negative transitions T2EX. RCLK TCLK timer auto reload Timer overflow, this effect. Figure Timer/Counter Control (T2CON) Register which used generate interrupt. operated three operating modes: auto-reload down counting), capture, baud rate generator (for either both UARTs SFRs T2MOD T2CON). These modes shown Table Capture Mode capture mode there options which selected EXEN2 T2CON. EXEN2 then timer 16-bit timer counter, which upon overflowing sets TF2, timer overflow bit. This will cause interrupt when timer interrupt enabled. EXEN2 then Timer still does above, with added feature that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively. addition, transition T2EX causes EXF2 T2CON set. This will cause interrupt same fashion when Timer interrupt enabled. capture mode illustrated Figure
Timer-Overflow Toggle Output timer module outputs, which toggle overflow from individual timers. same device pins that used count inputs also used overflow outputs. (TnOE TSTAT register) associated with each counter indicates whether Port-SFR data overflow signal output pin. These outputs could used applications generating variable duty cycle outputs (changing auto-reload register values). Also variable frequency (Osc/8 Osc/8,388,608) outputs could achieved adjusting prescaler along with auto-reload register values. With 30.0MHz oscillator, this range would 3.58Hz 3.75MHz. Timer Timer 16-bit Timer/Counter which operate either timer event counter. This selected C/T2 special function register T2CON. Upon timer overflow/underflow, flag set,
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timer incremented TCLK. Auto-Reload Mode Down Counter) Baud Rate Generator Mode auto-reload mode, timer registers loaded with 16-bit value T2CAPH T2CAPL when count overflows. T2CAPH T2CAPL initialized software. EXEN2 T2CON set, timer registers will also reloaded EXF2 flag when 1-to-0 transition occurs input T2EX. autoreload mode shown Figure this mode, Timer configured count down. This done setting clearing DCEN (Down Counter Enable) T2MOD special function register (see Table T2EX then controls count direction. When T2EX high, count direction, when T2EX low, count down direction. Figure shows Timer which will count automatically, since DCEN this mode there options selected EXEN2 T2CON register. EXEN2 then Timer counts FFFFH sets (Overflow Flag) upon overflow. This causes Timer registers reloaded with 16-bit value T2CAPL T2CAPH, whose values preset software. EXEN2 16-bit reload triggered either overflow -to-0 transition input T2EX. This transition also sets EXF2 bit. enabled, either EXF2 generate Timer interrupt. Figure DCEN this enables Timer count down. this mode, logic level T2EX controls direction count. When logic applied T2EX, Timer will count Timer will overflow FFFFH flag, which then generate interrupt enabled. This timer overflow, also causes 16-bit value T2CAPL T2CAPH reloaded into timer registers TH2, respectively. logic T2EX causes Timer count down. When counting down, timer value compared 16-bit value contained T2CAPH T2CAPL. When value equal, timer register loaded with FFFF hex. underflow also sets flag, which generate interrupt enabled. external Flag EXF2 toggles when Timer underflows overflows. This EXF2 used 17th resolution, needed. EXF2 flag does generate interrupt this mode. baud rate generator,
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setting TCLKn and/or RCLKn T2CON T2MOD, Timer chosen baud rate generator either both UARTs. baud rates transmit receive simultaneously different. Programmable Clock-Out duty cycle clock programmed come This pin, besides being regular pin, alternate functions. programmed input external clock Timer/Counter output duty cycle clock ranging from 3.58Hz 3.75MHz 30MHz operating frequency. configure Timer/Counter clock generator, C/T2 T2CON) must cleared T2OE T2MOD must set. (T2CON.2) also must start timer. Clock-Out frequency depends oscillator frequency reload value Timer capture registers (TCAP2H, TCAP2L) shown this equation:
TCLK (65536 TCAP2H, TCAP2L)
Clock-Out mode Timer roll-overs will generate interrupt. This similar when used baud-rate generator. possible Timer baud-rate generator clock generator simultaneously. Note, however, that baud-rate will ClockOut frequency.
MX10EXA
Table Timer Operating Modes CP/RL2 RCLK+TCLK OCEN MODE Timer (stopped) 16-bit auto-reload, counting 16-bit auto-reload, counting down depending T2EX 16-bitcapture Baud rate generator
TSTAT Address:411 Addressable Reset Value:00H
T1OE
T0OE
TSTAT.2 TSTAT.0
SYMBOL T1OE T0OE
FUNCTION When this allows clock Timer when counter mode. When acts output toggles every Timer overflow. When this allows clock Timer when counter mode. When acts output toggles every Timer overflow.
Figure Timer Extended Status (TSTAT)
T2MOD Address:419 Addressable Reset Value:00H
RCLK1 TCLK1 T2OE DCEN
T2MOD.5 T2MOD.4 T2MOD.1 T2MOD.5
SYMBOL RCLK1 TCLK1 T2OE DCEN
FUNCTION Receive Clock Flag. Transmit Clock Flag. RCLK1 TCLK1 used select Timer overflow rate clock source UART1 instead Timer When this allows clock Timer when counter mode. When acts output toggles every Timer overflow. Controls count direction Timer autoreload mode. DCEN=0 counter count only DCEN=1 counter count down, depending T2EX (see text). Figure Timer Mode Control (T2MOD)
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TCLK C/T2=0 C/T2=1 Control Capture Timer Interrupt Transition Detector T2CAPL T2CAPH (8-bits) (8-bits)
T2EX Control EXEN2
EXF2
Figure Timer Capture Mode
TCLK C/T2=0 (8-bits) C/T2=1 Control Reload (8-bits)
T2CAPL Transition Detector T2EX
T2CAPH Timer Interrupt EXF2
Control EXEN2
Figure Timer2 Auto-Reload Mode(DECN=0)
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(DOWN COUNTING RELOAD VALUE) TOGGLE
EXF2
TCLK C/T2=0 C/T2=1 CONTROL COUNT DIRECTION 1=UP 0=DOWN T2CAPL T2CAPH T2EX COUNTING RELOAD VALUE) OVERFLOW INTERUPT
Figure Timer Auto Reload Mode (DCEN=1)
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WATCHDOG TIMER watchdog timer subsystem protects system from incorrect code execution causing system reset when watchdog timer underflows result failure software feed timer prior timer reaching terminal count. important note that watchdog timer running after type reset must turned user software application does watchdog function. before feeding watchdog. instructions should move WFEED1 register then WFEED2 register. WFEED1 correctly loaded WFEED2 correctly loaded, then immediate watchdog reset will occur. program sequence feed watchdog timer cause WDCON settings take effect follows: disable global interrupts. Mov.b wfeed1, #A5h watchdog feed part mov.b wfeed2, #5Ah watchdog feed part setb re-enable global interrupts. This sequence assumes that interrupt system enabled there possibility interrupt request occurring during feed sequence. interrupt allowed serviced service routine contained access, would trigger watchdog reset. known that interrupt could occur during feed sequence, instructions disable re-enable interrupts removed. software must written that feed operation takes place every seconds from last feed operation. Some tradeoffs need made. advisable include feed operations minor loops subroutines unless feed operation specific subroutine. turn watchdog timer completely off, following code sequence should used: mov.b wdcon, control register clear WDRUN. mov.b wfeed1 #A5h watchdog feed part mov.b wfeed2, #5Ah watchdog feed part This sequence assumes that watchdog timer being turned beginning initialization code that interrupt system been enabled. watchdog timer turned point when interrupts enabled, instructions disable re-enable interrupts should added this sequence.
Watchdog Function watchdog consists programmable prescaler main timer. prescaler derives clock from TCLK source that also drives timers watchdog timer subsystem consists programmable 13-bit prescaler, 8-bit main timer. main timer clocked (decremented) taken from 8-bits prescaler shown Figure clock source prescaler same TCLK (same clock source timers). Thus main counter docked often once every TCLKs (see Table watchdog generates underflow signal (and autoloaded from WDL) when watchdog count clock decrement watchdog occurs. watchdog bits wide autoload value range from FFH. (The autoload value permissible since prescaler cleared upon autoload). This leads following user design equations. Definitions: tOSC oscillator period, selected prescaler value, main counter autoload value, prescaler value from Table tMIN minimum watchdog time-out value (when autoload value tMAX maximum time-out value (when autoload value FFH), design time-out value. tMIN tOSC tMAX tOSC 4096 =255, =64) tOSC watchdog timer directly loadable user. Instead, value loaded into main timer held autoload register. order cause main timer loaded with appropriate value, special sequence software action must take place. This operation referred feeding watchdog timer. feed watchdog, instructions must sequentially executed successfully. intervening accesses allowed, interrupts should disabled
Watchdog Control Register (WDCON) reset values WDGON registers will such that watchdog timer timeout period 4096 tOSC watchdog running. WDCON written software changes only take effect after executing valid watchdog feed sequence.
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Table Prescaler Select Values WDCON PRE2 PRE1 PRED DIVISOR 1024 2048 4096 Watchdog Detailed Operation When external RESET applied, following takes place: Watchdog control (1). Autoload register (mm. count). Watchdog time-out flag cleared. Prescaler cleared. Prescaler highest divide. Autoload takes place. When coming hardware reset, software should load autoload register then feed watchdog (cause autoload). watchdog running happens underflow time external RESET applied, watchdog time-out flag will cleared.
WATCHDOG FEED SEQUENCE WFEED1,#A5H WFEED2,#5AH
TCLK
PRESCALER
8-BIT DOWN COUNTER
INTERNAL RESET
PRE2
PRE1
PRE0
WDRUN WDTOF
WDCON
Figure Watchdog Timer
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When watchdog underflows, following action takes place (see Figure 14): Autoload takes place. Watchdog time-out flag Watchdog unchanged. Autoload (WDL) register unchanged. Prescaler unchanged. other device action same external reset. Note that watchdog underflows, program counter will loaded from reset vector case internal reset. watchdog time-out flag examined determine watchdog caused reset condition. watchdog time-out flag cleared software. WDCON Register Definitions WDCON.7 PRE2 Prescaler Select reset WDCON.6 PREl Prescaler Select reset WDCON.5 PRE0 Prescaler Select reset WDCON.4 WDCON.3 WDCON.2 WDRUN Watchdog Control bit, WDCON.1 WDTOF Time flag WDCON.0 Timer defaults clock both UART0 UART1. Timer programmed clock either UART0 through T2CON (via bits R0CLK T0CLK) UART1 through T2MOD (via bits R1CLK CLK). this case, UART clocked could clock source. serial port receive transmit registers both accessed Special Function Register SnBUF Writing SnBUF loads transmit register, reading SnBUF accesses physically separate receive register. serial port operate modes: Mode Serial expansion mode. Serial data enters exits through RxDn. TxDn outputs shift clock. bits transmitted/received (LSB first). (The baud rate fixed 1/16 oscillator frequency.) Mode Standard 8-bit UART mode. bits transmitted(through TxDn) received (through RxDn): start (0), data bits (LSB first), stop (1). receive, stop goes intoRB8 Special Function Register SnCON. baud rate variable. Mode Fixed rate 9-bit UART mode. bits transmitted (through TxD) received (through RxD): start (0), data bits (LSB first), programmable data bit, stop (1). Transmit, data TB8_n SnCON) assigned value example, parity PSW) could moved into TB8_n. receive, data goes into RB8_n Special Function Register SnCON, while stop ignored. baud rate programmable 1/32 oscillator frequency. Mode Standard 9-bit UART mode. bits transmitted (through TxDn) received (through RxDn): start (0), data bits (LSB first), programmable data bit, stop (1). fact, Mode same Mode respects except baud rate. baud rate Mode variable. four modes, transmission initiated instruction that uses SnBUF destination register. Reception initiated Mode condition RI_n REN_n Reception initiated other modes incoming start REN_n
UARTs Baud rate selection somewhat different clocking scheme used timers. Some other enhancements have been made UART operation. first that there separate interrupt vectors each UART's transmit receive functions. UART transmitter been double buffered, allowing packed transmission data with gaps between bytes less critical interrupt service routine timing. break detect function been added UART. This operates independently UART itself provides start-of-break status that program test. Finally, Overrun Error flag been added detect missed characters received data stream. double buffered UART transmitter require some software changes code written original single buffered UART. Each UART baud rate determined either fixed division oscillator UART modes timer timer overflow rate UART modes
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MX10EXA
Serial Port Control Register serial port control status register Special Function Register SnCON, shown Figure This register contains only mode selection bits, also data transmit receive (TB8_n RB8_n), serial port interrupt bits TI_n RI_n). 9-bIt Mode Please note that ninth data (TB8) double buffered. Care must taken insure that contains intended data point where transmitted. Double buffering UART transmitter bypassed simple means synchronizing rest data stream.
Flag Bypassing Double Buffering order allow easy double buffered UART transmitter feature, TI_n flag UART hardware under conditions. first condition completion byte transmission. This occurs stop modes eighth data mode second condition when SnBUF written while UART transmitter idle. this case, TI_n flag order indicate that second UART transmitter buffer still available. Typically, UART transmitters generate interrupt byte transmitted. case UART, additional interrupt generated defined stated conditions setting TI_n flag. This additional interrupt does occur double buffering bypassed explained below. Note that character oriented approach used transmit data through UART; there could second interrupt each character transmitted, depending timing writes SBUF. this reason, generally better bypass double buffering when UART transmitter used character oriented mode. This also true UART polled rather than interrupt driven, when transmission character oriented rather than message string oriented. interrupt occurs last byte transmitted when UART becomes idle. Among other things, this allows program determine when message been transmitted completely. interrupt service routine should handle this additional interrupt. recommended method using double buffering application program have interrupt service routine handle single byte each interrupt occurrence. this manner program essentially does require special considerations double buffering. Unless higher priority interrupts cause delays servicing UART transmitter interrupt, double buffering will result transmitted bytes being tightly packed with intervening gaps. UART transmitter used single buffered. recommended UART transmitter interrupt service routine (ISR) technique bypass double buffering first clears TI_n flag upon entry into ISR, standard practice. This clears interrupt that activated ISR. Secondly, TI_n flag cleared immediately following each write SnBUF. This clears interrupt flag that would otherwise direct program write second transmitter buffer. there possibility that higher priority interrupt might become active between write SnBUF clearing TI_n flag, interrupt system have temporarily disabled during that sequence clearing, then setting register.
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CLOCKING SCHEME/BAUD RATE GENERATION UARTS clock rates determined either fixed division (modes oscillator clock Timer Timer overflow rate (modes clock UARTs runs Baud rate. timers used source Baud Clock, since maximum speed timers/Baud Clock Osc/4, maximum baud rate timer overflow divided i.e. Osc/64. Mode fixed Osc/1 Mode however, fixed rate Osc/32. Pre-scaler Timers controlled PT1, bits Osc/4 Osc/16 Osc/64 reserved Baud Rate UART Mode Baud_Rate Osc/32
Using Timer Generate Baud Rates Timer 16-bit up/down counter baud rate generator, timer selected clock source either/both UART0 UART1 transmitters and/or receivers setting TCLKn and/or RCLKn T2CON T2MOD. baud rate generator, incremented Osc/N where depending TCLK programmed bits PT1, PTO. source UART, other UART could clocked either overflow fixed clock, UARTs could independently with different baud rates. T2CON 0x418 bit5 RCLK0 bit4 TCLK0
Baud Rate UART Mode Baud_Rate Osc/16 Baud Rate calculation UART Mode Baud_Rate Timer_Rate/16 Timer_Rate where TCLK prescaler value: 4,16, Timer_Range timer mode 65536 timer mode timer count mode. timer reload value calculated follows: Timer_Reload_Value Timer_Range(Osc/ (Baud_Rate*N*1 NOTES: 1.The maximum baud rate UART mode Osc/64. 2.The lowest possible baud rate (for given oscillator frequency value) found using timer reload value 3.The timer reload value never larger than timer range. 4.If timer reload value calculation gives negative fractional result, baud rate requested possible given oscillator frequency value.
T2MOD 0x419
bit5 RCLK1
bit4 TCLK1
Prescaler Select Timer Clock (TCLK) 0x440 bit3 bit2
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SnSTATAddress: S0STAT S1STAT Addressable Reset Value:00H STINTn
SnSTAT.3 SnSTAT.2
SYMBOL
SnSTAT.1
SnSTAT.0
STINTn
FUNCTION Framing Error flag when receiver fails valid STOP frame. Cleared software. Break Detect flag character received with bits (including STOP bit) being logic `0'. Thus gives "Start Break Detect" Mode Modes break detect feature operates independently UARTs provides START Break Detect status that user program poll. Cleared software. Overrun Error flag character received receiver buffer while still full (before software read previous character from buffer), i.e., when byte received while SnCON still set. Cleared software. This flag must enable above status flags generate receive interrupt (Rln). only cleared software write this register.
Figure Serial Port Extended Status (SnSTAT) Register (See also Figure regarding Framing Error flag) INTERRUPT SCHEME There separate interrupt vectors each UART transmit receive functions. Table Vector Locations UARTS Vector Address Interrupt Source Arbitration UART Receiver UART Transmitter ACH-AFH UART Receiver UARTI Transmitter received. goes into RB8. Then comes stop bit. port programmed such that when stop received, serial port interrupt will activated only This feature enabled setting SCON. this feature multiprocessor systems follows: When master processor wants transmit block data several slaves, first sends address byte which identifies target slave. address byte differs from data byte that address byte data byte. With slave will interrupted data byte. address byte, however, will interrupt slaves, that each slave examine received byte being addressed. addressed slave will clear prepare receive data bytes that will coming. slaves that weren't being addressed leave their SM2s about their business, ignoring coming data bytes. effect Mode Mode used check validity stop although this better done with Framing Error (FE) flag. Mode reception, receive interrupt will activated unless valid stop received.
NOTE: transmit receive vectors could contain same address work like 8051 interrupt scheme Error Handling, Status Rags Break Detect UARTs following error flags; Figure
Multiprocessor Communications Modes have special provision multiprocessor communications. these modes, data bits
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Automatic Address Recognition Automatic Address Recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes, mode mode Receive Interrupt flag (RI) will automatically when received byte contains either "Given"" address "Broadcast" address. mode requires that information indicate that received information address data. Automatic address recognition shown Figure Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking Given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits used which bits "don't care". SADEN mask logically ANDed with create "Given" address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples will help show versatility this scheme: Siave0 SADDR SADEN Given Slavel SADDR SADEN Given =1100 =1111 =1100 =1100 =1111 =1100 0000 1101 00X0 0000 1110 000X Slave0 SADDR SADEN Given SADDR SADEN Given SADDR SADEN Given =1100 0000 =1111 1001 =1100 0XX0 =1110 0000 =1111 1010 =1110 0X0X =1110 0000 =1111 1100 =1110 00XX
Slave
SIave2
above example differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logical SADDR SADEN. Zeros this result tested don't-cares. most cases, interpreting don't-cares ones, broadcast address will hexadecimal. Upon reset SADDR SADEN loaded with This produces given address "don't cares" well Broadcast address "don't cares". This effectively disables Automatic Addressing mode allows microcontroller standard UART drivers which make this feature.
above example SADDR same data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address Slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000. more complex system following could used select slaves while excluding slave
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MX10EXA
SnCON Address:S0CON S1CON Addressable Reset Value:00H
Where SM0, SM1, specify serial port mode, bollows: Mode Description Baud Rate shift register fOSC/16 8-bit UART variable 9-bit UART fOSC/32 9-bit UART variable SnCON.5 SYMBOL FUNCTION Enables multiprocessor communication feature Modes Mode then will activated received data (RB8) Mode SM2=1 then will activated valid stop received. Mode should Enables serial reception. software enable reception. Clear software disable reception. data that will transmitted Modes clear software desired. double buffered. text details. Modes data that received. Mode SM2=0, stop that received. Mode used. Transmit interrupt flag. when another byte written UART transmitter. text details. Must cleared software. Receive interrupt flag. hardware time Mode stop time other modes (except SM2). Must cleared software. Figure Serial Port Control (SnCON) Register
SnCON.4 SnCON.3 SnCON.2 SnCON.1 SnCON.0
START
ONLY MODE STOP
DATA BYTE
sets
STINTn SnSTAT
Figure UART Framing Error Detection
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SM0_n SM1_n SM2_n REN_n TB8_n
RB8_n
TI_n
RI_n
SnCON
RECEIVED ADDRESS PROGRAMMED ADDRESS
COMPARATOR
UART MODE MODE SM2=1: INTERRUPT REN=1, RB8=1 "RECEIVED ADDRESS" "PROGRAMMED ADDRESS" -WHEN ADDRESS RECEIVED, CLEAR RECEIVED DATA BYTES -WHEN DATA BYTES HAVE BEEN RECEIVED:SET WAIT NEXT ADDRESS
Figure UART Multiprocessor Communication, Automatic Address Recognition
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PORT OUTPUT CONFIGURATION Each port user configured output types. types Quasi-bidirectional (essentially same standard 80C51 family ports), Open-Drain, Push-Pull, (high impedance). default configuration after reset Quasi-bidirectional. However, less mode (the reset), port pins that comprise external data will default push-pull outputs. port output configurations determined settings port configuration SFRs. There SFRs each port, called PnCFGA PnCFGB, where port number. each SFRs relates output setting corresponding port pin, allowing combination output types mixed those port pins. instance, output type port controlled setting SFRs P1CFGA P1CFGB. Table shows configuration register settings port output types. electrical characteristics each output type found Characteristic table. Table Port Configuration Register Settings PnCFGB PnCFGA Port Output Mode Open Drain Quasi-bidirectional (high impedance) Push-Pull NOTE: Mode changes cause glitches occur during transitions. When modifying both registers, WRITE instructions should carried consecutively. RESET device reset whenever logic applied least microseconds, placing level re-initializes on-chip logic. Reset must asserted when power initially applied held until oscillator running. duration reset must extended when power initially applied when using reset exit power down mode. This need allow oscillator time start stabilize. most power supply ramp conditions, this time milliseconds. brought high again, exception generated which causes processor jump reset address. Typically, this address contained memory location 0000. destination reset jump must located first code address power-up, vectors 16-bit values point page zero addresses only. After reset contents indeterminate. Alternatively, Boot Vector supply reset address. This happens when Boot Vector forced when Flash status byte non-zero. These cases described section "Hardware Activation Boot Vector" page
RESET
EXTERNAL external program/data allows 8-bit 16-bit width, address sizes from bits. width selected input reset (see Reset Options below), while address size program configuration register. off-chip code selected (through pin), initial code fetches will done with maximum address size bits).
SOME TYPICAL VALUES R=100K, C=1.0uF R=1.0M, C=0.1uF (ASSUMING THAT RISE TIME LESS)
Figure Recommended Reset Circuit
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RESET OPTIONS sampled rising edge pulse, determines whether device begin execution from internal external code memory. pulled high configures single-chip mode. driven low, device enters ROMless mode. After Reset released, EA/WAIT becomes wait signal external transactions. BUSW/P3.5 weakly pulled high while reset asserted, allowing simple biasing with resistor ground select altermate width. BUSW driven reset, weak pullup will causes loaded width, giving 16-bit external bus. BUSW pulled with 2.7K smaller value resistor, giving 8-bit external bus. width setting from BUSW overridden software once user program running. Both BUSW must held three oscillator clock times after reset deasserted guarantee that their values latched correctly. defines tour types interrupts: Exception Interrupts These system level errors other very important occurrences which include stack overflow, divid-by-0, reset. Event Interrupts These peripheral interrupts from devices such UARTs, timers, external interrupt inputs. Software Interrupts These equivalent hardware interrupt, requested only under software control. Trap Interrupts These TRAP instructions, generally used call system services multi-tasking system. Exception interrupts, software interrupts, trap interrupts generally standard derivatives detailed User Guide. Event interrupts tend different different derivatives. supports total maskable event interrupt sources (for various peripherals), seven software interrupts, exception interrupts (plus reset), traps. maskable event interrupts share global interrupt disable (the register) each also separate individual interrupt enable registers). Only three bits register values used Each event interrupt occur priority levels bits Interrupt Priority (IP) registers, IPA0 through IPA5. value field gives interrupt priority effect disabling interrupt. value gives interrupt priority value gives priority etc. result same four bits were used values except complete interrupt vector list including interrupt types, shown following tables. tables include address vector each interrupt, related priority register bits any), arbitration ranking that interrupt source. arbitration ranking determines order which interrupts processed more than interrupt same priority occurs simultaneously.
POWER REDUCTION MODES supports Idle Power Down modes power reduction. idle mode leaves some peripherals running allow them wake processor when interrupt generated. power down mode stops oscillator order minimize power. processor made exit power down mode reset external interrupt inputs. order external interrupt re-activate while power down mode, external interrupt must enabled configured level sensitive mode. power down mode, power supply voltage reduced keep-alive voltage (2V), retaining RAM, register, values point where power down mode entered.
INTERRUPTS supports vectored interrupt sources. These include maskable event interrupts, exception interrupts, trap interrupts, software interrupts. maskable interrupts each have priority levels globally and/or individually enabled disabled.
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Table Interrupt Vectors EXCEPTION/TRAPS PRECEDENCE DESCRIPTION Reset (h/w, watchdog, s/w) Breakpoint (h/w trap Trace (h/w trap Stack Overflow (h/w trap Divide (h/w trap User RETI (h/w trap TRAP 0-15 (software) EVENT INTERRUPTS DESCRIPTION FLAG External interrupt Timer interrupt External interrupt Timer interrupt Timer interrupt Serial port Serial port Serial port Serial port TF2(EXF2) RI.0 TI.0 RI.1 TI.1
VECTOR ADDRESS 0000-0003 0004-0007 0008-000B 000C-000F 0010-0013 0014-0017 0040-007F
ARBITRATION RANKING (High)
VECTOR ADDRESS 0080-0083 0084-0087 0088-008B 008C-008F 0090-0093 00A0-00A3 00A4-00A7 00A8-00AB OOAC-00AF
ENABLE ERI0 ETI0 ERI1 ETI1
INTERRUPT PRIORITY lPA0.2-0 (PX0) IPA0.6-4 (PT0) IPA1.2-0 (PX1) lPA1.6-4 (PT1) lPA2.2-0(PT2) lPA4.2-0(PRIO) lPA4.6-4 (PTIO) lPA5.2-0(PRT1) lPA5.6-4(PTI1)
ARBITRATION RANKING
SOFTWARE INTERRUPTS DESCRIPTION Software interrupt Software interrupt Software interrupt Software interrupt Software interrupt Software interrupt Software interrupt FLAG SWR1 SWR2 SWR3 SWR4 SWR5 SWR6 SWR7 VECTOR ADDRESS 0100-0103 0104-0107 0108-010B 010C-010F 0110-0113 0114-0117 0118-011B
ENABLE SWE1 SWE2 SWE3 SWE4 SWES SWE6 SWE7
INTERRUPT PRIORITY (fixed (fixed (fixed (fixed (fixed (fixed (fixed
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ABSOLUTE MAXIMUM RATINGS PARAMETER Operating temperature under bias Storage temperature range Voltage EA/VPP Voltage other Maximum Power dissipation (based package heat transfer limitations, device power consumption) RATING 13.0 0.5V UNIT
ELECTRICAL CHARACTERISTICS 4.5V 5.5V unless otherwise specified; Tamb 70°C commercial 40OC +85OC industrial, unless otherwise specified.
Symbol PARAMETER TEST CONDITIONS Supplies IPDI VRAM VIH1 VIL1 VOH1 VOH2
LIMITS
UNIT
Supply current operating Idle mode supply current Power-down current Power-down current RAM-keep-alive voltage Input voltage Input high voltage, except XTAL1, Input high voltage XTAL1, Input voltage XATL1, Output voltage ports, ALE,
5.5V, 5.5V,
RAM-keep-alive voltage
-0.5
0.22VDD 0.12VDD
5.0V 5.0V 5.0V IOL=3.2mA, VDD=5.0V IOH=-100uA, VDD=4.5V IOH=3.2mA, VDD=4.5V 0.45V
0.8VDD
Output high voltage ports, ALE, PSEN
Output high voltage, ports P0-3, ALE, PSEN Input/Output capacitance Logical input current, P0-3 Input leakage current, P0-3
-650
Logical transition current ports
5.5V
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NOTES: 1.Ports Quasi bi-directional mode with weak pull-up (applies ALE, PSEN only during RESET). 2.Ports Push-Pull mode, both pull-up pull-down assumed same strength. 3.In output modes. 4.Port pins source transition current when used quasi-bidirectional mode externally driven from This current highest when approximately 5.Measured with port high impedance output mode. 6.Measured with port quasi-bidirectional output mode. 7.Load capacitance outputs=80pF 8.Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: (*NOTE: This 85°C specification VDD= 5V.) Maximum 8-bit port: 26mA Maximum total output: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions.
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ELECTRICAL CHARACERISTICS (5V) 4.5V 5.5V; Tamb +70°C commercial 40OC +85OC Industrial SYMBOL FIGURE PARAMETER VARIABLE CLOCK External Clock Oscillator frequency Clock period timing cycle CHCX Clock high time 0.57 tCLCX Clock time 0.47 CLCH Clock rise time CHCL Clock fall time Address Cycle CRAR Delay from clock rising edge rising edge tLHLL pulse width (programmable) tC)-6 tAVLL Address valid de-asserted (set-up) tC)-12 tLLAX Address hold after de-asserted (tC/2)-10 Code Read Cycle tPLPH PSEN pulse width )-10 tLLPL de-asserted PSEN asserted (tC/2)-7 tAVIVA Address valid instruction valid, cycle tC)-36 (access time) tAVIVB Address valid instruction valid, non-ALE cycle tC)-29 (access time) tCPLIV PSEN asserted instruction valid tC)-29 (enable time) tPXIX Instruction hold after PSEN de-asserted tPXIZ tIXUA 3-State after PSEN de-asserted (disable time) Hold time unlatched part address after instruction latched pulse width de-asserted asserted Address valid data input valid, cycle (access time) Address valid data input valid, non-ALE cycle (access time) valid data enable time Data hold time after de-asserted 3-State after de-asserted (disable time) Hold time unlatched part address after data latched
UNIT
Data Read Cycle RLRH tLLRL tAVDVA tAVDVB tRLDV RHDX RHDZ tDXUA
)-10 (tC/2)-7 tC)-36 tC)-29 tC)-29 tC-8
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SYMBOL FIGURE Data Write Cycle WLWH tLLWL tQVWX WHQX tAVWL UAWH PARAMETER VARIABLE CLOCK UNIT
pulse width tC)-10 falling edge asserted (V12 tC)-10 Data valid before asserted (data setup time) (V13 tC)-22 Data hold time after de-asserted (Note (V11 tC)-5 Address valid asserted (address setup time) tC)-22 (Note Hold time unlatched part address after (V11 tC)-7 de-asserted WAIT stable after strobe (RD,WR,or PSEN) asserted WAIT hold after strobe (RD,WR,or PSEN) asserted (V10*tC)-30 (V10 tC)-5
Wait Input
NOTES: 1.Load capacitance outputs 2.Variables through reflect programmable timing, which programmed Timing registers (BTRH BTRL). Refer User Guide details timing settings. This variable represents programmed width pulse determined ALEW BTRL register. ALEW ALEW This variable represents programmed width PSEN pulse determined bits CRAl, CRA0, ALEW bits BTRL register. cycle with ALE, CR1/0 CR1/0 CR1/0 CR1/0 Note that during burst mode code fetches, PSEN does exhibit transitions boundaries cycles. still applies purpose determining peripheral timing requirements. cycle with ALE, total cycle duration CRA1/0 CRA1/0 CRA1/0 CRA1/0 minus number clocks used 0.5). Example: CRA1/0 ALEW (1.5 0.5) This variable represents programmed length entire code read cycle with ALE. This time deter mined CRA1 CRA0 bits BTRL register. total cycle duration CRA1/0 =00, CRA1/0 =01, CRA1/0 CRA1/0 11). This variable represents programmed length entire code read cycle with ALE. This time determined bits BTRL register. CR1/0 00,2 CR1/0= 01,3 CR1/0= CR1/0 This variable represents programmed length entire data read cycle with ALE. this time determined bits BTRH register. DR1/0 00,2 DR1/0 01,3 DR1/0 DR1/0 This variable represents programmed length entire data read cycle with ALE. time determined DRA1 DRA0 bits BTRH register. total cycle duration DRA1/0 DRA1/0 DRA1/0 DRA1/0 11). This variable represents programmed width pulse determined bits DRA1, DRA0 BTRH register, ALEW BTRL register. Note that during 16-bit operation 8-bit external bus, remains does exhibit transition between first second byte cycles. V7still applies purpose determining peripheral timing requirements. timing first byte cycle with ALE, timing second byte cycle with ALE.
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cycle with ALE, DR1/0 DR1/0 01,3 DR1/0 DR1/0 cycle with ALE, total cycle duration DR1/0 DRA1/0 DRA1/0 DRA1/0 minus number clocks used 0.5). Example: DRA1/0 ALEW then V7=2 (0.5 0.5) This variable represents programmed width and/or pulse determined BTRL register. =0,and2 This variable represents programmed address setup time write determined data write cycle duration (defined DWA1 DWA0 bits BTRH register), BTRL register, value cycle with ALE, total write cycle duration DWA1/0 DWA1/0 DWA1/ DWA1/0= minus number clocks used and/or pulse (V8), minus number clocks used data hold time WM0= Example: DWA1/0=10,WM0= then V9=4-1 -2=1. cycle with ALE, total cycle duration DW1/0 OW1/0 DW1/0 DW1/0 minus number clocks used and/or pulse (V8), minus number clocks used data hold time Example: DW1/0=11, WM0=1, then V9=5-1 -1=3. V10) This variable represents length strobe calculation WAIT setup hold times. strobe (for data read cycles), and/or (for data write cycles), PSEN (for code read cycles), depending type cycle being widened WAIT. WAIT associated with code read cycle using PSEN data write cycle using and/or WRH. V7-1 data read cycle using This means that single clock data read cycle cannot stretched using WAIT. WAIT used vary duration data read cycles, strobe width must least clocks duration. Also Note V11) This variable represents programmed write hold time determined BTRL register. V11=0 bit=0, bit=1. V12) This variable represents programmed period between pulse beginning and/or pulse determined data write cycle duration (defined DWA1 DWA0 bits BTRH register), BTRL register, values V12= total cycle duration DWA1/0 =00, DWA1/0 DWA1/0 DWA1/0 minus number clocks used and/or pulse (V8), minus number clocks used data hold time minus width pulse (V1). Example:If DWA1/0= 11,WM0=1,WM1 ALEW then V12=5-1 -1-1.5=1.5. V13) This variable represents programmed data setup time write determined data write cycle duration (defined DWA1 DWA0 bits BTRH register), BTRL register, values cycle with ALE, total cycle duration DWA1/0 DWA1/0 DWA1/0 DWA1/0 minus number clocks used and/or pulse (V8), minus number clocks used data hold time minus number clocks used 0.5). Example:If DWA1/0= WM0=1, ALEW=0,then V13=5-1-2-1= -For cycle with ALE, total cycle duration DW1/0 DW1/0 DW1/ DW1/0= minus number clocks used and/or pulse (V8), minus number clocks used data hold time Example:If DW1/0=01, WM0=1, then V13=3 -1=1. combinations timing configuration values result valid cycles. Please refer User Guide section External details. 4.When code being fetched execution external bus, burst mode fetch used that does have PSEN edges every fetch cycle. Thus, WAIT used delay code fetch cycles, change order address lines must detected locate beginning cycle. This would A3-A0 8-bit bus, A3-A1 16-bit bus. Also, 16-bit data read operation conducted 8-bit wide similarly does include separate strobes. rising edge order address line (A0) must used trigger WAIT second halt such cycle.
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5.This parameter provided peripherals that have data clocked tailing edge strobe. This usually case, most applications this parameter used. 6.Please note that requires that extended data hold time (WM0 used with external write cycles. 7.Applies only external clock source, when crystal ceramic resonator connected XTAL1 XTA12 pins.
tLHLL
tAVLL
PSEN
tLLPL
tPLPH tPLIV tPXIZ
tLLAX
MULTIPLEXED ADDRESS DATA
A4-A11 A4-A19
tPXIX
INSTR
tAVIVA
UNMULTIPLEXED ADDRESS A1-3, A12-19
tIXUA
INSTR either D0-D7 D0-D15, depending width bits).
Figure External Program Memory Read Cycle (ALE Cycle)
PSEN
MULTIPLEXED ADDRESS DATA
A4-A11 A4-A19
INSTR
tAVIVB
UNMULTIPLEXED ADDRESS A1-3, A12-19 A1-A3, A12-19
INSTR either D0-D7 D0-D15, depending width bits).
Figure External Program Memory Read Cycle (Non-ALE Cycle)
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tLLRL
tRLRH tRHDZ
tAVLL
MULTIPLEXED ADDRESS DATA
tLLAX
tRLDV
tRHDX
INSTR
A4-A11 A4-A19
tAVDVA
UNMULTIPLEXED ADDRESS A1-A3, A12-19
tDXUA
INSTR either D0-D7 D0-D15, depending width bits).
Figure External Data Memory Read Cycle (ALE Cycle)
MULTIPLEXED ADDRESS DATA
A4-A11
D0-D7
DATA
tAVDVB
UNMULTIPLEXED ADDRESS A0-A3,A12-A19 A0-A3, A12-A19
Figure External Data Memory Read Cycle (Non-ALE Cycle)
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MX10EXA
tLLWL
tWLWH
tAVLL
MULTIPLEXED ADDRESS DATA
tLLAX
tQVWX
DATA OUT*
tWHQX
A4-A11 A4-A15
tAVWL
UNMULTIPLEXED ADDRESS A1-A3, A12-19
tUAWH
INSTR either D0-D7 D0-D15, depending width bits).
Figure External Data Memory Write Cycle
XTAL1
tCRAR
ADDRESS
WAIT
tWTH
STROBE (WRL,WRH, RD,OR PSEN)
tWTL
(The dashed line shows strobe without WAIT.)
Figure WAIT Signal Timing
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VDD-0.5 0.45V 0.7VDD 0.2VDD-0.1
tCHCX tCLCX tCHCH
tCHCL
Figure External Clock Drive
VDD-0.5
0.2VDD+0.9 0.2VDD-0.1
0.45V
NOTE: inputs during testing driven VDD-0.5 logic 0.45V logic "0". Timing measurements made point transitions.
VLOAD
VLOAD+0.1V VLOAD-0.1V
VOH-0.1V TIMING REFERENCE POINTS VOL+0.1V
NOTE: timing purposes, port longer floating when 100mV change from load voltage occurs, begins float when 100mV change from loaded VOH/VOL level occurs. IOH/IOL ±20mA
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(NC) CLOCK SIGNAL
XTAL2 XTAL1
(NC) CLOCK SIGNAL
XTAL2 XTAL1
Figure Test Condition, Active Mode other pins disconnected
Figure Test Condition, Idle Mode other pins disconnected
MAX.IDD (ACTIVE) CURRENT(mA) MAX.IDD (IDLE)
FREQUENCY (MHz)
Figure Frequency Valid only within frequency specification device under test.
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VDD-0.5 0.45V 0.7VDD 0.2VDD-0.1
tCHCX tCLCX tCLCH
tCHCL
Figure Clock Signal Waveform Tests Active Idle Modes tCLCH=tCHCL=5ns
XTAL2 XTAL1
(NC)
Figure Test Condition, Power Down Mode other pins disconnected. VDD=2V 5.5V
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PACKAGE INFORMATION
44-PIN PLASTIC LEADED CHIP CARRIER(PLCC)
ITEM
MILLIMETERS 17.53 16.59 16.59 17.53 1.95 4.70 max. 2.55 min. 1.27 [Typ.] 15.50 [Typ.]
INCHES .690 .005 .653 .005 .653 .005 .690 .005 .077 .185 .100 .010 .020 min. .050 [Typ.] .028 .004 .018 .004 .610 .020 .025 .010 [Typ.]
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LQFP44 plastic profile quad flat package leads body 1.4mm
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