DESCRIPTIO Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DESCRIPTIO Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S

Datasheet Thumbnail

Top Searches for this datasheet

LTC1419 14-Bit, 800ksps Sampling Converter with Shutdown
DESCRIPTIO
Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S/(N 93dB Missing Codes Pipeline Delay Sleep Shutdown Modes Operates with 2.5V Internal 15ppm/°C Reference External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full-Power Bandwidth Sampling Bipolar Input Range: ±2.5V 28-Pin SSOP Packages
®1419 1µs, 800ksps, 14-bit sampling converter that draws only 150mW from supplies. This easy-to-use device includes high dynamic range sample-and-hold precision reference. digitally selectable power shutdown modes provide flexibility power systems. LTC1419 full-scale input range ±2.5V. Outstanding performance includes 81.5dB S/(N 93dB with 100kHz input; 80dB S/(N 86dB Nyquist input frequency 400kHz. unique differential input sample-and-hold acquire single-ended differential input signals 20MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. compatible, 14-bit parallel output port. There pipeline delay conversion results. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors.
registered trademarks Linear Technology Corporation.
APPLICATIO
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
TYPICAL APPLICATIO
800kHz, 14-Bit Sampling Converter
LTC1419 DIFFERENTIAL AVDD +AIN ANALOG INPUT (-2.5V 2.5V) -AIN DVDD VREF REFCOMP BUSY 10µF AGND D13(MSB) CONVST SHDN 14-BIT PARALLEL DGND CONTROL LINES 10µF 10µF
Effective Bits Signal-to-(Noise Distortion) Input Frequency
EFFECTIVE BITS
VREF OUTPUT 2.50V
fSAMPLE 800kHz 100k INPUT FREQUENCY (Hz)
1419 TA01
SIGNAL/(NOISE DISTORTION) (dB)
1419 TA02
LTC1419
ABSOLUTE
RATI
PACKAGE/ORDER ATIO
VIEW +AIN -AIN VREF REFCOMP AGND D13(MSB) DGND PACKAGE 28-LEAD PLASTIC SSOP AVDD DVDD BUSY CONVST SHDN PACKAGE 28-LEAD PLASTIC
AVDD DVDD (Notes
Supply Voltage (VDD) Negative Supply Voltage (VSS) Total Supply Voltage (VDD VSS) Analog Input Voltage (Note 3).(VSS 0.3V) (VDD 0.3V) Digital Input Voltage (Note (VSS 0.3V) Digital Output Voltage (VSS 0.3V) (VDD 0.3V) Power Dissipation 500mW Operating Temperature Range LTC1419C 70°C LTC1419I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1419ACG LTC1419ACSW LTC1419AIG LTC1419AISW LTC1419CG LTC1419CSW LTC1419IG LTC1419ISW
TJMAX 110°C, 95°C/W TJMAX 110°C, 130°C/W (SW)
Consult factory Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note Internal Reference External Reference 2.5V IOUT(REF) (Note CONDITIONS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With Internal Reference (Notes
LTC1419 ±0.8 ±0.7
±1.5
LTC1419A ±0.6 ±0.5 ±1.25
UNITS Bits ppm/°C
ALOG denotes specifications which apply over full operating temperature range, otherwise
specifications 25°C. (Note
SYMBOL PARAMETER tACQ jitter CMRR Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio 2.5V AIN) 2.5V CONDITIONS 4.75V 5.25V, -5.25 4.75V High Between Conversions During Conversions
±2.5
UNITS
-1.5
psRMS
LTC1419
ACCURACY denotes specifications which apply over full operating temperature range,
otherwise specifications 25°C. (Note
SYMBOL S/(N SFDR PARAMETER Signal-to-(Noise Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth S/(N 77dB CONDITIONS 100kHz Input Signal 390kHz Input Signal 100kHz Input Signal, First Harmonics 390kHz Input Signal, First Harmonics 100kHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT IOUT
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 4.75V 10µA 200µA 4.75V 160µA 1.6mA VOUT VDD, High High (Note VOUT VOUT CONDITIONS 5.25V 4.75V
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
Level Output Voltage
ISOURCE ISINK
Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Mode Sleep Mode Negative Supply Current Mode Sleep Mode
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS (Note (Note
81.5 80.0
UNITS
(Note
2.480 2.500 0.05 4.06 2.520 UNITS ppm/°C LSB/V
4.75V 5.25V, 5.25 4.75V 0.1mA IOUT 0.1mA IOUT
UNITS
0.05 0.10
4.75 4.75
5.25 5.25
UNITS
SHDN SHDN
SHDN SHDN
LTC1419
POWER REQUIRE
SYMBOL PARAMETER PDIS Power Dissipation Mode Sleep Mode
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ CONV PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Conversion Time Setup Time CONVST Setup Time SHDN Setup Time CONVST Time CONVST BUSY Delay Data Ready Before BUSY
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS
SHDN CONVST Wake-Up Time (Note (Notes 25pF
Delay Between Conversions Wait Time After BUSY Data Access Time After
Relinquish Time 70°C 40°C 85°C Time CONVST High Time
Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together unless otherwise noted. Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below VSS, they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD. Note fSAMPLE 800kHz, unless otherwise specified. Note Linearity, offset full-scale specifications apply singleended +AIN input with grounded.
UNITS
SHDN SHDN
1040
1150 1250
UNITS
(Notes (Notes (Notes
(Note (Note 25pF
100pF
Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111 Note Guaranteed design, subject test. Note Recommended operating conditions. Note falling edge CONVST starts conversion. CONVST returns high critical point during conversion create small errors. best performance ensure that CONVST returns high either within 650ns after start conversion after BUSY rises.
LTC1419 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N Input Frequency Amplitude
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL/(NOISE DISTORTION) (dB)
SIGNAL-TO -NOISE RATIO (dB)
-20dB
-60dB
100k INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
-100 -110 -120 100k INPUT FREQUENCY (Hz) -100
AMPLITUDE (dB)
ERROR (LSBs)
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Integral Nonlinearity Output Code
-100 DGND 100k RIPPLE FREQUENCY (Hz)
COMMON MODE REJECTION (dB)
ERROR (LSBs)
-1.0 4096 12288 8192 OUTPUT CODE 16384
1419
1419 1419
Signal-to-Noise Ratio Input Frequency
-100
Distortion Input Frequency
100k INPUT FREQUENCY (Hz)
1419
100k INPUT FREQUENCY (Hz)
1419
Intermodulation Distortion Plot
fSAMPLE 800kHz fIN1 95.8984375kHz fIN2 104.1015625kHz
Differential Nonlinearity Output Code
-1.0
FREQUENCY (kHz)
1419
4096
12288 8192 OUTPUT CODE
16384
1419
Power Supply Feedthrough Ripple Frequency
Input Common Mode Rejection Input Frequency
1000 INPUT FREQUENCY (Hz)
10000
1419
1419
LTC1419
CTIO
(Pin ±2.5V Positive Analog Input. (Pin ±2.5V Negative Analog Input. VREF (Pin 2.5V Reference Output. Bypass AGND with 1µF. REFCOMP (Pin 4.06V Reference Output. Bypass AGND with 10µF tantalum parallel with 0.1µF 10µF ceramic. AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. output format complement. DGND (Pin 14): Digital Ground Internal Logic. AGND. (Pins 20): Three-State Data Outputs. output format complement. SHDN (Pin 21): Power Shutdown Input. selects shutdown. Shutdown mode selected mode sleep mode. (Pin 22): Read Input. This enables output drivers when low. CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select. input must recognize CONVST inputs. also sets shutdown mode when SHDN goes low. SHDN select quick wake-up mode. high SHDN select sleep mode. BUSY (Pin 25): BUSY output shows converter status. when conversion progress. Data valid rising edge BUSY. (Pin 26): Negative Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF 10µF ceramic. DVDD (Pin 27): Positive Supply. Short AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF 10µF ceramic.
CTIO BLOCK DIAGRA
+AIN
VREF 2.5V ZEROING SWITCHES
REFCOMP (4.096V) AGND DGND INTERNAL CLOCK CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER OUTPUT LATCHES
CSAMPLE
CSAMPLE
AVDD DVDD
14-BIT CAPACITIVE COMP
1419
SHDN
CONVST
BUSY
LTC1419
TEST CIRCUITS
Load Circuits Access Timing
100pF 100pF
Load Circuits Output Float Delay
Hi-Z
Hi-Z
1419 TC01
Hi-Z
Hi-Z
1419 TC02
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1419 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 14-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs (please refer Digital Interface section data format). Conversion start controlled CONVST inputs. start conversion, successive approximation register (SAR) reset. Once conversion cycle begun, cannot restarted.
+CSAMPLE +AIN SAMPLE HOLD SAMPLE -CSAMPLE HOLD +CDAC ZEROING SWITCHES HOLD
-AIN
HOLD
+VDAC -CDAC COMP
-VDAC
OUTPUT LATCHES
1419
Figure Simplified Block Diagram
During conversion, internal differential 14-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure +AIN inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 200ns will provide enough time sampleand-hold capacitors acquire analog signal. During convert phase, comparator zeroing switches open, putting comparator into compare mode. input switches CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances input charges. contents 14-bit data word) which represents difference loaded into 14-bit output latches. DYNAMIC PERFORMANCE LTC1419 excellent high speed sampling capability. (Fast Fourier Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined
LTC1419
APPLICATIONS INFORMATION
frequencies outside fundamental. Figure shows typical LTC1419 plot.
-100 -120 -140 FREQUENCY (kHz)
1419 F02a
fSAMPLE 800kHz 99.804687kHz SFDR 98dB -93.3dB
AMPLITUDE (dB)
Figure LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency 100kHz
-100 -120 -140 FREQUENCY (kHz)
1419 F02b
EFFECTIVE BITS
fSAMPLE 800kHz 375kHz SFDR 88.3dB SINAD 80.1
AMPLITUDE (dB)
Figure LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency 375kHz
Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 800kHz sampling rate 100kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 400kHz.
Effective Number Bits effective number bits (ENOBs) measurement resolution directly related S/(N equation: [S/(N 1.76]/6.02 where effective number bits resolution S/(N expressed maximum sampling rate 800kHz, LTC1419 maintains near ideal ENOBs Nyquist input frequency 400kHz (refer Figure
fSAMPLE 800kHz 100k INPUT FREQUENCY (Hz)
SIGNAL/(NOISE DISTORTION) (dB)
1419 TA02
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
Total Harmonic Distortion Total harmonic distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
where amplitude fundamental frequency through amplitudes second through harmonics. Input Frequency shown Figure LTC1419 good distortion performance Nyquist frequency beyond. 20Log
LTC1419
APPLICATIONS INFORMATION
AMPLITUDE BELOW FUNDAMENTAL)
-100 100k INPUT FREQUENCY (Hz)
1419
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies ±nfb, where etc. example, order terms include
AMPLITUDE (dB)
fSAMPLE 800kHz fIN1 95.8984375kHz fIN2 104.1015625kHz
-100 -120
FREQUENCY (kHz)
1419
Figure Intermodulation Distortion Plot
fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
Amplitude Amplitude
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Full-Power Full-Linear Bandwidth full-power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full-linear bandwidth input frequency which S/(N dropped 77dB (12.5 effective bits). LTC1419 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1419 easy drive. inputs driven differentially singleended input (i.e., input grounded). inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sampleand-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit low, then LTC1419 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time with high source impedance, buffer amplifier should used. only requirement
LTC1419
APPLICATIONS INFORMATION
that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 200ns full throughput rate).
ACQUISITION TIME (µs)
0.01 0.01
SOURCE RESISTANCE
1419
Figure tACQ Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance 100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz should less than 100. second requirement that closed-loop bandwidth must greater than 20MHz ensure adequate small-signal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1419 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1419. More detailed information available Linear Technology databooks, LinearViewCD-ROM site www.lineartech. com.
LinearView trademark Linear Technology Corporation.
1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ±15V supplies. Excellent specifications. LT1223: 100MHz video current feedback amplifier. ±15V supplies, supply current. distortion frequencies above 400kHz. noise. Good applications. LT1227: 140MHz video current feedback amplifier. ±15V supplies, 10mA supply current. Lowest distortion frequencies above 400kHz. noise. Best applications. LT1229/LT1230: Dual/quad 100MHz current feedback amplifiers. ±15V supplies, supply current each amplifier. noise. Good specs. LT1360: 50MHz voltage feedback amplifier. ±15V supplies, 3.8mA supply current. Good specs. LT1363: 70MHz, 1000V/µs amps, 6.3mA supply current. Good specs. LT1364/LT1365: Dual quad 70MHz, 1000V/µs amps. 6.3mA supply current amplifier. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1419 noise distortion. small-signal bandwidth sample-and-hold circuit 20MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient
ANALOG INPUT 1000pF -AIN LTC1419 VREF +AIN
10µF
REFCOMP
AGND
1419
Figure Input Filter
LTC1419
APPLICATIONS INFORMATION
many applications. example, Figure shows 1000pF capacitor from ground source resistor limit input bandwidth 1.6MHz. 1000pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. Input Range ±2.5V input range LTC1419 optimized noise distortion. Most amps also perform well over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1419 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1419 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure
VREF BANDGAP REFERENCE
LT1019A-2.5 VOUT ANALOG INPUT +AIN -AIN VREF LTC1419
2.500V
4.0625V
REFCOMP
REFERENCE LTC1419
1419 F08a
10µF
AGND
Figure LTC1419 Reference Circuit
10µF 0.1µF
REFCOMP
AGND
1419 F08b
Figure Using LT1019-2.5 External Reference
resistor series with output that easily overdriven external reference other circuitry, Figure reference amplifier gains voltage VREF 1.625 create required internal reference voltage. This provides buffering between VREF high speed capacitive DAC. reference amplifier compensation (REFCOMP, must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended. VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1419 reference amplifier will limit bandwidth settling time this circuit. settling time should allowed after reference adjustment.
ANALOG INPUT 1.25V DIFFERENTIAL +AIN
-AIN LTC1419
LTC1450
1.25V
VREF
10µF
REFCOMP
AGND
1419
Figure Driving VREF with
LTC1419
APPLICATIONS INFORMATION
Differential Inputs LTC1419 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference AIN) independent common mode voltage (see Figure 11a). common mode rejection holds extremely high frequencies, Figure 10a. only requirement that both inputs exceed AVDD AVSS power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage, however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Dynamic performance also affected common mode voltage. will degrade inputs approach either power supply rail, from 86dB with common mode 76dB with common mode 2.5V 2.5V.
COMMON MODE REJECTION (dB)
OUTPUT CODE
1000 INPUT FREQUENCY (Hz) 10000
1419
Figure 10a. CMRR Input Frequency
±2.5V
ANALOG INPUT
+AIN -AIN
VREF LTC1419
10µF
REFCOMP AGND
1419
Figure 10b. Selectable ±2.5V Input Range
Differential inputs allow greater flexibility accepting different input ranges. Figure shows circuit that converts analog input signal with only additional buffer that signal path. Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1419. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,. 1.5LSB, 0.5LSB). output two's complement binary with 1LSB FS)/16384 5V/16384 305.2µV. applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset
011.111 011.110
000.001 000.000 111.111 111.110 100.001 100.000 1LSB) 1LSB
1419 F11a
INPUT VOLTAGE [+AIN (-AIN)]
Figure 11a. LTC1419 Transfer Characteristics
ANALOG INPUT
+AIN -AIN LTC1419 VREF REFCOMP AGND
1419 F11b
10µF
0.1µF
Figure 11b. Offset Full-Scale Adjust Circuit
LTC1419
APPLICATIONS INFORMATION
applied input. zero offset error, apply 152µV (i.e., 0.5LSB) adjust offset input until output code flickers between 0000 0000 0000 1111 1111 1111 full-scale adjustment, input voltage 2.499544V (FS/2 1.5LSBs) applied adjusted until output code flickers between 0111 1111 1111 0111 1111 1111 BOARD LAYOUT GROUNDING Wire wrap boards recommended high resolution high speed converters. obtain best performance from LTC1419, printed circuit board with ground plane required. Layout should ensure that digital analog signal lines separated much possible. Particular care should taken digital track alongside analog signal track underneath ADC.The analog input should screened AGND. analog ground plane separate from logic system ground should established under around ADC. (AGND), (ADC's DGND) other analog grounds should connected this single analog ground point. REFCOMP bypass capacitor DVDD bypass capacitor should also connected this analog ground plane. other digital grounds should connected this analog ground plane. impedance analog digital power supply common returns essential noise operation foil width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into WAIT state during conversion using three-state buffers isolate data bus. traces connecting pins bypass capacitors must kept short should made wide possible. LTC1419 differential inputs minimize noise coupling. Common mode noise leads will rejected input CMRR. input used ground sense input; LTC1419 will hold convert difference voltage between AIN. leads (Pin (Pin should kept short possible. applications where this possible, traces should side side equalize coupling. SUPPLY BYPASSING High quality, series resistance ceramic, 10µF bypass capacitors should used REFCOMP pins shown Typical Application fist page this data sheet. Surface mount ceramic capacitors such Murata GRM235Y5V106Z016 provide excellent bypassing small board space. Alternatively, 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Example Layout Figures 13a, 13b, show schematic layout suggested evaluation board. layout demonstrates proper decoupling capacitors ground plane with 2-layer printed circuit board.
+AIN -AIN REFCOMP AGND 10µF
ANALOG INPUT CIRCUITRY
ANALOG GROUND PLANE
1419
Figure Power Supply Grounding Practice
LTC1419 10µF AVDD DVDD DGND
DIGITAL SYSTEM
10µF
LTC1419
22µF 74HC574 B[00:13] 0.1µF DATA READY VLOGIC HC14 HC14 0.1µF HC14 HC14 15pF 74HC574 HC14 J6-13 J6-14 J6-11 J6-12 J6-9 J6-10 J6-7 J6-8 J6-5 J6-6 J6-3 J6-4 J6-1 J6-2 J6-15 J6-16 J6-17 J6-18 DGND DGND HEADER 18-PIN DGND AGND DVDD AVDD SHDN CONVST BUSY REFCOMP VREF -AIN +AIN LTC1419 0.1µF VOUT
1000pF
AGND
DGND
1000pF
LT1363
APPLICATIONS INFORMATION
1000pF
10µF
HC14
HC14
VLOGIC 10µF 10µF
JP5C
JP5B
JP5A
SHDN
NOTES: UNLESS OTHERWISE SPECIFIED RESISTOR VALUES OHMS, 1/10W, CAPACITOR VALUES 25V, 50V,
DC124 SCHEM
Figure 13a. Suggested Evaluation Circuit Schematic
10µF
-VIN D[00:13] 1.2k 22µF 0.1µF 0.1µF VLOGIC -15V
LT1121-5
+VIN
VOUT
TABGND
SS12
79L05 SS12
LTC1419
APPLICATIONS INFORMATION
Figure 13b. Suggested Evaluation Circuit Board-Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board-Component Side Layout
LTC1419
APPLICATIONS INFORMATION
Figure 13d. Suggested Evaluation Circuit Board-Solder Side Layout
DIGITAL INTERFACE converter designed interface with microprocessors memory mapped device. control inputs common peripheral memory interfacing. separate CONVST used initiate conversion. Internal Clock converter internal clock that eliminates need synchronization between external clock signals found other ADCs. internal clock factory trimmed achieve typical conversion time 0.95µs maximum conversion time over full operating temperature range 1.15µs. external adjustments required. guaranteed maximum acquisition time 300ns. addition, throughput time 1.25µs minimum sampling rate 800ksps guaranteed. Power Shutdown LTC1419 provides power shutdown modes, sleep, save power during inactive periods.
mode reduces power leaves only digital logic reference powered wake-up time from active 400ns. sleep mode, reference shut down only small current remains, about 250µA. Wake-up time from sleep mode much slower since reference circuit must power settle 0.005% full 14-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 10ms with recommended 10µF capacitor. Shutdown controlled (SHDN); shutdown when low. shutdown mode selected with (CS); selects nap.
SHDN
1419 F14a
Figure 14a. SHDN Timing
LTC1419
APPLICATIONS INFORMATION
SHDN CONVST
1419 F14b
Figure 14b. SHDN CONVST Wake-Up Timing
Timing Control Conversion start data read operations controlled three digital inputs: CONVST, logic applied CONVST will start conversion after been selected (i.e., low). Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Figures through show several different modes operation. modes (Figures 17), both tied low. falling edge CONVST starts conversion. data outputs always enabled data latched with BUSY rising edge. Mode shows operation with narrow logic CONVST pulse. Mode shows narrow logic high CONVST pulse. mode (Figure 18), tied low. falling edge CONVST signal again starts conversion. Data outputs three-state until read with signal. Mode used operation with shared databus.
(SAMPLE CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
1419
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled (CONVST
slow memory modes (Figures 20), tied CONVST tied together. starts conversion reads output with signal. Conversions started external sample clock). slow memory mode, processor applies logic CONVST), starting conversion. BUSY goes low, forcing processor into WAIT state. previous conversion result appears data outputs. When conversion complete, conversion results appear data outputs; BUSY goes high, releasing processor processor takes CONVST) back high reads conversion data. mode, processor takes CONVST) low, starting conversion reading previous conversion result. After conversion complete, processor read result initiate another conversion.
1419
Figure CONVST Set-Up Timing
CONV
LTC1419
APPLICATIONS INFORMATION
CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
1419
tCONV
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled (CONVST
(SAMPLE tCONV
CONVST BUSY DATA DATA DB13
1419
Figure Mode CONVST Starts Conversion. Data Read
(SAMPLE CONVST BUSY DATA
CONV
DATA DB13
Figure Slow Memory Mode Timing
DATA DB13 DATA DB13 DATA DB13
1419
LTC1419
APPLICATI
ATIO
CONV (SAMPLE
CONVST BUSY DATA
DATA DB13
Figure Mode Timing
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise noted. Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
5.20 5.38** (0.205 0.212)
0.13 0.22 (0.005 0.009)
0.55 0.95 (0.022 0.037)
NOTE: DIMENSIONS MILLIMETERS *DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.152mm (0.006") SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.254mm (0.010") SIDE
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
DATA DB13
1419
10.07 10.33* (0.397 0.407)
7.65 7.90 (0.301 0.311)
1.73 1.99 (0.068 0.078)
0.65 (0.0256)
0.25 0.38 (0.010 0.015)
0.05 0.21 (0.002 0.008)
SSOP 1098
LTC1419
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise noted.
Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC 05-08-1620)
0.697 0.712* (17.70 18.08)
NOTE
0.394 0.419 (10.007 10.643)
0.291 0.299** (7.391 7.595) 0.010 0.029 (0.254 0.737)
0.093 0.104 (2.362 2.642)
0.037 0.045 (0.940 1.143)
0.009 0.013 (0.229 0.330)
NOTE 0.016 0.050 (0.406 1.270)
0.050 (1.270)
NOTE: IDENT, NOTCH CAVITIES BOTTOM PACKAGES MANUFACTURING OPTIONS. PART SUPPLIED WITH WITHOUT OPTIONS *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.014 0.019 (0.356 0.482)
0.004 0.012 (0.102 0.305)
(WIDE) 1098
RELATED PARTS
PART NUMBER LTC1278/79 LTC1400 LTC1409 LTC1410 LTC1415 LTC1604 LTC1605 LTC1606 LTC1608 DESCRIPTION Single Supply, 500ksps/600ksps ADCs High Speed, Serial 12-Bit Power, 12-Bit, 800ksps Sampling 12-Bit, 1.25Msps Sampling with Shutdown Single 12-Bit 1.25Msps 16-Bit 333ksps Single 16-Bit 100ksps 16-Bit 250ksps 16-Bit 500ksps COMMENTS Power, Supply 400ksps, Complete with Internal Reference, SO-8 Package Best Dynamic Performance, fSAMPLE 800ksps, 80mW Dissipation Best Dynamic Performance, 84dB SINAD 71dB Nyquist Single Supply, 55mW Dissipation ±2.5V Inputs, Compatible with LTC1608 Power, ±10V Inputs ±10V Inputs, Compatible with LTC1605 ±2.5V Inputs, Compatible with LTC1604
1419fa LT/TP 0600 PRINTED
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417 (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1997

DESCRIPTIO Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S

Top Searches for this datasheet

Other recent searches