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Raybarman 1394 Applications Group
Abstract
This document makes recommendations layout Link layer devices IEEE 1394 environment. optimal performance IEEE 1394 depend good board layout. IEEE 1394 board that does adhere good layout guidelines susceptible noise interference, which could diminish signal integrity. This document meant general tutorial good printed circuit board (PCB) layout practice; meant highlight those areas 1394 node that need special attention special requirements IEEE 1394 nodes.
Contents
Introduction Guidelines Layout Interference.13 PowerPAD Packaging.14
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical IEEE 1394 Node.2 Connector Cable Connector Terminating Resistor Conservative Etch Length Between PHY-Link Best-Case Etch Length Between PHY-Link Signal Traveling Over Long Etch Signal Traveling Over Short Etch.7 Etch Length Differential Signals Equal Etch Length TPA- Longer Than TPA+.8 Etch Length Both Differential Signal Pairs Align Headed Pair Etches Matched Each Other Longer Than Pair Vias More Likely Pick Interference From Other Layers Board Power Supply Clock Connection Physical Layer.11 View 41LV0x PHY.11 Power Groups PHY.12 PHY/Link Interface Signals Should Close Have Same Etch Length Bottom View Different Packages.14 PowerPAD Package Layout Section View PowerPAD Package
Digital Signal Processing Solutions
March 1999
Introduction
Figure Typical IEEE 1394 Node
Cable Connector
Micro-Controller
LINK Layer
Layer
Physical Layer (PHY) provides digital logic analog transceiver functions needed implement one- multiple-port physical layer IEEE 1394 network. Each cable port incorporates differential line transceivers. transceivers include circuitry monitor line conditions needed determining connection status, initialization arbitration, packet reception transmission. 1394 link layer communicates with physical layer, packetizes data decoded physical layer, provides cycle timing functions, communicates packets from node controller. Figure illustrates logical layout points discussed this document. Distance between physical layer cable connector distance between link layer physical layer discussed this document. layout distance between micro-controller link layer heavily dependent microprocessor chosen outside scope this document.
Guidelines Layout
This section discusses following guidelines layout:
physical layer should close possible 1394 connector (refer Figure Figure Because frequencies involved Mbps) etches propagating differential twisted pair (TP) signal 1394 cable should treated transmission lines. signal swing lines relatively small (~110 mV), differential noise picked twisted pair affect received signal. When twisted pair signal propagated etch without shielding, etch tends behave antenna picks noise generated surrounding components environment. minimize effect this behavior well other artifacts documented below, minimize distance twisted pair signal must propagated etch. shielding standard 1394 cable inhibits this sort interference while signal propagated through cable.
Recommendations Layout
Figure Connector Cable Connector
Minimize this distance
TPA+
TPA+
TSB41LV0x
TPATPB+ TPB-
Connector
TPATPB+ TPB-
Cable Connector
Since etch traces should treated transmission lines, they must match impedance with cable connector they connected IEEE standard 1394 twisted pair cable specified have (±6) ohms differential characteristic with common mode characteristic impedance (±6) ohms (IEEE 1394-1995 paragraph 4.2.1.4.1). input impedance node also specified (±1) ohms receive mode (IEEE 1394-1995 paragraph 4.2.2.5), hence recommended termination network (±1%) resistors (for more information, TSB41LV0x data sheet). minimize reflections maximize power transmitted input pin, etch length between termination physical layer 1394 cable connector ports should designed with characteristic impedance ohms between lines with minimum ohms ground. That etch should have same impedance cable termination network. Having different impedance causes reflections with less power being transmitted input terminals physical layer, which reduce signal integrity.
Recommendations Layout
Figure Terminating Resistor
note related termination resistors ohms ±1%) should located close possible (twisted pair) pins 1394 physical layer (refer Figure purpose terminating resistor network match impedance with cable transmission line, minimizing induced signal reflections. Placing termination resistors close physical layer signal reduces stub length between physical layer terminal termination resistor. longer stub, better antenna makes, more noise interference picks that distort signal. There tradeoffs between these first three recommendations. better etch impedance matches cable, longer etches be-to point. lower induced noise sources around etches, longer they be-to point. better impedance match etches, longer termination resistors from physical layer-to point. point breaks will vary with above factors (and more).
Rule thumb maximum etch length without matching impedance. following justification calculate maximum length etch PCB. After signal been transmitted, travels length etch reflection travels equal length back, this must take place well under rise time signal. rise time longer, behaves transmission line.
Recommendations Layout
following equation: Letch acceptable etch length Dmax distance traveled during rise time propagation speed signal speed light Letch Dmax/ ~2.5, more conservative Letch Dmax Trisetime rise time Dmax Trisetime*S propagation speed signal C=2.997E Dielectric constant Here conservative example etch length without impedance match:
Letch (Trisetime* S)/divisor_factor
Minimum 1394a Spec rise time Maximum typical FR-4 dielectric constant Maximum divisor factor Letch {(0.5E s)(2.997E m/s) 5.3} Letch 0.011 meters (0.4")
Figure Conservative Etch Length Between PHY-Link
LINK
0.4"
Here unrealistic best-case example: Letch (Trisetime S)/divisor_factor Maximum1394a Spec rise time (400 Mbps) Minimum typical FR-4 dielectric constant Minimum divisor factor 2.51 Letch {(1.2E s)(2.997E m/s) 2.51 Letch 0.071 meters (2.8")
Recommendations Layout
Figure Best-Case Etch Length Between PHY-Link
LINK
2.8"
length etch depends rising edge signal. longer etch, greater chances signal reflect back behave transmission line.
Figure Signal Traveling Over Long Etch
Recommendations Layout
Figure depicts signal traveling over length etch inches long. time there activity bus, flatline. start rising edge signal. time complete signal that been launched. When looking signal from inch etch, logic high. When looking same signal same instant from other 20-inch etch, logic `0', low. time same signal that with change except that traveling horizontally over etch. This instant when signal leading-edge wave distributed across impedance 20-inch etch itself. these cases, etch path should treated transmission line. After signal launched, must travel over impedance etch. This causes signal lose strength integrity.
Figure Signal Traveling Over Short Etch
Figure depicts same signal shown Figure traveling over etch length inch. time there activity flatline. time progresses, observe that point logic high etch while simultaneously seeing logic other etch.
Recommendations Layout
This indicates that voltage every part etch uniform (almost) without significant change swing that would indicate high other vice versa. short length transmission line effects take place signal integrity maintained.
Figure Etch Length Differential Signals Equal
Figure Etch Length TPA- Longer Than TPA+
Figure Etch Length Both Differential Signal Pairs Align Headed
Recommendations Layout
Figure Pair Etches Matched Each Other Longer Than Pair
etch lengths TPA+ TPA- must matched. same reasons, TPB+ TPB- etch lengths must same. both cases this required reduce skew differential signals (skew measured comparing propagation delay signals being measured). sensed difference between TPx+ TPx- signals what sensed receiver determine zero. difference length will change timing relationship between signals, reducing skew margin built into system, (see Figure illustration). Also related this, pair should have approximately same etch length pair single port. Data-Strobe encoding data being sent across twisted pair depends relative timing between "1"s "0"s being signaled differential pairs. delay signals through etches different, will change timing relationship these signals, again reducing skew margin coding. Therefore etch lengths twisted pairs should kept close same possible.
Recommendations Layout
Figure Vias More Likely Pick Interference From Other Layers Board
minimize number vias twisted pair lines. When must used, increase clearance size around minimize capacitance. Each introduces discontinuities signal's transmission line increases chance picking interference from other layers board. similar reasons careful using through-hole pins test points twisted pair lines. Through-hole pins inductance transmission line, which reduce signal integrity. Keep 24.576-MHz crystal load capacitors close possible pins (Refer Figure 13). greater distance greater chances interference from noise that interfere with frequency lock internal phase locked loop (PLL). Maintaining frequency extremely crucial critical applications. Components board that interfere with clock frequency should placed close proximity clock. Frequencies from power sources large capacitors cause modulations within clock cause sync. these instances errors such dropped packets occur. external crystal internal oscillator drive internal phase locked loop, which generates required reference signal. reference signal internally divided provide clock signals used control transmission outbound encoded Strobe Data information system clock (SCLK) sent link layer synchronize PHY-Link interface. modulation) 49.152 MHz. When designing application with 1394 Physical layer, termination capacitor each crystal, feeding XI/XO terminals must properly chosen ensure reliable operation. capacitance used low, then frequency accuracy SCLK terminal will 100-ppm specification. This cause data errors large packets. capacitance high, oscillator will oscillate. optimal results load capacitance crystal must matched with capacitor placed crystal
SCLK (clock generated PHY) must within (pulse-position
Recommendations Layout
terminals. adjacent nodes more than with another, long packets sent across 1394 corrupt, with final bits packet being lost.
Figure Power Supply Clock Connection Physical Layer
Place power decoupling capacitors close possible power supply
pins. capacitors create filter reduce noise coupled into device across power plane, which helps maintain signal integrity. Keeping etch short between capacitors device minimizes stub antenna, minimizing noise coupled device side filter network. noise also very much dependent application, take precautions conservatively noisy environment example.
Figure View 41LV0x
DIGITAL
ANALOG
There parts PHY, analog digital. analog pins
concentrated half PHY, digital pins other half. optimal performance suggest having 0.001-mF each power pin, i.e. VCC, VDD, PLL. Also have 0.1-mF capacitor each separate power group. group number power pins from higher that adjacent each other.
Recommendations Layout
Figure Power Groups
Figure there three separate groups. first group consists pins adjacent each other, next group pin, third group consists three pins together. this scenario, need 0.1-mF capacitor each group.
When using switching power regulator produce regulated power from
unregulated cable power from another higher voltage supply, should placed carefully. switching regulator should kept away from, specifically, twisted pair etches, external clock crystal clock oscillator used), physical layer device general. Switching regulators source noise and, placed close sensitive areas circuit board, increase chance noise being coupled into sensitive signal.
Figure PHY/Link Interface Signals Should Close Have Same Etch Length
keep PHY-Link interface (SCLK, LREQ, [0,1], DATA [0:x]) short
(less than inches practical). signals driven across PHY-Link interface 3.3-V CMOS levels both Link 3.3-V CMOS) 49.152 should treated with care. These signals should also approximately same length. (Refer Figure 16). short distance minimize noise coupling from other devices signal loss resistance. They should kept same length reduce propagation delay mismatches across this synchronous interface.
Recommendations Layout
Interference
significance electromagnetic compatibility (EMC) electronic circuits systems more stringent requirements electromagnetic properties equipment. electronic circuit mainly determined components laid with respect each other electrical connections made between components. Every current flowing line generates current same magnitude flowing corresponding return line. This loop creates antenna that radiate electromagnetic energy whose magnitude determined current amplitude, repetition frequency signal, geometry current loops. strategy reduce radiated (electromagnetic interference) terminate SCLK signal ensure clean clock signal. This done with approximately 10ohm 20-ohm series resistor source (PHY) side SCLK signal increase source impedance reduce reflections. impedance value used will function characteristic impedance your board. minimize change delays PHY-Link interface, same termination should also placed data lines, control lines, LREQ line. Additionally, reduce propagated through cable shield, experiment with different values capacitors used parallel network isolate cable shield ground from chassis ground. Additional recommendations reduce found application note Printed Circuit Board Layout Improved Electromagnetic Compatibility
Ensure ground return paths close possible signal paths. Longer return paths create loops that likely radiate EMI. Series terminate SCLK help clean clock signal Avoid discontinuities ground return paths. Isolated ground planes should capacitively coupled together provide signal return path. Avoid running digital CMOS-level signals (SCLK) near sensitive analog signals lines, Crystal) when running traces. Place resistor ACAP PHY. Resistor value dependent characteristic impedance board. Series Resistor Source Impedance Etch Impedance reduce from cable shield noise coupled chassis ground, experiment with different value caps isolate cable shield ground from chassis ground. 90-degree corner traces-this causes discontinuities.
Recommendations Layout
PowerPAD Packaging
400-Mbps housed high-performance, thermally-enhanced package. PowerPADpackage does require special consideration except note that PowerPAD, which exposed bottom device, metallic thermal electrical conductor. Therefore, implementing PowerPAD features, solder mask required prevent shorting exposed PowerPAD connections, etches, vias under package. recommended option etches signal vias under package have grounded thermal land.
Figure Bottom View Different Packages
Typical Package
PowerPAD Package
Leadframe
recommended that there thermal land, area solder-thinned-copper, underneath PowerPAD package. thermal land will vary size depending PowerPAD package being used, construction, amount heat that needs removed. thermal bottom device directly connected silicon die.
Figure PowerPAD Package Layout
Leadframe Ground
Recommendations Layout
Using PowerPAD feature, only able improve thermal performance also electrical grounding device. also recommended that device ground landing pads connected directly grounded thermal land. land size should large possible without shorting device signal pins. thermal soldered exposed PowerPAD using standard reflow soldering techniques. Using PowerPAD packaging, able Theta (junction ambient) 17.3, Theta (junction case) 0.12 additional cost.
Figure Section View PowerPAD Package
Recommendations Layout
Contact Numbers
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty, endorsement thereof. Copyright 1999 Texas Instruments Incorporated
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