Bhaskar Goswami Rajiv Mantri ABSTRACT This application report discusse

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Using ADS8411/ADS8412 Serial
Bhaskar Goswami Rajiv Mantri ABSTRACT This application report discusses parallel serial using low-cost CPLD. This concept tested with Texas Instruments ADS8411/12 (16-bit, MSPS ADC) AlteraMAX 3000A CPLD. full solution with schematic, layout, software programming CPLD presented report. Contents Introduction Hardware.2 ADS8411 3000A CPLD.2 ByteBlasterMV Cable Hardware Interface.2 Timing QuartusII Appendix Logic Diagram, Description, Verilog Code CPLD Program Appendix ADS8411 Schematic Figures Simplified Block Diagram Timing Diagram MSPS.3 Tables Chipset Timings Data Acquisition Products
Figure Figure
Table
Altera, Quartus, MAX, ByteBlaster trademarks Altera Corporation.
SLAA199
Introduction
Texas Instruments ADS8411 16-bit, MSPS, unipolar single-ended with parallel interface internal reference. ADS8412 16-bit, MSPS, unipolar differential with parallel interface internal reference. complement serial interface, this application report discusses this serial output ADC. convert parallel data serial output, CPLD (complex programmable logic device) used. same CPLD converts serial control signals SCLK, etc.) parallel control signals sends them device. user, along with CPLD (henceforth referred chipset) serial device. user sends serial control signals chipset receives serial data outputs. AlteraMAX 3000A-series CPLD used.
Hardware
hardware platform comprises ADS8411 3000A CPLD. program one-time programmable CPLD, AlteraByteBlasterMV cable used.
ADS8411
ADS8411 16-bit, 2-MHz converter with internal 4.096-V reference. device includes 16-bit, capacitor-based, converter with inherent sample hold capability.
3000A CPLD
AlteraMAX 3000A-series CPLD selected this solution because cost, ease use, does need configuration device. 3000A CPLD part number EPM3032ATC44-10.
ByteBlasterMV Cable
ByteBlasterMV parallel port download cable (ordering code: PL-BYTEBLASTERMV) connects standard parallel port (also known port). This cable drives configuration data from 3000A devices configuration devices. Because design changes downloaded directly CPLD, prototyping easy, multiple design iterations accomplished quickly.
Hardware Interface
ADS8411 sends parallel data (D0-D15) CPLD (see Figure SCLK sent CPLD from outside. CPLD generates CONVST signal control parallel device also outputs serial data. schematics Appendix more detail.
Using ADS8411/ADS8412 Serial
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Parallel Data Analog Input ADS8411/2 CPLD
Serial Control Signal
Serial Data Parallel Control Signal
Figure
Simplified Block Diagram
system inside dashed line Figure works serial part.
tsu1
SCLK
BUSY
ttp4
Figure
Timing Diagram MSPS
Timing
serial interface used this chipset (serial peripheral interface) compatible. SCLK signals control chipset (see Figure data only available when low. Otherwise, 3-state mode. After falling edge, chipset waits falling edge SCLK. This clock counted first SCLK. data appears after falling edge. Then, next data appears after rising edge second SCLK. Only clocks frame necessary chipset work. After that, clock free-running withdrawn.
Using ADS8411/ADS8412 Serial
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Table
Symbol tsu1
Chipset Timings
15.5 15.5
Parameter Width full frame Pulse duration, high time Hold time, falling edge (first SCLK falling edge after toggles from high low) SCLK falling edge
Setup time, clock rising edge rising edge
Unit
Cycle time, SCLK Pulse duration, SCLK high Pulse duration, SCLK Delay, high 3-state Delay, Falling edge Pulse duration, Busy high clock rising edge Busy High Delay, Rising edge SCLK toggle
Maximum pulse duration data taken from ADS8411 data sheet (SLAS369).
QuartusII
logic converting parallel data serial data serial control signals parallel control signals written Quartus software from Altera. Verilog used write hardware description. program CPLD, user needs download Quartus free evaluation version from www.altera.com. program downloaded ByteBlasterMV cable through parallel port. Verilog file schematics also available appendixes.
Using ADS8411/ADS8412 Serial
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Appendix Logic Diagram, Description, Verilog Code CPLD Program
Figure A-1.
Logic Diagram
Using ADS8411/ADS8412 Serial
SLAA199 CPLD Program Logic
A.1.1 Parallel Data Serial Data
Shift_register (inst) 16-bit parallel-to-serial shift register (see Figure A-1). loads 16-bit data when load Otherwise, shifts 16-bit data every positive edge clock. Serial data given MSB-first format. When high, 16-bit data loaded into shift register, SCLK disabled until low. After goes low, chipset responds SCLK falling edge. incorporate this logic, inverted Chip Select signal sent input (inst2), inverted SCLK signal sent clock input DFF. output generates enable signal clock shift register.
CONVST Generation
3-bit counter (inst6) along with gates (inst7, generates CONVST parallel device. This conversion start signal required parallel device. resets counter, output 4-input gate sets counter. ensures that counter stopped after 16th clock. Otherwise, counter keeps producing CONVST even toggled. CONVST remains high from clock 15th clock. 16th clock, falls conversion starts.
Verilog Code CPLD Program (File: shift_register.v)
module shift_register(clk, load, data, sdo); parameter length=16; input clk, load; input [length-1:0] data; output sdo; sdo; [length-1:0] always (posedge posedge load) begin if(load) q<=data; else begin q[15]<=q[14]; q[14]<=q[13]; q[13]<=q[12]; q[12]<=q[11]; q[11]<=q[10]; q[10]<=q[9]; q[9]<=q[8];
Using ADS8411/ADS8412 Serial
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q[8]<=q[7]; q[7]<=q[6]; q[6]<=q[5]; q[5]<=q[4]; q[4]<=q[3]; q[3]<=q[2]; q[2]<=q[1]; q[1]<=q[0]; sdo<=q[length-1]; endmodule
Using ADS8411/ADS8412 Serial
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Appendix ADS8411 Schematic
Sheets ADS8411 schematic follow.
Using ADS8411/ADS8412 Serial
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