SDYA006 February 1997 Copyright 1997, Texas Instruments Incorpora

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SDYA006 February 1997 Copyright 1997, Texas Instruments Incorpora

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Metastable Response Logic Circuits
SDYA006 February 1997
Copyright 1997, Texas Instruments Incorporated
Contents
Title Page Abstract Introduction Definition Metastable State Description Test Circuit Test Results Circuitry Measures Integrated Synchronization Circuits Summary Acknowledgment
List Illustrations
Figure Title Page Bipolar Master-Slave D-Type Flip-Flop Timing Conditions D-Type Flip-Flop Timing Metastable States Different Output Signals Metastable State Test Circuit Examining Metastable State Oscillogram Clock Data Signal Flip-Flop Timing Test Signals Metastable Characteristic Logic Circuits Interrupt Synchronization Two-Stage Synchronization Circuit Timing Conditions READY Signal TMS320C25 Synchronization READY Input Logic Diagram SN74AS4374B Synchronization Circuit
Abstract
This application report describes metastable response digital circuits. After defining phenomenon itself, this report describes test circuit with which response analyzed gives test results. Using examples, influence metastability response asynchronous circuits measures improving reliability assessed.
Introduction
Designers digital systems constantly confronted with problem synchronizing systems that operate different frequencies. problem usually resolved synchronizing signals with local clock generator using flip-flop. such solution, necessity, leads violation operating conditions flip-flops defined data sheets, i.e., these cases, setup time hold time maintained. Therefore, flip-flop into metastable state, endangering operability circuit and, thereby, reliability whole system. purpose this report first, acquaint designers with phenomenon metastability dynamic circuits (flip-flops) and, second, look test results more common bipolar, CMOS, BiCMOS circuit families. Using these data designer determine influence metastable states application take necessary countermeasures.
Definition Metastable State
Figure illustrates internal circuitry master/slave D-type flip-flop. Only those parts shown that interest purpose this application report. there input, emitters transistors (master flip-flop) high that they turned off. input, depending logic level applied here, there also high potential bases transistors. positive edge input means that, first, gates disabled. result hole-storage effects, outputs these gates maintain their output voltage certain time. same time, emitters transistors low. transistor whose base higher voltage appeared conducts, while other transistor remains turned off. flip-flop composed transistors held this stable state feedback resistors same time, slave flip-flop consisting gates state level appears outputs.
Figure Bipolar Master-Slave D-Type Flip-Flop Flip-flop operation, described here, only ensured setup time hold time input maintained (see Figure This means that short time before positive edge input (setup time) short time afterward (hold time) level input must change above function executed correctly.
Figure Timing Conditions D-Type Flip-Flop
synchronous systems this timing maintained easily. situation different with asynchronous circuits, particular, synchronization circuits. Assume that, because change level input, voltage output gate goes from high, meaning that voltage output gate goes from high low, that clock signal switches same time. this happens instant when difference voltage between bases transistors Q1and virtually zero, master flip-flop will able adopt stable, defined state. logic state neither high low. This known metastable state. consequence, defined state slave flip-flop ensured under these circumstances. output signal this flip-flop also adopts unstable metastable state (see Figure noise transistors (the master flip-flop forms feedback amplifier) interference penetrating from exterior ensures that master flip-flop and, consequently, slave revert possible unpredictable stable states after certain time.
Metastable
Figure Timing Metastable States case illustrated Figure output slave flip-flop adopts level that between proper high levels. output metastable state master circuit consisting transistors Q1and output voltages master flip-flop correspond normal logic levels metastable state, internal voltage values corrupted through voltage gain gates (slave) such extent that signals shown Figure output flip-flop. Curve Figure illustrates correct output signal. Curve Figure shows that slave, first, does recognize metastable state master. until latter goes unstable state that reaction detected output, expressing itself very slow output edge appearing, practice, much longer delay. Curve Figure shows that metastable state master first generates high level output slave. master then reverts stable state, level will appear again output flip-flop. inverted signal shapes viewed same way. phenomena shown here described with reference bipolar circuit, same effects occur CMOS BiCMOS circuits.
Figure Different Output Signals Metastable State Analyzing metastable state flip-flops difficult because critical time window which unstable state described generated extremely short, about circuit which asynchronous signal synchronized with clock, mean time between failures (MTBF) which failure (metastable state) occurs calculated from frequency asynchronous signal (fin), clock frequency (fclk), duration critical time window (td): MTBF
fclk MHz, kHz, result MTBF
33.3
designer using flip-flop synchronize signals this application cannot expect maximum delays stated data sheets. ensure reliable operation system, necessary know long wait after clock pulse before data evaluated. Conventional test equipment capable measuring these parameters. Therefore, special test circuit needed determine MTBF time (tx) between clock edge valid signal output. Once these parameters known, designer choose type flip-flop used after much time valid data expected.
Description Test Circuit
probability flip-flop going into metastable state greatest when input signal (fin) always violates setup-time hold-time conditions. This case when state input flip-flop changes with each clock edge. other relationship between frequency signal input clock frequency would reduce probability flip-flop that tested going into metastable state. worst case when frequency (fin) input precisely one-half clock frequency (fclk). Figure shows simplified test circuit determining MTBF particular flip-flop. oscillator (O1) with frequency drives flip-flop FF1, which configured divider, thus satisfying condition fclk. increase probability tested flip-flop going into metastable state, high/low low/high transition signal input must jitter edge clock input. width this jitter should equal greater than setup hold times flip-flop being tested. output signal flip-flop applied integrator that slows down rise fall time about (tsu th). signal obtained this impressed delta signal free-running oscillator kHz) comparator This produces data signal tested flip-flop output comparator, with positive negative edge jittering signal oscillator applied same time delay line clock input flip-flop that tested (fCLK1). This delay line compensates delays flip-flop FF1, integrator comparator chosen that jitter input flip-flop tested covers setup hold times stated data sheet (see Figure
Uh(min)
fCLK2
UI(max) CLK1
Figure Test Circuit Examining Metastable State
INPUT
V/div
CLOCK
20ns
40ns
60ns
80ns
100ns
Figure Oscillogram Clock Data Signal Flip-Flop output flip-flop then applied comparators which form window comparator. Their outputs adopt same state when there valid high level output adopt different states when output voltage (VO) flip-flop undefined range: IH(min)
IL(max)
clock signal (fCLK2), delayed time (tx) delay line DL2, samples comparator outputs after this same time sets flip-flops accordingly. there metastable state present this time, output exclusive-OR gate goes high. This event registered following counter. From number metastable states detected within certain time interval (t), then possible determine mean time between metastable states according equation MTBF
fCLK1 fCLK2
Figure Timing Test Signals With circuit described here, possible determine time between failures function time (tx). this relation entered semilogarithmic scale, metastable characteristic flip-flop being examined required frequency input signal (fin) obtained. Before discussing test results, necessary analyze limitations test circuit, which influence result. things have considerable influence test results: jitter input signal that centered clock signal delay evaluating circuit (K2, FF3, FF4). edge input signal (fin) does jitter around switching edge clock signal (fCLK1), probability that flip-flop being tested will enter metastable state reduced. Care must taken ensure that jitter input signal covers time window formed setup hold times. equation assumed that asynchronous signal alters level randomly distributed over clock period (tfclk µs). shown Figure signal input device under test changes only mentioned time window (tj) probability examined flip-flop being driven into metastable state increases factor
fclk
test results give impression somewhat poorer response than expected practice. evaluating circuit, consisting comparators flip-flops FF4, delays output signal device under test thus influences result. example, flip-flop being tested might have left metastable state, outputs comparators have responded (because delay this part circuit) when edge clock signal (fCLK2) arrives flip-flops FF4. difficult, practice, determine magnitude these errors precisely. keep error small possible, extremely fast devices technology were used this part test circuit. This ensures that uncertainty resulting from delay comparators actual time their sampling smaller than When evaluating test results, this error taken into consideration appropriate horizontal shift line Figure
Test Results
Using test circuit Figure different devices from major logic families were examined with different values frequency fclk MHz, frequency data input (fin) kHz. duration test long enough sufficient number failures appear. number failures then divided test duration. This result mean time between failures (MTBF) particular time (tx). result also recorded semilogarithmic scale further evaluation (see Figure Basically, circuits from faster logic families also leave metastable state faster. Different circuits logic family showed virtually same response, with only very slight deviations. This expected because same technology practically identical circuit techniques used within logic family. curves Figure typical. measurements circuits same type from different fabrication batches, differences were noted that corresponded roughly variation propagation delay times stated data sheets. allowance this variation should made when calculating worst case particular circuit. Also, devices same type from different producers exhibited substantial differences.
other clock frequencies used testing, probability metastable state occurring changes. higher frequency, greater probability that metastable state will occur; probability decreases lower frequencies. With data derived from these experiments possible devise equation that describes metastable response component frequencies: MTBF
fexp
produce worst case during test, that setup-and-hold timing conditions violated often possible, frequency (fin) input signal already mentioned, chosen one-half clock frequency (fin fclk). basis this, equation changes MTBF
1000 years 1010 year MTBF seconds 10-1 10-2 10-3 10-4 74AS 74HC 74LS fclk hour 74ALS 74ABT 74BCT 74AC
74Standard
minute
Figure Metastable Characteristic Logic Circuits Constants describe metastable response circuit. These calculated circuit family from experimental data Figure example, values family determined. Constant determines slope lines (for semilogarithmic representation Figure function appears straight line). figure determined from following equation:
MTBF(2) MTBF(1)
x(2) x(1)
this case:
19.510ns* 10*ns 1.02 10.5
calculate constant solve equation this case: MTBF
(10)
(1.02 19.5)
(11)
including figures found equation equation that describes metastable response circuits MTBF
(1.02
(12)
With this equation, describing worst case, designer calculate metastable response circuits given input clock frequencies. corresponding equations other digital circuits determined same method. values constants (TO) most popular logic circuits listed Table Table Constants Describing Metastable Behavior
Family Std-TTL (1/ns) 0.74 0.74 0.36 1.51 3.61 0.55 10-4 10-3 10-9 10-6 1.14 10-6 10-3 1.46 10-6 10-4
First, equation logarithmized: MTBF
(13)
This shows that constant determines slope lines and, consequently, greatest influence failure rate that expected. Constant exponent equation more than proportional effect probability that output synchronization circuit will adopt stable state. This means, turn, that those logic circuits best suited this purpose where constant high figure, ABT, circuits. circuits other families come into question when circuit sufficiently long settling time. Constant (TO) much smaller influence characteristics circuits. produces parallel shift lines diagram Figure Although figures this constant differ several powers different circuit families, influence constant still more dominant.
Circuitry Measures
possible prevent metastability flip-flops, systems must designed that, sufficient degree probability, malfunctions appear circuitry. possible errors avoid them explained with reference circuit Figure circuit question interrupt input computer system. External interrupts normally asynchronous timing system, appropriate synchronization stage (FF1) must provided. this flip-flop goes into metastable state, reasons mentioned, voltage levels output longer defined; extreme cases they close threshold voltages following circuit. Assume that gate which collects interrupt signals different sources signals presence interrupt state control computer, accepts metastable level valid interrupt signal. priority encoder, which responsible generating appropriate interrupt vector, does recognize this signal
such case differences threshold voltage individual circuits just millivolts enough create situation described here). result that interrupt triggered state control, wrong interrupt vector generated, causing dramatic malfunctioning computer. This result aggravated fact that such errors practically undetectable, even with high-grade instruments like logic analyzers. sampling clock logic analyzer most likely will sample signals question examined circuit critical moment. also highly improbable that threshold voltage this test instrument will have exactly same value circuit examined, meaning that abnormal operating state cannot detected without special, cumbersome test setup.
From Other Interrupt Sources Interrupt State Control Asynchronous Interrupt Clock
HPRI/BIN Priority Encoder Interrupt Vector
Figure Interrupt Synchronization Actual figures used calculate reliability error rate (MTBF) above circuit. data used are: Type flip-flop Mean frequency asynchronous interrupt signal System clock frequency Setup time following circuit SN74ALS74 fclk
output synchronization stage, settling time (tx) calculated follows:
(14)
(15)
Taking equation values Table MTBF (1.0 MHzexp
3273
(16)
This error rate much high. reduce there first all, possibility using circuits that exhibit much shorter settling time and, therefore, leave metastable state faster. mentioned previously, these components which constant high, e.g., circuits SN74AS series. make same calculation SN74AS74, mean time between failures (MTBF) 1021 years, ensuring adequate reliability. However, there many applications which cannot just switch different family circuits, e.g., where programmable circuits used type flip-flop prescribed parts densely integrated circuitry. remedy this case two-stage synchronization circuit (see Figure 10).
Input
Output
Clock
Figure Two-Stage Synchronization Circuit second flip-flop receives output signal first stage clock period later into metastable state only input conditions also violated. That output first flip-flop still metastable during setup hold time. critical input frequency fin(2) second stage calculated from reciprocal mean time between failures first stage: in(2) MTBF(1) in(1)
(17)
)tsu
again take equation insert fin(2) value calculated here input frequency, result, assuming that same type flip-flop used both stages synchronization circuit, MTBF(2)
in(2)
(18)
MTBF(2)
in(2)
CLK2
*tsu
(19)
O(2)
Now, back synchronization circuit interrupt input that described previously. Using SN74ALS74 flip-flop, MTBF minutes. Again, assuming that second flip-flop sampled after result MTBF(2)
(1.0 25ns)
million years
(20)
selecting right component right circuit, excellent reliability achieved without difficulty, even time-critical applications. example shown above, problem resolved incorporating additional flip-flop stage, without having resort especially fast circuit families. This possible, most part, because extra delay clock period interrupt input marked effect system characteristics. most modern microprocessors there already appropriate circuits integrated (like above two-stage synchronization circuit), which engineer only take particular measures when designing special interrupt control circuits). With READY input microprocessor, example, things different. this kind input there setup hold times specified data sheets devices, with flip-flops, that must maintained. integration extra flip-flop processor, reducing probability errors through metastable states, wise because such circuit would extend each cycle clock period synchronous systems also and, most cases, processor works synchronously with assigned memory. Such integration acceptable. asynchronous operation additional synchronization stage must provided externally (see Figure 12). arrive reliable circuit avoid unnecessary delays, critical times must analyzed closely. This will done TMS320C25 microprocessor. Figure shows timing conditions READY input associated clock signals CLKOUT1 CLKOUT2.
CLKOUT
CLKOUT2
READY
synchronization purposes, negative edge clock CLKOUT1 used. READY signal must, when referred this event, valid after time D-type flip-flop, required this application, triggered with positive edge, CLKOUT1 signal inverted. SN74AS04 inverter that used this delays clock signal maximum system clock frequency fclk MHz. Assuming that mean data rate that flip-flop type SN74ALS74 used, equation Table produce: MTBF MTBF
[1.0 MHzns ns)]
this case, synchronization error expected about every min, which, experience shows, leads crash, making unacceptable. SN74AS74 flip-flop instead, MTBF more acceptable: MTBF 10exp [4.03 MHzns ns)] 2.58
Figure illustrates circuit question.
Asynchronous Ready Ready
There nothing more obvious than integrating two-stage synchronization devices described previously into circuit order reduce component count system. Figure shows circuit such synchronization stage SN74AS4374B.
Figure Timing Conditions READY Signal TMS320C25
(21)
CLKOUT
(22)
years
(23)
TMS320C25
SN74AS04
CLKOUT
Figure Synchronization READY Input
Integrated Synchronization Circuits
Figure Logic Diagram SN74AS4374B Synchronization Circuit This integration produces additional advantages terms metastable response and, thus, system reliability. first flip-flop requires buffer stage output, which largely responsible delay flip-flop, delay considerably shorter than with SN74AS74, example. This time saving (about then available addition stabilization first flip-flop goes into metastable state. Furthermore, input second flip-flop does need input buffer stage, thus reducing setup time this point about time gained here also available stabilization first stage after metastable state. Constants (To) this flip-flop were derived experimentally are:
3.96
(24)
two-stage synchronization circuit, shown Figure mean time between failures calculated using equation
MTBF
O(2)
(25)
CLK2
simplicity, assumed that first flip-flop time stabilize, which corresponds precisely clock period. time again time which output second flip-flop evaluated later following circuit, that time that second flip-flop stabilization. most cases, also corresponds period clock frequency reduced setup time following circuit.
Summary
metastable characteristic flip-flop synchronization circuit determines, large degree, reliability system. basis what been said this report, designer decide what type flip-flop should used given application what extent metastable response will manifest. From experimental data Figure seen that fast logic circuits, like those series SN74AS, SN74F, 74AC, SN74ABT, exhibit best metastable response. These devices have very short setup-and-hold time window, thus reducing probability that they will into metastable state. Apart from this, they return stable state much faster they have gone metastable. ALS, circuits, example, also produce satisfactory results clock frequency application enough. When choosing flip-flop, speed requirements system must considered.
Acknowledgment
author this document Eilhard Haseloff.

SDYA006 February 1997 Copyright 1997, Texas Instruments Incorpora

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