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Metastability Performance Clocked FIFOs
First-In, First-Out Technology
Chris Wellheuser Advanced System Logic Semiconductor Group
SCZA004A
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
Contents
Title Page Introduction Metastability Clocked FIFOs Test Setup Measuring FIFO Flag Metastability Test Results MTBF Comparisons Conclusion References
Introduction
This report intended help user understand more clearly issues relating metastable performance Texas Instruments (TI) clocked FIFOs asynchronous-system applications. discusses basic metastable-operation theory, shows equations used calculate metastable failure rates stages synchronization, describes approach used synchronizing status flags series clocked FIFOs. Additionally, test setup measuring failure rate device determine metastability parameters shown results given both advanced BiCMOS (ABT) FIFO advanced CMOS (ACT) FIFO. Using these parameters, calculations MTBF under varying conditions performed.
Metastability
Metastability digital systems occurs when asynchronous signals combine such that their resulting output goes indeterminate state. common example case data violating setup hold specifications latch flip-flop. synchronous system, data always fixed relationship with respect clock. When that relationship obeys setup hold requirements device, output goes valid state within specified propagation delay time. However, asynchronous system, relationship between data clock fixed; therefore, occasional violations setup hold times occur. When this happens, output intermediate level between valid states remain there indefinite amount time before resolving itself simply delayed before making normal transition1. either case, metastable event occurred. Metastable events occur system without causing problem, necessary define what constitutes failure before attempting calculate failure rate. simple CMOS latch, shown Figure valid data must present input specified period time before clock signal arrives (setup time) must remain valid specified period time after clock transition (hold time) assure that output functions predictably. This leaves small window time with respect clock (t0) during which data allowed change. data edge occurs within this aperture, output intermediate level remain there indefinite amount time before resolving itself either high low, illustrated Figure This metastable event cause failure only output resolved itself time that must valid (for example, input another stage); therefore, amount resolve time allowed device plays large role calculating failure rate.
Data Input Clock
Output
Figure Simple CMOS Latch
Clock
Data Input
Output
Figure Output Intermediate Level Data Edge Within Aperture
probability metastable state persisting longer than time, decreases exponentially increases2. This relationship characterized equation
where function f(r) probability nonresolution function resolve time allowed, circuit time constant (which also been shown inversely proportional gain-bandwidth product circuit)3,4.
single-stage synchronizer with given clock frequency asynchronous data edge that uniform probability density within clock period, rate generation metastable events calculated taking ratio setup hold time window previously described time between clock edges multiplying data edge frequency. This generation rate metastable events coupled with probability nonresolution event function time allowed resolution gives failure rate that conditions. inverse failure rate mean time between failure (MTBF) device calculated with formula shown equation failure rate Where: resolve time allowed excess normal propagation delay time device metastability time constant flip-flop constant related width time window aperture wherein data edge triggers metastable event clock frequency asynchronous data edge frequency
MTBF1
parameters constants that related electrical characteristics device question. simplest determine their values measure failure rate device under specified conditions solve them directly. failure rate device measured different resolve times plotted, result exponentially decaying curve. When plotted semilogarithmic scale, this becomes straight line slope which equal therefore, data points line sufficient calculate value using equation
ln(N1
Where: resolve time resolve time number failures relative number failures relative
After determining value solved directly. formula calculating MTBF two-stage synchronizer, equation merely extension equation
MTBF Where:
resolve time allowed first stage synchronizer resolve time allowed excess normal propagation delay previously defined, with assumed same both stages.
first term calculates MTBF first stage synchronizer, which effect becomes generation rate metastable events next stage. second term then calculates probability that metastable event will resolved based value tr2, resolve time allowed external synchronizer. product terms gives overall MTBF two-stage synchronizer.
Clocked FIFOs
clocked FIFOs designed reduce occurrence metastable errors asynchronous operation. This achieved through two- three-stage synchronizing circuits that generate status-flag outputs input ready (IR) output ready (OR). typical application, words written then read from FIFO varying rates independent another, resulting asynchronous flag-signal generation (internally) boundary conditions full empty; example, operation when FIFO full boundary condition with writes taking place faster than asynchronous reads. flag low, signifying that FIFO full accept more words. When read occurs, FIFO longer completely full. This causes internal flag signal high, allowing another write take place. Since exit from full state happens asynchronously write clock (WRTCLK) FIFO, this flag useful system write-enable signal. solution synchronize this internal flag write clock through D-type flip-flop stages output this synchronized signal flag (see Figure status flag generated similar manner empty boundary condition synchronized read clock through three-stage synchronizing circuit.
Internal Asynchronous Flag Signal Internal Logic Delay
WRTCLK
Figure IR-Flag Synchronizer remainder this report pertains metastability performance two-stage synchronizer, which limiting case terms MTBF characteristics. internal flag signal that goes high read write synchronized write clock through D-type flip-flop stages. Since this results flag status FIFO being delayed clock cycles, predictive circuit used clock status into synchronizer (full minus two) words that action flag going coincides with actual full status FIFO. However, once FIFO full low, read that causes internal flag high reflected status flag until write clocks occur. With FIFO full flag low, read causes internal flag signal high. This signal clocked into first stage two-stage synchronizer next write clock. Because these signals asynchronous another, potential output first stage synchronizer metastable state exists. this condition persists until next write clock rising edge, metastable condition could generated second stage reflected flag output. This metastable condition manifests itself delay propagation time considered failure only exceeds maximum delay allowed design. effectiveness two-stage synchronizer becomes apparent when attempting generate failures rate high enough count reasonable period time. metastable event generated first stage must persist until next write clock, i.e., when that data transferred second stage. resolve time first stage governed frequency period write clock. slower frequencies, failure rate first stage very low, resulting metastable generation rate second stage. second stage synchronizer further reduces probability metastable failure based resolve time allowed output. overall failure rate device affected increasing initial asynchronous data generation rate (adding jitter data centered about setup hold window), decreasing resolve time first stage (increasing write clock frequency), reducing external resolve time output.
Test Setup Measuring FIFO Flag Metastability
failure rate device measured test fixture shown Figure input waveforms used this setup also shown Figure Rising data jittered asynchronously about setup hold aperture device under test (DUT) 400-ps window with respect device clock (CLK). output then clocked into separate flip-flops, FF2, different clock signals, CLK1 CLK2. resolve time, relationship between CLK1 measured delta between normal output transition time rising edge CLK1 minus setup time required FF1. CLK2 occurs long enough after CLK1 allow sufficient time have resolved itself valid state. outputs compared exclusive gate, output state which latched into CLK3. When metastable failure occurs, output exclusive gate goes high caused having opposite data having resolved itself time next cycle, data clocked into order reset status latch, FF3. Failures counted different resolve times, then calculated using equation Using test setup Figure failure rates measured both SN74ABT7819, clocked FIFO, SN74ACT7807, clocked FIFO. device initially written full boundary condition. read clock generated send internal flag high, jitter signal superimposed sweep asynchronously with respect write clock 800-ps-wide envelope centered such that flag goes high alternately second third write clocks. nominal write-clock frequency test setup MHz, increase failure rate observable level, pulse injected into write-clock stream just after read clock occurs such that first second write clocks (the ones that clock status through synchronizer) only 5.24 apart. This increases effective write clock frequency MHz, reducing resolve time allowed first stage increasing failure rate. This test setup these actions together create necessary conditions generate metastable occurrence output that seen after second write clock manifests itself delay propagation time. this instance, write clock synchronizing clock read clock generates asynchronous internal data signal. CLK1 adjusted vary external resolve time, tr2, resulting failure rates recorded (see Table
RCLK (FIFO)
CLK1 CLK2 CLK3
Event Counter
Jitter RDCLK (data)
WRTCLK (clock)
(out) Load CLK1 Load CLK2 Reset Reset Reset
CLK3
Injected Pulse Metastable Event
Load
Figure Metastable Event Counter Input Waveforms
Test Results
Table SN74ABT7819 Failure Rates{
RESOLVE TIME, (ns) 0.27 0.39 0.53 25°C NUMBER FAILURES/HOUR NUMBER FAILURES/SECOND 0.2472 0.1692 0.1101 MTBF (seconds) 4.04 5.91 9.08
After measuring metastable performance SN74ABT7819, some assumptions must made calculate parameters Because individual flip-flops comprising two-stage synchronizer cannot measured separately, first assumed that values same both. This safe assumption, these constants driven process technology because schematics identical. other assumption made involves determining resolve time allowed first stage synchronizer. clock period 5.24 delay through flip-flop setup time next stage must subtracted from clock period arrive true resolve time (tr1). These values could measured directly were, therefore, estimated from SPICE analysis Using equation measured failure rates calculate results value 0.33 conditions given. following values from test setup must used solve Where: MTBF2 3.94 (5.24-ns clock period 1.3-ns setup delay time) 0.27 (set externally output CLK1) (4-MHz input adjusted 25/0.8 jitter ratio) 4.04
Substituting these values into equation solving yields value 16.9 Table summarizes results SN74ABT7819 SN74ACT7807 clocked FIFOs. internal setup delay time assumed SN74ACT7807. Table Values SN74ABT7819 SN74ACT7807
25°C SN74ABT7819
SN74ACT7807
(ns)
(ps) 16.9 28.8
(ns)
(ps) 1.13 2.05 9.40
0.33 0.30 0.23
0.50 0.40 0.30
These numbers indicate performance only devices intended represent fully characterized parameter. However, they should valid purpose relative performance comparisons, values fall within expected range given circuit configuration process technology which devices fabricated.
MTBF Comparisons
With constants known, calculations MTBF device under different operating conditions performed. First, however, consider example metastability performance single-stage synchronizer using equation circuit constants from Table Assume application running with 33-MHz write clock, 8-MHz read clock, 9-ns maximum propagation delay time path, 5-ns setup time next device. Therefore: (30-ns clock period 9-ns propagation delay 5-ns tsu) Using equation calculate MTBF gives 2.55 1017 seconds little more than billion years. reliability one-stage synchronizer degrades operating frequency increases. With 50-MHz write clock, 12-MHz read clock, 9-ns maximum delay, 5-ns setup time: (20-ns clock period 9-ns propagation delay 5-ns tsu) Substituting these values into equation yields MTBF about hours. This performance unacceptable, even with device fabricated 0.8-mm BiCMOS process, which more resistant metastability than other processes. benefits two-stage synchronization become evident with next example. Using conditions stated last example: 18.7 (20-ns clock period 1.3-ns setup delay time) (20-ns clock period 9-ns propagation delay 5-ns tsu)
Using equation calculate MTBF gives 3.16 1028 seconds 1.00 1021 years. Table gives performance summary both one- two-stage synchronizing solutions under different conditions. Table MTBF Comparisons
CONDITIONS MHz, MHz, MHz, STAGE 8400 years days STAGE years 1400 years STAGE 2.62 1028 years 3.56 1019 years 4.90 1010 years STAGE 4.77 1047 years 2.18 1034 years 1.00 1021 years
hours MHz, years 1.28 years MHz, 2900 years Assumptions MTBF comparisons: values those given previously both devices with VCC= 25°C. Flag propagation delay time assumed Setup times next device 50-MHz operation), 67-MHz operation), 80-MHz operation).
Conclusion
Metastability failures must accounted design asynchronous digital circuits. These failures become increasingly prevalent higher operating frequencies. When higher frequencies used, extreme care must taken ensure that system reliability adversely affected inadequate synchronization methods. Clocked FIFOs from provide solution this problem synchronizing boundary flags with least flip-flop stages improve metastable MTBF over one-stage synchronization. This architecture allows designers utilize high-throughput performance memory without endangering reliability their products.
References
Horstmann, Eichel, Coates, "Metastability Behavior CMOS ASIC Flip-Flops Theory Test," 146, IEEE Journal Solid State Circuits, February 1989. Veendrick, "The Behavior Flip-Flops Used Synchronizers Prediction Their Failure Rate," 169, IEEE Journal Solid State Circuits, April 1980. Flannagan, "Synchronization Reliability CMOS Technology," 880, IEEE Journal Solid State Circuits, August 1985. Kacprzak Albicki, "Analysis Metastable Operation CMOS Flip-Flops," IEEE Journal Solid State Circuits, February 1987. Kleeman Cantoni, "Metastable Behavior Digital Systems," IEEE Design Test Computers, December 1987.
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