SCLA011 1996 Copyright 1996, Texas Instruments Incorporated

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SCLA011 1996 Copyright 1996, Texas Instruments Incorporated

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SN54/74HCT CMOS Logic Family Applications Restrictions
SCLA011 1996
Copyright 1996, Texas Instruments Incorporated
Contents
Title Page Introduction TTL/HC Interface Operating Voltages Circuits Noise Circuits Power Consumption Circuits Delay Times Bergeron Analysis Summary
List Illustrations
Figure Title Page TTL-CMOS Interface With Open-Collector Output Pullup Resistor Noise Margin Specified Noise Margins HCT, Devices Crosstalk (First Case) Crosstalk (Second Case) Input-Stage Structure Circuits Supply Current Function Input Voltage Current Consumption Function Frequency Bergeron Diagram, SN74ALS245 Driver Line Reflections, SN74ALS245 Driver Bergeron Diagram, SN74HC245 Driver Line Reflections, SN74HC245 Driver
Introduction
This report describes applications, features, system design SN54/74HCT high-speed CMOS family. simplify interfacing outputs high-speed CMOS inputs, Texas Instruments (TI) introduced circuits, subgroup family. features functions identical devices with exception modified input circuitry, which makes input threshold voltage compatible with circuits. outputs similar family.
TTL/HC Interface
output voltages input voltages incompatible, especially between high-level output voltage (VOH) high-level input voltage (VIH). This problem solved three different ways. first devices with their TTL-compatible input voltages interface between circuits. Another solution provide pullup resistors outputs ensure adequate high-level output voltage. third method requires level shifters. three alternatives mentioned, using circuits solve incompatibility problem, most convenient. Designed meet requirements this application, devices allow engineer benefit from advantages devices (low power consumption) without using discrete components, such pullup resistors.
Figure TTL-CMOS Interface With Open-Collector Output Pullup Resistor Using pullup resistors accommodate output signals interface with input circuits (see Figure design engineer choose resistance that appropriate application. minimum value resistor determined maximum current that circuit supply low-level output (VOL). pmin
where number inputs driven, their input current. IIL, having value only nanoamperes, negligible calculations. case SN74ALS03, following equation defines Rpmin: pmin
calculate upper limit this resistor, sufficient high level must ensured. pmax
this situation, input current devices negligible very high values also obtained.
When calculating maximum allowable resistance, important ensure that maximum allowable rise time input exceeded. following equation then applies:
where total load capacitance circuit. composed output capacitance driving gate pF), total input capacitances gates driven each), line capacitance pF/cm). actual value calculated solving equation
Assuming total capacitance, maximum resistor
5001ns
Faster rise times result lower impedance more power consumption. previous calculation based assumption that driving gate open collector. Conditions become more satisfactory, however, when gate with totem-pole output (i.e., SN74ALS00) used. that case, gate output provides voltage brought value less than (the rise time signal). pullup resistor only pull level within desired time. According previous formula, with required rise time resistor defined following calculation: pmax
3.12
upper limiting value resistor primarily dictated rise time required. larger resistance, longer rise times propagation delay times. Reducing resistance increases speed power dissipation. third method accommodating signals circuits accomplished with special level shifters. This solution recommended because level shifter itself inherent logic functions increases component space requirements. design engineers, using circuits match signal levels with devices most convenient efficient solve incompatibility problems. devices contain necessary level shifters additional logic functions single circuit. Furthermore, designer forced compromise among signal rise time, system speed, power consumption stages.
Operating Voltages Circuits
circuits feature limited operating voltage range fact that they have work with voltage levels. Since internal switching layout equivalent circuits (with exception input stage), these components could operated from range. circuits operating less than load-level noise margin reduced becomes incompatible with thresholds, thus losing primary advantages devices.
Noise Circuits
noise margin logic family very important consideration system design. Composed low-level high-level noise margins, each these components considered separately. high-level noise margin voltage difference between specified output voltage (VOH) driving gate specified input voltage (VIH) triggered gate. Accordingly, low-level noise margin defined voltage difference between specified output voltage (VOL) input voltage, (see Figure
VOHmin Noise margin high VIHmin VILmax VOLmax Undefined region Noise margin
Figure Noise Margin Regarding magnitude relations, desirable keep both noise margins large possible undefined range between them narrow possible. noise margin large enough certain application, internally externally sourced interference modify (i.e., falsify) signal fall within undefined range. Internal noise caused inductive ohmic drops inductive capacitive couplings with other signaling lines. coupling between signal lines more critical aspect most cases. Figure shows voltage conditions HCT, circuits.
Input Voltage
Supply Voltage
Figure Specified Noise Margins HCT, Devices
Since certain percentage always transmitted from noise-emitting line interfered line, absolute noise margin volts) that consequence, rather quotient absolute noise margin signal-voltage swing. percentile high- low-level noise margins would defined following equations: Vmin VVmax
100% 100%
obtain realistic values, specified VOHmin VOLmax data sheet voltage values must used when calculating signal deviation VOL. Data sheet specifications would indicate smaller signal deviation thus wider noise margin. values should based low- high-level voltages supplied circuit under normal operating conditions. following table lists different voltages HCT, circuits, resulting noise margins. calculations supply voltage achieve comparable results. Table Voltage Levels Noise Margins
VOHtyp VOLtyp Signal voltage swing VOHtyp VOLtyp VIHmin VILmax VOHmin VIHmin VILmin VOLmin 29.1 18.7 60.4 14.6 22.5 12.9 UNIT
low-level noise margin (SL) most critical value three logic families, ranging from 18.7% (HC) 12.9% (TTL). With respect noise margins, devices feature significantly better performance than bipolar logic circuits. practice, however, ability individual circuits attenuate noise impressed into line most important. test setups Figures used measure actual noise margin expected system. measured value refers crosstalk between parallel lines. Twenty-five centimeters, usually maximum length that occurs printed circuit board, regarded basic line length. Figure signals propagating across line same direction. noise that induced line line immediately shorted output impedance gate. Signal Figure shows signal noise-emitting line, signals show noise generated line high levels. Both maintain noise values that stay below their allowable limits.
Line
Line
SN74HC00
SN74ALS00
Figure Crosstalk (First Case) same configuration used second case, signals both lines propagate opposite directions. noise impressed parallel-running line interfering line attenuated immediately because that place line terminated high-impedance input only. noise becomes more effective runs across line driver output. output impedance driver output shorts noise large extent. attenuated interfering signal reflected beginning line, then, after double signal propagation time, noise eliminated interfered line well. larger signal swing (deviation) circuits (4.8 opposed devices (3.5 larger noise amplitude expected. This value does fully explain significant amplitude differences oscillographs shown Figure this case, output impedance level significantly lower circuits compared devices
Line
Line
SN74HC00
SN74ALS00
Figure Crosstalk (Second Case)
addition, slew rate edge (dv/dt), particularly positive edge circuits, significantly larger value compared circuits. However, devices usually operate without interference because typical threshold voltage circuit inputs this value reached demonstrated examples. contrast, noise amplitude circuits significantly exceeds typical threshold voltage summarize, inherent noise remains below critical limits within pure system. When devices used, maximum line length should exceed maintain crosstalk below critical values. Because logical application devices interfacing between circuits, line lengths normally shorter, this requirement presents serious restriction.
Power Consumption Circuits
threshold voltage CMOS circuit determined geometry input transistors. These transistors designed sink same input current required threshold voltage. resulting voltage output equivalent supply voltage VCC. circuit, channel width p-channel transistor input approximately twice value n-channel transistor. purpose make both transistors have same current characteristics, thus making threshold voltage their input about supply voltage VCC. This circuit area been modified devices: n-channel transistor about seven times wider than p-channel transistor (see Figure This shifts threshold voltage that amounts supply voltage. supply voltage threshold voltage similar threshold voltage circuits.
Input Circuit
Width Channel Channel
Input Circuit
Channel
Channel
Width
Figure Input-Stage Structure Circuits Some compromises necessary circuits reach parameters required. unlimited size reduction p-channel transistor impossible without reducing drain current thus whole circuit speed. This n-channel transistor must enlarged shift threshold voltage accordingly. supply current circuit rises (see Figure input voltage equal supply voltage (p-channel transistor off) ground potential (n-channel transistor off). this case, both transistors conducting, especially when circuits triggered voltage levels. includes parameter circuits, value that specifies increase supply current driven levels (VIL This parameter allows circuit design engineer calculate expected power consumption.
Figure Supply Current Function Input Voltage Figure shows effects power consumption complete system. shows power consumption SN74HCT243 with four inputs triggered. case, input signal levels (VIL other case, levels (VIL duty cycle input signal 50%. Each output load Supply current about higher device triggered levels.
SN74HCT245 25°C
Level CMOS Level
Figure Current Consumption Function Frequency frequencies above MHz, this effect secondary importance, since current consumption then determined primarily power required reversing charge load capacitance. Moreover, increase current consumption devices driven levels much lower practice because circuits supply typical voltage swing that significantly higher than data sheet value used measurement Figure
Delay Times
Another restriction circuits results from increased transmission delay times. Although these circuits contain more stages than devices, time reversing charge output first stage extended because smaller p-channel transistor higher capacitance n-channel transistor. This prolongs delay time approximately circuits compared circuits.
Bergeron Analysis
speed logic families associated higher slew rate (especially devices) force system design engineer carefully evaluate behavior electrical waves lines. addition, line reflections have considered when rise fall times logic signals faster than propagation time signals unterminated lines. Under certain circumstances, these reflections distort transferred signals that receiver other line cannot recognize signal. Because digital circuits have linear input output characteristics, equations known evaluating line reflections applicable. better solution Bergeron diagram, graphical method that supplies results with sufficient precision examples question. Figure shows high- low-level output characteristics SN74ALS245A, well input characteristic device. Because input current these circuits very (and negligible), this characteristic coincides with axis range from voltage curve transmitter receiver positive negative edges obtained drawing resistance line with slope onto graph (see Figure 10). Both cases achieve voltages that fall within required limits (VILmax VIHmin undershoot negative edges right sides pulses sufficiently damped diodes integrated into input circuitry devices.
7.00 6.00 5.00 Output Voltage 4.00 3.00 2.00 1.00 0.00 -1.00 -2.00 -200 Low-High Transition High-Low Transition
-160
-120
Output Current
Figure Bergeron Diagram, SN74ALS245 Driver
Channel Channel
Figure Line Reflections, SN74ALS245 Driver Figures show associated diagrams driver. There problem with positive-going edge. line end, voltage applied, which valid high both HCT. negative edge, voltage line reaches level approximately This value sufficient drive circuit, cannot securely drive device that requires low-level value below
7.00 6.00 5.00 Output Voltage 4.00 3.00 2.00 1.00 0.00 -1.00 -2.00 -200
-160
-120
Output Current
Figure Bergeron Diagram, SN74HC245 Driver
Channel Channel
Figure Line Reflections, SN74HC245 Driver
Summary
SN74HCT circuit family from subgroup SN74HC series. Whereas devices both families equivalent their features functions, input circuitry modified meet interfacing requirements. These devices driven circuits directly, without additional components. Thus, family offers ideal, simple, cost-effective solution mixing systems using both devices. However, employing instead devices pure CMOS systems cannot recommended. There several advantages using technology, such broad supply-voltage range reduction adverse effect caused lower switching threshold dynamic behavior. lower noise margin, there increased risk interference caused crosstalk, especially when lines printed circuit board exceed certain length. Moreover, reduced switching threshold longer ensures faultless operation advanced systems used microprocessor applications today.

SCLA011 1996 Copyright 1996, Texas Instruments Incorporated

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