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Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics

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Application Report
SCHA004 - October 2002
Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
R. E. Funk ABSTRACT Both buffered and unbuffered CMOS B-series gates, inverters, and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products, with applications literature focusing on the attributes and use of the buffered types. This practice has left an imbalance in the understanding and application of both buffered and unbuffered gates. In some instances, customers are not using unbuffered products when they are the best choice for the intended application. This application report offers clarification of the relative merits of the buffered and unbuffered CMOS devices. This application report was acquired by TI from Harris Semiconductor Corporation and edited and reformatted in December 2001. This application report is adapted from AN6558.1, published by Harris (1992), which, in turn, was adapted from ICAN-6558, published by RCA (1983). Standard Linear & Logic
Trademarks are the property of their respective owners.
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List of Figures 1 2 3 4 5 6 7 8 9 10 11 Buffered (CD4001B) and Unbuffered (CD4001UB) Two-Input NOR Gates . . . . . . . . . . . . . . . . . . . . 4 Schematic Diagrams of Buffered and Unbuffered Two-Input NOR Gates . . . . . . . . . . . . . . . . . . . . . 5 Constant Output Impedance of Buffered Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Variable Output Impedance of Unbuffered Two-Input NOR Gate (The Resistors Represent the ON Impedance of a p- or n-Channel MOS Transistor) . . . . . . . . . . . 7 Voltage Transfer Characteristics of Buffered Two-Input NOR Gate (CD4001B) . . . . . . . . . . . . . . . . 8 Voltage Transfer Characteristics of Unbuffered Two-Input NOR Gate (CD4001UB) With Output Voltages of 5 V and 15 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Linear-Gain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical Linear-Mode Gain of Buffered and Unbuffered Two-Input NOR Gates . . . . . . . . . . . . . . . . 13 Buffered Output Oscillation for Slow Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Capacitance of Buffered Two-Input NOR Gate (CD4001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Capacitance of Unbuffered Two-Input NOR Gate (CD4001UB) . . . . . . . . . . . . . . . . . . . . . . . . 15 List of Tables 1 2 3 4 5 Comparison of Buffered and Unbuffered Gate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Characteristics of Buffered and Unbuffered Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input-Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Applications of Buffered and Unbuffered CMOS Gates and Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TI COS / MOS Buffered and Unbuffered Gate, Inverter, and Driver Types . . . . . . . . . . . . . . . . . . . . . . . 16
Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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Background
Historically, most CMOS gates, inverters, and high-current IC products were unbuffered and exhibited good logic-system performance, speed, noise immunity, and quasi-linear characteristics in a wide variety of applications. As the scope of CMOS products broadened and additional manufacturers began making them, buffered gate and inverter products became available. While initial buffered products were confined to OR and AND functions, buffered NOR and NAND gates were introduced with the same generic 4000A-series designations as the original, widely used, unbuffered gates. Users were surprised by the noninterchangeability of the devices in applications where speed, noise immunity, output impedance, and linear gain-bandwidth characteristics were critical. It is of benefit to CMOS users to have available the definitions and designations of both buffered and unbuffered B-series CMOS devices as determined by the JEDEC CMOS Standardizing Committee under the cognizance of the JC40.2 JEDEC Committee of EIA. The official JEDEC definitions are repeated in the following paragraphs, along with detailed explanations and examples. Comparisons of user-oriented characteristics and the use of buffered and unbuffered gates are also reviewed.
Definitions
Buffered CMOS
A buffered CMOS device is one for which the output ON impedance is independent of any and all valid input logic conditions, both preceding and present, and is said to have a buffered output or to be a buffered CMOS device. All such products are designated by the suffix B.
Unbuffered CMOS
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A Output B OR A Output B (a) Buffered - CD4001B A B Output
(b) Unbuffered - CD4001UB
92CS-28330
Figure 1. Buffered (CD4001B) and Unbuffered (CD4001UB) Two-Input NOR Gates
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Figure 2 is a schematic representation of the TI buffered and unbuffered two-input NOR gates. The improved four-diode-input gate-oxide protection circuit is shown at the inputs.
VDD VDD VDD VDD
A Output
VSS VDD
VSS VDD VSS
VSS (a) Buffered
VSS VDD
Output
VSS (b) Unbuffered
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Figure 2. Schematic Diagrams of Buffered and Unbuffered Two-Input NOR Gates
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Examples
Examination of the dc performance characteristics of both the buffered and unbuffered two-input NOR gates reveals the two electrical characteristics, output impedance and noise immunity, by which the types are differentiated by the JEDEC standard specifications.
Output Impedance Buffered Output
Figure 3 shows the buffered output stage and shows the MOS transistor as switched on, with a channel resistance, R, which is the same value for the n switch closed or for the p switch closed.
p Switch
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Figure 3. Constant Output Impedance of Buffered Gate
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Unbuffered Output
Figure 4 shows the unbuffered two-input gate p- and n-channel MOS switches and appropriate on-channel resistances. Note that the two stacked p-channel switches are designed for an on resistance of R / 2, so that the output impedance is R when both the logic inputs are low see Figure 4(b). In Figure 4(a), the output impedance is R to the negative supply terminal (usually ground) for an input logic state of 1, or input high. Figure 4(c) shows the condition when the unbuffered gate has an output impedance of R / 2 for both logic inputs high, hence, the variable output impedance of the unbuffered gate. For a four-input gate, this variable is R to R / 4. The maximum output resistance of TI buffered or unbuffered gates is R. Thus, minimum IOL and IOH specifications for buffered and unbuffered gates are identical.
Inputs Low High A B A p +V Inputs Low Low A B A p +V Inputs High High A B A p +V
Output R ZO 2
-V (a) Input Low, Input High
-V (b) Both Inputs Low
-V (c) Both Inputs High
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Figure 4. Variable Output Impedance of Unbuffered Two-Input NOR Gate (The Resistors Represent the ON Impedance of a p- or n-Channel MOS Transistor)
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Noise Immunity
The second JEDEC-defined difference between the buffered and unbuffered CMOS gates (or inverters) is the difference in input noise-immunity characteristics.
Buffered NOR Gate
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Figure 5. Voltage Transfer Characteristics of Buffered Two-Input NOR Gate (CD4001B)
Unbuffered NOR Gate
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Figure 6. Voltage Transfer Characteristics of an Unbuffered Two-Input NOR Gate (CD4001UB) With Output Voltages of 5 V and 15 V
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The previous definitions use gate characteristics to illustrate the JEDEC definitions for buffered and unbuffered characteristics relative to variable output impedance and noise-immunity performance. Inverters and high-current drivers also can be defined as buffered (B) types or unbuffered (UB) types by virtue of the squared or rounded transfer characteristics of Figures 5 and 6, respectively. Even though both types have a single NMOS and single PMOS output transistor, the rounded transfer characteristic of the unbuffered inverters makes them UB types by virtue of:
Comparisons
Table1 shows the qualitative comparisons of user-oriented performance characteristics of buffered and unbuffered CMOS gates, inverters, or drivers. Table 1. Comparison of Buffered and Unbuffered Gate Characteristics
CHARACTERISTICS Propagation delay Noise immunity / margin Output impedance and output transition time AC gain Output oscillation for slow inputs Input capacitance BUFFERED GATE Slow Excellent Constant High Yes Low UNBUFFERED GATE Fast Good Variable Low No High
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Table 2 is a quantitative comparison of the key performance characteristics, with explanations for propagation delay, noise immunity, output impedance, and output transition time. Table 2. Characteristics of Buffered and Unbuffered Gates
Typical propagation delay
Noise margin
Typical output transition time AC gain AC bandwidth Output oscillation for slow inputs Typical input capacitance
Propagation Delay
Propagation delay times in Table 2 are applicable to TI two-, three-, and four-input NOR and NAND gates.
Noise Immunity
Table 3 shows the detailed data-sheet input-voltage specifications for buffered and unbuffered gates. From the test conditions in Table 3, the user-oriented noise immunity and noise-margin data of Table 2 are derived. Also, refer to Figures 5 and 6 for the voltage-transfer characteristics that illustrate the reason for the different input-voltage-specification requirements for buffered and unbuffered devices.
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Table 3. Input-Voltage Specifications
CHARACTERISTICS VO 4.5 Buffered VIL Input voltage Unbuffered 9 13.5 4.5 9 13.5 0.5 Buffered VIH Input voltage Unbuffered 1 1.5 0.5 1 1.5 VDD 5 10 15 5 10 15 5 10 15 5 10 15 3.5 7 11 4 8 12.5 V LIMITS MIN MAX 1.5 3 4 1 2 2.5 V UNIT
Output Impedance
For output impedance, refer to Figures 3 and 4 and accompanying descriptions of the constant output impedance of buffered gates and the variable output impedance of unbuffered gates. Note that both buffered and unbuffered TI two-, three-, and four-input gates are designed to meet the same maximum output impedance output current ratings (IOL and IOH) have the same minimum limit on TI data sheets.
Output Transition Time
The time required for a CMOS output to transfer high or transfer low is constant for buffered gates, but varies according to input logic states for unbuffered gates. Output transition time varies as a function of the driving source resistance of the output, which is state dependent, as indicated in Figure 4, as well as the device output capacitance, which is dependent on both device size and input logic state. Because of variable output capacitance, output transition-time variations are not a linear function of output resistance. As Table 2 shows, TI two-, three-, and four-input unbuffered gates exhibit a net two-to-one difference in output transition time, even though the output resistance has a net four-to-one variation for the four-input gate.
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AC Gain and Bandwidth
CMOS linear-mode gain was measured for both the buffered and unbuffered TI two-input NOR gates using the test circuit of Figure 7. Figure 8 shows typical linear-mode gain difference between buffered and unbuffered TI two-input NOR gates. While absolute performance depends on device type (inverters or two-, three-, and four-input gates) and test configurations, Figure 8 defines the approximately three-to-one difference in linear-mode performance between buffered and unbuffered gates.
+V 22 M Sine-Wave Generator 50- Source
CD4001
dB Meter
92CS-28338
Figure 7. Linear-Gain Test Circuit
Frequency - kHz (a) Typical CD4001B Linear Gain
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Figure 8. Typical Linear-Mode Gain of Buffered and Unbuffered Two-Input NOR Gates
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Output Oscillation for Slow Inputs
The high linear-mode gain of buffered CMOS devices can lead to undesirable oscillation at outputs when input ramps are in excess of approximately 1-ms duration. Figure 9 shows this effect when approximately 1 mV to 2 mV of ac noise within the device bandwidth on the input signal are amplified through the device and tend to develop a few cycles of oscillation between the positive and negative rails under 5-V operation. In contrast, unbuffered gates do not tend to oscillate unless a noise voltage of 200 mV to 300 mV is present within the bandwidth of the device. An input ramp of up to 100-ms duration did not create oscillation in laboratory tests of TI unbuffered gates.
2 mV to 3 mV of Noise on Ramp
Transition Begins
Output
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Figure 9. Buffered Output Oscillation for Slow Input
Input Capacitance
Figures 10 and 11 show the dynamic input capacitance of the TI buffered and unbuffered two-input NOR gates, respectively. The large MOS transistor geometry of the unbuffered NOR gate is responsible for the higher peak input capacitance (Miller effect) in the linear switching range. The longer dwell in this linear region also tends to broaden the Miller capacitance and, therefore, increases the effective average input capacitance. Buffered gates and inverters are rated at a maximum input capacitance of 1 unit load (7.5 pF JEDEC standard) unbuffered gates and inverters are rated at 2 unit loads (15 pF maximum). High-current unbuffered drivers, such as the CD4049UB, are rated at 3 unit loads (22.5 pF maximum).
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Figure 10. Input Capacitance of Buffered Two-Input NOR Gate (CD4001B)
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Figure 11. Input Capacitance of Unbuffered Two-Input NOR Gate (CD4001UB)
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Applications Guidance
TI Gate, Inverter, and Driver Products
Table 5 is a list of small-scale integrated (SSI) B and UB products presently in production by TI. Refer to TI data sheets for detailed product information. Table 5. TI COS / MOS Buffered and Unbuffered Gate, Inverter, and Driver Types
BUFFERED CD4001B CD4002B CD4010B CD4011B CD4012B CD4023B CD4025B CD4050B CD4068B CD4071B CD4072B CD4073B CD4075B CD4078B CD4081B CD4082B UNBUFFERED CD4001UB CD4007UB CD4009UB CD4011UB CD4041UB CD4049UB CD4069UB
Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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