Prasad Dhond ABSTRACT Supply voltages continue migrate lower nodes sup
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Selecting Right Level-Translation Solution
Prasad Dhond ABSTRACT Supply voltages continue migrate lower nodes support today's low-power, high-performance applications. While some devices capable running lower supply nodes, others might have this capability. have switching compatibility between these devices, output each driver must compliant with input receiver that driving. There several level-translation schemes interface these devices with another. Depending application needs, approach might more suitable than other. This application report gives overview methods products used translate logic levels lists advantages disadvantages each Texas Instruments (TI) level-translation solution. Keywords: Dual-supply, split-rail, level translation, level shifter, mixed-voltage, T45, T245, 4245, 3245, open-drain, overvoltage tolerant, TTL, CMOS, TVC, CB3T, CBTD Standard Linear Logic
Contents Introduction Dual-Supply Level Translators Features Product Portfolio Open-Drain Devices Application Example Level Translation Using SN74LVC2G07 Pullup Resistors Outputs CMOS Drivers Switches CBTD Devices Using Translation Voltage Clamp (TVC) Devices Overvoltage-Tolerant Devices Devices With TTL-Compatible Inputs Summary Translation Solutions Conclusion References
Trademarks property their respective owners.
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List Figures Typical Situation Which Level Translator Needed Digital Switching Levels SN74AVCB324245 Translating From (Bank (Bank Same Time Dual-Supply Level-Translation Device Nomenclature Level Translation Using Open-Drain Device Open-Drain Device Level-Translation Application Output Edge Slows With Increasing Value Pullup Resistors Output CMOS Drivers Recommended CB3T Device Used Interface With (TTL) SN74CBT1G384 3.3-V Application 3.3-V Translation Using Device Simplified Schematic Typical TVC-Family Device SN74TVC3306 Used Level-Translation Application Waveforms Bidirectional Translation Using Device Down-Translation Using Logic Device With Overvoltage-Tolerant Inputs Shift Output Duty Cycle When Using Overvoltage-Tolerant Device Level Translation Characteristics SN74HCT541 List Tables Possible Voltage-Translation Combinations Using Dual-Supply Translators Possible Voltage-Translation Combinations Using Switch Possible Voltage-Translation Combinations Using Device Possible Voltage-Translation Combinations Using Overvoltage-Tolerant Devices
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Introduction
need voltage level translation prevalent most electronic systems today. example, ASIC might operating with supply-voltage VCCA, while device operates with supply-voltage VCCB. enable these devices communicate with each other, level-translation solution needed shown Figure
VCCA* VCCB*
ASIC
Level Translation Solution
Devices
*VCCA equal VCCB
Figure Typical Situation Which Level Translator Needed Input-voltage thresholds output-voltage levels electronic devices vary, depending device technology supply voltage used. Figure shows threshold levels different supply voltages device technologies. interface devices successfully, certain requirements must met: driver must greater than receiver. driver must less than receiver. output voltage from driver must exceed voltage tolerance receiver.
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4.44
-0.45 0.65yVCC 0.35yV 0.45 0.65yV 0.35yV 0.65yVCC 0.35yVCC
CMOS
3.3-V LVTTL
2.5-V CMOS
1.8-V CMOS
1.5-V CMOS
1.2-V CMOS
Figure Digital Switching Levels
Dual-Supply Level Translators
Features
Dual-supply devices designed asynchronous communication between buses devices operating different supply voltages. These devices supply voltages: VCCA interface with side VCCB interface with side. bidirectional level translators, data transmitted from depending logic level input. devices with output enable (OE) control input, buses effectively isolated when inactive. Dual-supply devices from available variety widths cover nearly every supply-voltage node today. These devices flexible, easy use, translate bidirectionally (up-translate down-translate), which makes them ideal choice most level-translation applications. Their active current-drive capability makes them suitable applications with long trace lengths heavy output loads. SN74AVCB324245 32-bit dual-supply level translator that organized four banks eight bits each. Figure shows bank SN74AVCB324245 translating from while, same time, another bank translates from
Selecting Right Level-Translation Solution
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Output
Voltage
Input
Time
Input
Voltage
Output
Time
Figure SN74AVCB324245 Translating From (Bank (Bank Same Time Advantages dual-supply devices:
Flexibility translating to/from variety voltage nodes Active current drive capability Available variety widths
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Product Portfolio
Table summarizes TI's dual-supply device offerings. Table Possible Voltage-Translation Combinations Using Dual-Supply Translators
Possible Voltage-Translation Combinations Device SN74LVCC3245A SN74LVC4245A SN74LVCC4245A SN74ALVC164245 Supply Voltage VCCA VCCB VCCA VCCB VCCA VCCB VCCA VCCB Port 2.5-V CMOS 3.3-V LVTTL/LVCMOS CMOS CMOS CMOS 2.5-V CMOS 3.3-V LVTTL/LVCMOS 1.5-V CMOS CMOS 3.3-V LVTTL/LVCMOS 3.3-V LVTTL/LVCMOS CMOS 3.3-V LVTTL/LVCMOS CMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS 1.5-V CMOS, 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS Port 3.3-V LVTTL/LVCMOS
SN74AVCA164245(1) SN74AVCB164245(1) SN74AVCB324245(1)
VCCA VCCB
1.8-V CMOS
2.5-V CMOS
3.3-V CMOS
1.2-V CMOS SN74AVC1T45(1) SN74AVC2T45(1) SN74AVC4T245(1)(2) SN74AVC8T245(1) SN74AVC16T245(1) SN74AVC20T245(1) SN74AVC24T245(1) SN74AVC32T245(1)
1.5-V CMOS VCCA VCCB
1.8-V CMOS
2.5-V CMOS
3.3-V CMOS Bus-hold option available development, check http://www.ti.com/trans availability.
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Table Possible Voltage-Translation Combinations Using Dual-Supply Translators (Continued)
Possible Voltage-Translation Combinations Device Supply Voltage Port 1.8-V CMOS Port 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS, CMOS 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS, CMOS 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS, CMOS 1.8-V CMOS, 2.5-V CMOS, 3.3-V LVTTL/LVCMOS, CMOS
SN74LVC1T45 SN74LVC2T25 SN74LVC8T25(1)(2) SN74LVC16T25(1)(2)
2.5-V CMOS 1.65 VCCA 1.65 VCCB 3.3-V LVCMOS/LVTTL
CMOS Bus-hold option available development, check http://www.ti.com/trans availability.
adopted easy-to-understand naming convention dual-supply level-translation devices that have been released since January 2004. Figure shows interpretation SN74AVC8T245 device name. Translators using this naming convention have control circuitry powered VCCA, unless otherwise stated data sheet.
SN74
Standard Logic Prefix
Width
Function
Family Name
Translator
Figure Dual-Supply Level-Translation Device Nomenclature
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Open-Drain Devices
Devices with open-drain outputs have N-channel transistor between output GND. These devices used level-translation applications shown Figure output voltage determined VCCB. VCCB greater than input high-level voltage (up-translation) lower than input high-level voltage (down-translation). Open-drain devices useful translating from variety supply-voltage nodes. However, there some drawbacks this method level translation. When output driver low, i.e., when output N-channel transistor there constant current flow from VCCB through resistor Rpullup transistor This contributes higher system power consumption. Using higher-value pullup resistor minimize this current flow. However, larger resistor also slows down rise time output signal because higher time constant resistor Rpullup output load.
VDPU
Rpullup
Receiver
Open-Drain Driver (e.g., SN74LVC1G07)
Figure Level Translation Using Open-Drain Device Advantages open-drain devices:
used up-translate down-translate to/from variety voltage nodes used wired-OR interface
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Application Example Level Translation Using SN74LVC2G07
Figure shows buffer SN74LVC2G07 translating from while other translates down from
VPU1 VPU2
RPU1
RPU2
Vin1 1.8-V CMOS Signals
Vin2 3.3-V LVTTL/ LVCMOS Signals
Figure Open-Drain Device Level-Translation Application supply voltage used, which enables device recognize lowest expected input device valid high signal. minimum value output pullup resistor restricted maximum current-sinking capability (IOL max) open-drain device, whereas maximum value limited maximum allowable rise time output signal. PU(min) OL(max)
SN74LVC2G07 case shown Figure assuming VPU1 VPU2 0.15 using resistors with tolerance: PU1(min) 0.45 PU2(min) 0.45 1.33 0.95
closest (next highest) value standard resistor with tolerance 394.73 0.95
closest (next highest) value standard resistor with tolerance Figure shows output waveforms with capacitive load different values pullup resistors. pullup resistor value increased, rise time output signal increases.
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1.8-V Up-Translation
Output signal with RPU1 Output signal with RPU1
Output signal with RPU1 Voltage
1.8-V input signal
Time
3.3-V 1.8-V Down-Translation
Voltage
3.3-V input signal Output signal with RPU2 Output signal with RPU2
Output signal with RPU2 Output signal with RPU2 Output signal with RPU2
Time
Figure Output Edge Slows With Increasing Value
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Pullup Resistors Outputs CMOS Drivers
achieve level translation, system designers should pullup resistor output device with CMOS (push-pull) outputs. This technique several flaws should avoided. drawback increased power consumption whenever output switches low, discussed beginning section Another problem occurs when output CMOS driver high. this state, lower N-channel transistor off, while upper P-channel transistor There backflow current from high supply supply through resistor upper P-channel transistor. This current flow into supply could cause undesirable effects.
Receiver
CMOS Inverter
Figure Pullup Resistors Output CMOS Drivers Recommended
Switches
switches from TI's CB3T, CBT, CBTD, families used level-translation applications. switches ideal translation applications which active current drive required where very fast propagation delays desired. Advantages switches:
Fast propagation delays devices configured TVC) used bidirectional level translation without direction control.
Devices from TI's CB3T family used down-translation from when operated with down-translation from when operated with CB3T devices used bidirectional translation some applications shown Figure
Selecting Right Level-Translation Solution
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System
(TTL) System
CB3T Switch
(TTL) Memory
Memory
(TTL)
(TTL)
Figure CB3T Device Used Interface With (TTL) Figure SN74CB3T3306 used interface with (TTL) bus. CB3T device operated with supply voltage When channeling signal from bus, CB3T device clamps output voltage When channeling signal from bus, output signal side clamped about which valid level device. drawbacks this approach must considered: 2.8-V level from `CB3T3306 poses reduced high-level noise margin side. this case, noise margin would Because high output from CB3T device driven rail, receiver exhibits excess power consumption called current (more discussion about presented Section NOTE: 2.8-V level with 25°C, This would valid level CMOS receiver; therefore, CB3T devices cannot used up-translate when interfacing with CMOS (without pullup resistor).
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CBTD Devices
Devices from CBTD families used interface systems with 3.3-V systems. These devices only used down-translate when interfacing CMOS system with 3.3-V system. They used bidirectional translation when interfacing system with 3.3-V system. Figure shows SN74CBT1G384 used 3.3-V translation. external diode must connected between supply device. external diode drops gate voltage pass transistor down additional drop results Additional diodes used limit output even lower voltages. some cases, quiescent current (ICC) flowing through diode enough turn diode, resistor added ground ensure enough bias current through diode.
External Diode
CBT1G384
2.87
Device 3.3-V Device
Figure SN74CBT1G384 3.3-V Application Figure shows waveforms this 3.3-V down-translation; propagation delay from input output very minimal. devices also configured like Translation Voltage Clamp (TVC) devices flexible, bidirectional translation without direction control. This discussed detail application report, Flexible Voltage-Level Translation With Devices, literature number SCDA006.
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Input Signal
Voltage
Output Signal (3.3
Time
Figure 3.3-V Translation Using Device
Using Translation Voltage Clamp (TVC) Devices
devices used bidirectional level translation. These devices need direction control signal. Each device consists array N-channel pass transistors with their gates tied together internally shown Figure
GATE
Figure Simplified Schematic Typical TVC-Family Device
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translating application, FETs connected reference transistor, other transistors used pass transistors. most positive voltage low-voltage side each pass transistor limited voltage reference transistor. transistors array have same electrical characteristics; therefore, them used reference transistor. Because transistors fabricated symmetrically, signals bidirectional through each FET, either port connection each used low-voltage side.[1] drain reference transistor must connected VDDREF through resistor shown Figure VREF must less than equal (VBIAS bias reference transistor into conduction. gate reference transistor tied drain saturate transistor.
VDDREF (VREF VDPU
TVC3306 GATE
VREF
VBIAS Chip Memory
Figure SN74TVC3306 Used Level-Translation Application example shown Figure VREF equal voltage level CPU, whereas VDPU voltage level desired side. When down-translating from side side, voltage side clamped VREF. When up-translating from (A3) (B3), voltage side approaches VREF, pass transistor between (A3) (B3) switches off, voltage (B3) pulled VDPU through 150- pullup resistor. Figure waveforms bidirectional translation using device Tables possible voltage-translation combinations.
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Output Signal (3.3
Input Signal (3.3
Voltage Voltage Input Signal (1.8
Output Signal (1.8
Time
Time
Figure Waveforms Bidirectional Translation Using Device Table Possible Voltage-Translation Combinations Using Switch
Switch Family (with external diode) CBTD Range From CMOS CMOS CMOS 3.3-V LVTTL/LVCMOS 3.3-V LVTTL/LVCMOS 3.3-V LVTTL/LVCMOS 3.3-V LVTTL/LVCMOS CB3T 2.5-V LVCMOS 2.5-V LVCMOS Used
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Table Possible Voltage-Translation Combinations Using Device
Switch Family VREF Range Bidirectional Translation Between 3.3-V LVTTL/LVCMOS 2.5-V CMOS 1.8-V CMOS CMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS CMOS 2.5-V CMOS 1.8-V CMOS 3.3-V LVTTL/ LVCMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS CMOS 3.3-V LVTTL/LVCMOS 1.8-V CMOS 2.5-V CMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS CMOS 3.3-V LVTTL/LVCMOS device used TVC) VREF 2.5-V CMOS 1.8-V CMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS CMOS 3.3-V LVTTL/LVCMOS 2.5-V CMOS 1.5-V CMOS 1.8-V CMOS 1.2-V CMOS 0.8-V CMOS CMOS 3.3-V LVTTL/LVCMOS 2.5-V CMOS 1.2-V CMOS 1.8-V CMOS 1.5-V CMOS 0.8-V CMOS CMOS 3.3-V LVTTL/LVCMOS 2.5-V CMOS 0.8-V CMOS 1.8-V CMOS 1.5-V CMOS 1.2-V CMOS VDDREF VREF VDPU
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Overvoltage-Tolerant Devices
Devices with overvoltage-tolerant inputs tolerate input voltages greater than device supply voltage. This made possible eliminating input clamp diode using thicker gate oxides that tolerate voltage levels higher than VCC. These devices used perform down-translation shown Figure There ways identify device with overvoltage-tolerant inputs:
Look input voltage (VI) parameter under recommended operating conditions data sheet. Devices with overvoltage-tolerant inputs have value that independent VCC. specified definite number, example, Look input diode current (IIK) under absolute maximum ratings. Devices with overvoltage-tolerant inputs have only minus sign front number, example, instead This implies that only clamp diode present input, that input clamp diode absent.
Devices from AUC, LVC, LV-A, families have overvoltage-tolerant inputs. transceiver functions within these families, I/Os overvoltage-tolerant only device IOFF feature. NOTE: Devices from family have IOFF feature; therefore, transceiver functions from this family have overvoltage-tolerant I/Os.
SN74LVC244A
Figure Down-Translation Using Logic Device With Overvoltage-Tolerant Inputs When using overvoltage-tolerant devices level translation, input signal slow edges, then duty cycle output signal might affected. example shown Figure inputs swing from because device operated with switches 3.3-V threshold levels. input signal slow rise fall times, this will result change output duty cycle shown Figure Therefore, overvoltage-tolerant devices might ideal translation solution applications where output duty cycle critical, example, certain clock applications.
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Input Signal With Duty Cycle Slow Edges
Voltage
3.3-V Output Signal With Duty Cycle
Time
Figure Shift Output Duty Cycle When Using Overvoltage-Tolerant Device Level Translation Advantages overvoltage-tolerant devices:
Only supply voltage needed Broad portfolio AHC, AUC, AVC, LV-A, devices
Table possible voltage-translation combinations.
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Table Possible Voltage-Translation Combinations Using Overvoltage-Tolerant Devices
Device Family Range From CMOS 3.3-V LVTTL/LVCMOS 3.3-V LVTTL/LVCMOS AHC, LV-A 2.5-V CMOS 2.5-V CMOS 3.3-V LVTTL/LVCMOS CMOS 1.65 1.65 (Little Logic) 2.5-V CMOS 1.8-V CMOS 2.5-V CMOS 3.3-V LVTTL/LVCMOS 2.5-V CMOS 1.8-V CMOS 1.8-V CMOS 2.5-V CMOS 3.3-V LVTTL/LVCMOS 2.5-V CMOS 1.8-V CMOS 1.8-V CMOS 1.5-V CMOS 1.8-V CMOS 1.5-V CMOS 1.5-V CMOS 2.5-V CMOS 1.8-V CMOS 3.3-V LVTTL/LVCMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS 1.8-V CMOS 1.5-V CMOS 2.5-V CMOS 1.2-V CMOS 0.8-V CMOS 1.5-V CMOS 1.8-V CMOS 1.2-V CMOS 0.8-V CMOS 1.2-V CMOS 1.5-V CMOS 1.2-V CMOS 0.8-V CMOS 0.8-V CMOS Used
Devices With TTL-Compatible Inputs
Devices from HCT, AHCT, ACT, ABT, families accept TTL-level input signals output CMOS signals. Because LVTTL/LVCMOS switching thresholds equal (see Figure these devices used translate from However, because input high signals driven rail, input stages receiver device draw extra static current called current. Figure shows plot characteristics SN74HCT541. static 3.3-V input signal, device draws continuous excess current about input.
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DICC when
-0.5
Figure Characteristics SN74HCT541 Advantages devices with TTL-compatible inputs:
Only supply voltage needed Broad portfolio HCT, AHCT, ACT, ABT, devices choose from
Summary Translation Solutions
Dual-supply devices: This best choice most voltage level-translation applications. These devices perform bidirectional level translation between variety voltage nodes. They offer power consumption, fast propagation delays, active current drive. Open-drain devices: Open-drain devices used up-translate down-translate, with external pullup resistor output. This solution very flexible, very power efficient. Devices with overvoltage-tolerant inputs: These devices good option easily down-translate signal. input signal slow rising falling edges, then duty cycle output signal might affected. CB3T devices: These switches ideal 2.5-V, 3.3-V, 3.3-V 2.5-V down-translation applications. CB3T devices offer 1-ns propagation delays very power consumption. These devices provide drive current, dual-supply translator should used buffering needed. CBT/CBTD devices: (with external diode) CBTD devices used perform 3.3-V down-translation. These devices offer fast propagation delays power consumption. These devices provide current drive, alternate solution should used buffering needed. devices: devices allow bidirectional level translation without need direction control signal. This solution requires external pullup resistors. Power consumption depends values external pullup resistors. device configured operate device well.
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Devices with TTL-compatible inputs: Devices from HCT, AHCT, ACT, ABT, families used 3.3-V up-translation. This solution causes excess system power consumption should avoided applications where power consumption major concern.
Conclusion
There several ways achieve logic-level translation, each approach merits demerits. Using dual-supply level translators usually best option most level-translation applications. offers broad portfolio dual-supply level translators meet your mixed-voltage interfacing needs. situations where these devices might most optimal solution, other solutions should considered. Open-drain devices used down-translation applications where power consumption major concern. switches overvoltage-tolerant devices should considered down-translation applications, devices with TTL-compatible inputs used 3.3-V up-translation increased system power consumption acceptable.
References
Thomas McCaughey, Stephen Nolan, John Pietrzak, Flexible Voltage-Level Translation With Family Devices, literature number SCDA006.
Selecting Right Level-Translation Solution
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