Analog-to-Digital Converter with 8051 Microcontroller Flash Memor

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Analog-to-Digital Converter with 8051 Microcontroller Flash Memor

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MSC1210
Analog-to-Digital Converter
with 8051 Microcontroller Flash Memory
User's Guide
December 2002
SBAU077
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Copyright 2002, Texas Instruments Incorporated
Contents
Contents
Introduction MSC1210 MSC1210 Description MSC1210 Pin-Out 1.2.1 Ports (P0, 1.2.2 Oscillator Inputs (XTAL1 XTAL2) 1.2.3 Reset Line (RST) 1-10 1.2.4 Address Latch Enable (ALE) 1-10 1.2.5 Program Store Enable (PSEN) 1-10 1.2.6 External Access (EA) 1-11 Enhanced 8051 Core 1-12 Family Device Compatibility 1-13 Flash Memory 1-13 High Performance Analog Functions 1-13 High-Performance Peripherals 1-14 MSC1210 Memory Organization Description Program Memory Data Memory 2.3.1 On-Chip Extended Static (SRAM) 2.3.2 On-Chip Flash Data Memory 2.3.3 External Data Memory Internal 2.4.1 Stack 2.4.2 Register Banks 2.4.3 Memory 2.4.4 Special Function Register (SFR) Memory 2-10 Special Function Registers (SFRs) Description Referencing SFRs 3.2.1 Referencing Bits SFRs Bit-Addressable SFRs Types Definitions Basic Registers Description Accumulator Registers Register Program Counter (PC) Data Pointer (DPTR0/DPTR1) Stack Pointer (SP)
Contents
Contents
Addressing Modes Description Immediate Addressing Direct Addressing Indirect Addressing External Direct Addressing External Indirect Addressing Code Indirect Adressing Program Flow Description Conditional Branching Direct Jumps Direct Calls Returns From Routines Interrupts System Timing Description System Timers 7.2.1 Microseconds Timer 7.2.2 Milliseconds Timer Startup Timing 7.3.1 Normal-Mode Power-On Reset Timing 7.3.2 Flash Programming Mode Power-On Reset Timing
Timers Description Does Timer Count? Using Timers Measure Time 8.3.1 Long Does Timer Take Count? 8.3.2 Timer SFRs 8.3.3 TMOD 8.3.4 TCON 8.3.5 Initializing Timer 8.3.6 Reading Timer 8.3.7 Timing Length Events 8-11 Using Timers Event Counters 8-12 Using Timer 8-13 8.5.1 T2CON 8-13 8.5.2 Timer Auto-Reload Mode 8-14 8.5.3 Timer Capture Mode 8-15 8.5.4 Timer Baud Rate Generator 8-16 Serial Communication Description Setting Serial Port Mode 9.2.1 Serial Mode Synchronous Half-Duplex 9.2.2 Serial Mode Asynchronous Full-Duplex 9.2.3 Serial Mode Asynchronous Full-Duplex 9.2.4 Serial Mode Asynchronous Full-Duplex 9-11 Setting Serial Port Baud Rate 9-13 Writing Serial Port 9-15 Reading Serial Port 9-16
Contents
Interrupts 10-1 10.1 Description 10-2 10.2 Events That Trigger Interrupts 10-3 10.3 Enabling Interrupts 10-5 10.4 Polling Sequence 10-6 10.5 Interrupt Priorities 10-7 10.6 Interrupt Triggering 10-8 10.7 Exiting Interrupts 10-8 10.8 Types Interrupts 10-9 10.8.1 Serial Interrupts 10-9 10.8.2 External Interrupts 10-9 10.8.3 Timer Interrupts 10-11 10.8.4 Watchdog Interrupt 10-11 10.8.5 Auxiliary Interrupts 10-11 10.9 Waking from Idle Mode 10-15 10.10 Register Protection 10-16 10.11 Common Problems with Interrupts 10-18 Pulse Width Modulator/Tone Generator 11-1 11.1 Description 11-2 11.2 Tone Generator 11-3 11.2.1 Tone Generator Waveforms 11-4 11.3 Generator 11-5 11.3.1 Example Tone Generation 11-8 11.3.2 Example Tone Generation Idling 11-9 11.3.3 Example Updating 11-11 Analog-to-Digital Converter 12-1 12.1 Description 12-2 12.2 Input Multiplexer 12-3 12.3 Temperature Sensor 12-5 12.4 Burnout Current Sources 12-7 12.5 Input Buffer 12-8 12.6 Analog Input 12-8 12.7 Programmable Gain Amplifier (PGA) 12-9 12.8 Offset 12-10 12.9 Modulator 12-10 12.10 Calibration 12-11 12.11 Digital Filter 12-12 12.11.1 Multiplexing Channels 12-14 12.12 Voltage Reference 12-15 12.13 Summation/Shifter Register 12-16 12.13.1 Manual Summation Mode 12-18 12.13.2 Summation Mode 12-18 12.13.3 Manual Shift (Divide) Mode 12-19 12.13.4 Summation with Shift (Divide) Mode 12-19 12.14 Interrupt-Driven Sampling 12-20 12.15 Syncronizing Multiple MSC1210 Devices 12-22 12.16 Ratiometric Measurements 12-24 12.16.1 Differential Vref 12-25
Contents
Contents
Serial Peripheral Interface (SPI) 13-1 13.1 Description 13-2 13.2 Functional Description 13-2 13.3 Clock Phase Polarity Controls 13-4 13.4 Signals 13-5 13.4.1 Master Slave 13-5 13.4.2 Master Slave 13-5 13.4.3 Serial Clock 13-5 13.4.4 Slave Select 13-5 13.5 System Errors 13-6 13.6 Data Transfers 13-7 13.7 FIFO Operation 13-9 13.8 Code Examples 13-10 13.8.1 Master Transfer Double-Buffer Mode using Interrupt Polling 13-10 13.8.2 Master Transfer FIFO Mode using Interrupts 13-11 Additional MSC1210 Hardware 14.1 Description 14.2 Low-Voltage Detect 14.2.1 Power Supply 14.3 Watchdog Timer 14.3.1 Watchdog Timer Hardware Configuration 14.3.2 Enabling Watchdog Timer 14.3.3 Resetting Watchdog Timer 14.3.4 Disabling Watchdog Timer 14.3.5 Watchdog Timeout/Activation 14-1 14-2 14-2 14-3 14-4 14-4 14-5 14-7 14-8 14-8
Advanced Topics 15-1 15.1 Hardware Configuration 15-2 15.1.1 Hardware Configuration Registers 15-2 15.1.2 Hardware Configuration Memory 15-5 15.1.3 Accessing Configuration Memory User Program 15-5 15.2 Advanced Flash Memory 15-6 15.2.1 Write Protecting Flash Program Memory 15-6 15.2.2 Updating Interrupts with Reset Sector Lock 15-6 15.3 Breakpoint Generator 15-7 15.3.1 Configuring Breakpoints 15-7 15.3.2 Breakpoint Auxiliary Interrupt 15-8 15.3.3 Disabling Breakpoint 15-8 15.4 Power Optimization 15-9 15.5 Flash Memory Data Memory 15-10 15.6 Advanced Topics Other Information 15-12 15.6.1 Serial Parallel Programming MSC1210 15-12 15.6.2 Debugging Using MSC1210 Boot Routines 15-12 15.6.3 Using MSC1210 with Raisonance Development Tools 15-12 15.6.4 Using MSC1210 Evaluation Module (EVM) 15-12
Contents
8052 Assembly Language 16-1 16.1 Description 16-2 16.2 Syntax 16-2 16.3 Number Bases 16-4 16.4 Expressions 16-4 16.5 Operator Precedence 16-5 16.6 Characters Character Strings 16-5 16.7 Changing Program Flow (LJMP, SJMP, AJMP) 16-6 16.8 Subroutines (LCALL, ACALL, RET) 16-7 16.9 Register Assignment (MOV) 16-8 16.10 Incrementing Decrementing Registers (INC, DEC) 16-11 16.11 Program Loops (DJNZ) 16-12 16.12 Setting, Clearing, Moving Bits (SETB, CLR, CPL, MOV) 16-13 16.13 Bit-Based Decisions Branching (JB, JBC, JNB, JNC) 16-15 16.14 Value Comparison (CJNE) 16-16 16.15 Less Than Greater Than Comparison (CJNE) 16-17 16.16 Zero Non-Zero Decisions (JZ/JNZ) 16-18 16.17 Performing Additions (ADD, ADDC) 16-18 16.18 Performing Subtractions (SUBB) 16-20 16.19 Performing Multiplication (MUL) 16-21 16.20 Performing Division (DIV) 16-22 16.21 Shifting Bits (RR, RRC, RLC) 16-23 16.22 Bit-Wise Logical Instructions (ANL, ORL, XRL) 16-24 16.23 Exchanging Register Values (XCH) 16-26 16.24 Swapping Accumulator Nibbles (SWAP) 16-26 16.25 Exchanging Nibbles Between Accumulator Internal (XCHD) 16-26 16.26 Adjusting Accumulator Addition (DA) 16-27 16.27 Using Stack (PUSH/POP) 16-28 16.28 Setting Data Pointer DPTR (MOV DPTR) 16-30 16.29 Reading Writing External RAM/Data Memory (MOVX) 16-31 16.30 Reading Code Memory/Tables (MOVC) 16-32 16.31 Using Jump Tables (JMP @A+DPTR) 16-34 Keil Simulator 17-1 17.1 Description 17-2 17.2 Timers 17-4 17.2.1 Timer Example 17-5 17.3 Timer 17-11 17.4 Watchdog Timer 17-12 17.4.1 Watchdog Reset Facility Example 17-13 17.5 System Timer 17-16 17.6 Clock Control 17-16 17.7 Analog-to-Digital Converter 17-17 17.8 Summation/Shifter 17-20 17.8.1 ADC/Summation/Shifter Example 17-21 17.9 Interrupts 17-30 17.10 Ports 17-31 17.11 Serial Peripheral Interface (SPI) 17-32 17.11.1 Sample Code 17-34 17.12 mVision Debug Program Example 17-38 17.13 Serial Port 17-40 17.13.1 Serial Port Operation Mode Example 17-42 17.13.2 Transmit Block Baud Rate Computation 17-43 17.13.3 Receive Block Baud Rate Computation 17-44 17.14 Additional Resource 17-46
Contents
Contents
Additional Features MSC1210 Compared 8052 Additional Features MSC1210 Compared 8052 Clock Timing Diagram MSC1210 Timing Chain Clock Control Diagram Boot Routines Description C.1.1 Note Regarding put_string Function 8052 Instruction-Set Quick-Reference Guide 8052 Instruction-Set Quick-Reference Guide 8052 Instruction Description 8052 Instruction Bit-Addressable SFRs (alphabetical) Addressable SFRs (alphabetical) SFRs/Address Cross-Reference Guide (alphabetical) SFR/Address Cross-Reference
Contents
Figures
1-1. 1-2. 1-3. 2-1. 2-2. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 7-7. 8-1. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 11-1. 11-2. 11-3. 11-4. 11-5. 11-6. 12-1. 12-2. 12-3. 12-4. 12-5. 12-6. 13-1. 13-2. 13-3. 13-4. 14-1. 14-2. MSC1210 Block Diagram Configuration MSC1210 MSC1210 Timing Compared Standard 8051 Timing 1-12 MSC1210 Memory MSC1210 Memory Register Bank. Standard 8051 Timing. MSC1210 Timing Chain Clock Control SPI/PWM/Flash Write Timing System Timing Interrupt Control Reset Timing Parallel Flash Programming Power-On Timing ignored) Serial Flash Programming Power-On Timing ignored) 7-10 Timer Block Diagram Modes Serial Port Mode Transmit Timing-High Speed Operation. Serial Port Mode Receive Timing-High Speed Operation. Serial Port Mode Transmit Timing. Serial Port Mode Receive Timing. Serial Port Mode Transmit Timing. Serial Port Mode Receive Timing. 9-10 Serial Port Mode Transmit Timing. 9-11 Serial Port Mode Receive Timing. 9-11 Block Diagram 11-2 Tone Generator Circuit 11-3 Timing Diagram Tone Generator Staircase Mode 11-4 Timing Diagram Tone Generator Square Wave Mode 11-4 Timing Diagram Waveform 11-6 Timing 11-11 MSC1210 Architecture 12-2 Input Multiplexer Configuration 12-3 Basic Input Structure MSC1210 12-8 Filter Step Responses 12-12 Filter Frequency Responses 12-13 Circuit Drawing 12-24 block diagram 13-2 Clock/Data Timing 13-3 Reset State 13-7 FIFO Operation 13-9 Brownout Reset Low-Voltage Detection 14-2 System Timing Interrupt Control 14-4
Contents
Contents
16-1. 17-1. 17-2. 17-3. 17-4. 17-5. 17-6. 17-7. 17-8. 17-9. 17-10. 17-11. 17-12. 17-13. 17-14. 17-15. 17-16. 17-17. 17-18. 17-19. 17-20. B-1.
Rotate Operations 16-23 Timer/Counter Mode 17-4 Timer/Counter 17-5 Parallel Port Peripheral 17-5 Timer/Counter Mode 17-6 Interrupt System 17-6 Timer/Counter 17-11 Status Watchdog Peripheral 17-12 Analog-to-Digital Converter Peripheral 17-18 Error Message 17-19 Accumulator/Shifter Peripheral 17-20 summation/Shifter Peripheral 17-28 Peripheral Mid-Stride Typical 8-Sample Averaging Block 17-28 List Interrupt Peripheral 17-30 Parallel Port Contents Display Window 17-31 Error Message 17-31 Peripheral Window 17-32 Keil Debugger 17-39 Serial Channel Communication Peripheral 17-41 Clock Control Peripheral 17-45 USART0 Preipheral 17-45 MSC1210 Timing Chain Clock Control
viii
Contents
Tables
1-1. 2-1. 2-2. 3-1. 5-1. 7-1. 8-1. 8-2. 8-3. 8-4. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 10-1. 10-2. 10-3. 10-4. 10-5. 10-6. 10-7. 10-8. 10-9. 10-10. 10-11. 10-12. 10-13. 11-1. 11-2. 11-3. 11-4. 11-5. 12-1. 12-2. 12-3. 12-4. 12-5. Descriptions MSC1210 Program Data Memory Size. Program Data Memory Addresses. Names Addresses. MSC1210 Addressing Modes. Signal Definitions Reset Timing Diagrams 7-10 Timer Conrol SFRs. Timer Modes Usage Example 8-Bit Auto-Reload TCON (88h) Function Definitions. Common Baud Rates Using Timer Common Baud Rates Using Timer Mode Commonly Used Baud Rates. 9-13 Baud Rate Settings Timer 9-14 Baud Rate Settings Timer 9-15 Interrupt Sources 10-3 (A8h) 10-5 EICON (D8h) 10-5 (E8h) 10-5 (B8h) 10-7 (F8h) 10-7 EXIF (91h) 10-10 Clearing Auxiliary Interrupts 10-12 (A6h) 10-12 AISTAT (A7h) 10-13 (A5h) 10-13 Bits 10-14 (C6h) 10-15 Polarity Conditions 11-5 Configuring Tone Generation 11-8 Statement Explanations 11-8 Configuring Tone Generation with Idling 11-10 Statement Explanations 11-10 Settings 12-9 Calibration Mode Control Bits 12-11 Filter Settling 12-14 Output Data Rate Channel Rate 12-14 Output Data Rate Channel Rate (10x faster) 12-15
Contents
Contents
14-1. 14-2. 14-3. 16-1. 16-2. 16-3. 16-4. 17-1. C-1.
Typical Sub-Circuit Current Consumption 14-3 Comparator Specification 14-3 Band Parameters 14-3 Order Precedence Mathematical Operators 16-5 Results 16-24 Results 16-24 Results 16-24 Timer/Counter Control Bits 17-11 Boot Routines
Chapter
Introduction MSC1210
This chapter describes basic function MSC1210 analog-to-digital converter (ADC).
Topic
Page
MSC1210 Description MSC1210 Pin-Out Enhanced 8051 Core 1-12 Family Device Compatibility 1-13 Flash Memory 1-13 High-Performance Analog 1-13 High-Performance Peripherals 1-14
Introduction MSC1210
MSC1210 Description
MSC1210 Description
MicroSystem family devices designed high-resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation. They provide highperformance mixed signal solutions. MicroSystem family only includes high-end analog features digital processing capability, also integrates high-performance peripherals offer unique system solution. main components MicroSystem product include:
Enhanced 8051 microcontroller core FLASH memory High-performance analog functions High-performance peripherals
enhanced 8052 microcontroller core includes dual data pointers executes instructions three times faster than standard 8052 core. This MIPS capability allows optimize speed, power, noise tradeoffs based specific requirements. block diagram MSC1210 shown Figure 1-1.
Figure 1-1. MSC1210 Block Diagram
MSC1210 Pin-Out
on-chip FLASH memory programmable variety modes over wide temperature operating voltage range. This greatly simplifies programming both manufacturing level field. on-chip high-performance analog features state-of-the-art. performance features analog functions rival best industry. lownoise precision voltage reference along with integration other analog features greatly simplify achieving high-end analog performance. on-chip high-performance peripherals only reduce cost, design time, board space required external circuitry, also blend analog digital functions that simplify system design. high-performance peripherals designed from system perspective, thereby decreasing processing requirements providing greater system throughput.
MSC1210 Pin-Out
names functions these pins similar those found traditional 8052 core, MSC1210 includes additional assignments support additional functions specific part.
Figure 1-2. Configuration MSC1210
Introduction MSC1210
MSC1210 Pin-Out
Table 1-1. Descriptions MSC1210
Name XOUT Description crystal oscillator XOUT supports parallel resonant crystals ceramic resonators. XOUT serves output crystal amplifier. crystal oscillator supports parallel resonant crystals ceramic resonators. also input there external clock source instead crystal. Port bidirectional port. alternate functions Port3 listed below. Port 3-Alternate Functions: PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 DVDD DGND AGND AVDD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6, EXTD AIN7, EXTA AINCOM ALTERNATE RxD0 TxD0 INT0 INT1/TONE/ MODE Serial Port Input Serial Port Output External Interrupt External Interrupt 1/TONE/PWM Output Timer External Input Timer External Input External Data Memory Write Strobe External Data Memory Read Strobe
3-10
P3.0-P3.7
Digital Power Supply Digital Ground HIGH reset input instruction clock cycles will reset device. Connection Analog Ground Analog Power Supply Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Digital Voltage Detect Input Analog Input Channel Analog Voltage Detect Input Analog Common Single-Ended Inputs Voltage Reference Negative Input Voltage Reference Positive Input Voltage Reference Output
MSC1210 Pin-Out
Table Descriptions MSC1210 (Continued)
34-40, Name P2.0-P2.7 Description Port bidirectional port. alternate functions Port listed below. Port 2-Alternate Functions: PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN, OSCCLK, MODCLK ALTERNATE MODE Address Address Address Address Address Address Address Address
34-40,
P2.0-P2.7
Program Store Enable: Connected optional external memory chip enable. PSEN will provide active pulse. programming mode, PSEN used input along with define serial parallel programming mode. PSEN held HIGH parallel programming tied serial programming. This also selected (when using external program memory) output Oscillator clock, Modulator clock, HIGH, LOW. PSEN Program Mode Selection Normal Operation Parallel Programming Serial Programming Reserved
Address Latch Enable: Used latching byte address during access external memory. emitted constant rate oscillator frequency, used external timing clocking. pulse skipped during each access external data memory. programming mode, used input along with PSEN define serial parallel programming mode. held HIGH serial programming tied parallel programming. External Access Enable: must externally held enable device fetch code from external program memory locations starting with 0000H. Port bidirectional port. alternate functions Port listed below. Port 0-Alternate Functions: PORT P0.0 P0.1 P0.2 P0.3 P0.4 ALTERNATE MODE Address/Data Address/Data Address/Data Address/Data Address/Data
49-54
P0.0-P0.7
Introduction MSC1210
MSC1210 Pin-Out
Table Descriptions MSC1210 (Continued)
49-54 Name P0.0-P0.7 Description P0.5 P0.6 P0.7 59-64 P1.0-P1.7 Address/Data Address/Data Address/Data
Port bidirectional port. alternate functions Port listed below. Port 1-Alternate Functions: PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 ALTERNATE T2EX RxD1 TxD1 INT2/SS INT3/MOSI INT4/MISO INT5/SCK MODE Input External Input Serial Port Input Serial Port Output External Interrupt/Slave Select External Interrupt/Master Out-Slave External Interrupt/Master In-Slave External Interrupt/Serial Clock
1.2.1
Ports (P0,
pins MSC1210, them dedicated lines that have one-to-one relation with SFRs developer raise lower these lines writing corresponding bits SFRs. Likewise, current state these lines found reading corresponding bits SFRs. ports have optional pull-up resistors that enabled when port 8051 mode, configured PxDDRL/H SFRs. pull-up resistors disabled when port configured other mode, when accessing external memory.
1.2.1.1
Port Port dual-function: some designs port lines available developer access external devices, while other designs used access external memory. circuit requires external RAM, microcontroller will port latch in/out 8-bit data word, well eight bits address response MOVX instruction, long hardware configuration registers correctly. Port lines used other functions long external data memory being accessed same time hardware configuration registers correctly. circuit requires external code memory, microcontroller will port lines access each instruction executed. this case, port cannot used other purposes, because state lines constantly being modified access external code memory.
MSC1210 Pin-Out
1.2.1.2
Port Port consists eight lines that used interface external parts. Port commonly used interface external hardware such LCDs, keypads, other devices. opposed standard 8052 core, lines MSC1210 serve optional alternate functions, described below. These lines still used developing purposes, functions described below needed. P1.0 (T2): T2CON.1 (C/T2), then timer incremented whenever there transition this line. With C/T2 set, P1.0 clock source timer P1.1 (T2EX): timer auto-reload mode T2CON.3 (EXEN2) set, transition this line causes timer reloaded with auto-reload value. This also causes T2CON.6 (EXF2) external flag set, which cause interrupt, enabled. P1.2 (RxD1): secondary USART being used, P1.2 (RxD1) that receives serial data. Data received this read using SBUF1 SFR. P1.3 (TxD1): secondary USART being used, P1.3 (TxD1) that transmits serial data. Data written SBUF1 sent this pin. P1.4 (INT2/SS): This dual functions. used trigger external interrupt when transition detected this line. also used slave select applications. P1.5 (INT3/MOSI): This used trigger external interrupt when transition detected. also used Master Out/Slave applications. P1.6 (INT4/MISO): This used trigger external interrupt when transition detected. also used Master In/Slave applications. P1.7 (INT5/SCK): This used trigger external interrupt when transition detected. also used serial clock applications.
Introduction MSC1210
MSC1210 Pin-Out
1.2.1.3
Port Like port port dual-function. some circuit designs, available accessing external devices, while others used address external external code memory. When more than bytes external used, port used output high byte address that accessed MOVX operation. Whether port used address external memory general lines defined EGP23 hardware configuration Register Note: When EGP23 hardware configuration Register set, Port assumes value high byte DPTR when using MOVX @DPTR instruction. When using MOVX instructions, port assumes value MPAGE SFR. circuit requires external code memory, microcontroller automatically uses port lines access each instruction executed, only EGP23 HCR1 equals one. this case, port cannot used other purposes because state lines constantly being modified access external code memory.
1.2.1.4
Port Port consists entirely dual-function lines. While access these lines from software reading/writing SFR, each predefined function that microcontroller handles automatically when configured and/or when necessary. P3.0 (RxD0): primary USART/serial port uses P3.0 receive line. in-circuit designs that using microcontroller internal serial port, this line into which serial data clocked. Note: When interfacing 8052 RS-232 port, cannot connect this line directly RS-232 pin; must pass through part such MAX233 obtain correct voltage levels. assign function this long circuit need receive data integrated serial port. P3.1 (TxD0): primary USART/serial port uses P3.1 transmit line. in-circuit designs that using microcontroller internal serial port, this line used microcontroller clock data written SBUF SFR. Note: When interfacing 8052 RS-232 port, cannot connect this line directly RS-232 pin; must pass through part such MAX233 obtain correct voltage levels. assign function this long circuit need transmit data integrated serial port.
MSC1210 Pin-Out
P3.2 (INT0): When configured, this line used trigger external Interrupt. This either low-level triggered triggered transition (see Chapter Interrupts, details). assign function this long circuit need trigger external interrupt. P3.3 (INT1/TONE/PWM): When configured, this line used trigger external Interrupt. This either low-level triggered triggered transition (see Chapter Interrupts, details). This also used outputting PWM, configured. P3.4 (T0): When configured, this line used clock source timer Timer incremented either every instruction cycle that high, every time there transition this line, depending timer configured (see Chapter Timers, details). assign function this long circuit need control timer externally. P3.5 (T1): When configured, this line used clock source timer Timer incremented either every instruction cycle that high, every time there transition this line, depending timer configured (see Chapter Timers, details). assign function this long circuit need control timer externally. P3.6 (WR): This external memory write strobe line when EGP23 hardware configuration Register This line asserted microcontroller whenever MOVX instruction writes external RAM. This line should connected write line. assign function this long circuit does write external using MOVX. P3.7 (RD): This external memory read strobe line when EGP23 hardware configuration Register This line asserted microcontroller whenever MOVX instruction read from external RAM. This line must connected read line. assign function this long circuit does read from external using MOVX.
1.2.2
Oscillator Inputs (XTAL1 XTAL2)
MSC1210 typically driven crystal connected pins (XOUT) (XIN). Common crystal frequencies 11.0592MHz well 12MHz, although MSC1210 capable accepting frequencies high 33MHz. While crystal normal clock source, this always case. digital clock source also attached XOUT provide clock microcontroller.
Introduction MSC1210
MSC1210 Pin-Out
1.2.3
Reset Line (RST)
master reset line microcontroller. When this brought high instruction cycles, microcontroller effectively reset. SFRs, including ports, restored their default conditions program counter reset 0000H. Keep mind that Internal affected reset. microcontroller begins executing code 0000H when returns state. reset line often connected reset button/switch that press reset circuit. also common connect reset line watchdog supervisor (such MAX707). Traditional resistor-capacitor networks attached reset line also work well because input Schmitt trigger input.
1.2.4
Address Latch Enable (ALE)
output-only that controlled entirely microcontroller allows microcontroller multiplex low-byte memory address 8-bit data itself port This because, while high byte memory address sent port port used both send byte memory address data itself. This accomplished placing byte address port exerting high-to-low transition latch byte address into latch (such 74HC573), then placing data bits port this way, MSC1210 able output 16-bit address 8-bit data word with lines instead line used this fashion both access external with MOVX @DPTR, well accessi instructions external code memory. When program executed from external code memory, pulses rate that that oscillator frequency. Thus, oscillator operates 11.0592MHz, pulses rate times second. When MOVX instruction executed, PSEN pulse missed lieu pulse This also used when programming part, along with PSEN, input during reset indicate whether programming will occur serial parallel mode. this line held high when programming mode, programming will occur serial mode.
1.2.5
Program Store Enable (PSEN)
program store enable (PSEN) line exerted automatically microcontroller whenever accesses external code memory. This line should attached output enable (OE) device that contains your code memory. PSEN signal applied both internal external memory access. This also used when programming part, along with ALE, input indicate whether programming will occur serial parallel mode. this line held high when programming mode, programming will occur parallel mode.
1-10
MSC1210 Pin-Out
1.2.6
External Access (EA)
external access (EA) line used determine whether MSC1210 will execute your program from external code memory from internal code memory. tied high (connected supply), microcontroller will execute program finds internal/on-chip code memory. tied ground), will attempt execute program that finds attached external program memory. course, external program memory must properly connected microcontroller able access program external program memory. ignored during serial parallel flash programming modes. Note: Even when tied high (indicating that microcontroller should execute from internal code memory), microcontroller will attempt execute from external code memory program counter references address available chip using, accessing program memory excess amount flash memory that have partitioned program memory. example, have partitioned flash memory program memory high, derivative starts executing program finds on-chip. However, your on-chip program attempts execute code above 0FFFH (that exceeding 4k), then MSC1210 will attempt execute that code that address from external code memory. Thus, possible have split design, which some code found on-chip rest found off-chip.
Introduction MSC1210
1-11
Enhanced 8051 Core
Enhanced 8051 Core
MSC1210 8052-based family high-performance, mixed-signal controllers. instructions MSC1210 family perform exactly same function they would standard 8052 core. Although effect bits, flags, registers same, timing different. MSC1210 family uses efficient 8052 core that results improved instruction execution speed three times faster than original core same external clock speed clock cycles instruction versus clock cycles instruction, shown Figure 1-3). This allows device slower external clock speeds, which reduces system noise power consumption, provides greater throughput.
Figure 1-3. MSC1210 Timing Compared Standard 8051 Timing
timing software loops faster with MSC1210 than with standard 8052. However, timer/counter operation MSC1210 maintained clocks increment optionally clocks increment. develop software MSC1210 with existing 8052 development tools because MSC1210 fully compatible with standard 8052 instruction set. Additionally, complete integrated development environment provided with each demonstration board.
1-12
Family Device Compatibility
Family Device Compatibility
hardware functionality outs across MSC1210 family fully compatible. only difference between family members memory configuration this enables simple migration between family members. Code written bytes program memory version MSC1210 executed directly 16K, versions. This allows delete software functions freely migrate between family members. MSC1210 become standard device used across several application platforms.
Flash Memory
MSC1210 features flexible flash memory that allows uniquely configure program non-volatile data memory maps meet needs application. flash memory programmable over entire operating voltage range temperature range using both serial parallel programming methods.
High Performance Analog Functions
analog functionality state-of-the-art. extremely noise, which enables meet even most stringent analog requirements. integrated programmable gain amplifier (PGA) further improves performance ADC. This effectively provides resolution into nanovolt range. on-chip voltage reference provides drift high accuracy, thus eliminating need external voltage reference. These features integrated with other analog functions, such programmable filter, multiplexer, temperature sensor, burnout current sources, analog input buffer, offset correction digital-to-analog converter (DAC).
Introduction MSC1210
1-13
High-Performance Peripherals
High-Performance Peripherals
High-performance peripherals included on-chip, which offload processing control functions from core further improve overall device efficiency throughput. On-chip peripherals include additional SRAM, 32-bit accumulator, SPI-compatible serial port with FIFO buffer, dual USARTs, on-chip power-on reset, brownout reset, low-voltage detect, multiple digital ports with configurable I/O, 16-bit pulse width modulator (PWM), watchdog timer, three timer/counters. instance, interface uses FIFO buffer, which allows serial transmission reception data with virtually overhead. FIFO buffer function allows transfer large amounts data faster transfer rates than more conventional methods. Additionally, 32-bit accumulator significantly reduces processing overhead multiple byte data from other sources. This allows 24-bit addition, subtraction, shifting accomplished without using resources. This reduce both code size code execution time.
1-14
Chapter
MSC1210 Memory Organization
This chapter defines Memory Organization MSC1210 ADC.
Topic
Page
Description Program Memory Data Memory Internal
MSC1210 Memory Organization
Description
Description
MCS1210 three very general types memory. program MCS1210 effectively, necessary have basic understanding these memory types:
Special Function Registers refer bytes that control operation
MSC1210.
Program Memory used store actual program that reside
chip, off-chip, both.
Data Memory static random access memory (SRAM) that reside
on-chip, off-chip, both. MSC1210 four types data memory:
On-chip extended SRAM Off-chip external SRAM On-chip Flash Data memory Internal
Program Memory
Program memory holds actual program that run. This memory includes on-chip flash memory designated program memory and/or external memory. MSC1210 family offers maximum on-chip flash program memory. exact amount on-chip program memory depends specific MSC1210 version selected flash memory that chip been partitioned between program data memory. Figure illustrates flash memory distributed between these types memory.
Figure 2-1. MSC1210 Memory
Program Memory
example, model there flash memory available. This configured either program memory, data memory, both. This configuration moment firmware loaded onto MSC1210 setting hardware configuration register HCR0 Table 2-1. This table indicates total amount program data memory available each part revision given specific HCR0 setting.
Table 2-1. Program Data Memory Size.
HCR0 DFSEL (default)
Note:
MSC1210Y2
MSC1210Y3
MSC1210Y4 12kB 14kB 15kB 16kB 16kB 16kB 16kB
MSC1210Y5 16kB 24kB 28kB 30kB 31kB 32kB 32kB 32kB 16kB
When program memory configuration selected, program execution external
example, setting DFSEL bits with MSC1210Y5 would cause 31kb on-chip flash memory partitioned program memory flash memory partitioned data memory. Table indicates where assigned memory will located address space. This table provides essentially same information Table 2-1, also indicates where memory will located. example, DFSEL example previous paragraph (31kb on-chip flash program memory, on-chip flash data memory) appears Table flash program memory from 0000H 7BFFH (which 31k) flash data memory from 0400H 07FFH (which 1k). Note that Data memory address starts 0400H because first (0000H-03FFH) default, used address on-chip extended SRAM. location on-chip extended SRAM changed using Memory Control (MCON) SFR. setting MCON, on-chip extended SRAM moved from 0000H-03FFH 8400H-87FFH. However, on-chip extended flash data memory always begins 0400H regardless whether SRAM located 0000H 8400H.
MSC1210 Memory Organization
Data Memory
Table 2-2. Program Data Memory Addresses.
HCR0
DFSEL (reserved) (default) Note:
MSC1210Y2
0000 0000-07FF 0000-00BF 0000-0FFF 0400-13FF 0400-00BF 0400-07FF 0000
MSC1210Y3
0000 0000-0FFF 0000-17FF 0000-1BFF 0000-1FFF 0400-23FF 0400-13FF 0400-0BFF 0400-07FF 0000
MSC1210Y4
0000 0000-1FFF 0000-2FFF 0000-37FF 0000-3BFF 0000-3FFF 0400-43FF 0400-23FF 0400-13FF 0400-0BFF 0400-07FF 0000
MSC1210Y5
0000 0000-3FFF 0000-5FFF 0000-6FFF 0000-77FF 0000-7BFF 0000-7FFF 0400-83FF 0400-43FF 0400-23FF 0400-13FF 0400-0BFF 0400-07FF 0000
Program accesses above highest listed address will access external Program memory.
Program memory addressing beyond on-chip address range accessed externally ports total amount code memory, on-chip off, limited limitations 8052 architecture. Note: MSC1210 programs limited because code memory restricted 64k. Some compilers offer ways around this limit when used with specially wired hardware. However, without such special compilers hardware, programs limited 64k. MSC1210 includes boot code that controls operation during serial parallel programming. program mode, boot located first program memory. boot available your program long (hardware configuration register set, which default. When enabled, boot routines will located program memory addresses F800H-FFFFH. boot includes number functions such flash memory access, serial routines including data transmission, reception, auto-baud.
Data Memory
Data memory divided into four types memory, depending location volatility: internal RAM, on-chip extended SRAM, off-chip external SRAM, on-chip flash data memory. However, data memory (regardless location volatility) accessed using MOVX instruction, except internal RAM, which accessed using instruction.
2.3.1
On-Chip Extended Static (SRAM)
MSC1210 includes 1024 bytes on-chip extended static (SRAM). Even though this memory resides on-chip, accessed using MOVX instruction were external data memory. Whenever program accesses data memory addresses 0000H through 03FFH, on-chip external SRAM used.
Data Memory
On-chip extended static provides data memory that requires external circuitry available regardless MSC1210's flash memory designated. This makes convenient memory area purposes such temporary buffers, calculation scratchpads, other purpose that requires less memory, does require survive power failure.
2.3.2
On-Chip Flash Data Memory
addition on-chip extended SRAM described previous section, MSC1210 also capability offering on-chip flash data memory. Flash memory slower than SRAM, advantage being nonvolatile: contents will lost when power source removed. parts MSC1210 family come with some amount on-chip flash memory, ranging from MSC1210Y2 MSC1210Y5. This flash memory configured such that used either program memory, data memory, both. When configured data memory, on-chip flash data memory accessed starting address 0400H-immediately after on-chip SRAM. example, MSC1210Y5 configured on-chip flash data memory, addresses 0000H through 03FFH will access on-chip extended SRAM while addresses 0400H through 0BFFH will access on-chip flash data memory. attempts read data memory with addresses 0C00H higher will result part attempting fetch that data off-chip from external data memory (see next section), except when internal SRAM configured Neumann type, which occupies from 8400H87FFH.
2.3.3
External Data Memory
MSC1210 capable addressing data memory, however, maximum that on-chip: SRAM flash data memory. additional data memory necessary, must added circuit external data memory. External data memory off-chip data memory that connected MSC1210 ports uses control pins ALE, These ports combined with these three control lines allow MSC1210 address external RAM. External data memory also used access "memory mapped devices," which devices that appear MSC1210 external data memory reality external components such LCDs, buttons, keypads, etc. Note: MSC1210 must only address 64kB RAM. expand beyond this limit requires programming hardware tricks. necessary this hand" because many compilers assemblers, while providing support programmers excess 64kB, support more than 64kB RAM. more than 64kB necessary, compiler must checked verify that excess supported. not, will necessary hand."
MSC1210 Memory Organization
Internal
Figure 2-2. MSC1210 Memory Register Bank.
Internal
shown Figure 2-2, MSC1210 bank bytes internal RAM. This internal found on-chip within fastest available also most flexible terms reading, writing, modifying contents. internal volatile, when MSC1210 powered contents this memory bank random. bytes internal subdivided shown memory Figure 2-2. first eight bytes (00H-07H) register bank manipulating certain SFRs, program choose register banks These alternative register banks located internal addresses through 1FH. Register banks described greater detail chapters sufficient know that they reside part internal RAM. memory also resides part internal RAM. memory will described more section 2.4.3, just keep mind that memory actually resides internal addresses through 2FH. bytes remaining internal RAM, from addresses through FFH, used user variables that need accessed frequently high-speed. This area also used microcontroller storage area operating stack. This fact limits MSC1210 stack because, illustrated memory Figure 2-2, area reserved stack only bytes-and usually less because these bytes have shared between stack user variables. Note: Internal addresses through accessed either direct addressing indirect addressing, whereas internal addresses through only accessed indirect addressing. This will discussed completely Chapter Addressing Modes.
Internal
2.4.1
Stack
stack "last first out" (LIFO) storage area that exists internal RAM. used MSC1210 store values that user program manually pushes onto stack, well store return addresses CALLs interrupt service routines (ISRs)-more these topics later. stack defined controlled called standard 8-bit SFR, holds value between that represents internal address current stack. value removed from stack, taken from internal address pointed will subsequently decremented value pushed onto stack, first incremented then value inserted internal address pointed initialized when MSC1210 first powered This means first value pushed onto stack placed internal address (07H second placed 09H, etc. Note: default, MSC1210 initializes stack pointer (SP) when microcontroller reset. This means that stack will start address expand upwards. using alternate register banks (banks stack pointer must initialized address above highest register bank being used. Otherwise, stack will overwrite alternate register banks. Similarly, using variables, usually good idea initialize stack pointer some value greater than ensure that variables protected from stack. Following more information about register banks memory.
2.4.2
Register Banks
MSC1210 uses eight registers, which used many instructions. These registers numbered from through (R0, generally used assist manipulating values moving data from memory location another. example, value accumulator, following assembly language instruction would executed:
A,R4
Thus, accumulator contains value contains value accumulator will contain value after this instruction executed. However, memory Figure illustrates, Register really part internal RAM. Specifically, address internal RAM. This seen bright green section memory map. above instruction, therefore, accomplishes same thing following operation:
A,04h
This instruction adds value found internal address value accumulator, leaving result accumulator. above instruction effectively accomplishes same thing previous instruction because really internal address 04H.
MSC1210 Memory Organization
Internal
watch out! memory shows, MSC1210 four distinct register banks. When MSC1210 first reset, register bank (addresses through 07H) used default. However, MSC1210 instructed alternate register banks (i.e., register banks this case, will longer same internal address 04H. example, program instructs 8052 register bank register synonymous with internal address 0CH. register bank selected, synonymous with 14H, register bank selected, synonymous with address 1CH. concept register banks adds great level flexibility 8052, especially when dealing with interrupts (see chapter Interrupts, details). However, always remember that register banks really reside first bytes internal RAM. Note: only first register bank (i.e. bank used, internal locations through used program use. register banks used, very careful about using addresses below avoid overwriting value registers from other register banks.
2.4.3
Memory
MSC1210, being communications control-oriented microcontroller that often deal with situations, gives ability access number variables directly with simple instructions set, clear, compare these bits. These variables either There variables available user, numbered through 7FH. user make these variables with commands such SETB CLR. example, number (hex) user would execute instruction:
SETB
important note that memory, like register banks section 2.4.2, really part internal RAM. fact, 128-bit variables occupy bytes internal from through 2FH. Thus, value written internal address 20H, bits through have been effectively set. That that instruction:
20h,#0FFh
equivalent instructions:
SETB SETB SETB SETB SETB SETB SETB SETB
Internal
shown, memory really type memory, just subset internal RAM. However, because MSC1210 provides special instructions access these bytes memory bit-by-bit basis, useful think separate type memory. Always keep mind that just subset internal RAM, that operations performed internal change values variables. Note: your program does variables, internal locations through your use. When using variables, very careful about using addresses from through 2FH, overwriting value your bits.
Note: default, MSC1210 initializes when microcontroller booted. This means that stack will start address expand upwards. using alternate register banks (banks must initialized address above highest register bank being used. Otherwise stack will overwrite alternate register banks. Similarly, using variables, usually good idea initialize some value greater than ensure that variables protected from stack. memory through user-defined functions their programs. memory above used access certain SFRs (see section 2.4.4) bit-by-bit basis. example, output lines P0.0 through P0.7 clear (0), turn P0.0 output line, either execute:
P0,#01h
execute:
SETB
Both these instructions accomplish same thing. However, using SETB command will turn P0.0 line without affecting status other output lines. command effectively turns other output lines that, some cases, acceptable. When dealing with addresses above, remember that bits refer bits corresponding SFRs that divisible eight. This complicated saying that bits through refer bits through 80H, bits through refer bits through 88H, bits through refer bits through 90H, etc.
MSC1210 Memory Organization
Internal
2.4.4
Special Function Register (SFR) Memory
SFRs areas memory that control specific functionality MSC1210. example, four SFRs permit access input/output lines (eight lines SFR) MSC1210. Another allows program read write MSC1210 serial port. Other SFRs allow user serial baud rate, control access timers, configure MSC1210 interrupt system. When programming, SFRs have illusion being internal memory. example, writing value internal location 50H, execute instruction:
50h,#01h
Similarly, writing value MSC1210 serial port, write this value SBUF SFR, which address 99H. Thus, write value serial port, execute instruction:
99h,#01h
shown, appears part internal memory. This case. When using this method memory access called direct addressing-more that soon), instruction that address through refers internal memory address; instruction with address through refers control register. Note: SFRs used control MSC1210 functions. Each specific purpose format that will discussed later. addresses above assigned SFRs. However, this area used additional memory, even given address been assigned SFR.
Note: Direct access addressing cannot used access internal addresses through because direct access addresses through refers SFRs. upper bytes internal must accessed using indirect addressing, which explained Chapter Addressing Modes.
2-10
Chapter
Special Function Registers (SFRs)
Chapter defines MSC1210 SFRs.
Topic
Page
Description Referencing SFRs Bit-Addressable SFRs Types Definitions
Special Function Registers (SFRs)
Description
Description
MSC1210 flexible microcontroller with relatively large number modes operation. Your program inspect and/or change operating mode MSC1210 manipulating values SFRs. SFRs accessed they were normal internal RAM. only difference that internal addressed direct mode with addresses through 7FH, whereas registers accessed range through FFH. Each address (80H-FFH) name. Table provides graphical presentation 8052's SFRs, their names, their address. Although address range through offers possible addresses, there addresses that assigned SFR, shown Table 3-1. Note: Reading unassigned will 00H, writing unassigned ignored.
Table 3-1. Names Addresses.
TCON SCON0 SCON1 T2CON EICON ADRESL SSCON HWPC0 PDCON SECINT SBUF1 RCAP2L ADRESM SUMR0 HWPC1 PASEL MSINT USEC MSECL MSECH RCAP2H ADRESH SUMR1 HDWVER ADCON0 SUMR2 Reserved ADCON1 SUMR3 Reserved ADCON2 ODAC FMCON ACLK HMSEC ADMUX ADCON3 LVDCON FTCON SRST WDTCON TMOD EXIF SBUF0 PWMCON BPCON P2DDRL DPL0 MPAGE SPICON PWMLOW P2DDRH DPH0 CADDR SPIDATA PWMHI P3DDRL P0DDRL P3DDRH DPL1 CDATA SPIRCON DPH1 MCON SPITCON P0DDRH SPISTART P1DDRL SPIEND AISTAT P1DDRH CKCON PCON
Referencing SFRs
Referencing SFRs
When writing code assembly language, SFRs referenced either their name their address. example, SBUF0 address (see Table 3-1). order write value SBUF assembly language, would written code
99h,#24h
This instruction moves value into address 99H. value range FFH, and, therefore, refers SFR. Furthermore, because refers SBUF0 SFR, this instruction will accomplish goal writing value SBUF0 SFR. Although above instruction certainly works, necessarily easy remember address each when writing software. Thus, 8052 assemblers allow name used code rather than numeric address. above instruction would more commonly written
SBUF0,#24h
instruction much easier read because obvious SBUF0 being accessed. assembler will automatically convert this numeric address assemble time. Note: Many SFRs that MSC1210 uses MSC1210-specific; only recognized original 8052. usually necessary include header file include file your program define additional SFRs supported MSC1210. Failing result assembler compiler reporting compile errors. Please refer documentation compiler assembler discover SFRs MSC1210 must defined development platform used.
3.2.1
Referencing Bits SFRs
Individual bits SFRs referenced ways. general convention name followed period number. example, SCON0.0 refers (the least significant bit) SCON0 SFR. SCON0.7 refers (the most significant bit) SCON0. These bits also have names: SCON0.0 SCON0.7 SM0_0. also acceptable refer bits their name, although this document they will usually referred SCON0.0 format, because that defines which which SFR.
Special Function Registers (SFRs)
Bit-Addressable SFRs
Bit-Addressable SFRs
SFRs that have addresses divisible eight (i.e., 80H, 88H, 90H, 98H, etc.) bit-addressable. This means that individual bits these SFRs cleared using SETB instruction. Note: SFRs whose names appear BOLD Table SFRs that accessed operations; these also happen first column SFRs left side chart. other SFRs cannot accessed using operations such SETB CLR.
Types
Four SFRs related ports. MSC1210 four ports eight bits, total lines. Whether given line high low, value read from line, controlled these SFRs. Refer Section 15.1 detailed control port usages. SFRs control operation configuration MSC1210. example, TCON controls timers SCON controls serial port. remaining SFRs thought auxiliary SFRs, sense that they directly configure MSC1210, obviously MSC1210 cannot operate without them. example, once serial port been configured using SCON0, program read write serial port using SBUF0 register.
Definitions
Definitions
This section will endeavor quickly overview each SFRs found chart Table 3-1. intention this section fully explain functionality each SFR-this information will covered separate chapters. This section just give general idea what each does. (Port Address 80H, Bit-Addressable): This input/output port Each this corresponds pins microcontroller. example, port P0.0, P0.7. Writing value this sets high level corresponding pin, whereas value brings level. Note: Even though MSC1210 four ports (P0, P3), hardware uses external external code memory (i.e., program stored external EPROM chip, external chips being used), used. This because MSC1210 uses ports address external memory (refer Section 15.1 detailed control port usages). Thus, external code memory being used, only ports (except P3.6 P3.7) used application. (Stack Pointer, Address 81H): This stack pointer microcontroller. This indicates where next value taken from stack will read from Internal RAM. value pushed onto stack, value will written address That say, holds value 07H, PUSH instruction will push value onto stack address 08H. This modified instructions that modify stack, such PUSH, POP, LCALL, RET, RETI, whenever interrupts triggered microcontroller. Note: SFR, startup, initialized 07H. This means stack will start will grow larger addresses internal RAM. necessary initialize program some other value alternate register banks and/or memorywill used because alternate register banks well user variables, occupy internal from addresses through 2FH. idea initialize first instruction every programs, unless there complete confidence that program will using register banks variables.
Special Function Registers (SFRs)
Definitions
DPL0/DPH0 (Data Pointer Low/High, Addresses 82H/83H): SFRs DPL0 DPH0 work together represent 16-bit value called Data Pointer data pointer used operations regarding external some instructions involving code memory. represent values from 0000H FFFFH through 65,535 decimal) because unsigned 2-byte integer value, Note: DPTR really DPH0 DPL0 taken together 16-bit value. reality, DPTR must almost always dealt with byte time. example, push DPTR onto stack, first push DPL0 then DPH0. possible simply push DPTR onto stack single value. Additionally, there instruction increment DPTR. When this instruction executed, bytes operated upon 16-bit value. However, there instruction which decrements DPTR. necessary decrement value DPTR, special code must written DPTR useful storage location occasional 16-bit values that being manipulated your program-especially those values need incremented frequently. DPL1/DPH1 (Data Pointer Low/High, Addresses 84H/85H): These SFRs work together form 16-bit value called Data Pointer purpose function same DPL0/DPH0 just described. existence distinct data pointers allows program quickly copy data from area memory another. (Data Pointer Select, Address 86H): this determines whether instructions that refer DPTR will Data Pointer Data Pointer clear, Data Pointer will used (DPH0/DPL0). set, Data Pointer will used (DPH1/DPL1). PCON (Power Control, Address 87H): This used control MSC1210 power control modes. Certain operation modes allow MSC1210 into type sleep mode that requires much less power. These modes operation controlled through PCON. Additionally, bits PCON used double effective baud rate MSC1210 primary serial port. confuse with PDCON, which controls peripheral power-down. TCON (Timer Control, Address 88H, Bit-Addressable): This used configure modify which timers 8052 operate. This controls whether each timers running stopped, contains flag indicate whether each timer overflowed. Additionally, some non-timer related bits located TCON SFR. These bits used configure which external interrupts activated also contain external interrupt flags that when external interrupt occurred. T2CON (Timer Control Address C8H, Bit-Addressable): This used configure control which timer operates. This only available 8052s, 8051s.
Definitions
TMOD (Timer Mode, Address 89H): This used configure mode operation each timers. Using this SFR, program configure each timer 16-bit timer, 8-bit auto-reload timer, 13-bit timer, separate timers. Additionally, timers configured only count when external activated count events that indicated external pin. TL0/TH0 (Timer Low/High, Addresses 8AH/8BH): These SFRs, taken together, represent timer Their exact behavior depends timer configured TMOD SFR, however, these timers always count when they increment value configurable. TL1/TH1 (Timer Low/High, Addresses 8CH/8DH): These SFRs, taken together, represent timer Their exact behavior depends timer configured TMOD SFR, however, these timers always count when they increment value configurable. CKCON (Clock Control, Address 8EH): This used MSC1210 provide with number timing controls that allow MSC1210 mimic standard 8052 timing, fully exploit high-speed nature MSC1210. This allows timers clocked rate 1/12th crystal frequency (just like 8052), clocked rate 1/4th crystal frequency such that clocks will incremented once every instruction cycle. Additionally, CKCON allows modify long MSC1210 takes access external data memory. (Memory Write Select, Address 8FH): This contains single (bit that enables writing program flash memory. this clear, MOVX @DPTR MOVX write data flash memory data SRAM memory. this set, MOVX @DPTR MOVX write program flash memory. TL2/TH2 (Timer Low/High, Addresses CCH/CDH): These SFRs, taken together, represent timer Their exact behavior depends timer configured T2CON SFR. RCAP2L/RCAP2H (Timer Capture Low/High, Addresses CAH/CBH): These SFRs, taken together, represent timer capture register. used reload value timer capture value timer under certain circumstances. exact purpose function these SFRs depends configuration T2CON. (Port Address 90H, Bit-Addressable): This input/output port Each this corresponds pins microcontroller. example, port P1.0, P1.7. Writing value this will high level corresponding pin, whereas value will bring level. EXIF (External Interrupt Flag, Address 91H): This contains interrupt trigger flags external interrupts through When these bits set, corresponding interrupt will triggered, long that interrupt enabled.
Special Function Registers (SFRs)
Definitions
MPAGE (Memory Page, Address 92H): This contains high byte address access when using MOVX instructions. normal 8052 requires high byte address written MSC1210, however, requires that byte written MPAGE SFR. CADDR (Configuration Address Register, Address 93H): This used read bytes Flash hardware configuration data. contents Flash configuration data address pointed this will loaded into CDATA (see following definition). CDATA (Configuration Data Register, Address 94H): contents Flash hardware configuration data pointed CADDR will readable this SFR. This read-only. Also note that attempting read Flash configuration data while executing program from flash memory will return invalid data. Internal Boot routines external program memory user routines access this memory correctly. MCON (Memory Configuration, Address 95H): This used control memory configuration. determines breakpoints, well where internal static will mapped memory. SCON0 (Serial Control Address 98H, Bit-Addressable): This used configure behavior MSC1210 primary onboard serial port. This controls baud rate serial port, whether serial port activated receive data, also contains flags that when byte successfully sent received. Note: MSC1210 onboard serial port, generally necessary initialize following SFRs: SCON0, TCON, TMOD. This because SCON0 controls serial port, most cases program must timers establish serial port baud rate. this case, necessary configure timer timer initializing TCON TMOD, T2CON. SBUF0 (Serial Buffer Address 99H): This used send receive data primary serial port. value written SBUF0 will sent serial port pin. Likewise, value which MSC1210 receives serial port will delivered your program SBUF0. other words, SBUF0 serves output port when written input port when read from. SPICON (SPI Control, Address 9AH): This controls basic configuration interface, including clocking rate, master/slave, polarity. Note that writing updating this will reset interface. SPIDATA (SPI Data, Address 9BH): This acts fashion similar SBUF0 that data written this will sent port incoming data received port will readable this address.
Definitions
SPIRCON (SPI Receive Control, Address 9CH): This dual-purpose: when read, will return number bytes currently receive buffer; when written, used clear receive buffer and/or indicate many characters should accumulate receive buffer before triggering interrupt. SPITCON (SPI Transmit Control, Address 9DH): This SFR, like SPIRCON, dual-purpose: when read, will return number bytes currently transmit buffer; when written, used clear transmit buffer and/or configure whether SCLK driver enabled (when master mode). SPISTART (SPI Buffer Start Address, Address 9EH): This indicates where buffer begins. value between must written this SFR, buffer situated internal upper bytes. SPIEND (SPI Buffer Address, Address 9FH): This indicates where buffer ends. must value between 255, must larger than SPISTART. (Port Address A0H, Bit-Addressable): This input/output port Each this corresponds pins microcontroller. example, port P2.0, P2.7. Writing value this will high level corresponding pin, whereas value will bring level. Note: Even though MSC1210 four ports (P0, P3), hardware uses external external code memory (i.e., program stored external EPROM chip, external chips being used), P3.6, P3.7 used. This because MSC1210 uses ports address external memory. Thus, external code memory being used, only (except P3.6 P3.7) available application I/O. PWMCON (PWM Control, Address A1H): This controls that generated automatically MSC1210. PWMLOW/PWMHIGH (PWM Low/High-Byte, Addresses A2H/A3H): This works together with PWMCON determine length shape PWM. This contains byte. (Pending Auxiliary Interrupt, Address A5H): This contains information regarding which various possible conditions triggered auxiliary interrupt. This normally used determine highest priority pending auxiliary interrupt. (Auxiliary Interrupt Enable, Address A6H): This enables disables various interrupts that were described previous paragraph regarding PAI. interrupts mentioned will only triggered they enabled this EICON) enabled. When read, provides status interrupt, regardless state bit.
Special Function Registers (SFRs)
Definitions
AISTAT (Auxiliary Interrupt Status, Address A7H): This read-only that will provide with current status enabled (not masked AIE) auxiliary interrupts. Those interrupts that have been disabled (masked) will available AISTAT. (Interrupt Enable, Address A8H): This used enable disable specific interrupts. seven bits used enable disable specific interrupts, whereas highest used enable disable interrupts. Therefore, high interrupts disabled regardless whether individual interrupt enabled setting lower bit. BPCON (Breakpoint Control, Address A9H): This controls whether breakpoints enabled and, they are, what source breakpoint BPL/BPH (Breakpoint Address Low/High Byte, Addresses AAH/ABH): These SFRs hold 16-bit address which breakpoint will triggered. Which breakpoint SFRs reference depends configuration MCON SFR. P0DDRL/P0DDRH (Port Data Direction Low/High Byte, Addresses ACH/ADH): These SFRs, together, configure state each port pin: standard 8051 (pull-up), CMOS output, ppen-drain output, input. P1DDRL/P1DDRH (Port Data Direction Low/High Byte, Addresses AEH/AFH): These SFRs, together, configure state each port pin: standard 8051 (pull-up), CMOS output, open-drain output, input. (Port Address B0H, Bit-Addressable): This input/output port Each this corresponds pins microcontroller. example, port P3.0, P3.7. Writing value this will high level corresponding pin, whereas value will bring level. P2DDRL/P2DDRH (Port Data Direction Low/High Byte, Addresses B1H/B2H): These SFRs, together, configure state each port pin: standard 8051 (pull-up), CMOS output, open-drain output, input. P3DDRL/P3DDRH (Port Data Direction Low/High Byte, Addresses B3H/B4H): These SFRs, together, configure state each port pin: standard 8051 (pull-up), CMOS output, open-drain output, input. (Interrupt Priority, Addresses B8H, Bit-Addressable): This used specify relative priority each interrupt. interrupt either priority high priority. interrupt only interrupt interrupts lower priority. example, configure MSC1210 that interrupts priority except serial interrupt, serial interrupt will always able interrupt system, even another interrupt currently executing. However, serial interrupt executing, other interrupt will able interrupt serial interrupt routine, because serial interrupt routine highest priority.
3-10
Definitions
SCON1 (Serial Control Address C0H, Bit-Addressable): This used configure behavior MSC1210 secondary onboard serial port. SCON1 controls baud rate serial port, whether serial port activated receive data, also contains flags that when byte successfully sent received. SBUF1 (Serial Buffer Address C1H): This used send receive data secondary onboard serial port. value written SBUF1 will sent serial port TXD1 pin. Likewise, value that MSC1210 receives serial port RXD1 will delivered user program SBUF1. other words, SBUF1 serves output port when written input port when read from. (Enable Wake-up, Address C6H): controls under what conditions MSC1210 will wake from idle mode: external interrupt, external interrupt, watchdog interrupt. Idle wakeup from Auxint controlled EICON SFR. (Program Status Word, Address D0H, Bit-Addressable): This used store number important bits that cleared instructions. contains carry flag, auxiliary carry flag, overflow flag, parity flag. Additionally, contains register bank select flags that used select which register banks currently selected. Note: When writing interrupt handler routine, very good idea always save stack restore when interrupt complete. Many instructions modify bits PSW. interrupt routine does ensure that same upon exit upon entry, program bound behave rather erratically unpredictably, will tricky debug because behavior make sense. OCL/OCM/OCH (Offset Calibration Low/Middle/High Byte, Addresses D1H/D2H/D3H): These three SFRs make 24-bit value that sets offset calibration. GCL/GCM/GCH (Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H): These three SFRs make 24-bit value that sets gain calibration. ADMUX (ADC Multiplexer Register, Address D7H): This selects positive input and/or selects temperature sensor option. EICON (Enable Interrupt Control, Address D8H, Bit-Addressable): This controls whether additional interrupts provided MSC1210 will cause interrupt occur when their corresponding conditions enabled. ADRESL/ADRESM/ADRESH (ADC Conversion Results, Addresses D9H/DAH/DBH): These three SFRs make 24-bit value which holds results conversion.
Special Function Registers (SFRs)
3-11
Definitions
ADCON0/ADCON1 (ADC Control Addresses DCH/DDH): These SFRs allow user program configure various aspects ADC. ADCON2/ADCON3 (ADC Controls Addresses DEH/DFH): These SFRs control decimation rate ADC; other words, they control frequency which sampled data will provided user program ADRES SFRs. (Accumulator, Addresses E0H, Bit-Addressable): accumulator most-used SFRs, because involved many instructions. accumulator resides E0H, which means instruction A,#20h same E0h,#20h. However, good idea first method because only requires bytes, whereas second option requires three bytes. SSCON (Summation/Shift Control, Address E1H): This controls what action taken regards summation registers SUMR0/SUMR1/SUMR2/SUMR3. SUMR0/SUMR1/SUMR2/SUMR3 (Summation Registers 0/1/2/3, Addresses E2H/E3H/E4H/E5H): These four registers, together, make 32-bit summation value ADC. Writing value least significant byte (SUMR0) will cause values other three summation registers added summation result. ODAC (Offset Register, Address E6H): This allows MSC1210 shift input half input range. LVDCON (Low-Voltage Detection Control, Address E7H): LVDCON configures low-voltage detection both analog digital supplies. both cases, LVDCON allows user program specify trip voltage below which low-voltage detection will triggered. (Extended Interrupt Enable, Address E8H, Bit-Addressable): This configures whether extended interrupts enabled, including watchdog external interrupts through HWPC0/HWPC1 (Hardware Product Code, Addresses E9H/EAH): These SFRs read-only provide user program with information regarding part number version much flash memory available part. FMCON (Flash Memory Control, Address EEH): This controls certain aspects flash memory, including page erase byte write operation. FRCM controls power saving flash memory read operations when MSC1210 running clock frequency. also includes that indicates whether flash memory currently idle busy with prior memory access operation.
3-12
Definitions
FTCON (Flash Memory Timing Control, Address EFH): This controls timing period flash memory, specifically writing erasing flash memory. period writing flash memeory determined USEC four bits FTCON, should produce write period 30µs 40µs. Meanwhile, period erasing flash memory determined MSECH/MSECL high four bits FTCON, should produce erase period 11ms. Register, Address F0H, Bit-Addressable): register used instructions: multiply divide. register also commonly used programmers auxiliary register store temporary values. PDCON (Power-Down Control, Address F1H): This allows user program power down specific on-chip peripherals that program need given moment, thus contributing more energy-efficient design. This allows user power down power generator, ADC, watchdog, system, system timer. PASEL (PSEN/ALE select, Address F2H): This allows user program that runs entirely internal flash memory control PSEN lines. PASEL allows configure both PSEN such that they either behave normally forced high low. this manner, PSEN used additional output lines they needed their normal functions. Note: When these lines used output lines, they should only drive light capacitive loads avoid triggering serial parallel flash programming modes. ACLK (Analog Clock, Address F6H): This used determine analog clock ADC. value ACLK, plus multiplied represents number instruction cycles between each analog sample. example, instruction cycle lasts 100ns ACLK then ACLK 100ns 1µs, multiplied would result sample being made every 64µs. sample every 64µs equivalent samples second. SRST (System Reset Register, Address F7H): Setting this then will cause system reset occur. This provides easy reset system software without need external circuitry. (Extended Interrupt Priority, Address F8H): This pnterrupt priority register extended interrupts that enabled/disabled using (E8H). SECINT (Seconds Timer Interrupt, Address F9H): This cause interrupt occur after specified number fractions second. Specifically, this cause interrupt every milliseconds every 12.8 seconds, assuming HMSEC value that represents 100ms. precise frequency which SECINT will cause interrupt depends system clock values MSECH, MSECL, HMSEC, SECINT SFRs.
Special Function Registers (SFRs)
3-13
Definitions
MSINT (Milliseconds Interrupt, Address FAH): This cause interrupt occur after specified number milliseconds. This assumes that millisecond registers generate cycle every millisecond. precise frequency which MSINT will cause interrupt depends system clock value MSECH, MSECL, MSINT SFRs. USEC (Microsecond Register, Address FBH): This divided into clock speed determine timing 1ms. This value used programming flash memory. value USEC, taken together with four bits FTCON, should produce timing 30µs 40µs, which used flash write operations. MSECL/MSECH (Millisecond Low/High Registers, Addresses FCH/FDH): These SFRs, together, used system determine long millisecond This value used erasing flash memory, millisecond interrupt, second interrupt, watchdog time. Although named Millisecond Low/High, clock speed value placed these registers will determine exact length time measured. HMSEC (Hundred Millisecond Clock, Address FEH): This used create 100ms clock based MSECL/MSECH SFRs. However, exact frequency generated this will depend system clock, value MSECL/MSECH, value placed this register. WDTCON (Watchdog Control, Address FFH): WDTCON used enable, disable, reset watchdog timer. Once enabled, this must periodically reset order prevent system from resetting.
3-14
Chapter
Basic Registers
Chapter describes basic register functions MSC1210 ADC.
Topic
Page
Description Accumulator Registers Register Program Counter (PC) Data Pointer (DPTR0/DPTR1) Stack Pointer (SP)
Basic Registers
Description
Description
number MSC1210 registers considered basic. Very little done without them detailed explanation each warranted make sure reader understands these registers before getting into more complicated areas development.
Accumulator
accumulator familiar concept when working with assembly language. accumulator, name suggests, used general register accumulate results large number instructions. hold 8-bit (1-byte) value most versatile register MSC1210, shear number instructions that make accumulator. More than half opcodes MSC1210 manipulate accumulator some way. example, adding numbers resulting will stored accumulator. Once value accumulator, continue processed, stored another register memory.
Registers
registers sets eight registers that named through These registers used auxiliary registers many operations. continue with previous example adding original number stored accumulator, whereas value stored say, register process addition, following command would executed:
A,R4
After executing this instruction, accumulator will contain value registers considered very important auxiliary, helper, registers. accumulator alone would very useful were these registers. registers also used store values temporarily. example, values together then subtract values this would
A,R3 A,R4 R5,A A,R1 A,R2 ;Move value into accumulator ;Add value ;Store resulting value temporarily ;Move value into accumulator ;Add value
SUBB A,R5 ;Subtract value (which contains
shown, used temporarily hold course, this most efficient calculate R4), does illustrate registers store values temporarily.
Register
mentioned previously, there four sets registers: register bank When MSC1210 first powered register bank (addresses through 07H) used default. this case, example, same internal address 04H. However, yours program instruct MSC1210 alternate register banks (i.e., register banks this case, will longer same internal address 04H. example, your program instructs MSC1210 register bank register will synonymous with internal address 0CH. selecting register bank synonymous with 14H, selecting register bank synonymous with address 1CH. concept register banks adds great level flexibility MSC1210, especially when dealing with interrupts (see Chapter Interrupts, details). However, always remember that register banks really reside first bytes internal RAM.
Register
register very similar accumulator sense that hold 8-bit (1-byte) value. register only used MSC1210 instructions: Therefore, quickly easily multiply divide another number, other number stored Aside from instructions, register often used another temporary storage register much like register.
Program Counter (PC)
program counter (PC) 2-byte address that tells MSC1210 where next instruction execute found memory. When MSC1210 initialized, always starts 0000H incremented each time instruction executed. important note that always incremented one. will incremented three these cases because some instructions require three bytes. special that there directly modify value. That say, something like 2430H cannot done. other hand, executing LJMP 2430H, same thing effectively accomplished. also interesting note that although value changed executing jump instruction, etc.), there read value That say, there 8052 "what address about execute?"
Basic Registers
Data Pointer (DPTR0/DPTR1)
Data Pointer (DPTR0/DPTR1)
data pointer (DPTR0/DPTR1) user-accessible 16-bit (2-byte) register MSC1210. accumulator, registers, register 1-byte values. just described 16-bit value, directly user-accessible working register. DPTR0/DPTR1, name suggests, used point data. They used number commands that allow MSC1210 access data code memory. When MSC1210 accesses external memory, accesses memory address indicated DPTR0/DPTR1. Although DPTR0/DPTR1 most often used point data external memory code memory, many developers take advantage fact that only true 16-bit register available. often used store 2-byte values that have nothing with memory locations. DPTR0 DPTR1 selected DPS.
Stack Pointer (SP)
stack pointer (SP), like registers except DPTR hold 8-bit (1-byte) value. used indicate where next value removed from stack should taken from. When value pushed onto stack, MSC1210 first increments value then stores value resulting memory location. When value popped stack, MSC1210 returns value from memory location indicated then decrements value This order operation important. When MSC1210 initialized, will initialized 07H. value immediately pushed onto stack, value will stored internal address 08H. This makes sense, taking into account what mentioned paragraphs above. First MSC1210 will increment value (from 08H) then will store pushed value that memory address (08H). modified directly MSC1210 instructions: PUSH, POP, ACALL, LCALL, RET, RETI. also used intrinsically whenever interrupt triggered (more interrupts Chapter 10-do worry about them now).
Chapter
Addressing Modes
Chapter describes various addressing modes MSC1210.
Topic
Page
Description Immediate Addressing Direct Addressing Indirect Addressing External Direct External Indirect Code Indirect
Addressing Modes
Description
Description
case with microcomputers from PDP-8 onwards, MSC1210 uses several memory addressing modes. addressing mode refers accessing (addressing) given memory location data value. summary, addressing modes listed Table with example each.
Table 5-1. MSC1210 Addressing Modes.
Mode Immediate Addressing Direct Addressing Indirect Addressing External Direct External Indirect Code Indirect Example A,#20h A,30h A,@R0 MOVX A,@DPTR MOVX A,@R0 MOVC A,@A+DPTR
Each these addressing modes provides important flexibility programmer.
Immediate Addressing
Immediate addressing named because value stored memory immediately follows opcode memory. That say, instruction itself dictates what value will stored memory. example:
A,#20h
This instruction uses immediate addressing because accumulator will loaded with value that immediately follows; this case (hex). Immediate addressing very fast because value loaded included instruction. However, because value loaded fixed compile time, very flexible. used load same, known value every time instruction executes.
Direct Addressing
Direct Addressing
Direct addressing named because value stored memory obtained directly retrieving from another memory location. example:
A,30h
This instruction will read data internal address (hex) store accumulator (A). Direct addressing generally fast because, although value loaded included instruction, quickly accessible being stored MSC1210 internal RAM. also much more flexible than immediate addressing because value loaded whatever found given address, which change. Additionally, important note that when using direct addressing, instruction that refers address between referring internal RAM. instruction that refers address between referring control registers that control MSC1210 itself. obvious question that arise direct addressing address from through refers SFRs, acess upper bytes internal that available with MSC1210?" answer cannot accessed using direct addressing. stated, address through directly referred refers SFR. However, upper bytes MSC1210 accessed using next addressing mode, indirect addressing.
Addressing Modes
Indirect Addressing
Indirect Addressing
Indirect addressing very powerful addressing mode that many cases provides exceptional level flexibility. Indirect addressing also only access upper bytes Internal found 8052. Indirect addressing appears follows:
A,@R0
This instruction causes MSC1210 analyze value register. MSC1210 then loads accumulator with value from Internal that found address indicated example, suppose holds value internal address holds value 67H. When above instruction executed, 8052 checks value MSC1210 gets value internal address (which holds 67H) stores accumulator because holds 40H. Thus, accumulator ends holding 67H. Indirect addressing always refers internal RAM; never refers SFR. prior example, mentioned that used write value serial port. Therefore, think that following code would valid solution write value serial port:
R0,#99h ;Load address serial port @R0,#01h ;Send serial port WRONG!!
This valid. These instructions write value internal address MSC1210 because indirect addressing always refers internal RAM.
External Direct Addressing
External Direct Addressing
External memory accessed using suite instructions that external direct addressing. referred external direct because appears direct addressing, used access external memory rather than internal memory. There only commands that external direct addressing mode:
MOVX A,@DPTR MOVX @DPTR,A
see, both commands DPTR. these instructions, DPTR must first loaded with address external memory that wish read write. Once DPTR holds correct external memory address, first command moves contents that external memory address into accumulator. example, want read contents external address 1516H, execute instructions:
DPTR,#1516h ;Select external address read MOVX A,@DPTR ;Move contents external into ;accumulator
second command does opposite: allows write value accumulator external memory address pointed DPTR. example, want write contents accumulator external address 1516H, execute instructions:
DPTR,#1516h ;Select external address read MOVX @DPTR,A ;Move contents external into ;accumulator
MOVX data flash memory writes data flash memory location. clear flash content, page erase needed.
Addressing Modes
External Indirect Addressing
External Indirect Addressing
External memory also accessed using form indirect addressing called external indirect. This form addressing usually only used relatively small projects that have very small amount external RAM. example this addressing mode MOVX @R0,A Once again, value first read value accumulator written that address external RAM, internal extended SRAM, internal flash data memory. High address A8A15 provided MPAGE because value only through FFH-that A0A7 previous memories.
Code Indirect Adressing
last addressing mode called code indirect offers additional 8052 instructions that allow access program code itself. This useful accessing data tables, strings, etc. instructions are:
MOVC A,@A+DPTR MOVC A,@A+PC
example, want access data stored code memory address 2021H, execute instructions:
CLRA MOVC A,@A+DPTR DPTR,#2021h ;Set DPTR 2021h ;Clear accumulator (set 00h) ;Read code memory ;the accumulator address 2021h into
MOVC A,@A+DPTR instruction moves value contained code memory address that pointed adding DPTR accumulator. write flash code memory, MXWS MOVX will write flash code memory memory write protected harware configuration bits). same operation used perform flash page erase. section 1.5, Flash Memory, more details.
Chapter
Program Flow
Chapter describes program flow MSC1210 ADC.
Topic
Page
Description Conditional Branching Direct Jumps Direct Calls Returns From Routines Interrupts
Program Flow
Description
Description
When MSC1210 first initialized cleared 0000H. part then begins execute instructions sequentially memory unless program instruction causes otherwise altered. There various instructions that modify value specifically, conditional branching instructions, direct jumps calls, returns from subroutines. Additionally, interrupts (when enabled) cause program flow deviate from otherwise sequential scheme.
Conditional Branching
MSC1210 contains suite instructions that, group, referred "conditional branching" instructions. These instructions cause program execution follow non-sequential path certain condition true. instruction example. This instruction means jump set. example instruction might
45h,HELLO HELLO:.
this case, MSC1210 will analyze contents 45H. set, program execution will jump immediately label HELLO, skipping instruction. set, conditional branch fails program execution continues usual with instruction that follows. Conditional branching really fundamental building block program logic because decisions accomplished using conditional branching. Conditional branching thought THEN" structure assembly language. Note: Your program only branch instructions located within bytes prior bytes after address that follows conditional branch instruction. This means that above example, label HELLO must within -128 bytes +127 bytes memory address that contains conditional branching instruction.
Direct Jumps
While conditional branching extremely important, often necessary make direct branch given memory location without basing given logical decision. This equivalent saying GOTO Basic. this case, program flow will continue given memory address without considering conditions. This accomplished with MSC1210 using direct jump call instructions. illustrated last paragraph, this suite instructions causes program flow change unconditionally.
Direct Jumps
Consider example:
LJMP NEW_ADDRESS NEW_ADDRESS:
LJMP instruction this example means "Long Jump." When MSC1210 executes this instruction, loaded with address NEW_ADDRESS program execution continues sequentially from there. obvious difference between Direct Jump Call instructions conditional branching that with Direct Jumps Calls, program flow always changes; with conditional branching, program flow only changes certain condition true. worth mentioning that, aside from LJMP, there other instructions that cause direct jump occur: SJMP AJMP commands. Functionally, these commands perform exact same function LJMP command-that say, they always cause program flow continue address indicated command. However, these instructions differ from LJMP that they capable jumping address. They both have limitations range jumps. SJMP command, like conditional branching instructions, only jump address within -128/+127 bytes address following SJMP command. AJMP command only jump address that same block memory byte following AJMP command. That say, AJMP command code memory location 650H, only jump addresses 0000H through 07FFH through 2047, decimal). "why SJMP AJMP commands, which have restrictions they jump, they same thing LJMP command that jump anywhere memory?" answer simple: LJMP command requires three bytes code memory, whereas both SJMP AJMP commands require only two. When developing applications that have memory restrictions, quite memory saved using 2-byte AJMP/SJMP instructions instead 3-byte instruction. Note: Some assemblers will above conversion automatically. That they will automatically change LJMPs SJMPs whenever possible. This nifty very powerful capability that necessity assembler, planning develop many projects that have relatively tight memory restrictions.
Program Flow
Direct Calls
Direct Calls
Another operation that will familiar seasoned programmers LCALL instruction. This similar "GOSUB" command Basic. When MSC1210 executes LCALL instruction, immediately pushes current onto stack then continues executing code address indicated LCALL instruction.
Returns From Routines
Another structure that cause program flow change "Return from Subroutine" instruction, known Assembly language. instruction, when executed, returns address following instruction that called given subroutine. More accurately, returns address that stored stack. command direct sense that always changes program flow without basing condition, variable sense that where program flow continues different each time instruction executed, depending where subroutine originally called from.
Interrupts
interrupt special feature that allows MSC1210 break from normal program flow execute immediate task, providing illusion multitasking. word interrupt often substituted with word event. interrupt triggered whenever corresponding event occurs. When event occurs, MSC1210 temporarily puts normal execution program hold executes special section code referred interrupt handler. interrupt handler performs whatever special functions required handle event then returns control MSC1210, which point program execution continues never been interrupted. topic interrupts somewhat tricky very important. that reason, Chapter dedicated topic.
Chapter
System Timing
Chapter describes system timing MSC1210 ADC.
Topic
Page
Description System Timers Startup Timing
System Timing
Description
Description
order understand-and better make of-the MSC1210, necessary understand some underlying information concerning timing. MSC1210 operates with timing derived from external crystal clock signal generated some other system. crystal mechanical oscillator that allows electronic oscillator very precisely known frequency. find crystals virtually frequency depending application requirements. When using MSC1210, common crystal frequency 11.0592MHz baud rate accuracy considerations. Microcontrollers (and many other electrical systems) their oscillators synchronize operations. MSC1210 uses crystal clock precisely that-to synchronize internal operation. MSC1210 operates using what called instruction cycles. single instruction cycle minimum amount time which single MSC1210 instruction executed, although many instructions take multiple cycles. Note: standard 8052 executes instruction clock cycles rather than shown Figure 7-1. This means that, with program changes, MSC1210 will execute code approximately three times faster than same program under traditional 8052. also means that programs written standard 8052 have modified they depend certain instructions executing certain amount time. fact that MSC1210 executes instruction four cycles configurable.
Figure 7-1. Standard 8051 Timing.
TAL1
Description
instruction cycle reality, four clock cycles. That say, instruction takes instruction cycle execute, will take four clocks from crystal oscillator execute. Using maximum crystal frequency 33MHz, crystal oscillates times second. instruction cycle being four clock cycles, MSC1210 execute following number instruction cycles second: This means that MSC1210 execute single-cycle instructions second. important emphasize that instructions execute same amount time. fastest instructions require instruction cycle (four clock cycles), many others require instruction cycles (eight clock cycles), slow math operations require four instruction cycles clock cycles). instructions requiring different amounts time execute, very obvious question comes mind: keep track time time-critical application have reference time outside world? Luckily, MSC1210 includes timers that allow time events with high precision, which topic next chapter.
System Timing
System Timers
System Timers
addition standard 8052 timers described Chapter MSC1210 includes following system timers, both which capable triggering auxiliary interrupt (for more interrupts, chapter 10):
Microseconds Timer: USEC (FBH) SFR, used configure
flash writing timing also used module.
Milliseconds Timer: MSECH (FDH) MSECL (FCH) SFRs,
used base configure flash erase timing, well milliseconds interrupt, also base seconds interrupt watchdog timer. MSC1210 timers illustrated Figure 7-2. Clock signal that comes from oscillator other timing input. This signal used input part's timing logic, including following timing circuits:
(chapter PWM/Tone generation (chapter 11). Flash erase/write (chapter 15). Milliseconds/Seconds/Watchdog interrupts (chapter 14). conversion timing (chapter Standard 8052 timers (chapter
System Timers
Figure 7-2. MSC1210 Timing Chain Clock Control
Figure 7-3. SPI/PWM/Flash Write Timing
System Timing
System Timers
7.2.1
Microseconds Timer
microseconds timer used MSC1210 order establish clock. This clock, turn, used flash memory establish timing flash writes, well module. USEC (FBH) should value such that system clock divided value this SFR, plus one, generates clock. example, given system clock 12.000MHz, USEC should 000/1 Therefore, 12.000MHz system clock, USEC should generate clock. reality, USEC value that produces clock that something other than 1µs. This works fine long other timers that depend USEC adjusted accordingly.
7.2.1.1
Clock module microseconds timer input clock. clearing SPDSEL (PWMCON.3), input clock module will microsecond timer. This creates 1MHz input clock module, assuming microseconds timer correctly configured produce clock. this case, microseconds clock further divided value contained PWMHI/PWMLOW SFRs.
7.2.1.2
Flash Write Timing microseconds clock further used establish flash memory write timing. flash write timing uses microsecond clock input clock then further divides value FTCON[3:0] generate flash write clock. flash write clock must between 30µs 40µs flash writing operate properly. Specifically, FTCON[3:0] multiplied five, multiplied frequency microsecond clock, should produce appropriate flash write timer (30µs 40µs). Assuming USEC generate correct clock, FTCON[3:0] should FTCON[3:0] then 35µs, which right middle expected range.
7.2.2
Milliseconds Timer
milliseconds timer used MSC1210 order establish millisecond clock. This clock, turn, used base establishing flash erase timing, milliseconds interrupt, seconds interrupt, establish timing watchdog timer.
System Timers
Figure 7-4. System Timing Interrupt Control
MSECH (FDH) MSECL (FCH) SFRs should value such that system clock divided value these SFRs, plus one, generates clock. example, given system clock 12.000MHz, MSECH/MSECL should 1000 999. Thus, 12.000MHz system clock, MSECH/MSECL should generate clock. reality, MSECH/MSECL SFRs value that produces clock that something other than 1ms. This works fine, long other timers that depend MSECH/MSECL adjusted accordingly. 7.2.2.1 Milliseconds Auxiliary Interrupt milliseconds interrupt auxiliary interrupts that used user program. milliseconds auxiliary interrupt enabled setting EMSEC (AIE.4) enabling auxiliary interrupts (EICON.5) bit. frequency which milliseconds interrupt will triggered controlled value written MSINT (FAH) SFR. When enabled, millisecond auxiliary interrupt will triggered after MSINT 1ms, assuming that MSECH/MSECL have been configured produce correct milliseconds clock. value written MSINT value between 127, meaning that milliseconds interrupt triggered every 128ms (assuming correct milliseconds clock). example, given accurate milliseconds clock, setting MSINT would produce milliseconds auxiliary interrupt every 6ms. MSINT, when written, indicates whether MSINT value being written should written immediately, should written after current MSINT count expired. set, MSINT will immediately updated with value; clear, MSINT will updated with value soon current milliseconds count expired.
System Timing
System Timers
7.2.2.2
Hundred Millisecond Clock hundred millisecond clock used MSC1210 order establish 10Hz clock. This clock directly outputted MSC1210; used input into seconds auxiliary interrupt also used watchdog timer. 100ms clock uses output millisecond clock (MSECH/ MSECL) input, correct operation assumes that millisecond clock been value that fact generates millisecond clock. HMSEC (FEH) used indicate many millisecond clocks amount 100ms (1/10th second), less Therefore, assuming millisecond clock correctly configured generate 1kHz clock, HMSEC would (decimal) order generate accurate, 100ms clock.
7.2.2.3
Seconds Auxiliary Interrupt seconds auxiliary interrupt auxiliary interrupts that used user program. seconds auxiliary interrupt enabled setting ESEC (AIE.7) enabling auxiliary interrupts (EICON.5) bit. frequency which seconds interrupt will triggered controlled value written SECINT (F9H) SFR. When enabled, seconds auxiliary interrupt will triggered after SECINT 100ms, assuming MSECH/MSECL HMSEC SFRs have been configured produce correct 100ms clock. value written SECINT between 127, meaning that milliseconds interrupt triggered every 100ms 12.8 seconds (assuming correct 100ms clock). example, given accurate 100ms clock, setting SECINT would produce seconds auxiliary interrupt every seconds. SECINT, when written, indicates whether SECINT value being written should written immediately, should written after current SECINT count expired. set, SECINT will immediately updated with value; clear, SECINT will updated with value soon current seconds count expired.
7.2.2.4
Watchdog Timer functioning watchdog timer fully described section 14.3. However, important keep mind that watchdog timer dependent 100ms timer. length watchdog timer directly dependent 100ms timer being configured reasonable value because watchdog timer frequency configured WDTCON (FFH) using units HMSEC.
Startup Timing
Startup Timing
When power turned reset initiated, power-on delay circuit implemented with 17-bit counter guarantee that power supply reached certain level, oscillator stable. delay introduced this counter 24MHz System clock: (217 (1/24) 10-6 0.005461s 1MHz System clock: (217 10-6 0.131071s
7.3.1
Normal-Mode Power-On Reset Timing
sampled during power-on reset code security purposes. PSEN internally pulled during reset serial parallel flash programming mode detection. After reset sequence, PSEN signals driven CPU, internal pull resistors removed saving power.
7.3.2
Flash Programming Mode Power-On Reset Timing
ignored serial parallel flash programming operations.
Figure 7-5. Reset Timing
Figure 7-6. Parallel Flash Programming Power-On Timing ignored)
System Timing
Startup Timing
Figure 7-7. Serial Flash Programming Power-On Timing ignored)
Table 7-1. Signal Definitions Reset Timing Diagrams
Symbol trrd trfd
Notes:
Parameter Width rise PSEN internal pull high falling PSEN start Input signal falling setup time falling input signal hold time
tCLK Xtal clock period.
tCLK(1) tCLK(1) (217+512) tCLK(1)
(217+512) tCLK(1)
Unit
7-10
Chapter
Timers
Chapter describes timers MSC1210 ADC.
Topic
Page
Description Does Timer Count? Using Timers Measure Time Using Timers Event Counters 8-12 Using Timer 8-13
Timers
Description
Description
MSC1210 comes equipped with three standard timer/counters, which controlled, set, read, configured individually. timer/counters have three general functions: Keeping time and/or calculating amount time between events Counting events themselves Generating baud rates serial port uses three timer/counters distinct, will talk about each them separately. first uses will discussed this chapter, whereas timers baud rate generation will discussed Chapter Serial Communication.
Does Timer Count?
answer this question very simple: timer always counts does matter whether timer being used timer, counter, baud rate generator. timer always incremented microcontroller.
Using Timers Measure Time
Obviously, primary uses timers measure time. will discuss this timers first will subsequently discuss timers count events. When timer used measure time, also called interval timer, because measuring time interval between events.
8.3.1
Long Does Timer Take Count?
Before continuing, worth mentioning that when timer interval timer mode opposed event counter mode) correctly configured, timer will increment each instruction cycle. Therefore, running timer MSC1210 will incremented: times second However, maintain compatibility with existing 8052 code, default mode MSC1210 timers increment every three instruction cycles (i.e., operate timer increments every clocks). Thus, running timer configured incremented: times second Using first option, which increments timer every four clocks, allows user program obtain three times higher precision than would available default mode just explained. Whether timers incremented every four clocks controlled CKCON SFR.
Using Timers Measure Time
individual bits TMOD have following functions:
Reset Value
(bit 5)-Timer Clock Select. This controls division system clock that drives Timer This effect when timer baud rate generator clock output modes. Clearing this maintains 80C32 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. (bit 4)-Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. (bit 3)-Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. MD2, MD1, (bits 2-0)-Stretch MOVX Select 2-0. These bits select time which external MOVX cycles stretched. This allows slower memory peripherals accessed without using ports manual software intervention. strobe will stretched specified interval, which will transparent software except increased time execute MOVX instruction. internal MOVX instructions devices containing MOVX SRAM performed instruction cycle rate.
Strobe Width (SYS CLKs) Strobe Width (µs) 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
Stretch Value
MOVX Duration Instruction Cycles Instruction Cycles (default) Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles
Timers
Using Timers Measure Time
Unlike instructions-some which require instruction cycle, others others 4-the timers consistent. They will always incremented once every four) clocks. Therefore, timer counted from calculate: 0.020 seconds (fosc/12) 0.007 seconds (fosc/4) trade using fosc/12 fosc/4 clock source code compatibility resolution. With 33MHz external clock, resolution fosc/12 364ns increment, resolution fosc/4 121ns increment. Thus, have system that measures time. need review control timers initialize them provide with information needed.
8.3.2
Timer SFRs
mentioned before, MSC1210 three standard timers. these timers work essentially same way. timer Timer other Timer timers share SFRs (TMOD TCON) which control timers, each timer also SFRs dedicated solely maintaining value timer itself (TH0/TL0 TH1/TL1). third timer (Timer functions somewhat differently will explained separately. SFRs used control manipulate first timers presented Table 8-1.
Table 8-1. Timer Conrol SFRs.
Name TCON TMOD Description Timer high byte Timer byte Timer high byte Timer byte Timer control Timer mode Address Addressable?
Timer SFRs dedicated exclusively itself: TL0. byte value timer, while high byte value timer. That say, when Timer value both will contain When Timer value 1000, will hold high byte value decimal) will contain byte value (232 decimal). Reviewing low/high byte notation, recall that must multiply high byte byte calculate final value. this case: (TH0 256) 1000 256) 1000 Timer works exact same way, SFRs TL1.
Using Timers Measure Time
apparent that maximum value timer have 65,535 because there only bytes devoted value each timer. timer contains value 65,535 subsequently incremented, will reset-or overflow-back
8.3.3
TMOD
TMOD used control mode operation both timers. Each gives microcontroller specific information concerning timer. high four bits (bits through relate Timer whereas four bits (bits through perform exact same functions, Timer individual bits TMOD have following functions:
TIMER TIMER GATE Reset Value
GATE
GATE (bit 7)-Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT1. Timer will clock only when INT1 (bit 6)-Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.6, 88H) (bits 5-4)-Timer Mode Select. These bits select operating mode Timer
Mode Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto-reload. Mode Timer halted, holds count.
GATE (bit 3)-Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT0 (software control). Timer will clock only when INT0 (hardware control). (bit 2)-Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.4, 88H) (bits 1-0) Timer Mode Select. These bits select operating mode Timer
Mode Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto-reload. Mode Timer halted, holds count.
Timers
Using Timers Measure Time
shown previous chart, four bits (two each timer) used specify mode operation. modes operation shown Table 8-2.
Table 8-2. Timer Modes Usage
TxM1 TxM0 Timer Mode Description Timer Mode 13-bit timer/counter 16-bit timer/counter 8-bit timer/counter with auto-reload 8-bit counters (split timer mode) Timer Timer
TMOD.GATE controls gating timer/counter. TMOD.GATE cleared, timer/counter increments only TCON.TRx set. TMOD.GATE set, timer/counter increments only TCON.TRx corresponding INTx held high. This feature used pulse width measurements. TMOD.CT selects counter timer operation. TMOD.CT cleared, timer/counter register incremented either fosc/4 fosc/12 (based state CKCON.TxM TMOD.CT set, timer/counter register incremented pin. 8.3.3.1 13-Bit Time Mode (mode Timer mode 13-bit timer. This relic that kept around 8052 (and subsequently MSC1210) maintain compatibility with predecessor, 8048. 13-bit timer mode normally used development. this mode, timer/counter uses five bits register eight bits register 13-bit register. Therefore, upper three bits must masked they used software. When timer/counter rolls over transition from 01FFFH, timer/counter interrupt flag (TCON.TFx).
Figure 8-1. Timer Block Diagram Modes
Using Timers Measure Time
When timer 13-bit mode, will count from When incremented from will roll over overflow into THx, thus incrementing Therfore, only bits timer bytes being used: bits TLx, bits THx. This also means timer only contain 8192 values. 13-bit timer overflows back zero 8192 instruction cycles later. There very little reason this mode only mentioned there will surprise ever analyzing archaic code that been passed down through generations. 8.3.3.2 16-Bit Time Mode (mode Mode operates same manner mode except Timer Timer configured 16-bit timer/counter. timer/counter uses bits both register register 16-bit register. When timer/counter rolls over transition from 0FFFFH, timer/counter interrupt flag (TCON.TFx). Timer mode 16-bit timer. This very commonly used mode. functions just like 13-bit mode, except that bits used. incremented from 255. When incremented from 255, resets causes incremented timer contain distinct values because this full 16-bit timer. 16-bit timer will overflow back after machine cycles. 8.3.3.3 8-Bit Auto-Reload Time Mode (mode Timer mode 8-bit auto-reload mode. When timer mode holds reload value timer itself. starts counting When reaches subsequently incremented instead resetting case modes will reset value stored THx. example, holds value holds value FEH. Table shows what would occur values viewed machine cycles.
Table 8-3. Example 8-Bit Auto-Reload
Instruction Cycle Value Value
Timers
Using Timers Measure Time
shown, value never changed. fact, when mode used, almost always known value that constantly incremented. initialized once, then left unchanged. benefit auto-reload mode that, perhaps, timer need always have value from 255. When using mode code would have checked timer overflowed and, timer reset 200. This takes precious amounts execution time check value and/or reload When mode used, microcontroller takes care this.

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