MC92610 Quad SerDes Design Verification Board User's Guide Device
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MC92610DVBUG 3/2004 Rev.
MC92610 Quad SerDes Design Verification Board User's Guide
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Contents
Paragraph Section Number Title Chapter General Information
Contents
Page Number
Introduction. Features Specifications. Block Diagram Board Components Abbreviation List Related Documentation. Contact Information Chapter Hardware Preparation Installation
2.3.1 2.3.2 2.3.3 2.4.1 2.4.2 2.4.3 2.5.1 2.5.1.1 2.5.1.2 2.5.2 2.5.3 2.5.4
Unpacking Instructions MC92610DVB Package Contents Hardware Preparation Setting Power Supply Voltage Regulators Setting Voltage Regulators. HSTL Voltage Reference Regulator Reference Clock Source. Using Onboard Oscillator External Reference Clock Source 3.3V_CLK_OUTn Connectors Interface Components Parallel Inputs Outputs. Parallel Inputs Parallel Outputs +VDDQ Ground (GND) Access Connections. Receiver Interface Status LEDs. Serial Inputs Outputs. Special Test Connection. Test Traces
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Contents
Paragraph Number Title Chapter Laboratory Equipment Quick Setup Evaluation 3.2.1 3.2.1.1 3.2.1.2 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 Recommended Laboratory Equipment Quick Setup Data-Eye Diagram Quick Setup Data-Eye Generation Observation Equipment Setup. Parallel Input Connections. Basic Observation-Test Procedure. Quick Setup Error Rate Checking. Equipment Setup. Parallel Connections. Quick Setup BERC Test Procedure 3-10 Chapter Test Setups 4.1.1 4.1.2 4.2.1 4.2.2 4.2.3 4.2.4 Serial Link Verification Using Serial Error Rate Tester (BERT) Test Setup Double Data Rate Link Multiplex Modes. Test Setup Double Data Rate Link Multiplex Modes Jitter Testing. Jitter Test System Calibration Reference Clock Jitter Transfer Test. Reference Clock Jitter Tolerance Test Data Jitter Tolerance Test. Appendix Connector Signals A.1.1 A.1.2 Input: (0.100") Connectors. Control Signal Input Connectors Transmitter Parallel Data Input Connectors Output: (0.100") Connectors TEST_0 Connector Appendix Parts List Design Verification Board Parts List .B-1 Page Number
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Contents
Paragraph Number Title Appendix Crystal Oscillator Vendors Oscillator Vendors.C-1 Appendix Prescaler Jitter Measurement Page Number
Divide-by-xx Prescaler Description Prescaler Components. Appendix Revision History
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Chapter General Information
Introduction
This user's guide describes MC92610DVB design verification board, Rev. higher. should read conjunction with MC92610 Quad 3.125 Gbaud SerDes User's Manual. design verification board (DVB) facilitates full evaluation MC92610 Quad 3.125 Gbaud SerDes. intended evaluation testing purposes only. Motorola does guarantee performance production environment. This board designed used with laboratory equipment (pattern generators, data analyzers, BERT, scopes, connected other evaluation boards. Access MC92610 device (verification chip) through connectors each pin, allow complete in-depth `design verification' testing chip design. This allows user check features/functions MC92610 quad device. four parallel data input ports, configuration/control signal pins, accessed through common 0.100" male connectors (headers). parallel data output ports accessed through 0.100" connectors. JTAG port signals also accessed with separate connectors. MC92610 high-speed serial receivers transmitters accessed through coaxial connectors signal integrity measurements. single 5.0-V power source required operation. necessary voltages generated regulators onboard. reference clock MC92610 chip provided using either external clock onboard crystal oscillator. Clock drivers provide additional clock signals triggering analyzer instrumentation scopes.
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Features
Features
single external 5.0-V onboard regulators supply +3.3, +1.8, +1.5 HSTL voltage reference power onboard circuitry. Reference clock source 156.25-MHz crystal oscillator external clock source Parallel data interfaces accessible through standard 0.100", connectors data generators analyzers. Full-duplex differential data links accessible through connectors pairs test traces with connections facilitate measurements characteristic impedance representative board traces. Connector provided JTAG test access port
functional, physical, performance features MC92610DVB follows:
Specifications
Table 1-1. MC92610DVB Design Verification Board Specifications
Characteristics Specifications Rev. higher typical 0.15 0.15 MAPBGA 0°-30°C FR-4 Height Width Thickness 14.8", 12.3", 0.1", Three ground planes, split power plane, signal routing layers, bottom component layers with some additional signal routing
MC92610DVB design verification board specifications provided Table 1-1.
Board revision External power supply Support circuit regulator MC92610 core link regulator Interface (VDDQ) regulator MC92610 package Operating temperature Material Dimensions
Conducting layers
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Block Diagram
Block Diagram
3.3V_CLK_OUT5 CLK_IN X-TAL MC100ES 8111 3.3V_CLK_OUT4 3.3V_CLK_OUT3 3.3V_CLK_OUT6
Figure shows MC92610DVB design verification board block diagram.
+1.5 V/GND 0.100" Connector
MPC9456 R12V
1.5V_CLK_OUT1 1.5V_CLK_OUT2 +3.3 +1.5 TST1 TST2 Vertical Test Traces TST5 TST6 0.100" Connectors PG13 2x10, 0.100" Connectors
+3.3-V Regulator R22V1 +1.5-/+1.8-V Regulator
R22V +1.8-V Regulator +1.8
Ctrl/Tst
XMIT_C
XMIT_D RLINK_D1
RCVR Status LEDs
RECV_D
XLINK_D1 RLINK_C1
RECV_C RECV_B RECV_A
MC92610 Quad 3.125 Gbaud SerDes
XLINK_C1 RLINK_B1 XLINK_B1 RLINK_A1 XLINK_A1
HSTL_VREF XMIT_A HSTL_VREF R22V3 TST3 TST4 Horizontal Test Traces TST7 TST8 PG11 PG10 0.100" Connectors XMIT_B Control
Pairs Primary Redundant Links
Figure 1-1. MC92610DVB Design Verification Board Block Diagram
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Board Components
Board Components
Table list major components MC92610DVB design verification board. complete parts listing found Appendix "Parts List."
Table 1-2. Major Board Components
Component MC92610VF 0.100" connectors 0.100" connectors 0.100" connectors Description Motorola Quad 3.125 Gbaud SerDes PG1-PG11, PG13 provide access parallel inputs control signals. LA1-LA4 provide access parallel outputs. PG12 PG14 provide access +VDD ground planes. SMA1-SMA32: Serial transmit receive connections TST1-TST8: Impedance test trace connections CLK_OUT1-CLK_OUT6: Reference clock outputs CLK_IN: External reference clock input VR33, VR18, VR15: +3.3 +1.8 +VDD voltage regulators R12V, R22V, R22V1, R22V2: Potentiometers setting +3.3 +1.8 +VDD HSTL voltage reference levels Onboard 156.25-MHz crystal oscillator Level shift clock buffer +2.5- +3.3-V LVCMOS clock fanout buffer
connectors
LT1587 voltage regulators Potentiometers XTAL oscillator MC100EP8111 clock buffer MPC9456 clock buffer
Abbreviation List
Table 1-3. Acronyms Abbreviated Terms
Term BIST PRBS UIp-p Meaning High logic level (nominally logic level (nominally Built-in self-test Design verification board Interface connection Pseudo-noise Pseudo random sequence Test access port Time delay reflectometry Peak-to-peak unit interval
Table contains abbreviations used this document.
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Related Documentation
Related Documentation
MC92610 Quad 3.125 Gbaud SerDes User's Manual (MC92610UM) MC92610DVB schematics MC100ES8111 data sheet MPC9456 data sheet IEEE 802.3-2002®, Part Carrier sense multiple access with collision detection (CSMA/CD) access method physical layer specifications
Related documentation includes following:
Contact Information
questions concerning MC92610 design verification place order kit, contact local Motorola field applications engineer.
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Chapter Hardware Preparation Installation
This chapter provides instructions unpacking, hardware preparation, configuration installation, description interface components MC92610DVB.
Unpacking Instructions
Unpack board from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
MC92610DVB Package Contents
Table 2-1. MC92610DVB Contents
Quantity Item MC92610DVB design verification board MC92610DVBUG Quad SerDes Design Verification Board User's Guide MC92610 Quad 3.125 Gbaud SerDes User's Manual Complete MC92610DVB design verification board schematics 0.100" shunts Square receptacle patch cords
Table describes contents MC92610DVB kit.
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Hardware Preparation
Hardware Preparation
Operation MC92610DVB requires proper setup power supply voltage regulators well reference clock. Figure depicts location major components board. following sections describe proper setup MC92610DVB.
Connectors Crystal Oscillator Switch +3.3-V Power Connection Clock Buffers Voltage Regulators HSTL Reference Test Point
Connector
+5-V Power Connectors Vertical Test Traces Status LEDs MC92610
Connectors Connector +1.5- +1.8-V Power Connectors
Serial Differential Connectors
Horizontal Test Traces
Connectors
Figure 2-1. Side Part Location Diagram
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Hardware Preparation
2.3.1
Setting Power Supply Voltage Regulators
MC92610DVB requires single +5.0-V supply. Fully operational, board will draw maximum current less than from +5.0-V supply. Actual current consumption depends user-set voltage levels, clock frequencies MC92610 operating mode. board contains +5.0-V connection posts ground connection posts. These duplicate connections simplify using four-wire supply: supply ground, force sense.
2.3.2
Setting Voltage Regulators
+5.0-V supply powers onboard voltage regulators, VR33, VR18, VR15. These regulators generate +3.3, +1.8, +1.5/1.8 (VDDQ), respectively. +3.3-V supply provides power oscillator, clock buffer chips, drivers. This supply varied over range +3.3 using R12V potentiometer. +1.8-V supply powers MC92610 core logic, transceivers, on-chip phase-locked loop (PLL). This regulator adjusted over range +1.8 0.15 using R22V. +1.5-V (HSTL) VDDQ supply powers MC92610 control signal, parallel input, output interface circuitry. This voltage level determined desired logic interface. +1.5-V supply adjusted using R22V1 potentiometer from +1.5 0.45 V/-0.15 desired +1.5-V regulator adjusted match +1.8-V range evaluation those systems that will contain separate +1.5-V supply. +3.3-V, +1.8-V, +VDDQ supplies accessible through connection posts. Please note that these regulators should voltage limits within operating ranges described MC92610 Quad 3.125 Gbaud SerDes User's Manual. Failure operate within these ranges cause damage MC92610. Motorola does guarantee MC92610 operation beyond ranges specified. R12V, R22V, R22V1 potentiometers will factory +3.3, +1.8, +1.5 respectively.
2.3.3
HSTL Voltage Reference Regulator
HSTL voltage reference that must adjusted logic high/low switch point. nominal +1.5 +1.5-V (VDDQ) supply, R22V3 should such that voltage HSTL_VREF test point +0.75 those systems whose HSTL voltage will +1.8 this potentiometer should +0.9 R22V3 potentiometer typically factory +0.8
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Reference Clock Source
Reference Clock Source
Through combination clock buffers, reference clock supplied MC92610 several output connectors. input reference clock MC92610 supplied either using onboard crystal oscillator directly driving external reference clock into board's clock buffer circuit through connector, CLK_IN. clock circuitry MC92610DVB shown Figure 2-2.
156.25-MHz Oscillator CLK_0 CLK_1 CSEL CLK_IN MC100ES8111 REF_CLK_P REF_CLK_N
CLK_OUT_1 CLK_OUT_2
MPC9456 3.3V_CLK_OUT5 3.3V_CLK_OUT6 3.3V_CLK_OUT3 3.3V_CLK_OUT4
Figure 2-2. MC92610DVB Clock Circuitry
input reference clock, from either onboard oscillator external source, applied MC100EP8111 clock buffer. outputs differential low-voltage, +1.5-V HSTL signals. These signals drive MC92610 reference clock inputs, REF_CLK_P REF_CLK_N, connectors triggering other equipment, 1.5V_CLK_OUT1 1.5V_CLK_OUT2, inputs second clock buffer MPC9456. outputs MPC9456 single-ended series terminated +3.3-V signals driving four additional connectors, 3.3V_CLK_OUT3, 3.3V_CLK_OUT4, 3.3V_CLK_OUT5, 3.3V_CLK_OUT6. These connections provide board synchronized trigger signals with laboratory equipment.
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Reference Clock Source
2.4.1
Using Onboard Oscillator
crystal oscillator socketed board (not soldered) allow user easily change frequencies swapping crystal oscillators with other values. default reference clock frequency oscillator supplied with board 156.25 MHz. Crystal oscillators used with this board should have +3.3-V complementary PECL outputs capable driving lines terminated with These types crystal oscillators available from external vendors variety frequencies. listing recommended crystal oscillators refer Appendix "Crystal Oscillator Vendors." When selecting reference oscillators external reference frequencies, only those frequencies listed MC92610 Quad 3.125 Gbaud SerDes User's Manual considered valid. Motorola does guarantee operation MC92610 frequencies other than those listed user's manual. switch settings select either onboard oscillator external reference, well enable clock buffer chips.
2.4.2
External Reference Clock Source
supply external reference clock, switch number must `off' position. user must then supply Vp-p input clock through CLK_IN connector. This input coupled board and, therefore, does require biasing input signal. After coupling, CLK_IN input terminated with impedance. This input clock buffered MC100EP8111 level translated from PECL HSTL. provides REF_CLK_P, inputs MC92610, 1.5V_CLK_OUT1 1.5V_CLK_OUT2 connectors. Switch number must `on' position enable outputs MC100EP8111. NOTE outputs MCP100EP8111 expect path ground. Therefore, blocker being used with 1.5V_CLK_OUT1 1.5V_CLK_OUT2 outputs trigger signal oscilloscope, feed through termination must placed line before blocker before attachment oscilloscope. attenuator used place feed through termination. Section 3.2.1.1, "Equipment Setup," example oscilloscope setup.
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Interface Components
2.4.3
3.3V_CLK_OUTn Connectors
Four single-ended, 3.3-V level clock signals available connectors drive other instruments. Between MC100EP8111 output four SMAs, MPC9456 that performs differential HSTL single-ended +3.3-V LVTTL/CMOS level shift. These CMOS outputs series terminated board connected connectors labeled 3.3V_CLK_OUT3, 3.3V_CLK_OUT4, 3.3V_CLK_OUT5, 3.3V_CLK_OUT6. MPC9456 outputs disabled setting switch SW1, switch `off' position. Figure depicts switch settings using onboard oscillator with clock buffer outputs enabled.
Reset Reset External Onboard Enabled Enabled MPC9456 Output Enable_B MC100EP8111 Output Enable_B MC100EP8111 CLK_SEL
Figure 2-3. Switch Settings Using Onboard Oscillator
Interface Components
following sections list descriptions MC92610DVB interface connector components.
2.5.1
Parallel Inputs Outputs
MC92610 parallel supplied +1.5-V (HSTL) VDDQ voltage regulator (set rail-to-rail signal swing. There bidirectional signals MC92610 design verification board.
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Interface Components
2.5.1.1
Parallel Inputs
parallel inputs, both data control, accessible through 0.100" connectors. Figure depicts 0.100" connector numbering scheme, with being labeled board. complete mapping MC92610 inputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-4. 0.100" Input Connector Numbering Scheme (Top View)
description input functionality MC92610, refer MC92610 Quad 3.125 Gbaud SerDes User's Manual.
2.5.1.2
Parallel Outputs
parallel outputs, both data status bits, present four 0.100" connectors. Figure depicts 0.100" output connector numbering scheme, with labeled board. parallel output signals MC92610 1.5- 1.8-V HSTL compatible depending setting VDDQ regulator. complete mapping MC92610 outputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-5. 0.100" Output Connector Number Scheme (Top View)
information regarding MC92610 outputs, refer MC92610 Quad 3.125 Gbaud SerDes User's Manual.
2.5.2
+VDDQ Ground (GND) Access Connections
MC92610DVB also 0.100" connectors, PG12 PG14, with dedicated connections +1.5-V VDDQ ground planes. These useful biasing parallel input signals using jumper cables. number pins connected VDDQ plane. even number pins connected ground (0.0-V) plane.
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Special Test Connection
2.5.3
Receiver Interface Status LEDs
state three parallel receiver status bits, RECV_x_ERR, RECV_x_K, RECV_x_IDLE, also accessible through LEDs located next receiver parallel output connectors. illuminated corresponds logic `high' signal. Conversely, non-illuminated represents logic `low.' more information about state status bits, refer MC92610 Quad 3.125 Gbaud SerDes User's Manual.
2.5.4
Serial Inputs Outputs
MC92610 high-speed serial differential inputs differential outputs connected appropriately labeled pairs connectors through board traces with characteristic impedance (100- differential). output driver requires parallel termination mid-rail (+0.9 nominal +1.8-V supply). termination voltage +0.9 signal must coupled. There coupling blocking) serial outputs board. needed, coupling must done in-line before termination. During testing, serial transmitter outputs should terminated with This done connecting serial transmitter outputs serial receiver inputs, laboratory equipment with input impedance through in-line coupling, terminating outputs with terminations.
Special Test Connection
MC92610DVB also contains oscilloscope test socket, labeled TPA. When MC92610 configured factory test mode, this test socket enables special access PLL. NOTE This test mode factory testing purposes only. There system applications this mode, test socket should remain unconnected times.
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Test Traces
Test Traces
MCS92610DVB design verification board both vertical horizontal test traces: Vertical: TST1-TST5 TST2-TST6 Horizontal: TST3-TST7 TST4-TST8
These traces used determine impedance board using measurement techniques.
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Chapter Laboratory Equipment Quick Setup Evaluation
This chapter begins with listing recommended test equipment needed perform complete evaluations MC92610. Chapter "Test Setups," covers specific setup configurations this equipment depending desired feature under test. Appendix "Parts List," offers various suggested data test patterns that used with these test setups. quick setup evaluation procedures outlined below describe MC92610DVB used evaluate data `eye diagram' simple error rate test using internal test features MC92610 with minimal amount test equipment. Only power supply sampling oscilloscope required. Details testing specific systems left user. more information regarding MC92610 feature set, refer MC92610 Quad 3.125 Gbaud SerDes User's Manual.
Recommended Laboratory Equipment
Evaluation MC92610 feature possible using MC92610DVB evaluation conjunction with several pieces test equipment. quick setup evaluations other tests listed this guide utilize basic test equipment listed Table 3-1. Equivalent instrumentation substituted. pieces test equipment necessary tests.
Table 3-1. Recommended Test Equipment
Quantity MC92610DVB evaluation Tektronix 8000 digital sampling oscilloscope Tektronix 80E04 TDR/sampling head GHz) Tektronix 80E03 sampling heads GHz) Hewlett-Packard HP16700 logic analysis system Hewlett-Packard HP16522A pattern generators Hewlett-Packard HP16557D logic analyzers Hewlett Packard HP6624A system power supply Equipment
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Recommended Laboratory Equipment
Table lists laboratory accessories.
Table 3-2. Accessories
male each coax patch cords, lengths: various 3-dB attenuators 6-db attenuators blockers couplers) terminations ground) feed through terminations 5/16" torque wrench (fits SMA, 2.9- 3.5-mm connectors) Bias-T networks
Power splitters adapters female female adapters male male adapters
In-depth testing MC92610 performed using error rate tester jitter analysis system. Table provides listing test equipment that used these types tests.
Table 3-3. Jitter Analysis Test Equipment
Quantity each Equipment Agilent 71500C jitter analysis system 70820A microwave transition analyzer 70004A display 3325B synthesizer/function generator 83752A synthesized sweeper 86130A BitAlyzer (serial error rate tester) 70874C jitter personality card Assorted bandpass filters Rohde Schwarz SMIQ-04B signal generator Agilent 6624A system power supply Agilent 11636B power splitter Divide-by-xx prescalers
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Quick Setup Data-Eye Diagram
Quick Setup Data-Eye Diagram
MC92610DVB design evaluation comes equipped immediately demonstrate MC92610 functions: Data-eye signal generation observation error rate checking using internal built-in self-test (BIST) features
3.2.1
Quick Setup Data-Eye Generation Observation
transmitted data-eye observed either serial outputs MC92610 using integrated, 23rd order, pseudo-noise (PN) pattern generator. implementation 23-bit generator uses following polynomials. (Polynomial selection depends state BIST_MODE_SEL.)
(BIST_MODE_SEL
(BIST_MODE_SEL
Stimulus from this generator 8B/10B encoded also used further system testing. Refer MC92610 Quad 3.125 Gbaud SerDes User's Manual additional information.
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Quick Setup Data-Eye Diagram
3.2.1.1
Equipment Setup
Generation observation data-eye produced on-chip generator requires only MC92610DVB, power supply, high-speed digital sampling scope, 0.100" shunts, single-pin receptacle patch cords. shunts patch cords provided with MC92610DVB evaluation kit. MC92610DVB test equipment should connected shown Figure 3-1. Configure clock circuits with shown Figure 2-3. NOTE unconnected serial transmitter outputs should terminated This done connecting serial transmitter outputs serial receiver inputs terminations through in-line coupling blocking).
Blocker TRIG Blockers
Feed Through Termination
1.5V_CLK_OUT1
XMIT_P XMIT_N
MC92610DVB +5-V Sense +5-V Force Sense Force
+5-V Supply
Figure 3-1. Data-Eye Observation Setup
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3.2.1.2 Parallel Input Connections
Quick Setup Data-Eye Diagram
basic diagram will generated biasing parallel inputs according Table 3-4. Ground connections made using 0.100" shunts. Connections VDDQ made using square receptacle patch cords jumpering number pins headers PG12 PG14. shunts patch cords provided with MC92610DVB kit. even number pins connector headers connected board's ground plane. unlisted pins connected.
Table 3-4. Data-Eye Generation Parallel Input Biasing
Signal CTRL_SIG_0 REPE RCCE ADIE RESET DDRE CTRL_SIG_1 LBOE TBIE XMIT_EN_ALL XMIT_EQ_EN XMIT_REF_A +1.5 +1.5 +1.5 Bias Level Signal A_XMIT0 XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_4 XMIT_A_5 XMIT_A_6 XMIT_A_7 B_XMIT0 XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_4 XMIT_B_5 XMIT_B_6 XMIT_B_7 Bias Level Signal A_XMIT1 XMIT_A_K XMIT_A_IDLE
XCVR_A_DISABLE
Bias Level
+1.5
XCVR_A_RSEL XMIT_A_CLK B_XMIT1 XMIT_B_K XMIT_B_IDLE
XCVR_B_DISABLE
+1.5
XCVR_B_RSEL XMIT_B_CLK
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Quick Setup Data-Eye Diagram
Table 3-4. Data-Eye Generation Parallel Input Biasing (continued)
Signal CTRL_SIG_2 BSYNC DROP_SYNC TST_1 TST_0 BIST_MODE_SEL RECV_EQ_EN RECV_REF_A TEST_0 SCAN_EN TRST +1.5 +1.5 +1.5 +1.5 Bias Level Signal C_XMIT0 XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_4 XMIT_D_5 XMIT_D_6 XMIT_D_7 D_XMIT0 XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_4 XMIT_D_5 XMIT_D_6 XMIT_D_7 Bias Level Signal C_XMIT1 XMIT_C_K XMIT_C_IDLE
XCVR_C_DISABLE
Bias Level
+1.5
XCVR_C_RSEL XMIT_C_CLK D_XMIT1 XMIT_D_K XMIT_D_IDLE
XCVR_D_DISABLE
+1.5
XCVR_D_RSEL XMIT_D_CLK
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Quick Setup Data-Eye Diagram
3.2.2
Basic Observation-Test Procedure
Connect MC92610DVB test equipment described Figure Table 3-4. This will place MC92610 generation mode with MC92610 reset. Steps skipped they were previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (1.5 regulators connectors T10, respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT1 156.25 (period ns). Observe XMIT_x_P XMIT_x_N output. Since chip reset, transmitter should show constant output level ground, status LEDs should indicate that receiver startup, LEDs RECV_x_ERR RECV_x_K RECV_x_IDLE off. Connect RESET (connector CTRL_SIG_0, VDDQ access connection. This releases RESET signal. Observe XMIT_x_P XMIT_x_N. transmitter should outputting random data. Setting digital sampling oscilloscope infinite persistence mode will display data-eye. example data-eye shown Figure 3-2.
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Quick Setup Data-Eye Diagram
Figure 3-2. MC92610 Data-Eye Using Recommended Test Setup
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Quick Setup Data-Eye Diagram
3.2.3
Quick Setup Error Rate Checking
addition having integrated generator, MC92610 also error rate checker (BERC). integrated 23rd order signature analyzer that synchronized incoming stream used count code group mismatch errors relative internal reference pattern. following test procedure will describe this BIST feature. more information concerning MC92610 BIST, refer MC92610 Quad 3.125 Gbaud SerDes User's Manual.
3.2.3.1
Equipment Setup
Connect MC92610DVB shown Figure connecting transmitter outputs link under test (XLINK_x_P/N) receiver under test (RLINK_x_P/N).
Logic Analyzer D_RECV C_RECV B_RECV A_RECV RECV_P XMIT_P RECV_N XMIT_N MC92610DVB
+5-V Sense
+5-V Force
Sense
Force
+5-V Supply
Figure 3-3. Error Rate Check Test Setup
3.2.3.2
Parallel Connections
bias connections parallel inputs perform quick setup BERC test same those quick setup diagram shown Table 3-4. parallel outputs connected data analysis system. simple quick test, logic analyzer required, since errors reported observed channel status LEDs.
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Quick Setup Data-Eye Diagram
3.2.3.3
Quick Setup BERC Test Procedure
Connect MC92610DVB test equipment described Section 3.2.3.1, "Equipment Setup." This will place MC92610 generation mode with MC92610 held reset, receivers BERC mode using recovered clock. Step skipped previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (1.5 regulators connectors T10, respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT1 156.25 (period ns). Connect RESET (connector CTRL_SIG_0, +1.5-V VDDQ access connection. This releases RESET signal. Observe parallel outputs data analyzer status LEDs. described MC92610 Quad 3.125 Gbaud SerDes User's Manual, MC92610 will start lock PLL, initialize receivers, perform byte alignment, reset error counter. When receivers locked BIST running, recovered clock observable RECV_x_RCLK. Figure example receiver startup error detection sequence. sequence shown Table will occur each receiver's status outputs observable LEDs.
Table 3-5. State Sequence Receiver
Status Outputs Receiver State RECV_x_ERR Receiver startup Receiver byte/word synchronized, analyzer locked BIST running mismatch this character RECV_x_K RECV_x_IDLE
Once receiver initially locked receiver data bits, RECV_x_[7:0], zero (logic low). Should error occur, RECV_x_[7:0] will increment RECV_x_ERR will flag error during that byte time. value RECV_x_[7:0] remains constant until another error detected system reset. receiver counter fills with errors, bits RECV_x_[7:0] stay logic high (11111111) until receiver reset. Refer MC92610 Quad 3.125 Gbaud SerDes User's Manual more detail.
3-10
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Quick Setup Data-Eye Diagram
RESET RECV_x_ERR RECV_x_K RECV_x_IDLE RECV_x_RCLK RECV_x_[7:0] Start-Up RCVR Synchronized Analyzer Locked 0000 0000 0000 0001 0000 0010
RECV RECV RECV Synchronized Synchronized Synchronized Analyzer Analyzer Analyzer Locked Locked Locked Errors Error Detected Error Detected
Figure 3-4. Receiver Startup Error Detection Sequence
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Chapter Test Setups
This chapter outlines laboratory test equipment setup procedure evaluate features MC92610 more depth than those outlined previous chapter. These setups meant guidelines only implied complete. Details testing specific system applications left user.
Serial Link Verification Using Serial Error Rate Tester (BERT)
This test setup used observe rate which MC92610 produces errors given either pseudo-random (PRBS) patterns user-defined pattern sets generated serial error rate tester (BERT). MC92610 placed repeater mode, REPE high, thereby disabling parallel receiver transmitter buses. Testing performed using ten-bit interface mode does require insertion idle characters word recognition byte alignment. verification using 8B/10B encoder other MC92610 features required, appropriate idle insertion timing requirements outlined MC92610 Quad 3.125 Gbaud SerDes User's Manual must followed.
4.1.1
Test Setup Double Data Rate Link Multiplex Modes
Figure depicts test setup MC92610 double data rate mode (DDRE) link multiplex mode (LME) control bits follows: DDRE REPE XMIT_EQ_EN TBIE RECV_EQ_EN
other control bits except RESET, which initially then transitioned start MC92610.
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Serial Link Verification Using Serial Error Rate Tester (BERT)
Source
Power Splitter
Clean Clock 3.125
Error Rate Tester Pattern Generator CK_OUT Error Detector Serial Data Serial Data Prescaler Divide-by-40 Reference Clock 78.125 MC92610DVB (Repeater Mode)
Blocker
Prescaler Divide-by-20
Reference Clock 156.25
MC92610DVB (Repeater Mode)
Figure 4-1. DDRE Serial Link Test Setup
4.1.2
Test Setup Double Data Rate Link Multiplex Modes
Serial link testing also performed using both double data rate mode (DDRE) link multiplex mode (LME). This reduces reference frequency required MC92610 factor two. Figure depicts serial link test setup asserting both DDRE using divide-by-40 prescaler.
Clean Clock Source Power Splitter 3.125 Error Rate Tester Pattern Generator Error Detector
Blocker
Figure 4-2. DDRE Serial Link Test Setup
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Jitter Testing
Jitter Testing
following tests guidelines verifying performance MC92610 `noisy' conditions. Results will vary depending input reference frequencies, MC92610 mode operation, test setup equipment, test environment.
4.2.1
Jitter Test System Calibration
Before beginning type jitter measurement, system must first calibrated, shown Figure 4-3, produce desired frequency amplitude modulation jittered source. amplitude modulation then translated into jitter units peak-to-peak unit intervals (UIp-p). Different synthesized sweepers have different characteristics different frequencies. possible certain frequencies produce spurious side lobes that will affect jitter characterization. strongly advised that bandpass filter centered carrier frequency used input microwave transition analyzer. Refer synthesized sweeper reference manual more details.
Function Generator 10-MHz Reference Clock
Modulation Signal
HPIB
70000 Mainframe with Microwave Transition Analyzer
Filter
Synthesized Sweeper (Carrier Frequency)
Jittered Clock
Power Splitter
Figure 4-3. Jitter Measurement System Calibration
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Jitter Testing
4.2.2
Reference Clock Jitter Transfer Test
test setup shown Fig. used observe amount jitter placed reference clock that transferred data outputs. Example frequencies were chosen match narrow bandpass filters available with Agilent 71500C jitter analysis system. control bits follows: DDRE XMIT_EQ_EN TBIE RECV_EQ_EN
parallel data inputs must pattern shown Figure 4-4. This data pattern appears 622-MHz clock signal serial outputs.
Function Generator 10-MHz Reference Clock
Modulation Signal
Blocker 70000 Mainframe with Microwave Transition Analyzer Filter Filter
Serial Data
HPIB
Synthesized Sweeper (Carrier Frequency)
Jittered Clock
Power Splitter
Jittered Reference Prescaler Clock MC92610DVB Divide-by-10 62.2 XMIT Parallel Data
11001100110011001100
Figure 4-4. Reference Clock Jitter Transfer Test Setup
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Jitter Testing
4.2.3
Reference Clock Jitter Tolerance Test
test setup shown Figure used observe amount jitter placed reference clock that does produce errors serial data outputs compared input serial data stream. MC92610 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: DDRE XMIT_EQ_EN REPE TBIE RECV_EQ_EN
other control inputs
Error Rate Data over HPIB
Function Generator 10-MHz Reference Clock
Source
Clean Clock 3.125
Error Rate Tester Pattern Generator Error Detector
Modulation Signal
HPIB
Synthesized Sweeper (Carrier Frequency) 3.125
Jittered Clock
Power Splitter
Prescaler Divide-by-20
Jittered Reference Clock 156.25
MC92610DVB
Figure 4-5. Reference Clock Jitter Tolerance Test Setup
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Serial Data
70000 Mainframe with Microwave Transition Analyzer
Blocker
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Jitter Testing
4.2.4
Data Jitter Tolerance Test
test setup shown Figure used observe amount jitter placed serial data inputs that does produce errors serial data outputs. MC92610 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: DDRE XMIT_EQ_EN REPE TBIE RECV_EQ_EN
other control inputs
Error Rate Data Over HPIB Clean Clock Source 3.125
Function Generator 10-MHz Reference Clock
Error Rate Tester Pattern Generator Power Splitter Error Detector
Modulation Signal
Blocker Serial Data Reference Clock Prescaler MC92610DVB Divide-by-20 156.25 (Repeater Mode)
HPIB
70000 Mainframe with Microwave Transition Analyzer
Synthesized Sweeper (Carrier Frequency)
Jittered Clock 3.125
Figure 4-6. Data Jitter Tolerance Test Setup
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Appendix Connector Signals
parallel data input output signals MC92610DVB design verification board listed following tables. connection test points common 0.100" spaced type connectors.
Input: (0.100") Connectors
configuration, control, data, test inputs MC92610 connectors. There total input connectors DVB. each connector, even numbers connected ground plane. signal inputs numbers) have pull-up resistors board. Therefore, configuration requires `high' logic must jumper connected +1.5 (VDDQ) access connectors PG12 PG14. input required `low,' shorting jumper installed. signal name, description, MC92610 device `ball' (pin) number listed following tables each input connectors.
A.1.1
Control Signal Input Connectors
signals connectors CTRL_SIG_0, CTRL_SIG_1, CTRL_SIG_2 (PG1-PG3, respectively) control input signals that basic configuration MC92610. These signals corresponding connector pins listed Table A-1, Table A-2, Table A-3, respectively.
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Table A-1. CTRL_SIG_0 Connector
Connector MC92610 Input Signal Name REPE RCCE ADIE RESET DDRE
Input: (0.100") Connectors
Description Repeater mode enable Recovered clock enable Word synchronization enable Half-speed mode enable Add/drop idle enable System reset Double data rate enable Ground connection
Table A-2. CTRL_SIG_1 Connector
Connector MC92610 Input Signal Name LBOE TBIE XMIT_EN_ALL XMIT_EQ_EN XMIT_REF_A Description Loopback output enable Loopback enable Ten-bit interface enable Link multiplex enable Transmitter link broadcast enable Transmit equalization enable Transmit reference clock select Ground connection
Table A-3. CTRL_SIG_2 Connector
Connector MC92610 Input Signal Name BSYNC DROP_SYNC TST_1 TST_0 BIST_MODE_SEL RECV_EQ_EN RECV_REF_A Description Byte synchronization mode Drop synchronization Test mode-select Test mode-select Selects PRBS pattern Word synchronization input Receiver equalization enable Receiver reference clock select Ground connection
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Input: (0.100") Connectors
A.1.2
Transmitter Parallel Data Input Connectors
MC92610 parallel transmitter data input signals channels through mapped connectors listed tables below. Table shows 8-bit data byte input transmitter channels through respectively, connectors A_XMIT0-D_XMIT0 (PG8, PG10, PG6, PG4).
Table A-4. A_XMIT0, B_XMIT0, C_XMIT0, D_XMIT0 Connectors
MC92610 Ball Connector A_XMIT0, B_XMIT0, C_XMIT0, D_XMIT0, Input Signal Name XMIT_x_0 XMIT_x_1 XMIT_x_2 XMIT_x_3 XMIT_x_4 XMIT_x_5 XMIT_x_6 XMIT_x_7 Description
Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Transmitter data input Ground connection
Table lists remaining transmitter input signals four channels connectors A_XMIT-D_XMIT_1 (PG9, PG11, PG7, PG5), respectively.
Table A-5. A_XMIT1, B_XMIT1, C_XMIT1, D_XMIT1 Connectors
MC92610 Ball Connector A_XMIT1, B_XMIT1, C_XMIT1, D_XMIT1, Input Signal Name XMIT_x_K Description
Transmitter special character (data ten-bit mode) Transmitter Idle enable (data ten-bit mode)
XMIT_x_IDLE
XCVR_x_DISABLE Transceiver disable XCVR_x_RSEL XMIT_x_CLK Transceiver redundant link select Transmitter interface clock Ground connection
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Output: (0.100") Connectors
Output: (0.100") Connectors
MC92610 receiver parallel data outputs connected 0.100" connectors. mapping these signals shown Table A-6. Table lists signals A_RECV, B_RECV, C_RECV, D_RECV (LA1-LA4, respectively) connectors. Note that receive data clock, RECV_x_RCLK, brought connector pins. Care should exercised when connecting both these pins exceed drive capacity chip output. Refer MC92610 Quad 3.125 Gbaud SerDes User's Manual, more details.
Table A-6. A_RECV B_RECV Connectors
MC92610 Ball Connector A_RECV, B_RECV, C_RECV, D_RECV, RECV_x_CLK RECV_x_CLK Output Signal Name Description
XCVR_ receive data clock XCVR_ receive data clock Ground connection Ground connection
channel this WSO, (word sync. output). channel this (JTAG, test data out). channels this GND. RECV_x_ERR RECV_x_IDLE RECV_x_ RECV_x_K RECV_x_7 RECV_x_6 RECV_x_5 RECV_x_4 RECV_x_3 RECV_x_2 RECV_x_1 RECV_x_0 Receiver error detect Receiver Idle detect Receiver data mode Receiver special character (data mode) Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data Receiver data
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TEST_0 Connector
TEST_0 Connector
Table lists signals connector TEST_0 (PG13). This MC92610 test access port (TAP) interface IEEE 1149 JTAG testing. NOTE There internal pull ups/pull downs MC92610 JTAG inputs. These pins should shunted ground TEST_0 connector. more information test access port, Section MC92610 Quad 3.125 Gbaud SerDes User's Manual, more details.
Table A-7. TEST_0 Connector
Connector MC92610 Input Signal Name SCAN_EN TRST Test mode, scan shift enable (for factory only) JTAG test data JTAG test clock JTAG test mode select JTAG test reset Ground connection Description
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Appendix Parts List
Design Verification Board Parts List
Table shows parts used constructing MC92610DVB design verification board.
Table B-1. MC92610DVB Design Verification Board Parts List
Item Qty. Reference C24, C30-C33, C54-C57, C208-C210, C303-C304 C11, Value Manufacturer Bourns Manufacturer's Part C1812C105K5RAC Description Ceramic chip capacitor, size 1812
Kemet
T495X107K010AS
100-µF solid tantalum chip capacitor, ESR, size 7343 10-µF solid tantalum chip capacitor, ESR, size 7343H Ceramic chip capacitor, size 0805
C13, C12, C22-C23 C16, C10, C20, C18, C7-C9, C14-C15, C25, C26, C34-C53, C201-C207, C301-302
Kemet
T495X106K035AS
0.01 Kemet Kemet
C0805C101J1GAC
C0805X7R500-104KNE Ceramic chip capacitor, size 0805 C0805X7R500-103KNE Ceramic chip capacitor, 0.01 size 0805
156.25
ConnorWinfield Omron
EE14-521-156.25M A6S-6104
156.25-MHz through-hole, 14-pin crystal oscillator 6-pole slide switches, positions (open closed), surface mount
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Design Verification Board Parts List
Table B-1. MC92610DVB Design Verification Board Parts List (continued)
Item Qty. Reference PG12, PG14 Value Manufacturer Manufacturer's Part 2516-6002UB Description keyed header with shroud, 0.1" spacing, profile keyed header with shroud, 0.1" spacing keyed header with shroud, 0.1" spacing, profile Green surface mount Linear voltage regulator, 3-ampere, 3-lead 3.3-V clock buffer 32-pin gull wing LQFP Level shift clock buffer, 32-pin gull wing TQFP 4-mm screw terminal binding post, red/black/ yellow/blue/green
PG1-PG11, PG13 LA1-LA4
3428-6002UB 2540-6002UB
D1-D13 VR15, VR18, VR33 T1-T8,
Dialight Linear Technology Motorola Motorola Technology Texas Instruments
597-5311-402 LT1587CM MPC9456A MC100EP8111 2304/2303/ 9648/9649/9650
SN74HSTL16919DGGR Memory address latch (used +1.8 +3.3-V SN74HSTL16918DGGR buffer/level shift) TSOP package CR16B820JT CRCW08051240FT chip resistor, size 0603 124- chip resistor, size 0805 330- chip resistor, size 0805 chip resistor, size 0805 120- chip resistor, size 0805 chip resistor, size 0805 100- chip resistor, size 0805 1.0- chip resistor, size 1206 Scope test socket
R5-R6, R12, R23, R10, R15, R20, R22, R13, R14, R43-R54 R16-R19, R27, R61-R65 R33, R94,
SPC/ Multicomp Dale
Welwyn Dale Dale Dale
WCR0805330RG CRCW0805-10W680JT CRCW08051200FRT1 CR0805-10W-000T
Dale Dale Johnson
CRCW08051000FT-X CRCW12061R0JT 129-0701-202
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Design Verification Board Parts List
Table B-1. MC92610DVB Design Verification Board Parts List (continued)
Item Qty. Reference CLK_IN, CLK_OUT1- CLK_OUT6, SMA1-SMA32, TST1-TST8 R12V R22V, R22V1, R22V3 R42, R69, R67, R71, R72, R90-R92 socket R34, R35, R59, R60, R73-R76 Value Manufacturer Manufacturer's Part 901-144-8-RFX Description jack socket
2400 63.4 49.9
BOURNS BOURNS Motorola Pomona Panasonic Dale Panasonic Dale
3214W-1-102E 3214W-1-501E MC92610VF 929950-00 4741-12-0/4741-12-2 P825CCT CR16B242JT P63.4CCT CR0805-10W-103J AG11D
Surface mount trimming resistor, lead Surface mount trimming resistor, lead Quad 3.125 Gbaud SerDes 0.100" shunts Square receptacle patch cord 825- chip resistor, size 0805 2400- chip resistor, size 0603 63.4- chip resistor, size 0805 10-K chip resistor, size 0805 14-lead socket crystal oscillator 49.9- chip resistor, size 0805 12.1- chip resistor, size 0805 187- chip resistor, size 0805
Dale
CRCW080549R9FT
12.1
Panasonic Dale
P12ACT-ND CRCW0051870FT
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Appendix Crystal Oscillator Vendors
Oscillator Vendors
Table C-1. Crystal Oscillators Vendors
Manufacturer Model Number M2944 Website Maximum Frequency (MHz) 155.52
Table lists crystal oscillator vendors.
Electronics Connor-Winfield Champion Technologies Mercury Saronix
www.mfelectronics.com www.mfelec.com www.conwin.com www.champtech.com www.mecxtal.com www.saronix.com
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Appendix Prescaler Jitter Measurement
Divide-by-xx Prescaler Description
Evaluating jitter system requires that clocks within system based common source. this reason, often necessary prescalers derive needed reference clock. Motorola developed small programmable prescaler with maximum input frequency that assembled using commercially available parts. Figure depicts block diagram this prescaler.
Clock Divide Clock In_alt 5-Bit Programmable Counter Divide Prescaler Level Shift Clock
Bank Switch
Bank Switch
Figure D-1. Divide-by-xx Prescaler Block Diagram
input prescaler either through divide-by-2 directly into 5-bit programmable counter. bank bank switches used select variety prescaler values based following formula:
Modulus
where
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Prescaler Components
values commonly used 1.0-Gbit systems, refer Table D-1.
Table D-1. Switch Settings 1.0-Gbit SerDes Prescalers
Bank Input Clock In_alt Clock Clock Clock Bank Modulus
Schematics this prescaler available from local Motorola field applications engineers.
Prescaler Components
Table D-2. Major Components Divide-by-xx Prescaler
Table lists major integrated circuit components needed prescaler.
Part MC12093 MC100ELT23 MC100ELT21 MC100ELT26 HMMC-3122 HMC364S8G HMC394LP4
Manufacturer Motorola Semiconductor Semiconductor Semiconductor Agilent Hittite Microwave Hittite Microwave
Supplier Newark Newark Newark Newark Arrow Hittite Hittite
Comments 1.1-GHz prescaler (divide Dual differential PECL translator, with separate inputs Single differential PECL translator. Alternative above part. Dual differential PECL translator, with common inputs. Alternative above part. 12-GHz divide-by-2 prescaler, GaAs MMIC 12-GHz divide-by-2 prescaler, GaAs MMIC. Pin-for-pin alternative above part. 2.2-GHz programmable 5-bit counter, GaAs MMIC
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Appendix Revision History
This appendix provides list major differences between revisions MC92610 Quad SerDes Design Verification Board User's Guide (MC92610DVBUG).
Table provides revision history this document.
Table E-1. MC92610DVB Revision History
Rev. Date 05/02/2002 03/30/2004 Initial release. Reformatted release. Substantial Change(s)
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Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without
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