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MC92602 Reduced Interface SerDes Design Verification Board User's Guid


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MC92602DVBUG 3/2004 Rev.
MC92602 Reduced Interface SerDes Design Verification Board User's Guide
Device Supported: MC92602
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Contents
Paragraph Section Number Title Chapter General Information
Contents
Page Number
Introduction. Design Verification Board Features Specifications. Abbreviation List Related Documentation. Block Diagram Board Components Contact Information Chapter Hardware Preparation Installation
2.3.1 2.3.2 2.3.3 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5.1 2.5.1.1 2.5.1.2 2.5.2 2.5.3
Unpacking Instructions MC92602DVB Package Contents Hardware Preparation Setting Power Supply Voltage Regulators Setting Voltage Regulators. HSTL Voltage Reference Regulator Reference Clock Source. Using Onboard Oscillator External Reference Clock Source Supplying Clock MC92602 3.3V_CLK_OUTn Connectors Clock Frequency Selection Interface Components Parallel Inputs Outputs. Parallel Inputs Parallel Outputs +VDDQ Ground (GND) Access Connections. Serial Inputs Outputs. Special Test Connection. Test Traces
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Contents
Paragraph Number Title Chapter Laboratory Equipment Quick Setup Evaluation 3.2.1 3.2.1.1 3.2.1.2 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 Recommended Laboratory Equipment Quick Setup Data-Eye Diagram Quick Setup Data-Eye Generation Observation Equipment Setup. Parallel Input Connections. Basic Observation-Test Procedure. Quick Setup Error Rate Checking. Equipment Setup. Parallel Connections. Quick Setup BERC Test Procedure Chapter Test Setups 4.1.1 4.1.2 4.2.1 4.2.2 4.2.3 4.2.4 Serial Link Verification Using Serial Error Rate Tester (BERT) Test Setup Full-Speed Mode Test Setup Half-Speed Mode Jitter Testing. Jitter Test System Calibration Reference Clock Jitter Transfer Test. Reference Clock Jitter Tolerance Test Data Jitter Tolerance Test. Appendix Connector Signals A.1.1 A.1.2 Input: (0.100") Connectors. Control Signal Input Connectors Transmitter Parallel Data Input Connectors Output: (0.100") Connectors TEST_0 Connector Page Number
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Contents
Paragraph Number Title Appendix Parts List Design Verification Board Parts List .B-1 Appendix Prescaler Jitter Measurement Page Number
Divide-by-xx Prescaler Description .C-1 Prescaler Components.C-2 Appendix Revision History
MC92602 Design Verification Board User's Guide
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Chapter General Information
Introduction
This user's guide describes MC92602 design verification board, Rev. higher. design verification board (DVB) facilitates full evaluation MC92602 Quad Reduced Interface SerDes. should read conjunction with MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual. This design verification board intended evaluation testing purposes only. Motorola does guarantee performance production environment. This board designed used with laboratory equipment (pattern generators, data analyzers, BERT, scopes, etc.) connected other evaluation boards. Access MC92602 device (verification chip) through connectors each pin, allow complete in-depth `design verification' testing chip design. This allows user check features/functions MC92602 device. four parallel data input ports configuration/control signal pins, accessed through common 0.100" male connectors (headers). parallel data output ports accessed through 0.100" connectors. Device JTAG port signals also accessed with separate connector. MC92602 high-speed serial receivers transmitters accessed coaxial connectors signal integrity measurements. single 5.0-V power source required operation. necessary voltages generated regulators onboard. reference clock MC92602 chip provided using either external clock onboard crystal oscillator. Clock drivers provide additional clock signals triggering analyzer instrumentation scopes.
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Design Verification Board Features
Design Verification Board Features
single external 5.0-V onboard regulators supply power onboard circuitry. Reference clock source 250-MHz crystal oscillator external clock source. Parallel data control interfaces accessible through standard 0.100", connectors data generators analyzers. full-duplex differential data links accessible through connectors. pairs test traces with connections facilitate measurements characteristic impedance representative board traces. Connector provided JTAG test access port
functional, physical, performance features MC92602DVB follows:
Specifications
Table 1-1. MC92602DVB Design Verification Board Specifications
Characteristics Specifications Rev. higher typical 0.15 MAPBGA 0°-30°C FR-4 Height Width Thickness 14.8", 12.3", 0.1", Four ground planes, split power plane, three signal routing layers, bottom component layers with some additional signal routing.
MC92602DVB design verification board specifications provided Table 1-1.
Board revision External power supply Support circuit regulator MC92602 core link regulator Interface (VDDQ) regulator MC92602 package Operating temperature Material Dimensions
Conducting layers
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Abbreviation List
Abbreviation List
Table 1-2. Acronyms Abbreviated Terms
Term BIST Meaning High logic level (nominally logic level (nominally Built-in self-test Design verification board Interface connection Pseudo-noise Pseudo random sequence Test access port Time delay reflectometry Peak-to-peak unit interval
Table contains abbreviations used this document.
PRBS UIp-p
Related Documentation
MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual (MC92602RM) MC92602DVB schematics MC100ES6222 data sheet MC100ES8111 data sheetMPC9456 data sheet
Related documentation includes following:
Block Diagram
Figure shows MC92602 design verification board block diagram.
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Block Diagram
3.3V_CLK_OUT1 CLK_IN +1.5 V/GND 0.100" Connector X-TAL MC100 ES6222 3.3V_CLK_OUT2 3.3V_CLK_OUT3 3.3V_CLK_OUT4 MPC9456 R12V +3.3-V Regulator
1.5V_CLK_OUT5
MC100 ES8111
1.5V_CLK_OUT6
CLK_C_PG +3.3 CLK_D_PG +1.5 0.100" Connectors +1.8-V Regulator +1.8 RLINK_D0 XLINK_D0 RECV_D RLINK_C0 RECV_C RECV_B RECV_A HSTL_VREF XMIT_A XMIT_B Ctrl/Tst MC92602 Reduced Interface SerDes XLINK_C0 RLINK_B0 XLINK_B0 RLINK_A0 XLINK_A0 CLK_A_PG R22V2 PG10 PG11 0.100" Connectors PG13 CLK_B_PG R22V +1.5-V Regulator R22V1
TST1
TST2
Vertical Test Traces
TST5
TST6 0.100" Connectors
Control
XMIT_C
XMIT_D
HSTL_VREF
TST3 TST4
Horizontal Test Traces
TST7 TST8
Figure 1-1. MC92602 Design Verification Board Block Diagram
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Board Components
Board Components
Table list major components MC92602 design verification board. complete parts listing found Appendix "Parts List."
Table 1-3. Major Board Components
Component MC92602ZT 0.100" connectors 0.100" connectors 0.100" connectors Description Motorola Quad 1.25 Gbaud Reduced Interface SerDes PG1-PG11, PG13 provide access parallel inputs control signals LA1-LA4 provide access parallel outputs PG12 PG14 provide access connector +VDD/ground planes, respectively. SMA1-SMA16: Serial transmit receive connections TST1-TST8: Impedance test trace connections CLK_OUT1-CLK_OUT6: Reference clock outputs CLK_IN: External reference clock input CLK_A_PG CLK_D_PG: Input clock connectors VR33, VR18, VR1: +3.3 +1.8 +1.5 (VDDQ) voltage regulators R12V, R22V, R22V1, R22V2: Potentiometers setting +3.3 +1.8 +1.5 VDDQ, HSTL reference voltage levels Onboard 250-MHz crystal oscillator Divide-by-1 divide-by-2 clock buffer +3.3-V LVCMOS clock buffer Level shift clock buffer
connectors
LT1587 voltage regulators Potentiometers XTAL oscillator MC100ES6222 clock buffer MPC9456 clock buffer MC100ES8111 clock buffer
Contact Information
questions concerning MC92602 design verification place order kit, contact your local Motorola field applications engineer.
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Chapter Hardware Preparation Installation
This chapter provides unpacking, hardware preparation, configuration-installation instructions, description interface components MC92602DVB.
Unpacking Instructions
Unpack board from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
MC92602DVB Package Contents
Table 2-1. MC92602DVB Contents
Quantity Item MC92602DVB design verification board MC92602DVB Reduced Interface SerDes Design Verification Board User's Guide MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual Complete MC92602DVB design verification board schematics 0.100" shunts Square receptacle patch cords
Table describes contents MC92602DVB kit.
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Hardware Preparation
Hardware Preparation
Operation MC92602DVB requires proper setup power supply voltage regulators well reference clock. Figure depicts location major components board. following sections describe proper setup MC92602DVB.
Crystal Oscillator Connectors Switch +3.3-V Power Connection Clock Buffers Voltage Regulators HSTL Reference Test Point
Connector
Vertical Test Traces
+5-V Power Connectors
MC92602
Serial Differential Connectors
Connectors
Connector +1.5- +1.8-V Power Connectors
Horizontal Test Traces
Connectors
Figure 2-1. Side Part Location Diagram
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Hardware Preparation
2.3.1
Setting Power Supply Voltage Regulators
MC92602DVB requires single +5.0-V supply. Fully operational, board will draw maximum current less than amps from +5.0-V supply. Actual current consumption depends user voltage levels, clock frequencies, MC92602 operating mode. board contains +5.0-V connection posts ground connection posts. These duplicate connections simplify using four-wire supply: supply ground, force sense.
2.3.2
Setting Voltage Regulators
+5.0-V supply used power onboard voltage regulators, VR33, VR18, VR15. These regulators generate +3.3, +1.8, +1.5/1.8 (VDDQ), respectively. +3.3-V supply provides power oscillator clock buffer chips. This supply varied over range +3.3 using R12V potentiometer. +1.8-V supply used power MC92602 core logic, transceivers, on-chip phase-locked loop (PLL). This regulator adjusted over range +1.8 0.15 using R22V. +1.5-V (HSTL) VDDQ supply powers MC92602 control signal, parallel input, output interface circuitry. This voltage level determined desired logic interface. +1.5-V supply adjusted using R22V1 potentiometer from +1.5 0.45 0.15 desired, +1.5-V regulator adjusted match +1.8-V range evaluation those systems that contain separate +1.5-V supply. +3.3-V, +1.8-V, +VDDQ supplies accessible connection posts. Note that these regulators should voltage limits within operating ranges described MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual. Failure operate within these ranges could cause damage MC92602. Motorola will guarantee MC92602 operation beyond ranges specified. R12V, R22V, R22V1 potentiometers will factory +3.3, +1.8, +1.5 respectively.
2.3.3
HSTL Voltage Reference Regulator
HSTL voltage reference that must adjusted logic high/low switch point. nominal +1.5 +1.5-V, VDDQ supply, R22V2 should such that voltage HSTL_VREF test point +0.75 those systems whose HSTL voltage will +1.8 this potentiometer should +0.9 R22V2 potentiometer typically factory +0.8
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Reference Clock Source
Reference Clock Source
Through combination clock buffers, reference clock supplied MC92602 several output connectors. input reference clock MC92602 supplied using either onboard crystal oscillator, directly driving external reference clock into board's clock buffer circuit connector, CLK_IN. clock circuitry MC92602DVB shown Figure 2-2.
250-MHz Oscillator CLK_0 CLK_IN CLK_1 CSEL MPC9456 3.3V_CLK_OUT3 3.3V_CLK_OUT4 3.3V_CLK_OUT1 3.3V_CLK_OUT2 MC100ES6222 PECL HSTL Buffer MC100ES8111 REF_CLK_P REF_CLK_N 1.5V_CLK_OUT5 1.5V_CLK_OUT6
Figure 2-2. MC92602DVB Clock Circuitry
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Reference Clock Source
2.4.1
Using Onboard Oscillator
There available positions using onboard oscillators. standard 14-pin socket available board allow user easily change frequencies swapping crystal oscillators with other values. onboard oscillators must times desired MVC92602 reference clock frequency. default reference clock frequency oscillator supplied with board MHz. Crystal oscillators used with this board should have +3.3-V complementary PECL outputs capable driving line terminated with Oscillators conforming these specifications also available J-lead packages soldered onto underside MC92602DVB location This oscillator, then enabled placing switch `off' position. Both types crystal oscillators available from external vendors variety frequencies. Once either type oscillator installed, switch must placed `on' position select onboard oscillator.
2.4.2
External Reference Clock Source
input reference clock also supplied using external reference clock into clock buffer circuit board CLK_IN connector. supply external reference clock, switch number must `off' position. user must then supply 1.0-Vp-p input clock connector. CLK_IN input coupled board and, therefore, does require biasing input signal. This external clock input also terminated with impedance.
2.4.3
Supplying Clock MC92602
input reference clock, from either onboard oscillator external source, applied MC100ES6222 clock buffer. This buffer input clock select multiplexer, programmable divide-by-one/divide-by-two function. buffer also contains master reset (Enable). recommended that this reset, found switch activated, then deactivated after changing divide-by-xx switch. This will ensure proper frequency generation.
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Reference Clock Source
Between MC100ES6222 output MC92602 reference clock inputs, REF_CLK_P REF_CLK_N, MC100ES8111 which performs PECL HSTL level shift. also drives connectors, 1.5V_CLK_OUT5 1.5V_CLK_OUT6, with HSTL level clock signals.
NOTE
outputs MCP100EP8111 expect path ground. Therefore, blocker being used with 1.5V_CLK_OUT5 1.5V_CLK_OUT6 outputs trigger signal oscilloscope, feed through termination must placed line before blocker before attachment oscilloscope. attenuator used place feed through termination.
2.4.4
3.3V_CLK_OUTn Connectors
Four single-ended, 3.3-V level, clock signals available connectors drive other instruments. Between MC100EP8111 output SMAs, MPC9456 which performs differential PECL single-ended +3.3-V LVTTL/CMOS level shift. These CMOS outputs series terminated board, then connect connectors labeled 3.3V_CLK_OUT1, 3.3V_CLK_OUT2, 3.3V_CLK_OUT3, 3.3V_CLK_OUT4. outputs MPC9456 disabled setting switch SW1, switch `off' position.
2.4.5
Clock Frequency Selection
accommodate fact that MC92602 receive data both edges reference clock (DDR), which many pieces test equipment single-edge triggered (SDR), MC92602DVB clock outputs programmed either same supplied frequency half supplied frequency setting SW1, switches either `on' (divide-by-one) `off' (divide-by-2). This allows interface between board bench either single data rate (SDR) with double speed clock, double data rate (DDR) with single speed clock.
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Reference Clock Source
1.5V_CLK_OUTn outputs will always follow clock supplied MC92602 frequency programmed SW1, switch outputs 3.3V_CLK_OUT1 3.3V_CLK_OUT2 programmed setting SW1, switch 3.3V_CLK_OUT3 3.3V_CLK_OUT4 programmed setting SW1, switch Table lists switch positions output frequencies. input frequency, CLK_IN refers either onboard oscillator frequency externally applied clock source frequency. NOTE Only those frequencies listed MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual considered valid. Motorola does guarantee operation MC92602 frequencies other than those listed reference manual.
Table 2-2. Settings Output Frequencies
Switch Switch Position MC92602 REF_CLK_P, REF_CLK_N, 1.5V_CLK_OUTn CLK_IN CLK_IN/2 3.3V_CLK_OUT1, 3.3V_CLK_OUT2 3.3V_CLK_OUT, 3.3V_CLK_OUT4
CLK_IN CLK_IN/2
CLK_IN CLK_IN/2
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Interface Components
Figure depicts settings using onboard oscillator with divide-by-two function MC92602 3.3V_CLK_OUTn outputs. 3.3V_CLK_OUT1 3.3V_CLK_OUT2 outputs enabled divide-by-one function. 3.3V_CLK_OUT3 3.3V_CLK_OUT4 outputs also enabled divide-by-two function.
External Clk_In/2 Onboard Clk_In Enabled Clk_In Clk_In Enabled Alternate Oscillator ENABLE Onboard/External CLK_IN Select MC92602 REF_CLK Frequency Select MC100ES6222 Reset 3.3V_CLK_OUT1, _OUT2 Frequency Select 3.3V_CLK_OUT3, _OUT4 Frequency Select MPC9456 (3.3V_CLKS) OUTPUT ENABLE_B
Reset Clk_In/2 Clk_In/2 Reset
Figure 2-3. Reference Clock Selection Example Switch Settings
Interface Components
following sections list descriptions MC92602DVB interface connector components.
2.5.1
Parallel Inputs Outputs
MC92602 parallel supplied +1.5-V (HSTL) VDDQ voltage regulator (set rail-to-rail signal swing. There bi-directional signals MC92602 design verification board.
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Interface Components
2.5.1.1
Parallel Inputs
parallel inputs, both data control, accessible 0.100" connectors. Figure depicts 0.100" connector numbering scheme, with being labeled board. complete mapping MC92602 inputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-4. 0.100" Input Connector Numbering Scheme (Top View)
description input functionality MC92602, refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual.
2.5.1.2
Parallel Outputs
parallel outputs, both data status bits, present four 0.100" connectors. Figure depicts 0.100" output connector numbering scheme, with labeled board. parallel output signals MC92602 1.5- 1.8-V HSTL compatible depending setting VDDQ regulator. complete mapping MC92602 outputs 0.100" connectors listed Appendix "Connector Signals." Note that even number pins connected ground.
Figure 2-5. 0.100" Output Connector Number Scheme (Top View)
information regarding MC92602 outputs, refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual.
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Special Test Connection
2.5.2
+VDDQ Ground (GND) Access Connections
MC92602DVB also 0.100" connectors, PG12 PG14, with dedicated connections +1.5-V VDDQ ground planes. These useful biasing parallel input signals using jumper cables. number pins connected VDDQ plane. even number pins connected ground (0.0 plane.
2.5.3
Serial Inputs Outputs
MC92602 high-speed serial differential inputs differential outputs connected appropriately labeled pairs connectors through board traces with characteristic impedance (100- differential). output driver requires parallel termination mid-rail (+0.9 nominal +1.8-V supply). termination voltage +0.9 signal must coupled. There coupling blocking) serial outputs board. needed, coupling must done in-line before termination. During testing, serial transmitter outputs should terminated with This done connecting serial transmitter outputs serial receiver inputs, laboratory equipment with input impedance through in-line coupling, terminating outputs with terminations.
Special Test Connection
MC92602DVB also contains oscilloscope test socket, labeled TPA. When MC92602 configured factory test mode, this test socket enables special access PLL. NOTE This test mode factory testing purposes only. There system applications this mode test socket should remain unconnected times.
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Test Traces
Test Traces
MCS92602DVB design verification board both vertical horizontal test traces: Vertical: TST1-TST5 TST2-TST6 Horizontal: TST3-TST7 TST4-TST8
These traces used determine impedance board using measurement techniques.
2-11
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Chapter Laboratory Equipment Quick Setup Evaluation
This chapter begins with listing recommended test equipment needed perform complete evaluations MC92602. Chapter "Test Setups," covers specific setup configurations this equipment depending desired feature under test. quick setup evaluation procedures outlined below describe MC92602DVB used evaluate data `eye diagram' simple error rate test using internal test features MC92602 with minimal amount test equipment. Only power supply sampling oscilloscope required. Details testing specific systems left user. more information regarding MC92602 feature set, refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual.
Recommended Laboratory Equipment
Evaluation MC92602 feature possible using MC92602DVB evaluation conjunction with several pieces test equipment. quick setup evaluations other tests listed this guide utilize basic test equipment listed Table 3-1. Equivalent instrumentation substituted. pieces test equipment necessary tests.
Table 3-1. Recommended Test Equipment
Quantity Equipment MC92602DVB evaluation Tektronix 8000 digital sampling oscilloscope Tektronix 80E04 TDR/sampling head GHz) Tektronix 80E03 sampling heads GHz) Hewlett-Packard HP16700 logic analysis system Hewlett-Packard HP16522A pattern generators Hewlett-Packard HP16557D logic analyzers Hewlett Packard HP6624A system power supply
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Recommended Laboratory Equipment
Table lists laboratory accessories.
Table 3-2. Accessories
male each coax patch cords, lengths: various attenuators attenuators blockers couplers) terminations ground) feed through terminations 5/16" torque wrench (fits SMA, 2.9- 3.5-mm connectors) Bias-T networks
Power splitters adapters female female adapters male male adapters
In-depth testing MC92602 performed using error rate tester jitter analysis system. Table provides listing test equipment that used these types tests.
Table 3-3. Jitter Analysis Test Equipment
Quantity each Equipment Agilent 71500C jitter analysis system 70820A microwave transition analyzer 70004A display 3325B synthesizer/function generator 83752A synthesized sweeper 86130A BitAlyzer (serial error rate tester) 70874C jitter personality card Assorted bandpass filters Rohde Schwarz SMIQ-04B signal generator Agilent 6624A system power supply Agilent 11636B power splitter Divide-by-xx prescalers
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Quick Setup Data-Eye Diagram
Quick Setup Data-Eye Diagram
MC92602DVB design evaluation comes equipped immediately demonstrate MC92602 functions: Data-eye signal generation observation error rate checking using internal built-in self-test (BIST) features.
3.2.1
Quick Setup Data-Eye Generation Observation
transmitted data-eye observed serial outputs MC92602 using integrated, 23rd order, pseudo-noise (PN) pattern generator. implementation 23-bit generator uses following polynomial.
Stimulus from this generator 8B/10B encoded also used further system testing. Refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual, more information.
3.2.1.1
Equipment Setup
Generation observation data-eye produced on-chip generator requires only MC92602DVB, power supply, high-speed digital sampling scope, 0.100" shunts, single receptacle patch cords. shunts patch cords provided with MC92602DVB evaluation kit. MC92602DVB test equipment should connected depicted Figure 3-1. Configure clock circuits with shown Figure 2-3. NOTE unconnected serial transmitter outputs should terminated This done connecting serial transmitter outputs serial receiver inputs terminations through in-line coupling blocking).
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Quick Setup Data-Eye Diagram
Blockers
Feed Through Termination
TRIG Blocker
V_CLK_OUT1
XMIT_P XMIT_N
MC92602DVB +5-V Sense +5-V Force Sense Force
+5-V Supply
Figure 3-1. Data-Eye Observation Setup
3.2.1.2
Parallel Input Connections
basic diagram will generated biasing parallel inputs according Table 3-4. Ground connections made using 0.100" shunts. Connections +1.5 VDDQ made using square receptacle patch cords jumpering numbered pins headers PG12 PG14. even number pins connector headers connected board's ground plane. unlisted pins connected.
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Quick Setup Data-Eye Diagram
Table 3-4. Data-Eye Generation Parallel Input Biasing
Connector TEST_0 CTRL_SIG_0 Signal TRST REPE RCCE ADIE RESET STNDBY LBOE MEDIA TBIE COMPAT RECV_REF_A XMIT_REF_A BSYNC DROP_SYNC TST_1 TST_0 Bias Level +1.5 +1.5 +1.5 +1.5 +1.5 C_XCLK D_XMIT0 B_XCLK C_XMIT0 A_XCLK B_XMIT0 Connector A_XMIT0 D_XCLK Signal XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_K XCVR_A_DISABLE XMIT_A_CLK XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_K XCVR_B_DISABLE XMIT_B_CLK XMIT_C_0 XMIT_C_1 XMIT_C_2 XMIT_C_3 XMIT_C_K XCVR_C_DISABLE XMIT_C_CLK XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_K XCVR_D_DISABLE XMITD_CLK Bias Level +1.5 +1.5 +1.5 +1.5
CTRL_SIG_1 CTRL_SIG_2
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Quick Setup Data-Eye Diagram
3.2.2
Basic Observation-Test Procedure
Connect MC92Q602DVB test equipment described Figure Table 3-4. This will place MC92602 generation mode with MC92602 reset. Step skipped previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (1.5 regulators connectors T10, respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT5 (period ns). Observe XMIT_x_P XMIT_x_N output. Since chip reset, transmitter should show constant output level ground. Connect RESET (connector CTRL_SIG_0, VDDQ access connection. This releases RESET signal. Observe XMIT_x_P XMIT_x_N. transmitter should outputting random data. Setting digital sampling oscilloscope infinite persistence mode will display data-eye. example data-eye shown Figure 3-2.
Figure 3-2. MC92602 Data-Eye Using Recommended Test Setup
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Quick Setup Data-Eye Diagram
3.2.3
Quick Setup Error Rate Checking
addition having integrated generator, MC92602 also error rate checker (BERC). integrated 23rd order signature analyzer, that synchronized incoming stream used count code group mismatch errors relative internal reference pattern. following test procedure will describe this BIST feature. more information concerning MC92602 BIST, refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual.
3.2.3.1
Equipment Setup
Connect MC92602DVB shown Figure 3-3, connecting transmitter outputs link under test (XLINK_x_P/N) receiver under test (RLINK_x_P/N). NOTE receiver signature analyzers assume four channels being exercised. BIST testing being performed between devices, means external loopback selected channels, unused channel receivers must disabled analyzers will into Sync state. That receivers having stimulus must have XCVR_x_DISABLE asserted.
+5-V Supply +5-V Sense +5-V Force Sense Force
Logic Analyzer C_RECV B_RECV D_RECV
XLINK_D_P RLINK_D_P XLINK_D_N RLINK_D_N XLINK_C_P RLINK_C_P XLINK_C_N RLINK_C_N XLINK_B_P RLINK_B_P XLINK_B_N RLINK_B_N XLINK_A_P RLINK_A_P XLINK_A_N RLINK_A_N MC92602DVB
A_RECV
Figure 3-3. Error Rate Check Test Setup
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Quick Setup Data-Eye Diagram
3.2.3.2
Parallel Connections
bias connections parallel inputs perform quick setup BERC test same those quick setup eye-diagram shown Table 3-4. parallel outputs connected data analysis system. data analyzer used observe start sequence status errors detected internal data analyzers.
3.2.3.3
Quick Setup BERC Test Procedure
Connect MC92602DVB test equipment described Section 3.2.3.1, "Equipment Setup." This will place MC92602 generation mode with MC92602 held reset receivers BERC mode using recovered clock. Steps skipped previously performed when setting DVB. Apply +5.0 evaluation board. Verify voltage levels +3.3 +1.8 +VDDQ (1.5 regulators connectors T10, respectively. necessary, adjust R12V, R22V, R22V1 obtain desired voltage levels. Verify that reference clock frequency CLK_OUT1 156.25 (period ns). Connect RESET (connector CTRL_SIG_0, +1.5 VDDQ access connection. This releases RESET signal. Observe parallel outputs data analyzer. described MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual, MC92602 will start lock PLL, initialize receivers, perform byte alignment, reset error counter. When receivers locked BIST running, recovered clock observable RECV_x_RCLK. Refer Table receiver state sequence, which will occur each receiver's status output. Figure example receiver start-up error detection sequence.
Table 3-5. State Sequence Receiver
RECV_x_ERR Receiver State MC92602 reset mode Receiver startup High Receiver byte/word synchronized, analyzer locked BIST running mismatch this character High Don't care Don't care Don't care High Don't care Edge RECV_x_K RECV_x_RCLK
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Quick Setup Data-Eye Diagram
Once receiver initially locked receiver data bits, RECV_x_[4:0], zero (logic low). Should error occur, RECV_x_[4:0] will increment RECV_x_ERR will flag error during that byte time. value RECV_x_[4:0] remains constant until another error detected system reset. receiver counter fills with errors, bits RECV_x_[4:0] stay logic high (11111111) until receiver reset. Refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual more detail.
RESET RECV_x_RCLK RECV_x_ERR RECV_x_K RECV_x_3 RECV_x_2 RECV_x_1 RECV_x_0 MC92602 Reset Byte Sync RCVR Startup RCVR Synced Analyzer Locked BIST Running Mismatch This Character BIST Running Mismatches Counted
Figure 3-4. Receiver Startup Error Detection Sequence
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Chapter Laboratory Equipment Quick Setup Evaluation
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Chapter Test Setups
This chapter outlines laboratory test equipment setup procedure evaluate features MC92602 more depth than those outlined previous chapter. These setups meant guidelines only implied complete. Details testing specific system applications left user.
Serial Link Verification Using Serial Error Rate Tester (BERT)
This test setup used observe rate which MC92602 produces errors given either pseudo-random (PRBS) patterns user-defined pattern sets generated serial error rate tester (BERT). MC92602 placed repeater mode, REPE high, thereby disabling parallel receiver transmitter buses. Testing performed using ten-bit interface mode does require insertion idle characters word recognition byte alignment. verification using 8B/10B encoder other MC92602 features required, then appropriate idle insertion timing requirements outlined MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual, must followed.
Chapter Test Setups
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Serial Link Verification Using Serial Error Rate Tester (BERT)
4.1.1
Test Setup Full-Speed Mode
Figure depicts test setup MC92602 full-speed mode (HSE `0'). control bits follows: REPE TBIE
other control bits `0,' except RESET, which initially `0,' then transitioned start MC92602.
Power Splitter Clean Clock 1.25 Error Rate Tester Pattern Generator CK_OUT Error Detector Serial Data
Source
Blocker MC92602DVB (Repeater Mode) Prescaler Divide-by-10 Reference Clock
MC92602DVB (Repeater Mode)
Figure 4-1. Full Speed Serial Link Test Setup
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Serial Link Verification Using Serial Error Rate Tester (BERT)
4.1.2
Test Setup Half-Speed Mode
Serial link testing also performed using half-speed mode (HSE `1'). This reduces frequencies setup factor two. Figure depicts serial link test setup using using divide-by-10 prescaler.
Clean Clock Error Rate Tester Pattern Generator Error Detector
Source
Power Splitter
Blocker
Prescaler Divide-by-10
Reference Clock 62.5
MC92602DVB (Repeater Mode)
Figure 4-2. Half-Speed Serial Link Test Setup
MC92602 Design Verification Board User's Guide
Serial Data
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Jitter Testing
Jitter Testing
following tests guidelines verifying performance MC92602 `noisy' conditions. Results will vary depending input reference frequencies, MC92602 mode operation, test setup equipment, test environment.
4.2.1
Jitter Test System Calibration
Before beginning type jitter measurements, system must first calibrated, shown Figure 4-3, produce desired frequency amplitude modulation jittered source. amplitude modulation then translated into jitter units peak-to-peak unit intervals (UIp-p). Different synthesized sweepers have different characteristics different frequencies. possible that certain frequencies will produce spurious side lobes which will affect jitter characterization. strongly advised that bandpass filter centered carrier frequency used input microwave transition analyzer. Refer synthesized sweeper reference manual more details.
Function Generator 10-MHz Reference Clock
Modulation Signal
70000 Mainframe with Microwave Transition Analyzer
HPIB
Filter
Synthesized Sweeper (Carrier Frequency)
Jittered Clock
Power Splitter
Figure 4-3. Jitter Measurement System Calibration
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Jitter Testing
4.2.2
Reference Clock Jitter Transfer Test
This test setup used observe amount jitter placed reference clock that transferred data outputs. Example frequencies were chosen match narrow bandpass filters available with Agilent 71500C jitter analysis system. control bits follows: TBIE other control inputs `0.' parallel data inputs must pattern shown Figure 4-4. This data pattern appears 625-MHz clock signal serial outputs.
Function Generator
10-MHz Reference Clock
Modulation Signal
Blocker HPIB 70000 Mainframe with Microwave Transition Analyzer Filter Filter Blocker Prescaler Divide-by-2 Jittered Clock
Serial Data
Synthesized Sweeper (Carrier Frequency) 1.25
Power Splitter
Jittered Reference Prescaler Clock MC92602DVB Divide-by-10
Parallel
Data 10101 01010 10101 01010 10101
Figure 4-4. Reference Clock Jitter Transfer Test Setup
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Jitter Testing
4.2.3
Reference Clock Jitter Tolerance Test
test setup, shown Figure 4-5, used observe amount jitter placed reference clock that does produce errors serial data outputs compared input serial data stream. MC92602 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: REPE TBIE
other control inputs `0.'
Error Rate Data over HPIB
Function Generator 10-MHz Reference Clock
Source
Clean Clock 1.25
Error Rate Tester Pattern Generator Error Detector
Modulation Signal
Synthesized Sweeper (Carrier Frequency)
Jittered Clock 1.25
Power Splitter
Prescaler Divide-by-10
Jittered Reference Clock
MC92602DVB
Figure 4-5. Reference Clock Jitter Tolerance Test Setup
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MC92602 Design Verification Board User's Guide
Serial Data
HPIB
70000 Mainframe with Microwave Transition Analyzer
Blocker
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Jitter Testing
4.2.4
Data Jitter Tolerance Test
test setup, shown Figure 4-6, used observe amount jitter placed serial data inputs that does produce errors serial data outputs. MC92602 placed ten-bit interface mode (TBIE) repeater mode (REPE). serial data stream either PRBS user-defined data. control bits follows: REPE TBIE
other control inputs `0.'
Error Rate Data Over HPIB
Function Generator
Clean Clock Source 1.25
Error Rate Tester Pattern Generator Error Detector
10-MHz Reference Clock
Power Splitter 70000 Mainframe with Microwave Transition Analyzer
Blocker Serial Data Prescaler Divide-by-10 Reference Clock MC92602DVB (Repeater Mode)
Modulation Signal
HPIB
Synthesized Sweeper (Carrier Frequency)
Jittered Clock 1.25
Figure 4-6. Data Jitter Tolerance Test Setup
MC92602 Design Verification Board User's Guide
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Appendix Connector Signals
parallel data input output signals MC92602DVB design verification board listed following tables. connection test points common 0.100" spaced type connectors.
Input: (0.100") Connectors
configuration, control, data, test inputs MC92602 connectors. There total input connectors DVB. each connector, even numbers connected ground plane. signal inputs numbers) have pull-up resistors board. Therefore, configuration requires `high' logic must jumper connected +1.5 (VDDQ) access connectors PG12 PG14. input required `low,' shorting jumper installed. signal name, description, MC92602 device `ball' (pin) number listed following tables each input connectors.
A.1.1
Control Signal Input Connectors
signals connectors CTRL_SIG_0, CTRL_SIG_1, CTRL_SIG_2 (PG1-PG3, respectively) control input signals that basic configuration MC92602. These signals corresponding connector pins listed Table A-1, Table A-2, Table A-3, respectively.
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Input: (0.100") Connectors
Table A-1. CTRL_SIG_0 Connector
Connector
MC92602
Input Signal Name REPE RCCE ADIE RESET STNDBY Repeater mode enable Recovered clock enable
Description
Word synchronization enable Half-speed mode enable Add/drop idle enable System reset Standby mode enable Ground connection
Table A-2. CTRL_SIG_1 Connector
Connector MC92602 Input Signal Name LBOE MEDIA TBIE COMPAT RECV_REF_A XMIT_REF_A Loopback output enable Loopback enable Media impedance select Ten-bit interface enable IEEE 802.3 compatibility mode enable Receiver primary clock enable Transmit primary clock enable Ground connection Description
Table A-3. CTRL_SIG_2 Connector
Connector MC92602 Input Signal Name BSYNC DROP_SYNC TST_1 TST_0 Description Byte synchronization mode Drop synchronization Test mode-select Test mode-select Ground connection
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Input: (0.100") Connectors
A.1.2
Transmitter Parallel Data Input Connectors
MC92602 transmitter parallel data input signals channels through mapped connectors listed tables below. Table shows 4-bit data (DDR) input transmitter channels through respectively, A_XMIT0 D_XMIT0 (PG8, PG10, PG6, PG4) connectors.
Table A-4. A_XMIT0, B_XMIT0, C_XMIT0, D_XMIT0 Connectors
MC92602 Ball Connector A_XMIT0, B_XMIT0, C_XMIT0, D_XMIT0, (Channel (Channel (Channel (Channel Input Signal Name XMIT_x_0 XMIT_x_1 XMIT_x_2 XMIT_x_3 Description
Transmitter data input Transmitter data input Transmitter data input Transmitter data input
XMIT_x_K Transmitter special character XCVR_x_ DISABLE Transmitter disable Ground connection
Table lists transmitter clock signals four channels A_XCLK-D_XCLK (PG9, PG11, PG7, PG5) connectors, respectively.
Table A-5. A_XCLK, B_XCLK, C_XCLK, D_XCLK Connectors
MC92602 Ball Connector A_XCLK, B_XCLK, C_XCLK, D_XCLK, (Channel (Channel (Channel (Channel Input Signal Name CLK_x_PG XMIT_x_CLK Description
Clock connection Transmitter interface clock Ground connection
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Output: (0.100") Connectors
Output: (0.100") Connectors
MC92602 receiver parallel data outputs connected 0.100" connectors. mapping these signals contained Table A-6. Table lists signals A_RECV-D_RECV (LA1-LA4, respectively) connectors. Note that receive data clock, RECV_x_RCLK, brought connector pins. Care should exercised when connecting both these pins exceed drive capacity chip output. Refer MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual, more details.
Table A-6. A_RECV B_RECV Connectors
MC92602 Ball Connector A_RECV, B_RECV, C_RECV, D_RECV, (Channel (Channel (Channel (Channel Output Signal Name Description
RECV_x_CLK XCVR_ receive data clock
RECV_x_CLK XCVR_ receive data clock Ground connection Ground connection
channels this ground. channel this (JTAG, test data out) RECV_x_ERR Receiver error detect RECV_x_K RECV_x_3 RECV_x_2 RECV_x_1 RECV_x_0 Ground connection Ground connection Receiver special character (status) Ground connection Ground connection Ground connection Ground connection Receiver data Receiver data Receiver data Receiver data
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TEST_0 Connector
TEST_0 Connector
Table lists signals connector TEST_0 (PG13). This MC92602 test access port, TAP, interface IEEE 1149 JTAG testing. NOTE There 10-K internal pull-ups TMS, TDI, TRST. TRST held during power does receive active preset after power test logic assume indeterminate state disabling some normal transceiver functions. recommended that TRST terminated following ways:
TRST driven controller that provides reset after power Connect TRST RESET. Terminate TRST with resistor hardwire) ground.
important shorting jumper TRST input comply with above note. more information test access port, Section MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Manual, more details.
Table A-7. TEST_0 Connector
Connector MC92602 Input Signal Name TRST JTAG test data JTAG test clock JTAG test mode select JTAG test reset Ground connection Description
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Appendix Parts List
Design Verification Board Parts List
Table shows parts used constructing MC92602DVB design verification board.
Table B-1. MC92602DVB Design Verification Board Parts List
Item Qty. Reference C18-C19, C24, C27, C30-C33, C54-C57, C208-C210, C303-C304 C11, Value Manufacturer/ Supplier Newark Manufacturer's Part 99F3410 Description Ceramic chip capacitor, size 1812
Kemet
T495X107K010AS
solid tantalum chip capacitor, ESR, size 7343H solid tantalum chip capacitor, ESR, size 7343H Ceramic chip capacitor, size 0805 Ceramic chip capacitor, 0.01 size 0805
C12-C13, C22-C23 C10, C14, C5-C6, C15-C17, C25-C26, C28-C29, C34-C53, C58-C63, C201-C207, C301-302
Kemet
T495X106K035AS
0.01
Newark Newark
93F8740 93F2330
Electronics
M2988-250M
PECL crystal oscillator-14-pin Socket, 14-pin pole slide switches, position (open closed), surface mount
Socket
Newark
504-AG11D 08C7815
Appendix Parts List
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Design Verification Board Parts List
Table B-1. MC92602DVB Design Verification Board Parts List (continued)
Item Qty. Reference PG12, PG14 Value Manufacturer/ Supplier Manufacturer's Part 2516-6002UB Description keyed header with shroud, 0.1" spacing, profile keyed header with shroud, 0.1" spacing keyed header with shroud, 0.1" spacing, profile HDR_100MIL Dialight Linear Technology Motorola Motorola 597-5311-402 LT1587CM MPC9456S MC100EP222 Green surface mount Linear voltage regulator, amps, 3-lead 3.3-V clock buffer, 32-pin gull wing LQFP V/2.5 1:15 differential ECL/PECL clock driver 52-lead LQFP Level shift clock buffer, 32-pin gull wing TQFP screw terminal binding post, red/black/ yellow/ blue/green chip resistor, size 0603 chip resistor, size 0603
PG1-PG11, PG13 LA1-LA4
2520-6002UB 2540-6002UB
VR1, VR18, VR33
T1-T9
Motorola Technology Newark Newark
MC100EP8111S 2304/2303/ 9648/9649/9650 50N1713 50N1715
R--R6, R16, R23, R62-R63, R70-R71, R74-R75 R2--R32 R34-R56, R92-R95 R10, R14, R20, R60-R61, R68-R69, R72-R73 R11,
Dale
CR0805-10W-000T
chip resistor, size 0805 124- chip resistor, size 0805
Dale
CRCW08051240JT
Welwyn Newark Dale
WCR0805330RG
330- chip resistor, size 0805 chip resistor, size 0805
CRCW08051200JT
120- chip resistor, size 0805
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Design Verification Board Parts List
Table B-1. MC92602DVB Design Verification Board Parts List (continued)
Item Qty. Reference R17, R33, R76-R79 CLK_A_PG, CLK_B_PG, CLK_C_PG, CLK_D_PG, CLK_IN, CLK_OUT1-6, SMA1-16, TST1-8 R12V R22V, R22V1, R22V2 R18-R19, R22, R58, R78-R83 R7-R9, R57, R65, R85-R87 Value Manufacturer/ Supplier Dale Newark Johnson Manufacturer's Part CRCW08051000FT-X 95B6635 129-0701-202 901-144-8-RFX Description 100- chip resistor, size 0805 1.0- chip resistor, size 1206 Scope test socket jack socket
VRES,
BOURNS BOURNS Motorola Pomona Dale
3214W-1-102E 3214W-1-502E MC92602 929950-00 4741-12-0/4741-12-2 CR0805-10W-103J
Surface mount trimming resistor, lead Surface mount trimming resistor, lead Quad 1.25 Gbaud SerDes MAPBGA 0.100" shunts Square receptacle patch cord chip resistor, size 0805 chip resistor, size 0805 chip resistor, size 0805
MC92602 Design Verification Board User's Guide
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Appendix Prescaler Jitter Measurement
Divide-by-xx Prescaler Description
Evaluating jitter system requires that clocks within system based common source. this reason, often necessary prescalers derive needed reference clock. Motorola developed small programmable prescaler with maximum input frequency which assembled using commercially available parts. Figure depicts block diagram this prescaler.
Clock Divide Clock In_alt 5-Bit Programmable Counter Divide Prescaler Level Shift Clock
Bank Switch
Bank Switch
Figure C-1. Divide-by-xx Prescaler Block Diagram
input prescaler either through divide-by-2 directly into 5-bit programmable counter. bank bank switches used select variety prescaler values based following formula:
Modulus
where
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Appendix Prescaler Jitter Measurement
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Prescaler Components
values commonly used 1.0-Gbit systems refer Table C-1.
Table C-1. Switch Settings 1.0-Gbit SERDES Prescalers
Bank Input Clock In_alt Clock Clock Clock Bank Modulus
Schematics this prescaler available from your Motorola field applications engineer.
Prescaler Components
Table C-2. Major Components Divide-by-xx Prescaler
Table lists major integrated circuit components needed prescaler.
Part MC12093 MC100ELT23 MC100ELT21 MC100ELT26 HMMC-3122 HMC364S8G HMC394LP4
Manufacturer Motorola Semiconductor Semiconductor Semiconductor Agilent Hittite Microwave Hittite Microwave
Supplier Newark Newark Newark Newark Arrow Hittite Hittite
Comments 1.1-GHz prescaler (divide Dual differential PECL translator, with separate inputs. Single differential PECL translator. Alternative above part. Dual differential PECL translator, with common inputs. Alternative above part. 12-GHz divide-by-2 prescaler, GaAs MMIC. 12-GHz divide-by-2 prescaler, GaAs MMIC. Pin-for-pin alternative above part. 2.2-GHz programmable 5-bit counter, GaAs MMIC.
MC92602 Design Verification Board User's Guide
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Appendix Revision History
This appendix provides list major differences between revisions MC92602 Reduced Interface SerDes Design Verification Board User's Guide (MC92602DVBUG).
Table provides revision history this document.
Table D-1. MC92602DVB Revision History
Rev. Date 5/30/2002 10/1/2002 2/2004 Initial release. Editorial corrections. Appendix Added note concerning loading RECV_x_CLK. Reformatted release. Substantive Change(s)
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Appendix Revision History
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REACH USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution P.O. 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, King Street Industrial Estate, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors
limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
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